Semiconductor module

Abstract

A semiconductor module includes a substrate (100), a semiconductor package (111) disposed on the substrate, a housing for fixing the substrate, and Y capacitors (Y1 - Y4). The front surface wiring in the substrate includes a front surface ground wiring (G1) electrically connected to the housing and front surface main wirings (P1, N1) connected to the back surface wiring connected to the semiconductor package. The Y capacitors are disposed on the front surface of the substrate at positions facing the semiconductor package and between the front surface ground wiring and the front surface main wirings. The semiconductor package and the Y capacitors are arranged such that the direction of current flowing in the semiconductor package and the direction of current flowing in the Y capacitors are opposite to each other.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor module in which a semiconductor package having a semiconductor chip is mounted on a substrate. Background Art

[0002] Conventionally, a semiconductor module has been proposed in which a semiconductor package having a semiconductor chip is mounted on a substrate (for example, see JP 2017-79268A). Specifically, in this semiconductor module, an opening is provided in a printed circuit board serving as a substrate, a metal plate is disposed in the opening, and the semiconductor package is disposed in thermal connection with the metal plate. The semiconductor chip includes semiconductor elements such as transistors. In the semiconductor module, the metal plate is connected to a housing to ensure heat dissipation. Summary of the Invention

[0003] In the above semiconductor module, it is also desirable to suppress the influence of noise.

[0004] In view of the above points, an object of the present disclosure is to provide a semiconductor module capable of suppressing the influence of noise.

[0005] A semiconductor module according to an aspect of the present disclosure includes a substrate, a semiconductor package, a housing, and a Y capacitor. The substrate has a front surface, a rear surface opposite to the front surface, front surface wirings provided on the front surface, and rear surface wirings provided on the rear surface. The semiconductor package includes a semiconductor chip and pads electrically connected to the semiconductor chip. The semiconductor chip includes switching elements. The semiconductor package is set on the substrate in a state where the pads are connected to the rear surface wirings. The substrate is fixed to the housing in a state where the semiconductor package is in thermal connection with the housing. The front surface wirings include a front surface ground wiring electrically connected to the housing and a front surface main wiring connected to the rear surface wirings, and the rear surface wirings are connected to at least one semiconductor package. The Y capacitor is provided on the front surface of the substrate at a position facing the semiconductor package and between the front surface ground wiring and the front surface main wiring. The semiconductor package and the Y capacitor are arranged such that the direction of current flowing in the semiconductor package and the direction of current flowing in the Y capacitor are opposite to each other.

[0006] According to the above configuration, since the Y capacitor is provided, the influence of common mode noise can be reduced. In addition, the semiconductor package and the Y capacitor facing each other are arranged such that currents flow in opposite directions. Therefore, the magnetic fields generated by the flowing currents can cancel each other out, and since the parasitic inductance is reduced, switching surges can be reduced and noise generation can be suppressed. Brief Description of the Drawings

[0007] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings:

[0008] Figure 1 is a circuit diagram of a power conversion device according to the first embodiment;

[0009] Figure 2 is a cross-sectional view of a semiconductor module according to the first embodiment;

[0010] Figure 3A is a schematic top view of the vicinity of an insertion hole on the front surface side of a printed circuit board;

[0011] Figure 3B is a schematic top view of the vicinity of an insertion hole on the back surface side of a printed circuit board;

[0012] Figure 4A is a cross-sectional view of a semiconductor package;

[0013] Figure 4B is a plan view of a semiconductor package;

[0014] Figure 5A is a timing chart showing the amplitude of a primary current;

[0015] Figure 5B is a timing chart showing a resonance current when the resonance frequencies of an input capacitor and a Y capacitor are even multiples of a switching frequency;

[0016] Figure 5C is a timing chart showing a resonance current when the resonance frequencies of an input capacitor and a Y capacitor are odd multiples of a switching frequency;

[0017] Figure 6 is a circuit diagram showing a common-mode current according to the third embodiment;

[0018] Figure 7A is a schematic top view of the front surface side of a printed circuit board according to the fourth embodiment; and

[0019] Figure 7B is a schematic plan view of the back surface side of a printed circuit board according to the fourth embodiment. Specific Embodiments

[0020] Embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals.

[0021] (First Embodiment)

[0022] A semiconductor module according to the first embodiment will be described with reference to the accompanying drawings. The semiconductor module of the present embodiment is suitable for constructing a DC-DC converter that converts direct current into direct current with different voltages. For example, the semiconductor module is suitable for constructing a DC-DC converter mounted on an electric vehicle.

[0023] First, reference will be made to Figure 1Describe the circuit configuration of a power conversion device for a semiconductor module to which this embodiment is applied. This embodiment will describe an example in which the power conversion device converts a high DC voltage from a high-voltage battery BH into a low voltage to charge an auxiliary battery BL. When the power conversion device is installed in a vehicle, the auxiliary battery BL is, for example, a battery for in-vehicle devices such as an audio system.

[0024] The power conversion device according to this embodiment includes four primary-side transistors Q1 to Q4 as primary-side semiconductor elements that convert a high DC voltage into a high-frequency AC voltage and four Y capacitors Y1 to Y4. The power conversion device also includes a main transformer T as a magnetic component that reduces the AC voltage. In addition, the power conversion device includes secondary-side transistors Q5, Q6 as secondary-side semiconductor elements that rectify the reduced AC voltage and a choke coil CC and a smoothing capacitor CO as magnetic elements that smooth the rectified DC voltage. In Figure 1 this, one secondary-side transistor Q5 and one secondary-side transistor Q6 are shown, but in reality, two secondary-side transistors Q5 are arranged in parallel, and two secondary-side transistors Q6 are arranged in parallel.

[0025] The primary-side transistors Q1 to Q4 are formed of, for example, a gallium nitride (hereinafter simply referred to as GaN)-based semiconductor having a horizontal structure capable of high-speed operation. In addition, although not particularly limited, in this embodiment, the secondary-side transistors Q5, Q6 are also formed of a GaN-based semiconductor. The primary-side transistors Q1 to Q4 and the secondary-side transistors Q5, Q6 each have a gate, a source, and a drain.

[0026] Hereinafter, when distinguishing the four primary-side transistors Q1 to Q4, they are also referred to as the first to fourth transistors Q1 to Q4. In addition, hereinafter, when distinguishing the four Y capacitors Y1 to Y4, they are also referred to as the first to fourth Y capacitors Y1 to Y4. In this embodiment, the first to fourth transistors Q1 to Q4 correspond to switching elements. Each of the first to fourth Y capacitors Y1 to Y4 includes a plurality of Y capacitors arranged in parallel, as will be described in detail later.

[0027] First, the configuration of the primary side of the power conversion device will be described. The first to fourth transistors Q1 to Q4 are provided between a first main wiring P connected to the positive terminal of the high-voltage battery BH and a second main wiring N connected to the negative terminal of the high-voltage battery BH. Specifically, the first to fourth transistors Q1 to Q4 are arranged to form two legs between the first main wiring P and the second main wiring N. More specifically, the first transistor Q1 and the third transistor Q3 are connected via a first electrode wiring E1 and are serially provided, and the second transistor Q2 and the fourth transistor Q4 are connected via a second electrode wiring E2 and are serially provided. In the first and third transistors Q1 and Q3, the drain of the first transistor Q1, which constitutes the upper arm element of the leg, is connected to the first main wiring P, and the source of the third transistor Q3, which constitutes the lower arm element of the leg, is connected to the second main wiring N. In the second and fourth transistors Q2 and Q4, the drain of the second transistor Q2, which constitutes the upper arm element of the leg, is connected to the first main wiring P, and the source of the fourth transistor Q4, which constitutes the lower arm element of the leg, is connected to the second main wiring N. Among the first to fourth transistors Q1 to Q4, the serially connected first transistor Q1 and third transistor Q3 and the serially connected second transistor Q2 and fourth transistor Q4 are provided in parallel.

[0028] The gates of the first and third transistors Q1 and Q3 are connected to the first pulse transformer circuit PT1 via the first and third adjustment resistors R1 and R3 and the first and third gate connection wirings M1 and M3. The gates of the second and fourth transistors Q2 and Q4 are connected to the second pulse transformer circuit PT2 via the second and fourth adjustment resistors R2 and R4 and the second and fourth gate connection wirings M2 and M4.

[0029] The first and second pulse transformer circuits PT1 and PT2 are connected to the control circuit SC, and the gate voltages applied to the gates of the first to fourth transistors Q1 to Q4 are adjusted based on control signals from the control circuit SC. Although omitted in Figure 1 , as shown in Figure 3B described later, the first and second pulse transformer circuits PT1 and PT2 are also connected to the sources of the first to fourth transistors Q1 to Q4.

[0030] Between the source of the first transistor Q1 and the drain of the third transistor Q3, a first output wiring L1 connected to the first electrode wiring E1 is provided. Between the source of the second transistor Q2 and the drain of the fourth transistor Q4, a second output wiring L2 connected to the second electrode wiring E2 is provided. The first output wiring L1 and the second output wiring L2 are connected to a primary winding T1 described later.

[0031] Among the first to fourth Y capacitors Y1 to Y4, the first Y capacitor Y1 and the third Y capacitor Y3 are connected and serially arranged between the first main wiring P and the second main wiring N, and the second Y capacitor Y2 and the fourth Y capacitor Y4 are connected and serially arranged. The connection point between the first Y capacitor Y1 and the third Y capacitor Y3 and the connection point between the second Y capacitor Y2 and the fourth Y capacitor Y4 are grounded via the ground wiring G. In the present embodiment, as will be described later, the ground wiring G is electrically connected to the housing 200 and becomes the ground potential.

[0032] In addition, an input capacitor IC is provided between the high-voltage battery BH and the first to fourth transistors Q1 to Q4 and the first to fourth Y capacitors Y1 to Y4.

[0033] The above is the structure of the primary side of the power conversion device. The main transformer T includes a primary winding T1, a secondary winding T2, and a core C. One end of the primary winding T1 is connected to the first output wiring L1, and the other end is connected to the second output wiring L2.

[0034] Next, the structure of the secondary side of the power conversion device will be described. The secondary winding T2 has a center tap T3, and the center tap T3 is grounded. In addition, a secondary-side transistor Q5 is provided between one end side of the secondary winding T2 and the external output line L3, and a secondary-side transistor Q6 is provided between the other end side of the secondary winding T2 and the external output line L3. Similar to the gates of the first to fourth transistors Q1 to Q4, each gate of the secondary-side transistors Q5 and Q6 is connected to the third pulse transformer circuit PT3 via the fifth and sixth adjustment resistors R5 and R6. The third pulse transformer circuit PT3 is connected to the control circuit SC and adjusts the gate voltage applied to the gates of the fifth transistor Q5 and the sixth transistor Q6 based on the control signal from the control circuit SC.

[0035] In addition, on the external output line L3, a choke coil CC is provided between the connection point between the auxiliary battery BL and the secondary-side transistors Q5 and Q6. In addition, a grounded smoothing capacitor CO is provided between the choke coil CC and the auxiliary battery BL.

[0036] The above is the structure of the power conversion device according to the present embodiment. In the above power conversion device, the primary current flowing through the primary winding T1 is adjusted by appropriately adjusting the turns ratio of the primary winding T1 and the secondary winding T2 and controlling the on / off states of the first to fourth transistors Q1 to Q4, the high voltage of the high-voltage battery BH is reduced to a desired voltage, and the reduced voltage is applied to the auxiliary battery BL.

[0037] Next, with reference to Figure 2 、 Figure 3A and Figure 3B the structure of the semiconductor module constituting the power conversion device will be described.Figure 2 The printed circuit board 100 in Figure 3A and Figure 3B corresponds to a cross-sectional view taken along line II-II in

[0038] The semiconductor module of this embodiment is configured by mounting each part of a power conversion device such as first to fourth transistors Q1 to Q4, first to fourth Y capacitors Y1 to Y4, etc. on the printed circuit board 100. The semiconductor module is configured by fixing the printed circuit board 100 to the housing 200.

[0039] Hereinafter, the arrangement relationship of the first to fourth semiconductor packages 11 to 14 including the first to fourth transistors Q1 to Q4 and the first to fourth Y capacitors Y1 to Y4 will be mainly described. The main transformer T and the components on the secondary side of the power conversion device are appropriately formed and arranged on a cross-section different from the Figure 2 shown cross-section. Further, in the semiconductor module according to this embodiment, as Figure 2 shown, a cooling member 300 for improving heat dissipation is provided on the side of the housing 200 opposite to the printed circuit board 100. The cooling member 300 is configured, for example, by flowing cooling water or the like through a pipe.

[0040] First, the structure of the first semiconductor package 11 including the first transistor Q1 of this embodiment will be described with reference to Figure 4A and 4B The structures of the second to fourth semiconductor packages 12 to 14 including the second to fourth transistors Q2 to Q4 are the same as the structure of the first semiconductor package 11. Figure 4A corresponds to a cross-sectional view taken along line IVA-IVA in Figure 4B

[0041] The first semiconductor package 11 is configured to include an insulating heat dissipation substrate 20, a semiconductor chip 30, a sealing member 40, pads 61 to 63, etc.

[0042] The insulating heat dissipation substrate 20 is made of silicon nitride (SiN), aluminum nitride (AlN), etc., and has a plate shape with a front surface 20a and a rear surface 20b opposite to the front surface 20a. The insulating heat dissipation substrate 20 is formed with connection wirings 21 made of copper or the like on the front surface 20a. The thickness of the connection wirings 21 is about 10 μm to 100 μm.

[0043] In this embodiment, the semiconductor chip 30 is configured by using a semiconductor substrate 33 in which a semiconductor layer 32 containing gallium nitride is laminated on a silicon substrate 31 made of silicon. In other words, the semiconductor chip 30 is configured by using a so-called gallium nitride on silicon semiconductor substrate 33. The semiconductor chip 30 has the semiconductor layer 32 on the front surface 20a and the silicon substrate 31 on the rear surface 20b.​

[0044] The semiconductor layer 32 containing gallium nitride in this embodiment is formed by laminating epitaxial layers such as a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer. In this embodiment, a two-dimensional electron gas (i.e., 2DEG) is provided at the interface between the gallium nitride layer and the aluminum gallium nitride layer.

[0045] Although not particularly shown, a drain, a source, and a gate in the first transistor Q1 are formed on the front surface 30a of the semiconductor chip 30. The semiconductor chip 30 of this embodiment forms a high electron mobility transistor as the first transistor Q1, in which the two-dimensional electron gas is used to transfer current between the drain and the source. That is, the semiconductor chip 30 forms a horizontal transistor as the first transistor Q1, in which current flows in the plane direction of the semiconductor substrate 33.

[0046] In addition, a back surface electrode 34 is formed on the back surface 30b of the semiconductor chip 30. As will be described in detail later, the back surface electrode 34 is electrically connected to the source of the first transistor Q1. As a result, the semiconductor chip 30 of this embodiment is designed to suppress current collapse.

[0047] The above is the structure of the semiconductor chip 30 of this embodiment. The semiconductor chip 30 is disposed above the connection wiring 21 formed on the insulating heat dissipation substrate 20, and the back surface electrode 34 faces the insulating heat dissipation substrate 20 via the bonding member 50. At this time, the semiconductor chip 30 is disposed in a state of being insulated from the back surface 20b of the insulating heat dissipation substrate 20. The bonding member 50 is formed of a conductive member such as a sintered body containing silver tin alloy (AgSn) as a main component. Therefore, the back surface electrode 34 is electrically connected to the connection wiring 21 via the bonding member 50. The connection wiring 21 is formed to protrude from the semiconductor chip 30 when viewed from the normal direction of the front surface 20a of the insulating heat dissipation substrate 20 in a state where the semiconductor chip 30 is provided.

[0048] The sealing member 40 is disposed on the insulating heat dissipation substrate 20 so as to seal the semiconductor chip 30 while being bonded to the insulating heat dissipation substrate 20. However, the sealing member 40 is disposed on the insulating heat dissipation substrate 20 so as to expose the back surface 20b of the insulating heat dissipation substrate 20. The sealing member 40 of this embodiment has a side surface sealing member 41 that seals the side surface of the semiconductor chip 30 and a front surface sealing member 42 that seals the front surface of the semiconductor chip 30. Each of the side surface sealing member 41 and the front surface sealing member 42 is formed of a resin member such as a liquid crystal polymer and an epoxy resin.

[0049] On the sealing member 40, a drain pad 61, a source pad 62, and a gate pad 63 are formed. In the present embodiment, when viewed from the normal direction of the front surface 20a of the insulating heat dissipation substrate 20, the first semiconductor package 11 has a substantially rectangular shape with two sets of opposite first sides 11a to fourth sides 11d. When viewed from the normal direction of the front surface 20a of the insulating heat dissipation substrate 20, the drain pad 61, the source pad 62, and the gate pad 63 are arranged as follows.

[0050] That is, the drain pad 61 has a planar rectangular shape extending in the direction from the second side 11b toward the fourth side 11d and is disposed close to the first side 11a. The source pad 62 has a planar rectangular shape extending in the direction from the second side 11b toward the fourth side 11d and is disposed close to the third side 11c. The source pad 62 of the present embodiment is configured to have a protruding portion 62a protruding toward the center of the third side 11c from a part of the planar rectangular shape.

[0051] In the present embodiment, the gate pad 63 has a first gate pad 63a and a second gate pad 63b. The first gate pad 63a is disposed at the corner connecting the second side 11b and the third side 11c, and the second gate pad 63b is disposed at the corner connecting the third side 11c and the fourth side 11d. More specifically, the first gate pad 63a and the second gate pad 63b are arranged to sandwich the protruding portion 62a of the source pad 62 therebetween. In Figure 4B , the protective film 70, which will be described later, is omitted. Further, in the present embodiment, the drain pad 61 and the source pad 62 correspond to the first pad and the second pad, respectively.

[0052] The sealing member 40 has a first through hole 43 that penetrates the side sealing member 41 and the front surface sealing member 42 along the side surface of the semiconductor chip 30 to expose the connection wiring 21. In the first through hole 43, a first through electrode 44 that electrically connects the connection wiring 21 and the source pad 62 is provided.

[0053] The front surface sealing member 42 has a second through hole 45 for exposing the source. In the second through hole 45, a second through electrode 46 that electrically connects the source and the source pad 62 is provided. As a result, in the first semiconductor package 11, the source is electrically connected to the back surface electrode 34 via the second through electrode 46, the source pad 62, and the first through electrode 44.

[0054] Although not particularly shown, in a cross section different from the cross section in Figure 4A the front surface sealing member 42 has a through hole for exposing the drain. In the through hole, a through electrode that electrically connects the drain and the drain pad 61 is provided. Similarly, although not particularly shown, in a cross section different from the cross section in Figure 4AAmong the cross-sections with different cross-sections, the front surface sealing member 42 has a through-hole for exposing the gate. In the through-hole, a through electrode that electrically connects the gate and the gate pad 63 is provided. In the present embodiment, as described above, the first gate pad 63a and the second gate pad 63b are formed as the gate pad 63. Both the first gate pad 63a and the second gate pad 63b are electrically connected to the gate electrode through the through-hole.

[0055] In addition, on the front surface 30a of the first semiconductor package 11, a protective film 70 is provided, and the protective film 70 has contact holes 70a for exposing predetermined portions of the drain pad 61, the source pad 62, and the gate pad 63.

[0056] The above is the structure of the first semiconductor package 11 of the present embodiment. The second to fourth semiconductor packages 11 to 14 have the same structure as the first semiconductor package 11 described above. When the first to fourth semiconductor packages 11 to 14 are provided on the printed circuit board 100, in the gate pad 63, either the first gate pad 63a or the second gate pad 63b must be connected to the wiring of the printed circuit board 100. Therefore, the first to fourth semiconductor packages 11 to 14 can have the same structure, and the degree of freedom in wiring with the printed circuit board 100 can be improved.

[0057] As Figure 2 shown, the printed circuit board 100 has a front surface 100a and a rear surface 100b opposite to the front surface 100a. In the printed circuit board 100, a front surface wiring 111 is formed on the front surface 100a, and a rear surface wiring 112 is formed on the rear surface 100b. Although not particularly shown, the printed circuit board 100 has an inner layer wiring formed in the inner layer. The printed circuit board 100 has a via electrode 113 at a predetermined position to electrically connect the front surface wiring 111, the rear surface wiring 112, and the inner layer wiring.

[0058] In the printed circuit board 100 of the present embodiment, as Figure 2 and Figure 3A shown, as the surface wiring 111, a front surface ground wiring G1, a front surface first main wiring P1, and a front surface second main wiring N1 are formed as the front surface wiring 111. Specifically, the front surface ground wiring G1 is provided along one direction in the plane direction of the printed circuit board 100. The front surface first main wiring P1 and the front surface second main wiring N1 are provided along the extending direction of the front surface ground wiring G1 and are arranged to sandwich the front surface ground wiring G1 therebetween. The front surface first main wiring P1 of the present embodiment is bent at one end in the extending direction. Similarly, the front surface second main wiring N1 of the present embodiment is bent at one end in the extending direction, and the bent portion extends to a portion facing the bent portion of the front surface first main wiring P1.

[0059] In addition, the printed circuit board 100 has insertion holes 114 that penetrate the printed circuit board 100. In the insertion holes 114, fastening members 120 for fastening the printed circuit board 100 to the housing 200 are inserted. Specifically, the insertion holes 114 are formed to penetrate the front surface ground wiring G1. Although not particularly shown, a metal film is provided on the wall surface of the insertion holes 114. In Figure 3A etc., the fastening members 120 are omitted.

[0060] As Figure 2 and Figure 3B shown, on the rear surface 100b of the printed circuit board 100, a rear surface first main wiring P2, a rear surface second main wiring N2, a first electrode wiring E1, a second electrode wiring E2, first to fourth gate connection wirings M1 to M4, and first to fourth source connection wirings S1 to S4 are formed as rear surface wirings 112. In addition, on the rear surface 100b of the printed circuit board 100, a rear surface ground wiring G2 is formed around the insertion holes 114 as the rear surface wirings 112. The front surface ground wiring G1 and the rear surface ground wiring G2 are electrically connected via the fastening members 120 provided in the insertion holes 114 and the metal film formed in the insertion holes 114. As a result, a ground wiring G is constructed.

[0061] The rear surface first main wiring P2 is formed at a position facing the front surface first main wiring P1. The printed circuit board 100 has a via electrode 113 that electrically connects the front surface first main wiring P1 and the rear surface first main wiring P2. As a result, a first main wiring P is constructed.

[0062] The rear surface second main wiring N2 is formed at a position facing the front surface second main wiring N1. The printed circuit board 100 has a via electrode 113 that electrically connects the front surface second main wiring N1 and the rear surface second main wiring N2. As a result, a second main wiring N is constructed.

[0063] The first electrode wiring E1 is provided between the rear surface first main wiring P2 and the rear surface second main wiring N2. The second electrode wiring E2 is provided between the rear surface first main wiring P2 and the rear surface second main wiring N2 and is provided to be opposite to the first electrode wiring E1, with the insertion hole 114 therebetween. That is, the first electrode wiring E1 and the second electrode wiring E2 are provided with the insertion hole 114 sandwiched therebetween.

[0064] The first to fourth semiconductor packages 11 to 14 are provided to the rear surface 100b of the printed circuit board 100 via a conductive member such as solder. Figure 3B The pads 61, 62, 63a, and 63b in the first to fourth semiconductor packages 11 to 14 in

[0065] Specifically, the first semiconductor package 11 (i.e., the first transistor Q1) is arranged such that the source pad 62 is connected to the first electrode wiring E1, and the drain pad 61 is connected to the first main wiring P2 on the back surface. The second semiconductor package 12 (i.e., the second transistor Q2) is constructed such that the source pad 62 is connected to the second electrode wiring E2, and the drain pad 61 is connected to the first main wiring P2 on the back surface. The third semiconductor package 13 (the third transistor Q3) is constructed such that the source pad 62 is connected to the second main wiring N2 on the back surface, and the drain pad 61 is connected to the first electrode wiring E1. The fourth semiconductor package 14 (i.e., the fourth transistor Q4) is arranged such that the source pad 62 is connected to the second main wiring N2 on the back surface and the drain pad 61 is connected to the second electrode wiring E2.

[0066] In addition, on the printed circuit board 100, the first output wiring L1 is formed to be connected to the first electrode wiring E1, and the second output wiring L2 is formed to be connected to the second electrode wiring E2. In this embodiment, the first output wiring L1 is formed by the inner layer wiring of the printed circuit board 100 and is electrically connected to the first electrode wiring E1 via the via electrode formed inside the printed circuit board 100. Similarly, the second output wiring L2 is formed by the inner layer wiring of the printed circuit board 100 and is electrically connected to the second electrode wiring E2 via the via electrode formed inside the printed circuit board 100.

[0067] Furthermore, the first output wiring L1 is led out from a portion of the first electrode wiring E1 near the insertion hole 114 when viewed from the normal direction (hereinafter, also simply referred to as the normal direction) with respect to one surface 100a of the printed circuit board 100. The second output wiring L2 is led out from a portion of the second electrode wiring E2 near the insertion hole 114 when viewed from the normal direction.

[0068] The first to fourth gate connection wirings M1 to M4 are arranged to be connected to the gate pads 63 of the corresponding semiconductor packages 11 to 14. Specifically, each of the first and third semiconductor packages 11 and 13 is arranged such that the second gate pad 63b is arranged near the insertion hole 114, and the first gate pad 63a is arranged opposite to the insertion hole 114. In addition, each of the second and fourth semiconductor packages 12 and 14 is arranged such that the first gate pad 63a is arranged near the insertion hole 114, and the second gate pad 63b is arranged opposite to the insertion hole 114.

[0069] The first and third gate connection wirings M1 and M3 are led out to extend in a direction opposite to the insertion hole 114, and the first electrode wiring E1 is interposed therebetween. That is, when viewed from the normal direction, the first and third gate connection wirings M1 and M3 are led out in a direction opposite to the first output wiring L1. In addition, the second and fourth gate connection wirings M2 and M4 are led out to extend in a direction opposite to the insertion hole 114, and the second electrode wiring E2 is interposed therebetween. That is, when viewed from the normal direction, the second and fourth gate connection wirings M2 and M4 are led out in a direction opposite to the second output wiring L2.

[0070] In this embodiment, since the two gate pads 63a and 63b are arranged as described above, when viewed from the normal direction, the gate connection wirings M1 to M4 can be easily led out in a direction opposite to the insertion hole 114 and the first and second output wirings L1 and L2. Therefore, the degree of freedom of wiring on the printed circuit board 100 can be improved.

[0071] The first source connection wiring S1 is led out from the first electrode wiring E1 to extend in a direction opposite to the insertion hole 114. The third source connection wiring S3 is led out from the second main wiring N2 on the rear surface, thus extending in a direction opposite to the insertion hole 114. The second source connection wiring S2 is led out from the second electrode wiring E2 to extend in a direction opposite to the insertion hole 114. The fourth source connection wiring S4 is led out from the second main wiring N2 on the rear surface to extend in a direction opposite to the insertion hole 114

[0072] In addition, in this embodiment, the first to fourth gate connection wirings M1 to M4 and the first to fourth source connection wirings S1 to S4 are arranged to be orthogonal to the first main wiring P1 on the front surface or the second main wiring N2 on the rear surface at the portions overlapping in the normal direction. In this embodiment, the first and third gate connection wirings M1 and M3 and the first and third source connection wirings S1 and S3 overlap with the second main wiring N1 on the front surface in the normal direction. Therefore, the first and third gate connection wirings M1 and M3 and the first and third source connection wirings S1 and S3 are arranged to be orthogonal to the second main wiring N1 on the front surface in the normal direction.

[0073] As Figure 2 and Figure 3AAs shown, first to fourth Y capacitors Y1 to Y4 are provided on the front surface 100a of the printed circuit board 100. Specifically, the first Y capacitor Y1 includes three Y capacitors provided at positions facing the first semiconductor package 11 to connect the front surface ground wiring G1 and the front surface first main wiring P1. The second Y capacitor Y2 includes three Y capacitors provided at positions facing the second semiconductor package 12 to connect the front surface ground wiring G1 and the front surface first main wiring P1. The third Y capacitor Y3 includes three Y capacitors provided at positions facing the third semiconductor package 13 to connect the front surface ground wiring G1 and the front surface second main wiring N1. The fourth Y capacitor Y4 includes three Y capacitors provided at positions facing the fourth semiconductor package 14 to connect the front surface ground wiring G1 and the front surface second main wiring N1.

[0074] The first to fourth semiconductor packages 11 to 14 and the first to fourth Y capacitors Y1 to Y4 are arranged such that the directions of the currents flowing through the first to fourth semiconductor packages 11 to 14 are respectively opposite to the directions of the currents flowing through the first to fourth Y capacitors, as Figure 2 indicated by the arrows A and B in. In other words, in the printed circuit board 100, the front surface wiring 111, the back surface wiring 112, and the via electrode 113 are configured such that the directions of the currents flowing through the first to fourth semiconductor packages 11 to 14 are respectively opposite to the directions of the currents flowing through the first to fourth Y capacitors, which respectively face the first to fourth semiconductor packages 11 to 14.

[0075] For example, the first to fourth Y capacitors Y1 to Y4 are formed of chip capacitors such as ceramic capacitors. In addition, in the present embodiment, each of the first to fourth Y capacitors Y1 to Y4 includes three Y capacitors provided in parallel with each other.

[0076] In the present embodiment, an input capacitor IC is provided on the front surface 100a of the printed circuit board 100 to connect the front surface first main wiring P1 and the front surface second main wiring N1. In addition, the input capacitor IC is provided on the back surface 100b of the printed circuit board 100 to connect the back surface first main wiring P2 and the back surface second main wiring N2.

[0077] The printed circuit board 100 on which the first to fourth semiconductor packages 11 to 14 and the first to fourth Y capacitors Y1 to Y4 are provided in this manner is fixed to the housing 200 as follows. By inserting a fastening member 120 such as a screw into the insertion hole 114 and fastening the fastening member 120 to the housing 200, the printed circuit board 100 is fixed to the housing 200. Accordingly, the front surface ground wiring G1 and the back surface ground wiring G2 are electrically connected to the housing 200 and become the ground potential.

[0078] More specifically, the printed circuit board 100 is fixed to the housing 200 with the rear surface 100b facing the housing 200. In addition, the printed circuit board 100 is fixed to the housing 200 in such a manner that the rear surface 20b of the insulating heat dissipation substrate 20 in the first to fourth semiconductor packages 11 to 14 is joined to the housing 200 via the heat dissipation member 130. As a result, the heat of the first to fourth semiconductor packages 11 to 14 can be effectively dissipated to the housing 200. As the heat dissipation member 130, a grease or the like with a high thermal conductivity can be used. The housing 200 is provided with a protrusion 201 that protrudes in the normal direction with respect to the plane direction of the housing 200. Then, the printed circuit board 100 is fixed to the housing 200 in such a manner that the rear surface ground wiring G2 contacts (i.e., is electrically connected to) the protrusion 201.

[0079] The above is the structure of the semiconductor module of the power conversion device constituting this embodiment. The main transformer T, components on the secondary side, etc. are composed of wirings formed with cross-sections different from the cross-section shown on the printed circuit board 100, or are composed of external components, etc. Figure 2 The above is the structure of the semiconductor module of the power conversion device constituting this embodiment. The main transformer T, components on the secondary side, etc. are composed of wirings formed with cross-sections different from the cross-section shown on the printed circuit board 100, or are composed of external components, etc.

[0080] When constructing a power conversion device using the above semiconductor module, the primary current flowing through the primary winding T1 is adjusted by turning on and off the first to fourth transistors Q1 to Q4. In this embodiment, the first to fourth Y capacitors Y1 to Y4 are provided to be connected to the first to fourth transistors Q1 to Q4 and the ground. Therefore, the influence of common-mode noise can be reduced.

[0081] In addition, the first to fourth Y capacitors Y1 to Y4 and the first to fourth semiconductor packages 11 to 14 (i.e., the first to fourth transistors Q1 to Q4) are arranged to face each other, and the printed circuit board 100 is inserted between them. The first to fourth semiconductor packages 11 to 14 and the first to fourth Y capacitors Y1 to Y4 are arranged such that the directions of the currents flowing through the first to fourth semiconductor packages 11 to 14 are respectively opposite to the directions of the currents flowing through the first to fourth Y capacitors. Therefore, the magnetic fields generated by the flowing currents can cancel each other out between the first to fourth semiconductor packages 11 to 14 and the Y capacitors Y1 to Y4 facing each other, reduce the switching surge by reducing the parasitic inductance, and suppress the generation of noise.

[0082] According to the above embodiment of the present invention, the first to fourth Y capacitors Y1 to Y4 are provided between the first to fourth transistors Q1 to Q4 and the ground. Therefore, the influence of common-mode noise can be reduced.

[0083] In addition, in the present embodiment, the first to fourth Y capacitors Y1 to Y4 and the first to fourth semiconductor packages 11 to 14 (i.e., the first to fourth transistors Q1 to Q4) are arranged to face each other, and the printed circuit board 100 is inserted therebetween. The first to fourth semiconductor packages 11 to 14 and the first to fourth Y capacitors Y1 to Y4 are arranged such that the directions of the currents flowing through the first to fourth semiconductor packages 11 to 14 are opposite to the directions of the currents flowing through the first to fourth Y capacitors, respectively. Therefore, the magnetic fields generated by the flowing currents can cancel each other out between the first to fourth semiconductor packages 11 to 14 and the Y capacitors Y1 to Y4 facing each other, reducing the switching surge by reducing the parasitic inductance and suppressing the generation of noise.

[0084] In addition, in the present embodiment, the printed circuit board 100 is fixed to the housing 200 in such a manner that the first to fourth semiconductor packages 11 to 14 are thermally connected to the housing 200. Therefore, the heat of the first to fourth semiconductor packages 11 to 14 can be effectively dissipated to the housing 200.

[0085] In the present embodiment, in the first to fourth semiconductor packages 11 to 14, the semiconductor chip 30 and the pads 61 to 63 are electrically connected via the second through electrode 46. Therefore, for example, compared with the case where the semiconductor chip 30 and the pads 61 to 63 are connected via bonding wires or the like, the length of the connection portion can be shortened, and the parasitic inductance can be reduced.

[0086] In the present embodiment, the semiconductor chip 30 is configured by forming a lateral switching element that allows current to flow in the planar direction. Therefore, in the first to fourth semiconductor packages 11 to 14, the current flows in the planar direction, and the magnetic fields generated by the currents flowing through the first to fourth semiconductor packages 11 to 14 and the magnetic fields generated by the currents flowing through the first to fourth Y capacitors Y1 to Y4 are easily canceled out.

[0087] In the present embodiment, the semiconductor chip 30 is configured using a semiconductor substrate 33 in which a semiconductor layer 32 containing gallium nitride is laminated on a silicon substrate 31. Therefore, a switching element capable of high-speed operation can be configured. In addition, since the semiconductor layer 32 containing gallium nitride is laminated on the silicon substrate 31, mass production is easier and the cost is reduced compared with the case where the semiconductor substrate 33 is composed only of the semiconductor layer 32 containing gallium nitride.

[0088] In the present embodiment, each of the first to fourth semiconductor packages 11 to 14 has a structure in which a semiconductor chip 30 is disposed on the front surface 20a of an insulating heat dissipation substrate 20 and the semiconductor chip 30 is insulated from the rear surface of the insulating heat dissipation substrate 20. Then, in each of the first to fourth semiconductor packages 11 to 14, the rear surface 20b of the insulating heat dissipation substrate 20 is connected to the housing 200 via a heat dissipation member 130. Therefore, even if the heat dissipation member 130 is thinned, insulation between the housing 200 and the semiconductor chip 30 or the like can be ensured. In addition, since the semiconductor chip 30 is insulated from the rear surface 20b of the insulating heat dissipation substrate 20, the heat dissipation member 130 can be formed of a conductive member or the like, for example, and material selectivity can be improved.

[0089] In the present embodiment, the heat dissipation member 130 is disposed between the first to fourth semiconductor packages 11 to 14 and the housing 200. Therefore, the heat of the first to fourth semiconductor packages 11 to 14 can be effectively dissipated to the housing 200.

[0090] In the present embodiment, each of the first to fourth Y capacitors Y1 includes a plurality of capacitors connected in parallel. Therefore, the loss caused by the equivalent series resistance (i.e., ESR) can be reduced.

[0091] In the present embodiment, the first and third gate connection wirings M1, M3 are led out in a direction opposite to the first output wiring L1 when viewed from the normal direction. When viewed from the normal direction, the second and fourth gate connection wirings M2 and M4 are led out in a direction opposite to the second output wiring L2. Therefore, interference between the gate connection wirings M1 to M4 and the output wirings L1, L2 can be suppressed, and the transistors Q1 to Q4 can be prevented from malfunctioning due to noise superimposed on each gate voltage. In addition, the first to fourth gate connection wirings M1 to M4 are arranged to be orthogonal to the front surface first main wiring P1 or the rear surface second main wiring N2 at a portion where the first to fourth gate connection wirings M1 to M4 overlap the front surface first main wiring P1 or the rear surface second main wiring N2 in the normal direction. Therefore, interference between the gate connection wirings M1 to M4 and the front surface main wirings P1, N1 can be suppressed, and malfunction of the transistors Q1 to Q4 caused by noise superimposed on each gate voltage can be suppressed.

[0092] In the present embodiment, the ground wiring G is electrically connected to the housing 200 via a fastening member 120. Therefore, the ground wiring G can be electrically connected to the housing 200 while the printed circuit board 100 is fixed to the housing 200, and the size is reduced as compared with the case where the fastening member 120 is provided in a portion different from the ground wiring G.

[0093] (Second Embodiment)

[0094] The second embodiment will be described below. The difference between this embodiment and the first embodiment lies in that the resonance frequencies of the input capacitor IC and the first to fourth Y capacitors Y1 - Y4 are defined. Other configurations are the same as those of the first embodiment, and thus the description of the same configurations will be omitted below.

[0095] First, in the power conversion device as described above, the primary current flowing through the main wiring P is controlled by the conduction and cutoff of the first to fourth transistors Q1 to Q4. For example, when the primary current is generated as Figure 5A shown, among the first to fourth transistors Q1 to Q4, at time point T1, the first and fourth transistors Q1 and Q4 are conducting, and the second and third transistors are cutoff. At time point T2, the second transistor Q2 is conducting, and the fourth transistor Q4 is cutoff. At time point T3, the first transistor Q1 is cutoff, and the third transistor Q3 is conducting. At time point T4, the fourth transistor Q4 is conducting, and the second transistor Q2 is cutoff. Then, after time point T5, the on / off states of the first to fourth transistors Q1 to Q4 are controlled as in the time points from T1 to T4.

[0096] In this case, if the resonance frequencies of the input capacitor IC and the first to fourth Y capacitors Y1 to Y4 (hereinafter, also simply referred to as resonance frequencies) are not particularly defined, the noise may increase due to the increase in the resonance current. Here, the period from the conduction of the first transistor Q1 to Q4 to their next conduction is defined as the switching period. In this embodiment, for example, the period from time point T1 to time point T5 is the switching period. The switching frequency is represented by the reciprocal of the switching period.

[0097] In this case, as Figure 5B shown, when the resonance frequency is an even multiple of the switching frequency, a new resonance current is generated each time the primary current rises. Then, when the resonance current before the addition of the new resonance current is defined as the previous resonance current, and the sum of the previous resonance current and the new resonance current is defined as the total resonance current, since the resonance current is added to the new resonance current each time the primary current rises, the total resonance current gradually increases. In Figure 5B it, the total resonance current is represented by a solid line, the new resonance current is represented by a dashed line, and the previous resonance current is represented by a dashed line with alternating long and short segments, which is the same as that described later in Figure 5C the same.

[0098] On the other hand, as Figure 5C shown, even when the resonance frequency is an odd multiple of the switching frequency, a new resonance current is generated each time the primary current rises. However, in this case, the period in which the new resonance current is added to the previous resonance current alternates with the period in which the previous resonance current and the new resonance current cancel each other out. Therefore, when the resonance frequency is an odd multiple of the switching frequency, the total resonance current is less likely to increase.

[0099] Therefore, in this embodiment, the capacitances of the first to fourth Y capacitors Y1 to Y4 are adjusted such that the resonance frequency is an odd multiple of the switching frequency.

[0100] According to the above embodiment of the present invention, the first to fourth Y capacitors Y1 to Y4 are arranged to face the first to fourth transistors Q1 to Q4 respectively, and the printed circuit board 100 is disposed therebetween. The first to fourth semiconductor packages 11 to 14 and the first to fourth Y capacitors Y1 to Y4 are arranged such that the directions of the currents flowing through the first to fourth semiconductor packages 11 to 14 are opposite to the directions of the currents flowing through the first to fourth Y capacitors respectively. Therefore, the same effect as that of the first embodiment can be obtained.

[0101] In addition, in this embodiment, the resonance frequencies of the input capacitor IC and the first to fourth Y capacitors Y1 to Y4 are odd multiples of the switching frequencies of the first to fourth transistors Q1 to Q4. Therefore, an increase in the resonance current can be suppressed, and an increase in the noise generated due to the resonance current being superimposed on the primary current can be suppressed.

[0102] (Third Embodiment)

[0103] The third embodiment will be described below. The difference between this embodiment and the first embodiment is that the lengths of the wirings 111 and 112 formed on the printed circuit board 100 are defined. Other configurations are the same as those of the first embodiment, and thus the description of the same configurations will be omitted hereinafter.

[0104] First, in the power conversion device as described above, as Figure 6 shown, a parasitic capacitance Cp is formed between the first output wiring L1 and the ground, and the first common-mode current I1 and the second common-mode current I2 flow through the parasitic capacitance Cp. Specifically, the first common-mode current I1 flows through the first transistor Q1 and the first Y capacitor Y1 provided between the parasitic capacitance Cp and the ground wiring G. The second common-mode current I2 flows through the third transistor Q3 and the third Y capacitor Y3 provided between the parasitic capacitance Cp and the ground wiring G. In this case, if the amplitudes of the first common-mode current I1 and the second common-mode current I2 are different, one of them becomes larger and the common-mode noise becomes larger.

[0105] Therefore, in this embodiment, the front surface wiring 111, the back surface wiring 112, and the via electrode 113 in the printed circuit board 100 are formed such that the sum of the lengths of the wirings 111, 112, and the via electrode 113 through which the first common-mode current I1 flows is equal to the sum of the lengths of the wirings 111, 112, and the via electrode 113 through which the second common-mode current I2 flows.

[0106] In other words, wirings 111, 112 and via electrode 113 electrically connected between the insertion hole 114 of the first output wiring L1 and the surface ground wiring G1 are formed as follows. That is, in wirings 111, 112 that electrically connect the first output wiring L1 and the insertion hole 114 of the front surface ground wiring G1, the sum of the lengths of wirings 111, 112 passing through the back surface first main wiring P2 and the front surface first main wiring P1 is equal to the sum of the lengths of wirings 111 and 112 passing through the back surface second main wiring N2 and the front surface second main wiring N1. That is, the sum of the lengths of wirings 111 and 112 connected to the first semiconductor package 11 and the first Y capacitor Y1 is equal to the sum of the lengths of wirings 111 and 112 connected to the third semiconductor package 13 and the third Y capacitor Y3. The via electrode 113 connecting the front surface wiring 111 and the back surface wiring 112 has the same length.

[0107] Here, the sum of the lengths of wirings 111 and 112 through which the first common-mode current I1 flows is the following sum of lengths. That is, the length of wiring 111 through which the first common-mode current I1 flows includes the length between the insertion hole 114 and the portion connected to the first Y capacitor Y1 in the front surface ground wiring G1. However, in this embodiment, the first Y capacitor Y1 includes three Y capacitors. Therefore, the length between the insertion hole 114 and the portion connected to the first Y capacitor Y1 in the front surface ground wiring G1 is the average length. The length of wiring 111 through which the first common-mode current I1 flows includes the length between the portion connected to the first Y capacitor Y1 and the portion connected to the via electrode 113 in the front surface first main wiring P1. In addition, the length of wiring 112 through which the first common-mode current I1 flows includes the length between the portion connected to the first semiconductor package 11 and the portion connected to the via electrode 113 in the back surface first main wiring P2. The length of wiring 112 through which the first common-mode current I1 flows includes the length between the portion connected to the first semiconductor package 11 and the first output wiring L1 in the first electrode wiring E1. The total sum of the lengths of wirings 111 and 112 through which the first common-mode current I1 flows is the sum of these lengths.

[0108] Similarly, the sum of the lengths of wirings 111 and 112 through which the second common-mode current I2 flows is the following sum of lengths. That is, the length of wiring 111 through which the second common-mode current I2 flows includes the length between the insertion hole 114 in the front-surface ground wiring G1 and the portion connected to the third Y capacitor Y3. However, in the present embodiment, the third Y capacitor Y3 includes three Y capacitors. Therefore, the length between the insertion hole 114 in the front-surface ground wiring G1 and the portion connected to the third Y capacitor Y3 is the average length. The length of wiring 111 through which the second common-mode current I2 flows includes the length between the portion connected to the third Y capacitor Y3 and the portion connected to the via electrode 113 in the front-surface second main wiring N1. In addition, the length of wiring 112 through which the second common-mode current I2 flows includes the length between the portion connected to the third semiconductor package 13 and the portion connected to the via electrode 113 in the back-surface second main wiring N2. The length of wiring 112 through which the second common-mode current I2 flows includes the length between the portion connected to the third semiconductor package 13 and the first output wiring L1 in the first electrode wiring E1. The sum of the lengths of wirings 111 and 112 through which the first common-mode current I2 flows is the sum of these lengths.

[0109] Although Figure 6 only the parasitic capacitance Cp between the first output wiring L1 and the ground is shown, actually, a parasitic capacitance Cp is also formed between the second output wiring L2 and the ground. Then, between the parasitic capacitance Cp and the ground wiring G, a common-mode current flows through the second transistor Q2 and the second Y capacitor Y2, and a common-mode current flows through the fourth transistor Q4 and the fourth Y capacitor Y4.

[0110] Therefore, although not particularly shown, the front-surface wiring 111, the back-surface wiring 112, and the via electrode 113 of the printed circuit board 100 are formed as follows in the portion where the second output wiring L2 is electrically connected to the via 114 in the front-surface ground wiring G1. That is, the sum of the lengths of wirings 111 and 112 and the via electrode 113 connected to the second semiconductor package 12 and the second Y capacitor Y2 is equal to the sum of the lengths of wirings 111 and 112 and the via electrode 113 connected to the fourth semiconductor package 14 and the fourth Y capacitor Y4.

[0111] According to the present embodiment described above, the first to fourth Y capacitors Y1 to Y4 are arranged to face the first to fourth transistors Q1 to Q4 respectively, and the printed circuit board 100 is placed therebetween. The first to fourth semiconductor packages 11 to 14 and the first to fourth Y capacitors Y1 to Y4 are arranged such that the directions of the currents flowing through the first to fourth semiconductor packages 11 to 14 are respectively opposite to the directions of the currents flowing through the first to fourth Y capacitors. Therefore, the same effect as in the first embodiment can be obtained.

[0112] In addition, in the present embodiment, wirings 111, 112 and via electrode 113 that electrically connect the insertion holes 114 of the first output wiring L1 and the front surface ground wiring G1 are formed as follows. That is, the sum of the lengths of the wirings 111 and 112 and the via electrode 113 connected to the first semiconductor package 11 and the first Y capacitor Y1 is equal to the sum of the lengths of the wirings 111 and 112 and the via electrode 113 connected to the third semiconductor package 13 and the third Y capacitor Y3. In addition, the sum of the lengths of the wirings 111 and 112 and the via electrode 113 connected to the second semiconductor package 12 and the second Y capacitor Y2 is equal to the sum of the lengths of the wirings 111 and 112 and the via electrode 113 connected to the fourth semiconductor package 14 and the fourth Y capacitor Y4. Therefore, the common-mode current flows uniformly, the increase of the common-mode current can be suppressed, and the effect of noise suppression can be improved.

[0113] (Fourth Embodiment)

[0114] The fourth embodiment is described below. The difference between this embodiment and the first embodiment lies in the position of the insertion hole. Other configurations are the same as those of the first embodiment, and thus the description of the same configurations will be omitted below.

[0115] In the printed circuit board 100 of the present embodiment, as Figure 7A and 7B shown, when viewed from the normal direction, the insertion hole 114 is located outside the region R that is surrounded by the portion where the first to fourth semiconductor packages 11 to 14 are provided. In the first embodiment and the like, when viewed from the normal direction, the insertion hole 114 is located within the region R surrounded by the first to fourth semiconductor packages 11 to 14.

[0116] In the present embodiment, on the front surface 100a of the printed circuit board 100, the insertion hole 114 is positioned opposite to the front surface second main wiring N1, and the front surface first main wiring P1 is disposed therebetween. In addition, the front surface first main wiring P1 is divided into two parts arranged along the extending direction. The front surface ground wiring G1 extends through between the two parts of the front surface first main wiring P1 arranged along the extending direction to the insertion hole 114, and is also formed around the insertion hole 114. The separated parts of the front surface first main wiring P1 are electrically connected via the via electrode 113 and the back surface first main wiring P2.

[0117] Since the insertion hole 114 is located on the back surface 100b of the printed circuit board 100 as described above, the insertion hole 114 is located at a position opposite to the back surface second main wiring N2, and the back surface first main wiring P2 is disposed therebetween.

[0118] In addition, in the present embodiment, compared with the first embodiment, the insertion hole 114 is located outside the region R. Therefore, the first electrode wiring E1 and the second electrode wiring E2 are configured as follows. That is, compared with the first embodiment, the length of the portion of the first electrode wiring E1 connecting the first semiconductor package 11 and the third semiconductor package 13 is shortened. In addition, compared with the first embodiment, the length of the portion of the second electrode wiring E2 connecting the second semiconductor package 12 and the fourth semiconductor package 14 is shortened.

[0119] According to the present embodiment described above, the first to fourth Y capacitors Y1 to Y4 are arranged to face the first to fourth transistors Q1 to Q4 respectively, and the printed circuit board 100 is placed therebetween. The first to fourth semiconductor packages 11 to 14 and the first to fourth Y capacitors Y1 to Y4 are arranged such that the directions of the currents flowing through the first to fourth semiconductor packages 11 to 14 are opposite to the directions of the currents flowing through the first to fourth Y capacitors respectively. Therefore, the same effect as that of the first embodiment can be obtained.

[0120] In addition, in the present embodiment, on the front surface 100a of the printed circuit board 100, the insertion hole 114 is located outside the region R surrounded by the first to fourth semiconductor packages 11 to 14. Therefore, compared with the case where the insertion hole 114 is located inside the region R surrounded by the first to fourth semiconductor packages 11 to 14, the following effects can be obtained. That is, it is possible to easily shorten the length of the portion of the first electrode wiring E1 connecting the first semiconductor package 11 and the third semiconductor package 13, and it is possible to easily shorten the length of the portion of the second electrode wiring E2 connecting the second semiconductor package 12 and the fourth semiconductor package 14. Therefore, it is easy to shorten the length of the wiring connecting the upper arm element and the lower arm element in each leg, and the switching surge can be reduced by reducing the parasitic inductance.

[0121] The present embodiment shows an example in which the insertion hole 114 is configured on the front surface 100a of the printed circuit board 100 to be opposite to the front surface second main wiring N1 with the front surface first main wiring P1 interposed therebetween, but the position of the insertion hole 114 can be appropriately changed. For example, the insertion hole 114 can also be configured to be opposite to the front surface ground wiring G1 with the front surface second main wiring N1 interposed therebetween. In another example, on the rear surface 100b of the printed circuit board 100, the insertion hole 114 can be located at a position opposite to the first and third semiconductor packages 11 and 13, and the second and fourth semiconductor packages 12 and 14 are inserted therebetween. Similarly, on the rear surface 100b of the printed circuit board 100, the insertion hole 114 can be located at a position opposite to the second and fourth semiconductor packages 12 and 14, and the first and third semiconductor packages 11 and 13 are inserted therebetween. In addition, two or more insertion holes 114 can be provided instead of one.

[0122] (Other Embodiments)

[0123] Although the present disclosure has been described according to embodiments, it should be understood that the present disclosure is not limited to such embodiments or configurations. The present disclosure includes various modifications and variations within the equivalent scope. In addition, although various elements are shown in exemplary various combinations and configurations, other combinations and configurations including more, fewer, or only a single element are also within the spirit and scope of the present disclosure.

[0124] In each of the above embodiments, in the first to fourth semiconductor packages 11 to 14, a resin member may be provided between the back surface electrode 34 of the semiconductor chip 30 and the connection wiring 21, and the back surface electrode 34 and the connection wiring 21 may be electrically connected via a through electrode formed in the resin member.

[0125] In each of the above embodiments, the switching element formed on the semiconductor chip 30 can be appropriately changed, and an IGBT (Insulated Gate Bipolar Transistor) element or the like can be formed as the switching element. In addition, the switching element formed on the semiconductor chip 30 may be a vertical switching element in which current flows in the thickness direction of the semiconductor substrate 33.

[0126] In each of the above embodiments, the semiconductor substrate 33 in the semiconductor chip 30 may be composed only of the silicon substrate 31, or may be composed only of the semiconductor layer 32 containing gallium nitride. In addition, the semiconductor substrate 33 may be formed of a silicon carbide substrate, or may be formed of other compound semiconductor substrates.

[0127] In each of the above embodiments, each of the first to fourth Y capacitors Y1 to Y4 may include a plurality of capacitors connected in series. Therefore, even if a part of the capacitors connected in series fails, a short circuit can be suppressed by the other parts of the capacitors, and the durability can be improved.

[0128] In the above embodiments, an example has been described in which the gate pad 63 in each of the first to fourth semiconductor packages 11 to 14 includes a first gate pad 63a and a second gate pad 63b. However, the number of gate pads 63 in each of the first to fourth semiconductor packages 11 to 14 may be only one. In this case, the shape of the wiring on the printed circuit board 100 can be adjusted. The first to fourth semiconductor packages 11 to 14 do not have to have the same configuration, and a part of the first to fourth semiconductor packages 11 to 14 may have a different configuration. For example, a part of the first to fourth semiconductor packages 11 to 14 may have a configuration including a first gate pad 63a and a second gate pad 63b, while another part of the first to fourth semiconductor packages 11 to 14 may have a configuration without the second gate pad 63b.

[0129] In each of the above embodiments, the input capacitor IC may be provided on only one of the front surface 100a and the rear surface 100b of the printed circuit board 100. In another example, the input capacitor IC may be provided in a component different from the printed circuit board 100 and may be provided when constructing a power conversion device by using a semiconductor module.

[0130] In the second embodiment, the first to fourth Y capacitors Y1 to Y4 may be configured such that the resonance frequency with the input capacitor IC is an even multiple of the switching frequency.

[0131] In addition, the above embodiments may be appropriately combined together. For example, the second embodiment may be combined with the third or fourth embodiment to adjust the resonance frequencies of the first to fourth Y capacitors Y1 to Y4. The third embodiment may be combined with the fourth embodiment to adjust the lengths of the wirings 111 and 112. The combinations of each embodiment may be further combined.

Claims

1. A semiconductor module, comprising: a substrate having a front surface, a rear surface opposite to the front surface, front surface wirings provided on the front surface, and rear surface wirings provided on the rear surface; at least one semiconductor package including a semiconductor chip and pads electrically connected to the semiconductor chip, the semiconductor chip including a switching element, the at least one semiconductor package being disposed on the substrate in a state where the pads are connected to the rear surface wirings; a housing to which the substrate is fixed in a state where the at least one semiconductor package is thermally connected to the housing; and at least one Y capacitor, wherein the front surface wirings include a front surface ground wiring electrically connected to the housing and a front surface main wiring connected to the rear surface wirings, the rear surface wirings being connected to the at least one semiconductor package, the at least one Y capacitor is disposed on the front surface of the substrate at a position facing the at least one semiconductor package and between the front surface ground wiring and the front surface main wiring, and the at least one semiconductor package and the at least one Y capacitor are arranged such that the direction of current flowing in the at least one semiconductor package and the direction of current flowing in the at least one Y capacitor are opposite to each other.

2. The semiconductor module according to claim 1, wherein the at least one semiconductor package further includes a through electrode, and the semiconductor chip is electrically connected to the pads via the through electrode.

3. The semiconductor module according to claim 1 or 2, wherein the semiconductor chip is formed of a semiconductor substrate in which a lateral switching element serving as a switching element is formed, the lateral switching element allows current to flow in a plane direction of the semiconductor substrate.

4. The semiconductor module according to claim 3, wherein the semiconductor substrate in the semiconductor chip includes a silicon substrate and a semiconductor layer containing gallium nitride and laminated on the silicon substrate.

5. The semiconductor module according to claim 1 or 2, wherein the semiconductor package further includes an insulating heat dissipation substrate having a front surface and a rear surface opposite to the front surface, the semiconductor chip is disposed on the front surface of the insulating heat dissipation substrate, and the rear surface of the insulating heat dissipation substrate is insulated from the semiconductor chip and connected to the housing.

6. The semiconductor module according to claim 5, wherein the at least one semiconductor package further includes a heat dissipation member disposed between the rear surface of the insulating heat dissipation substrate and the housing.

7. The semiconductor module according to claim 1 or 2, wherein the at least one Y capacitor includes a plurality of chip capacitors connected in parallel or in series.

8. The semiconductor module according to claim 1 or 2, further comprising an input capacitor disposed in parallel with the switching element and the at least one Y capacitor, wherein the at least one Y capacitor is configured such that a resonance frequency with the input capacitor is an odd multiple of a switching frequency of the switching element.

9. The semiconductor module according to claim 1 or 2, wherein The pads in the at least one semiconductor package include a first pad, a second pad, and a gate pad, and a voltage for controlling a current flowing between the first pad and the second pad is applied to the gate pad. The front surface main wiring includes a front surface first main wiring and a front surface second main wiring. The back surface wiring includes a gate connection wiring connected to the gate pad and an electrode wiring connected to the first pad or the second pad. The substrate further includes an output wiring connected to the electrode wiring. When viewed from a normal direction of the front surface of the substrate, the output wiring and the gate connection wiring lead out in opposite directions, and The gate connection wiring overlaps with the front surface first main wiring or the front surface second main wiring in the normal direction of the front surface of the substrate, and is orthogonal to the front surface first main wiring or the front surface second main wiring that overlaps with the gate connection wiring.

10. The semiconductor module according to claim 1 or 2, further comprising a fastening member, wherein the substrate has an insertion hole penetrating the substrate at a portion where the front surface ground wiring is provided, the fastening member is disposed in the insertion hole to fasten the substrate to the housing, and the front surface ground wiring is electrically connected to the housing via the fastening member.

11. The semiconductor module according to claim 10, wherein the front surface main wiring includes a front surface first main wiring and a front surface second main wiring, the back surface wiring includes a back surface first main wiring, a back surface second main wiring, and an electrode wiring, the back surface first main wiring is disposed at a position facing the front surface first main wiring and is electrically connected to the front surface first main wiring, the back surface second main wiring is disposed at a position facing the front surface second main wiring and is electrically connected to the back surface second main wiring, the substrate further includes an output wiring connected to the electrode wiring, the at least one semiconductor package includes a plurality of semiconductor packages, one of the plurality of semiconductor packages is disposed between the back surface first main wiring and the electrode wiring, and a different one of the plurality of semiconductor packages is disposed between the back surface second main wiring and the electrode wiring, the at least one Y capacitor includes a plurality of Y capacitors, one of the plurality of Y capacitors is disposed on the front surface of the substrate at a position facing the one of the plurality of semiconductor packages and between the front surface first main wiring and the front surface ground wiring, and a different one of the plurality of Y capacitors is disposed on the front surface of the substrate at a position facing the different one of the plurality of semiconductor packages and between the front surface second main wiring and the front surface ground wiring, and Among the front surface wiring and the back surface wiring that electrically connect the output wiring and the insertion holes formed in the front surface ground wiring, the sum of the lengths of the back surface first main wiring and the front surface main wiring is equal to the sum of the lengths of the back surface second main wiring and the front surface second main wiring.

12. The semiconductor module according to claim 10, wherein the at least one semiconductor package includes a plurality of semiconductor packages, and when viewed from the normal direction of the front surface with respect to the substrate, the insertion holes are located outside a region surrounded by a plurality of portions where the plurality of semiconductor packages are respectively provided.

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