Chip stacking structure

Abstract

The application discloses a chip stacking structure, which comprises a lead frame, a first switch chip, a conductive clamp and a control chip. The lead frame comprises a chip base and a grounding pin. The first switch chip comprises a first drain electrode, a first source electrode and a first gate electrode. The first source electrode and the first gate electrode are arranged on a first surface of the first switch chip, the first drain electrode is arranged on a second surface of the first switch chip, and the first drain electrode is electrically connected with the chip base. The conductive clamp comprises a lead frame end and a chip end, and the chip end comprises a first surface and a second surface. The first surface is electrically connected with the first source electrode, and the lead frame end is electrically connected with the grounding pin. The control chip comprises a bonding surface, and the bonding surface is electrically connected with and adhered to the second surface or the first source electrode.

Description

Technical Field

[0001] This invention relates to a chip stacking structure, and more particularly to a chip stacking structure that can avoid magnetic field interference. Background Technology

[0002] In existing power converters, inductors and capacitors are typically used in conjunction with switching elements to control power conversion. Metal-oxide-semiconductor (MOSFET) transistors are commonly used as switching elements. Specifically, the switching elements in power converters mostly use MOSFET chips, combined with, but not limited to, chip packages for driving or controlling the MOSFET chips, to form switching elements with specific package structures.

[0003] by Figure 1 Take, for example, an existing switching element package structure. A traditional switching element package structure includes a leadframe 1, a first switching chip 2, and a control chip 4. The first switching chip 2 and the control chip 4 are bonded to the leadframe 1, and the control chip 4 is electrically connected to the terminals of the first switching chip 2 and the leadframe 1 via wire bonding. Because the components are arranged in a flat manner to form the switching element package structure, it occupies a large area in the power converter circuit, failing to effectively improve the overall circuit power density. Furthermore, the high-frequency switching of the first switching chip 2 during operation generates high-frequency noise. However, due to control and detection requirements, the wire bonding between the first switching chip 2 and the control chip 4 cannot isolate them from each other, thus failing to effectively prevent the noise from the first switching chip 2 during operation from interfering with the operation of the control chip 4 through a magnetic field.

[0004] Therefore, how to design a chip stacking structure that can avoid magnetic field interference, so as to prevent the noise of the first switching chip when it is powered on from interfering with the operation of the control chip through the magnetic field, and reduce the area of ​​the switching element package structure on the circuit board, is a major research topic that the creators of this project intend to conduct. Summary of the Invention

[0005] To solve the above problems, the present application provides a chip stacking structure capable of avoiding magnetic field interference to overcome the problems of the prior art. Therefore, the chip stacking structure of the present application comprises a lead frame, a first switch chip, a conductive clip and a control chip. The lead frame comprises a chip base and a grounding pin, and the grounding pin transmits a ground potential. The first switch chip comprises a first drain, a first source and a first gate; the first source and the first gate are arranged on a first surface of the first switch chip, and the first drain is arranged on a second surface of the first switch chip, and the first drain is electrically connected to the chip base. The conductive clip comprises a lead frame end and a chip end, and the chip end comprises a first surface and a second surface opposite to the first surface, the first surface is electrically connected to the first source, and the lead frame end is electrically connected to the grounding pin. The control chip comprises a coupling surface and a contact surface, the coupling surface is coupled to the second surface, and the contact surface comprises a first gate contact, and the first gate contact is electrically connected to the first gate. Wherein, the coupling surface is attached to the second surface.

[0006] In an embodiment, further comprising a first conductive layer, the first conductive layer is electrically connected to the first drain and the chip base, and the first conductive layer is selected from at least one of solder, conductive adhesive and metal tape.

[0007] In an embodiment, further comprising a second conductive layer, the second conductive layer is electrically connected to the first source and the first surface, and the second conductive layer is selected from at least one of solder, conductive adhesive and metal tape.

[0008] In an embodiment, the control chip further comprises an electrical signal contact. The electrical signal contact is arranged on the contact surface, and the electrical signal contact is electrically connected to one of the lead frame, the first switch chip and the conductive clip.

[0009] In an embodiment, the first surface completely covers the first source, and the first gate contact is electrically connected to the first gate through wire bonding.

[0010] In an embodiment, a first surface area of the coupling surface is smaller than a second surface area of the second surface.

[0011] In an embodiment, further comprising a second switch chip. The second switch chip comprises a second drain, a second source and a second gate, the second source and the second gate are arranged on a third surface of the second switch chip, and the second drain is arranged on a fourth surface of the second switch chip; the third surface is attached to the second surface, and the first drain is electrically connected to the second source.

[0012] To solve the above problems, the present application provides a chip stacking structure capable of avoiding magnetic field interference to overcome the problems of the prior art. Therefore, the chip stacking structure of the present application comprises a lead frame, a first switch chip, a conductive clip and a control chip. The lead frame comprises a chip base and a grounding pin, and the grounding pin transmits a ground potential. The first switch chip comprises a first drain, a first source and a first gate; the first source and the first gate are arranged on a first surface of the first switch chip, and the first drain is arranged on a second surface of the first switch chip, and the first drain is electrically connected to the chip base. The conductive clip comprises a lead frame end and a chip end, and the chip end comprises a first surface and a second surface opposite to the first surface, the first surface is electrically connected to the first source, and the lead frame end is electrically connected to the grounding pin, the conductive clip covers part of the first source, and the first source has a source exposed area not covered by the conductive clip. The control chip comprises a bonding surface and a contact surface, the bonding surface is coupled to the second surface, and the contact surface comprises a first gate contact, and the first gate contact is electrically connected to the first gate. Wherein, the bonding surface is attached to the source exposed area.

[0013] In an embodiment, further comprising a first conductive layer, the first conductive layer is electrically connected to the first drain and the chip base, and the first conductive layer is selected from at least one of solder, conductive adhesive and metal tape.

[0014] In an embodiment, further comprising a second conductive layer bonding the first source, the bonding surface of the control chip and the first surface of the conductive clip, the second conductive layer is selected from at least one of solder, conductive adhesive and metal tape, and the second conductive layer can electrically connect the first source and the conductive clip.

[0015] In an embodiment, the control chip further comprises an electrical signal contact. The electrical signal contact is arranged on the contact surface, and the electrical signal contact is electrically connected to one of the lead frame, the first switch chip and the conductive clip.

[0016] In an embodiment, the first surface does not completely cover the first source, and the first gate contact is electrically connected to the first gate by wire bonding.

[0017] In an embodiment, the first surface area of the bonding surface is smaller than the second surface area of the second surface.

[0018] In an embodiment, further comprising a second switch chip. The second switch chip comprises a second drain, a second source and a second gate, the second source and the second gate are arranged on a third surface of the second switch chip, and the second drain is arranged on a fourth surface of the second switch chip; the third surface is attached to the second surface, and the first drain is electrically connected to the second source.

[0019] The main purpose and effect of the present application is that the control chip and the first switch chip are separated by the ground layer, so that the electromagnetic radiation interference is inhibited, and the noise generated when the first switch chip is powered on and operated does not interfere with the operation of the control chip.

[0020] For further understanding of the technology, means and effects taken by the present application to achieve the predetermined purpose, please refer to the following detailed description and drawings of the present application. It is believed that the purpose, features and characteristics of the present application can be understood in depth and specifically from the above, however, the drawings are provided for reference and illustration only, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 The existing switch element packaging structure;

[0022] Figure 2 The side view of the first embodiment of the chip stacking structure of the present application which can avoid magnetic field interference;

[0023] Figure 3 The top view of the first embodiment of the chip stacking structure of the present application which can avoid magnetic field interference;

[0024] Figure 4 The side view of the second embodiment of the chip stacking structure of the present application which can avoid magnetic field interference;

[0025] Figure 5 The side view of the third embodiment of the chip stacking structure of the present application which can avoid magnetic field interference;

[0026] Figure 6 The top view of the third embodiment of the chip stacking structure of the present application which can avoid magnetic field interference; and

[0027] Figure 7 The side view of the fourth embodiment of the chip stacking structure of the present application which can avoid magnetic field interference.

[0028] Among them, the reference signs are:

[0029] 100A, 100B, 100C, 100D… chip packaging

[0030] 1… lead frame

[0031] 10, 10A… chip base

[0032] 12G… ground pin

[0033] 12… pin

[0034] 2… first switch chip

[0035] 22… first drain

[0036] 24 first source

[0037] 24a source-exposed region

[0038] 26 first gate

[0039] 2A first surface

[0040] 2B second surface

[0041] 3, 3' conductive clip

[0042] 32 lead frame end

[0043] 34 chip end

[0044] 342 first surface

[0045] 344 second surface

[0046] 4 control chip

[0047] 45 bonding surface

[0048] 47 contact surface

[0049] 42 contact

[0050] 42a ground contact

[0051] 42b first gate contact

[0052] 42c electrical signal contact

[0053] 42d second gate contact

[0054] 44 wire

[0055] 52 first conductive layer

[0056] 54 second conductive layer

[0057] 56 third conductive layer

[0058] 58 fourth conductive layer

[0059] 6 second switch chip

[0060] 62 second drain

[0061] 64 second source

[0062] 66 second gate

[0063] 6A third surface

[0064] 6B fourth surface

[0065] X length

[0066] Y…width DETAILED DESCRIPTION

[0067] The technical contents and detailed descriptions of the present application are described as follows in combination with the drawings:

[0068] Please refer to Figure 2 The side view of the first embodiment of the chip stacking structure of the present application, please refer to Figure 1 The chip package 100A is mainly a switch element package structure, and the chip package 100 includes a lead frame 1, a first switch chip 2, a copper clip 3, and a control chip 4. The lead frame 1 includes a die paddle 10 and a plurality of lead fingers, the plurality of lead fingers include lead fingers with different functions (such as but not limited to I / O, detection, etc.), and also include a ground lead 12G composed of one or more lead fingers, and the ground lead 12G is used to transmit the ground potential. The first switch chip 2 is a first transistor switch, and includes a first drain 22, a first source 24, and a first gate 26. The first source 24 and the first gate 26 are arranged on a first surface 2A of the first switch chip 2, and the first drain 22 is arranged on a second surface 2B of the first switch chip 2, and the first drain 22 is electrically connected to the die paddle 10. It is worth mentioning that the lead frame 1 can be preferably made of an alloy material, which can form a specific structure through etching, stamping, etc.

[0069] The first switch chip 2 is a conventional transistor chip. The electrode area of the first drain 22 is larger than the electrode areas of the first source 24 and the first gate 26, and the electrode area of the first source 24 is larger than the electrode area of the first gate 26. The processes of forming the source, the drain, and the gate on the wafer surface generally include ion implantation, deposition, oxidation, etching, etc., which are prior art and will not be described here. Since the first switch chip 2 of the present application uses a conventional switch chip (such as but not limited to, the drain is arranged on the first surface of the switch chip, and the gate and the source are arranged on the second surface of the switch chip), rather than a special switch architecture (such as but not limited to, the source is arranged on the second surface of the switch chip, and the gate and the drain are arranged on the first surface of the switch chip, the positions of the source and the drain are opposite to the present application), the cost of the two is obviously cheaper than the conventional switch chip. Therefore, compared with using a special switch architecture, the present application uses a conventional switch chip to achieve the effect of saving chip cost.

[0070] The conductive clip 3 includes a lead frame end 32 and a chip end 34, and the chip end 34 includes a first surface 342 and a second surface 344 opposite to the first surface 342. The first surface 342 is electrically connected to the first source electrode 24, and the lead frame end 32 is electrically connected to the ground pin 12G. The control chip 4 includes a bonding surface 45 and a contact surface 47, the bonding surface 45 is bonded to the second surface 344 of the conductive clip 3, and the contact surface 47 is provided with a plurality of contacts 42. The contacts 42 include at least a ground contact 42a and a first gate contact 42b, and the ground contact 42a is electrically connected to the conductive clip 3 for grounding or detection of the control chip 4. The first gate contact 42b is electrically connected to the first gate electrode 26 for control or detection of the control chip 4. Preferably, the ground contact 42a can be electrically connected to the conductive clip 3 through a wire bond 44, and the first gate contact 42b can also be electrically connected to the first gate electrode 26 through a wire bond 44 for good signal transmission. The material of the conductive clip 3 is preferably copper, but can also be a metal material with good electrical conductivity. It is worth mentioning that in an embodiment of the present application, the chip package 100A mainly includes a single first switch chip 2 combined with a control chip 4, which can control the conduction and turn-off of the first switch chip 2 through the control chip 4.

[0071] Preferably, the electrode of the first drain electrode 22 can be directly bonded to the chip base 10, and a first conductive layer 52 can be further included between the first drain electrode 22 and the chip base 10, which electrically connects the first drain electrode 22 and the chip base 10. The first surface 342 of the conductive clip 3 can be directly bonded to the electrode of the first source electrode 24, and the specific structure is that the first surface 342 completely covers the other surface of the first source electrode 24. Similarly, a second conductive layer 54 can be further included between the first surface 342 and the electrode of the first source electrode 24, which electrically connects the first source electrode 24 and the first surface 342. The first conductive layer 52 and the second conductive layer 54 can be selected from at least one of solder, conductive adhesive and metal tape, mainly for bonding the electrode of the first drain electrode 22 and the chip base 10, and the electrode of the first surface 342 and the first source electrode 24. Similarly, the lead frame end 32 of the conductive clip 3 can be directly bonded to the ground pin 12G, and a conductive layer for bonding can also be included between the lead frame end 32 and the ground pin 12G. Since the stacked structure of the chip package 100A in the high-frequency large power path (i.e. the path composed of the chip base 10, the first drain electrode 22, the first source electrode 24, the conductive clip 3 and the ground pin 12G) is implemented in a bonded and electrically connected manner, there is no wire bonding or other lines between elements and elements, so that the impedance of the connection between elements and elements (i.e. the impedance of the wire bonding or other lines) can be reduced.

[0072] Furthermore, when the first transistor switch 2 generates electromagnetic radiation due to changes in its on / off state, the conductive clip 3 can shield the electromagnetic radiation to reduce the intensity of the electromagnetic radiation reaching the control chip 4. Specifically, when the first switch chip 2 is energized and operating (i.e., when it is controlled to be turned on / off at a specific frequency), high-frequency, high-power noise can interfere with the signal transmission of the control chip 4, such as signal detection, feedback compensation, and output control, through the magnetic field. Since the signal transmission of the control chip 4 is very sensitive, even slight noise coupling can cause inaccurate signal detection, feedback compensation, and output control of the control chip 4, affecting its characteristics and even posing a risk of failure to the entire 100A chip package.

[0073] Therefore, high-frequency, high-power and low-power circuits are usually isolated from each other to avoid the aforementioned situation. However, because the control chip 4 and the first switch chip 2 of this invention have a grounding layer (i.e., the grounding layer formed by the conductive clip 3 and the second conductive layer 54), they are isolated from each other to suppress electromagnetic radiation interference (i.e., the grounding layer provides a more stable potential that can suppress or buffer noise). Therefore, the noise from the first switch chip 2 when it is energized and operating can be prevented from interfering with the operation of the control chip 4 through the magnetic field. In addition, since the chip package 100A of this invention has a structure in which each component is stacked upwards, compared with the existing planar configuration structure, the area occupied by the chip package 100A on the circuit board is smaller, which is beneficial to improving the power density of the overall circuit.

[0074] Please see Figure 3 This is a top view of the first embodiment of the chip stacking structure of the present invention that can avoid magnetic field interference, and can be viewed in conjunction with other references. Figures 1 to 3 The control chip further includes at least one electrical signal contact 42c, which is disposed on the contact surface 47 and is electrically connected to one of the lead frame 1, the first switch chip 2, and the conductive clip 3. Figure 3 Taking the electrical connection of the first switch chip 2 as an example, it is used for control or detection by the control chip 4. The electrical signal contact 42c can also be electrically connected to one of the lead frame 1, the first switch chip 2, and the conductive clip 3 via a bonding wire 44, to provide good signal transmission or grounding respectively. The first surface 342 of the conductive clip 3 completely covers the first source electrode 24, and the length X and width Y of the conductive clip 3 are both greater than those of the control chip 4, making the first surface area of ​​the bonding surface 45 (same as the contact surface 47) of the control chip 4 smaller than the second surface area of ​​the second surface 344 of the conductive clip 3. The width Y of the lead frame end 32 of the conductive clip 3 is also wider, so a lead frame 1 including multiple grounding pins 12G can be used for compatible bonding.

[0075] Since the conductive clip 3 has a large surface area, it has a good heat dissipation effect, so the control chip 4 can dissipate heat through the conductive clip 3, and the first switch chip 2 can dissipate heat through the first source electrode 24 in addition to dissipating heat through the chip base 10 by the first drain electrode 22. A large amount of heat generated when the first switch chip 2 is powered on and operates can be quickly transmitted through the large-area contact of the chip base 10 and the conductive clip 3 to dissipate heat. Therefore, by designing the conductive clip 3 to have a large surface area, the heat dissipation efficiency inside the chip package 100A can be greatly improved.

[0076] Please refer to Figure 4 The second embodiment of the chip stacking structure of the present application can avoid magnetic field interference. Please refer to Figures 1 to 3 The chip package 100B of the present embodiment is different from the chip package 100A of Figure 2 The chip package 100B further includes a second switch chip 6. The second switch chip 6 is a second transistor switch, and is also a conventional transistor chip like the first switch chip 2. The second switch chip 6 includes a second drain electrode 62, a second source electrode 64, and a second gate electrode 66. The second source electrode 64 and the second gate electrode 66 are arranged on the third face 6A of the second switch chip 6, and the second drain electrode 62 is arranged on the fourth face 6B of the second switch chip 6. The second drain electrode 62 is electrically connected to the chip base 10A of the lead frame 1, and the chip base 10A and the chip base 10 are separated from each other.

[0077] The third face 6A is attached to the second face 2B, and the first drain electrode 22 is electrically connected to the second source electrode 64. Among them, the electrodes of the chip base 10, the second source electrode 64, and the first drain electrode 22 are electrically connected to each other, so that the three are common points. Similar to Figure 2 The control chip 4 further includes a second gate electrode contact 42d electrically connected to the second gate electrode 66 for control or detection by the control chip 4. It is worth mentioning that in an embodiment of the present application, the chip package 100B mainly includes the architecture of two switch chips 2, 6 combined with a control chip 4, which can mainly control the conduction and turn-off of the first switch chip 2 and the second switch chip 6 through the control chip 4. It can be used for, for example but not limited to, a step-down converter, and the chip base 10A can be used to receive an external input voltage.

[0078] Preferably, the chip base 10 and the electrode of the second source 64 are partially covered by the electrode of the first drain 22 respectively, and a third conductive layer 56 can be further included between the second source 64 and the first drain 22. Similarly, the electrode of the second drain 62 can be directly attached to the chip base 10A, and a fourth conductive layer 58 can be further included between the second drain 62 and the chip base 10A. The third and fourth conductive layers 56 and 58 can be selected from at least one of solder, conductive glue and metal adhesive tape, and mainly serve as adhesive. Since the stacked structure of the chip package 100B is used in the path of high frequency and large power, the attachment and electrical connection are implemented, and there is no wire connection between the components, so that the impedance of the connection between the components (i.e. the impedance of the wire connection) can be reduced. Similarly, when the first and second transistor switches generate electromagnetic radiation due to the change of the on-off state, the conductive clip 3 can shield the electromagnetic radiation to reduce the intensity of the electromagnetic radiation reaching the control chip 4.

[0079] Please refer to Figure 5 For the third embodiment of the chip stacked structure of the present application which can avoid magnetic field interference, please refer to Figures 1 to 4 The chip package 100C of the present embodiment is different from the chip package 100A of Figure 2 The difference between the chip package 100C of the present embodiment and the chip package 100A of Since the electrode of the first source 24 is electrically connected to the first face 342 of the conductive clip 3', the first source 24 is at ground potential. Therefore, as in the chip package 100A of the first embodiment, the control chip 4 and the first switch chip 2 are separated from each other by the ground layer (i.e. the ground layer formed by the conductive clip 3' and the first source 24) between them, and the noise generated when the first switch chip 2 is powered on and operates can also be prevented from interfering with the operation of the control chip 4 through the magnetic field.

[0080] In particular, the first surface 342 of the conductive clip 3' can directly adhere to the other surface of the first source electrode 24, and the first surface 342 does not completely cover the electrode of the first source electrode 24 (only covers about half of the area of the electrode of the first source electrode 24), so that the bonding surface 45 of the control chip 4 can directly adhere to part of the electrode of the first source electrode 24. Similarly, a second conductive layer 54 can also be included between the first surface 342, the control chip 4 and the electrode of the first source electrode 24, mainly for bonding the first surface 342, the control chip 4 and the electrode of the first source electrode 24, and the second conductive layer 54 electrically connects the first source electrode 24 and the conductive clip 3. In addition, since the chip package 100C of the present application is a structure in which each element is stacked upward, and the upward stacking space of the conductive clip 3' is saved, the chip package 100C can have a smaller area occupied when arranged on a circuit board, and the height of the chip package 100C can be slightly smaller than the chip package 100C, which can more advantageously improve the power density of the overall circuit. It is worth mentioning that in an embodiment of the present application, Figure 5 the elements and structures not mentioned are similar to Figure 2 and will not be repeated here.

[0081] Please refer to Figure 6 the top view of the third embodiment of the chip stacking structure of the present application which can avoid magnetic field interference, and also refer to Figures 1 to 5 . The chip package 100C of the present embodiment is different from the chip package 100 Figure 2 in that the first surface 342 of the conductive clip 3' covers only about half of the area of the electrode of the first source electrode 24 and does not completely cover the electrode of the first source electrode 24. However, the length X and the width Y of the conductive clip 3' are still greater than the control chip 4, so that the first surface area of the control chip 4 is still smaller than the second surface area of the second surface 344 of the conductive clip 3'. The control chip 4 can dissipate heat through the path from the first source electrode 24 to the conductive clip 3', and the first switch chip 2 can dissipate heat not only through the first drain electrode 22 to the chip base 10, but also through the first source electrode 24 to the conductive clip 3'. Although the first embodiment is more preferred in terms of heat dissipation efficiency, a large amount of heat generated when the first switch chip 2 is powered on and operates can still be quickly transferred away from the first switch chip 2 through the large-area contact between the chip base 10 and the conductive clip 3'. Therefore, the same effect of improving the heat dissipation efficiency inside the chip package 100C can also be achieved. It is worth mentioning that in an embodiment of the present application, Figure 6 the elements and structures not mentioned are similar to Figure 3 and will not be repeated here.

[0082] Please refer to Figure 7 the side view of the fourth embodiment of the chip stacking structure of the present application which can avoid magnetic field interference, and also refer toFigures 1 to 6 The chip package 100D of the present embodiment is different from the chip package 100B of the prior art in that each of the points (such as but not limited to the first switch chip 2, the second switch chip 6, etc.) of the chip package 100D can be electrically connected to the pin 12 by wire bonding. The pin 12 is different from the ground pin 12G and is used for external circuit connection for I / O, detection, control, etc. Figure 4 For example, the second gate 66 is electrically connected to the pin 12 by wire bonding 44 for external circuit connection. It is worth mentioning that in an embodiment of the present application, the first switch chip 2 is electrically connected to the pin 12 by wire bonding 44 for external circuit connection. Figure 7 For example, the second gate 66 is electrically connected to the pin 12 by wire bonding 44 for external circuit connection. It is worth mentioning that in an embodiment of the present application, the first switch chip 2 is electrically connected to the pin 12 by wire bonding 44 for external circuit connection. Figure 7 The elements not mentioned and their structures are similar to those of the chip package 100B of the prior art and will not be described here again. Figure 4 The chip package 100D of the present embodiment is different from the chip package 100B of the prior art in that each of the points (such as but not limited to the first switch chip 2, the second switch chip 6, etc.) of the chip package 100D can be electrically connected to the pin 12 by wire bonding. The pin 12 is different from the ground pin 12G and is used for external circuit connection for I / O, detection, control, etc.

[0083] The chip package 100D of the present embodiment is different from the chip package 100B of the prior art in that each of the points (such as but not limited to the first switch chip 2, the second switch chip 6, etc.) of the chip package 100D can be electrically connected to the pin 12 by wire bonding. The pin 12 is different from the ground pin 12G and is used for external circuit connection for I / O, detection, control, etc.

[0084] Of course, the present application can have other various embodiments, and those skilled in the art can make various corresponding changes and modifications to the present application without departing from the spirit and essence of the present application, but these corresponding changes and modifications should all fall within the protection scope of the claims of the present application.

Claims

1. A chip stacking structure, characterized in that, include: A lead frame includes a chip base and a ground pin, the ground pin carrying a ground potential; A first switching chip includes a first drain, a first source, and a first gate; the first source and the first gate are disposed on a first side of the first switching chip, and the first drain is disposed on a second side of the first switching chip, and the first drain is electrically connected to the chip base; A conductive clip includes a lead frame end and a chip end, wherein the chip end includes a first surface and a second surface opposite to the first surface, the first surface of the chip end is electrically connected to a first source electrode, and the lead frame end is electrically connected to a ground pin; and A control chip includes a mating surface and a contact surface. The mating surface is coupled to the second surface of the conductive clip. The contact surface includes a first gate contact and an electrical signal contact. The first gate contact is electrically connected to the first gate, and the electrical signal contact is electrically connected to one of the lead frame, the first switch chip, and the conductive clip. Wherein, the bonding surface is attached to the second surface of the conductive clip, and the first surface area of ​​the bonding surface is smaller than the second surface area of ​​the second surface of the conductive clip.

2. The chip stacking structure according to claim 1, characterized in that, It further includes a first conductive layer that electrically connects the first drain to the chip substrate. The first conductive layer is selected from at least one of solder, conductive adhesive, and metal tape.

3. The chip stacking structure according to claim 1, characterized in that, It further includes a second conductive layer that electrically connects the first source electrode to the first surface of the conductive clip, and the second conductive layer is selected from at least one of solder, conductive adhesive and metal tape.

4. The chip stacking structure according to claim 1, characterized in that, The first side of the conductive clip completely covers the first source electrode, and the first gate contact is electrically connected to the first gate electrode via a wire.

5. The chip stacking structure according to claim 1, characterized in that, Including: A second switch chip includes a second drain, a second source, and a second gate. The second source and the second gate are disposed on a third surface of the second switch chip, and the second drain is disposed on a fourth surface of the second switch chip. The third surface of the second switch chip is attached to the second surface of the first switch chip, and the first drain is connected to the second source.

6. A chip stacking structure, characterized in that, include: A lead frame includes a chip base and a ground pin, the ground pin carrying a ground potential; A first switching chip includes a first drain, a first source, and a first gate; the first source and the first gate are disposed on a first side of the first switching chip, and the first drain is disposed on a second side of the first switching chip, and the first drain is electrically connected to the chip base; A conductive clip includes a lead frame end and a chip end, wherein the chip end includes a first surface and a second surface opposite to the first surface; the first surface of the chip end is electrically connected to a first source electrode, and the lead frame end is electrically connected to a ground pin; the conductive clip covers a portion of the first source electrode, and the first source electrode has an exposed source electrode area not covered by the conductive clip; and A control chip includes a mating surface and a contact surface. The mating surface is coupled to the second surface of the first switching chip. The contact surface includes a first gate contact and an electrical signal contact. The first gate contact is electrically connected to the first gate, and the electrical signal contact is electrically connected to one of the lead frame, the first switching chip, and the conductive clip. The bonding surface is attached to the exposed source region, and the first surface area of ​​the bonding surface is smaller than the second surface area of ​​the second surface of the first switch chip.

7. The chip stacking structure according to claim 6, characterized in that, It further includes a first conductive layer that electrically connects the first drain to the chip substrate. The first conductive layer is selected from at least one of solder, conductive adhesive, and metal tape.

8. The chip stacking structure according to claim 6, characterized in that, It further includes a second conductive layer that bonds the first source electrode, the bonding surface of the control chip, and the first surface of the conductive clip. The second conductive layer is selected from at least one of solder, conductive adhesive, and metal tape, and is capable of electrically connecting the first source electrode and the conductive clip.

9. The chip stacking structure according to claim 6, characterized in that, The first side of the conductive clip does not completely cover the first source electrode, and the first gate electrode contact is electrically connected to the first gate electrode via a wire.

10. The chip stacking structure according to claim 6, characterized in that, Including: A second switch chip includes a second drain, a second source, and a second gate. The second source and the second gate are disposed on a third surface of the second switch chip, and the second drain is disposed on a fourth surface of the second switch chip. The third surface of the second switch chip is attached to the second surface of the first switch chip, and the first drain is electrically connected to the second source.

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