Display panel and display device

Abstract

The present application discloses a display panel and a display device, relating to the field of display technologies. A dummy electrode pattern is provided in the first display area of the display panel, and the dummy electrode pattern and the first connection trace are located in different layers. Thereby, it is convenient to make the overlapping capacitance between the regions where each pixel circuit group in the first display area is located and the first connection trace consistent, and further, the display effect of the display panel can be ensured.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display panels have been widely used due to their advantages such as self-luminescence, low driving voltage, and fast response speed. The OLED display panel includes a plurality of pixel units, and each pixel unit includes a light-emitting unit and a pixel circuit unit connected to the light-emitting unit.

[0003] In related technologies, in order to increase the screen-to-body ratio of the display panel, the camera of the display device can be disposed in the display area of the display panel. Moreover, in order to increase the transmittance of the area where the camera is located, the pixel circuits of the light-emitting units in the area where the camera is located are usually disposed in a non-camera area. The pixel circuits located in the non-camera area are connected to the light-emitting units located in the camera area through connection traces, so as to provide driving signals for the light-emitting units located in the camera area.

[0004] However, since the overlapping capacitances between the areas where the respective pixel circuits in the non-camera area are located and the connection traces are inconsistent, the display effect of the display panel is poor. Summary of the Invention

[0005] This application provides a display panel and a display device, which can solve the problem of poor display effect in the camera area in related technologies. The technical solutions are as follows:

[0006] On the one hand, a display panel is provided, and the display panel includes:

[0007] a substrate, the substrate having an adjacent first display area and a second display area;

[0008] a plurality of first light-emitting units, the plurality of first light-emitting units being located in the first display area;

[0009] a plurality of first pixel circuit groups, the plurality of first pixel circuit groups being located in the first display area, and each of the first pixel circuit groups being electrically connected to at least one of the first light-emitting units;

[0010] a plurality of second light-emitting units, the plurality of second light-emitting units being located in the second display area;

[0011] a plurality of second pixel circuit groups, the plurality of second pixel circuit groups being located in the first display area;

[0012] a plurality of dummy electrode patterns, located in the first display area;

[0013] And, a plurality of first connection traces, one end of at least one of the plurality of first connection traces is electrically connected to at least one of the second light-emitting units, and the other end is electrically connected to the dummy electrode pattern and the second pixel circuit group;

[0014] Wherein, the plurality of first connection traces and the plurality of dummy electrode patterns are located on different layers.

[0015] Optionally, the display panel further includes: a plurality of second connection traces;

[0016] One end of at least one of the plurality of second connection traces is electrically connected to at least one of the second light-emitting units, and the other end is electrically connected to the dummy electrode pattern and the second pixel circuit group;

[0017] Wherein, the plurality of second connection traces, the plurality of first connection traces, and the plurality of dummy electrode patterns are all located on different layers.

[0018] Optionally, the sum of the number of the plurality of first connection traces and the plurality of second connection traces included in the display panel is the same as the number of the dummy electrode patterns, and they correspond one by one, and each of the plurality of first connection traces and the plurality of second connection traces is electrically connected to a corresponding one of the dummy electrode patterns.

[0019] Optionally, at least one of the dummy electrode patterns includes a main body portion and a first connection portion, the first connection portion extends along a first direction, the first connection traces and the second connection traces both extend along a second direction, and the first direction and the second direction intersect;

[0020] The first connection portion is electrically connected to at least one of the plurality of first connection traces and the plurality of second connection traces at the intersection through a via hole.

[0021] Optionally, each of the second pixel circuit groups includes: a source-drain metal layer located on the substrate, the source-drain metal layer includes a source electrode and a drain electrode arranged at intervals; the display panel further includes: a first insulating layer, a second insulating layer, and a third insulating layer;

[0022] The source-drain metal layer, the first insulating layer, the plurality of first connection traces, the second insulating layer, the plurality of second connection traces, the third insulating layer, and the dummy electrode pattern are stacked in sequence in a direction away from the substrate.

[0023] Optionally, the plurality of dummy electrode patterns at least include: a first dummy electrode pattern and a second dummy electrode pattern; the second insulating layer has a plurality of first vias and a plurality of second vias, the third insulating layer has a plurality of third vias corresponding to the plurality of first vias one by one, and a plurality of fourth vias corresponding to the plurality of second vias one by one;

[0024] The orthographic projection of each of the first vias on the substrate overlaps at least partially with the orthographic projection of the corresponding third via on the substrate. Each of the first vias is used to expose one of the first connection traces, and at least a part of the first connection portion in the first dummy electrode pattern is electrically connected to the first connection trace through the third via and the first via;

[0025] At least a part of each of the second connection traces is located in the second vias. Each of the fourth vias is used to expose one of the second connection traces, and at least a part of the first connection portion in the second dummy electrode pattern is electrically connected to the second connection trace through the fourth via.

[0026] Optionally, the orthographic projection of the intersection on the substrate overlaps with the orthographic projection of the first connection portion on the substrate.

[0027] Optionally, the display panel further includes: a plurality of second connection portions extending along a first direction, the first connection traces and the second connection traces both extend along a second direction, and the first direction intersects with the second direction;

[0028] The second connection portions and the dummy electrode patterns are located in different layers, and one of the second connection portions is electrically connected to a dummy electrode pattern through a via. The second connection portion is also electrically connected to at least one of the plurality of first connection traces and the plurality of second connection traces through a via at the intersection.

[0029] Optionally, each of the second pixel circuit groups includes: a source-drain metal layer located on the substrate, and the second connection portions and the source-drain metal layer are located in the same layer.

[0030] Optionally, the display panel further includes: a first insulating layer, a second insulating layer, and a third insulating layer;

[0031] The source-drain metal layer, the first insulating layer, the plurality of first connection traces, the second insulating layer, the plurality of second connection traces, the third insulating layer, and the dummy electrode patterns are stacked in sequence in a direction away from the substrate.

[0032] Optionally, the first insulating layer has a plurality of fifth vias, each of the fifth vias being configured to expose one of the second connection portions, and at least a part of one of the first connection traces is electrically connected to the second connection portion through one of the fifth vias;

[0033] The first insulating layer and the second insulating layer have a plurality of sixth vias, each of the sixth vias being configured to expose one of the second connection portions, and at least a part of one of the second connection traces is electrically connected to the second connection portion through one of the sixth vias.

[0034] Optionally, a positive projection of the intersection on the substrate does not overlap with a positive projection of any of the dummy electrode patterns on the substrate;

[0035] Alternatively, a positive projection of the intersection on the substrate is located within a positive projection of one of the dummy electrode patterns on the substrate.

[0036] Optionally, each of the second pixel circuit groups includes: a source-drain metal layer located on the substrate, the source-drain metal layer including a source electrode and a drain electrode arranged at intervals; the display panel further includes: a first insulating layer, a second insulating layer, and a third insulating layer; the source-drain metal layer, the first insulating layer, the plurality of first connection traces, the second insulating layer, the plurality of second connection traces, the third insulating layer, and the dummy electrode pattern are stacked in sequence in a direction away from the substrate;

[0037] The second insulating layer has a plurality of seventh vias and a plurality of eighth vias, the third insulating layer has a plurality of ninth vias corresponding to the plurality of seventh vias one by one, and a plurality of tenth vias corresponding to the plurality of eighth vias one by one;

[0038] A positive projection of each of the seventh vias on the substrate at least partially overlaps with a positive projection of the corresponding ninth via on the substrate, each of the seventh vias is configured to expose one of the first connection traces, and a first electrode of at least one of the second light-emitting units is electrically connected to the first connection trace through the seventh via and the ninth via;

[0039] At least a part of each of the second connection traces is located within the eighth via, each of the tenth vias is configured to expose one of the second connection traces, and a first electrode of at least one of the second light-emitting units is electrically connected to the second connection trace through the tenth via.

[0040] Optionally, the first insulating layer has a plurality of eleventh vias, the second insulating layer has a plurality of twelfth vias corresponding to the plurality of eleventh vias one by one, and the third insulating layer has a plurality of thirteenth vias corresponding to the plurality of twelfth vias one by one; the orthographic projection of each of the eleventh vias on the substrate at least partially overlaps with the orthographic projection of the corresponding twelfth via on the substrate, and the orthographic projection of each of the twelfth vias on the substrate at least partially overlaps with the orthographic projection of the corresponding thirteenth via on the substrate; the display panel further includes: a plurality of first connection patterns and a plurality of second connection patterns corresponding to the plurality of first connection patterns one by one;

[0041] Each of the eleventh vias is used to expose the drain of a transistor in one of the second pixel circuit groups, and at least a part of one of the first connection patterns is electrically connected to the drain through the eleventh via; each of the twelfth vias is used to expose one of the first connection patterns, and at least a part of one of the second connection patterns corresponding to one of the first connection patterns is electrically connected to the first connection pattern through the twelfth via; each of the thirteenth vias is used to expose one of the second connection patterns, and at least a part of a dummy electrode pattern is connected to the second connection pattern through the thirteenth via;

[0042] Wherein, the plurality of first connection patterns and the plurality of first connection traces are on the same layer, and the plurality of second connection patterns and the plurality of second connection traces are on the same layer.

[0043] Optionally, the orthographic projection of the plurality of first connection traces on the substrate does not overlap with the orthographic projection of the plurality of second connection traces on the substrate.

[0044] Optionally, the orthographic projection of the plurality of first connection traces on the substrate and the orthographic projection of the plurality of second connection traces on the substrate are staggered in the second direction of the display panel.

[0045] Optionally, the substrate includes: two of the first display areas, and the two first display areas are located on both sides of the second display area along the first direction; the substrate further includes: a first peripheral area and a second peripheral area, and the first peripheral area and the second peripheral area are respectively located on both sides of the two first display areas; the display panel further includes: a first row driving circuit located in the first peripheral area and a second row driving circuit located in the second peripheral area;

[0046] The first row driving circuit is electrically connected to the first pixel circuit group and the second pixel circuit group in one of the first display areas, and the second row driving circuit is electrically connected to the first pixel circuit group and the second pixel circuit group in the other first display area.

[0047] Optionally, the display panel further includes: a plurality of first scanning signal lines located in one of the first display areas, and a plurality of second scanning signal lines located in the other first display area;

[0048] The first row driving circuit is electrically connected to the first pixel circuit group and the second pixel circuit group in one of the first display areas through the plurality of first scanning signal lines, and the second row driving circuit is electrically connected to the first pixel circuit group and the second pixel circuit group in the other first display area through the plurality of second scanning signal lines;

[0049] Wherein, the plurality of first scanning signal lines and the plurality of second scanning signal lines are located on the same layer, and the orthographic projections of the plurality of first scanning signal lines on the substrate and the orthographic projections of the plurality of second scanning signal lines on the substrate are both outside the second display area.

[0050] Optionally, the substrate further includes: a third display area on the same side of the first display area and the second display area; the first peripheral area and the second peripheral area are located on both sides of the third display area along the first direction; the display panel further includes: a plurality of third light-emitting units located in the third display area, and a plurality of third pixel circuit groups respectively connected to the plurality of third light-emitting units in one-to-one correspondence;

[0051] Both the first row driving circuit and the second row driving circuit are connected to the third pixel circuit group in the third display area.

[0052] Optionally, the density of the plurality of third light-emitting units is greater than the density of the plurality of first light-emitting units and greater than the density of the plurality of second light-emitting units.

[0053] Optionally, the shape of the second display area is rectangular; the display panel further includes: a plurality of data lines;

[0054] The orthographic projection of the portion of each data line located in the second display area on the substrate is a straight line or a broken line, and is located in the area of the second display area close to the first display area.

[0055] Optionally, each of the second light-emitting units includes: a first electrode, a light-emitting layer, and a second electrode stacked in sequence away from the substrate;

[0056] Among them, the multiple dummy electrode patterns are on the same layer as the first electrode.

[0057] Optionally, the orthographic projection of each dummy electrode pattern on the substrate overlaps at least partially with the orthographic projection of at least one of the second pixel circuit groups on the substrate, and the orthographic projection of each dummy electrode pattern on the substrate does not overlap with the orthographic projection of any one of the first light-emitting units on the substrate.

[0058] Optionally, the orthographic projection of the connection between each dummy electrode pattern and the second pixel circuit group on the substrate does not overlap with the orthographic projection of the multiple first connection traces on the substrate, and does not overlap with the orthographic projection of the multiple second connection traces on the substrate.

[0059] On the other hand, a display device is provided, and the display device includes: a power supply component and the display panel as described in the above aspect;

[0060] The power supply component is used to supply power to the display panel.

[0061] The beneficial effects brought by the technical solution provided in this application at least include:

[0062] This application provides a display panel and a display device. A dummy electrode pattern is provided in the first display area of the display panel, and the dummy electrode pattern and the first connection trace are on different layers. This can facilitate making the overlapping capacitance between the regions where each pixel circuit group in the first display area is located and the first connection trace consistent, and further can ensure the display effect of the display panel. Description of the Drawings

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0064] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0065] Figure 2 It is a partial schematic diagram of a display panel provided by an embodiment of the present application;

[0066] Figure 3 It is a top view of a substrate provided by an embodiment of the present application;

[0067] Figure 4 It is a partial schematic diagram of another display panel provided by an embodiment of the present application;

[0068] Figure 5 It is a schematic diagram of a dummy electrode pattern provided by an embodiment of the present application;

[0069] Figure 6 It is a partial schematic diagram of another display panel provided by an embodiment of the present application;

[0070] Figure 7 is Figure 6 a cross-sectional view along the AA direction;

[0071] Figure 8 It is a partial schematic diagram of a first connection trace and a second insulating layer provided by an embodiment of the present application;

[0072] Figure 9 It is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application;

[0073] Figure 10 It is a schematic diagram of a first connection trace and a dummy electrode pattern provided by an embodiment of the present application;

[0074] Figure 11 It is a schematic diagram of a second connection trace and a second insulating layer provided by an embodiment of the present application;

[0075] Figure 12 It is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application;

[0076] Figure 13 It is a schematic diagram of a second connection trace and a dummy electrode pattern provided by an embodiment of the present application;

[0077] Figure 14 It is a schematic diagram of a second connection part and a first insulating layer provided by an embodiment of the present application;

[0078] Figure 15 It is a schematic diagram of a second connection part and a first connection trace provided by an embodiment of the present application;

[0079] Figure 16 It is a schematic diagram of a second connection part, a first insulating layer and a second insulating layer provided by an embodiment of the present application;

[0080] Figure 17 It is a schematic diagram of a second connection trace and a second connection part provided by an embodiment of the present application;

[0081] Figure 18 It is a partial schematic diagram of a first connection trace and a second insulating layer provided by an embodiment of the present application;

[0082] Figure 19 It is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application;

[0083] Figure 20 It is a schematic diagram of a first connection trace and a first electrode of a second light-emitting unit provided by an embodiment of the present application;

[0084] Figure 21 It is a schematic diagram of a second connection trace and a second insulating layer provided by an embodiment of the present application;

[0085] Figure 22 It is a schematic diagram of another third insulating layer provided by an embodiment of the present application;

[0086] Figure 23 It is a schematic diagram of a second connection trace and a first electrode of a second light-emitting unit provided by an embodiment of the present application;

[0087] Figure 24 It is a schematic diagram of a first insulating layer and a first connection pattern provided by an embodiment of the present application;

[0088] Figure 25 It is a schematic diagram of a second insulating layer and a second connection pattern provided by an embodiment of the present application;

[0089] Figure 26 It is a schematic diagram of yet another third insulating layer provided by an embodiment of the present application;

[0090] Figure 27 It is a schematic diagram of the structure of a first light-emitting unit provided by an embodiment of the present application;

[0091] Figure 28 It is a schematic diagram of a first light-emitting unit and a dummy electrode pattern provided by an embodiment of the present application;

[0092] Figure 29 It is a schematic diagram of a second light-emitting unit and a dummy electrode pattern provided by an embodiment of the present application;

[0093] Figure 30 It is a schematic diagram of the structure of another display panel provided by an embodiment of the present application;

[0094] Figure 31 It is a partial schematic diagram of a display panel provided by an embodiment of the present application;

[0095] Figure 32 It is a partial schematic diagram of another display panel provided by an embodiment of the present application;

[0096] Figure 33 It is a partial schematic diagram of a first connection trace and a second connection trace provided by an embodiment of the present application;

[0097] Figure 34 It is a schematic diagram of the structure of yet another display panel provided by an embodiment of the present application;

[0098] Figure 35 It is a schematic diagram of another first light-emitting unit and dummy electrode pattern provided by an embodiment of the present application;

[0099] Figure 36 It is an equivalent circuit diagram of a first pixel circuit group or a second pixel circuit group provided by an embodiment of the present application;

[0100] Figure 37 It is a partial planar structure schematic diagram of the active semiconductor layer of the pixel circuit in the first display area provided by an embodiment of the present application;

[0101] Figure 38 It is a partial schematic diagram of the first conductive layer in the first display area provided by an embodiment of the present application;

[0102] Figure 39 It is a partial schematic diagram of the second conductive layer in the first display area provided by an embodiment of the present application;

[0103] Figure 40 It is a partial schematic diagram of the source-drain metal layer of the first display area provided by an embodiment of the present application;

[0104] Figure 41 It is a stacked schematic diagram of the active semiconductor layer, the first conductive layer, the second conductive layer, and the source-drain metal layer in the first display area provided by an embodiment of the present application;

[0105] Figure 42 It is a structural schematic diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0106] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0107] The terms used in the embodiments section of this application are only for explaining the embodiments of this application and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the ordinary meaning understood by those of ordinary skill in the field to which this application belongs. The "first", "second", "third" and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "one" do not indicate a quantity limitation, but indicate that there is at least one. Terms such as "comprising" or "including" mean that the elements or objects appearing before "comprising" or "including" cover the elements or objects listed after "comprising" or "including" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", "right" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.

[0108] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of this application. Figure 2 It is a partial schematic diagram of a display panel provided by an embodiment of this application. Combining Figure 1 and Figure 2 it can be seen that the display panel 10 may include: a substrate 101, a plurality of first light-emitting units 102, a plurality of first pixel circuit groups 103, a plurality of second light-emitting units 104, a plurality of second pixel circuit groups 105, a plurality of dummy electrode patterns 106, and a plurality of first connection traces 107. Among them, Figure 2 each pixel circuit group is not shown.

[0109] Figure 3 It is a top view of a substrate provided by an embodiment of this application. Referring to Figure 3 it can be seen that the substrate 101 has adjacent first display areas 101a and second display areas 101b. Figure 3 Two first display areas 101a and one second display area 101b are shown therein. The second display area 101b may be an area where a camera is provided.

[0110] Combining Figures 1 to 3, a plurality of first light-emitting units 102 are located in the first display area 101a, and a plurality of first pixel circuit groups 103 are located in the first display area 101a. Each first pixel circuit group 103 is connected to at least one first light-emitting unit 102, and each first pixel circuit group 103 is configured to provide a driving signal for at least one first light-emitting unit 102 connected thereto, and the driving signal is used to drive the first light-emitting unit 102 to emit light.

[0111] And, in combination Figures 1 to 3 , a plurality of second light-emitting units 104 are located in the second display area 101b, and a plurality of second pixel circuit groups 105 are located in the first display area 101a. A plurality of dummy electrode patterns 106 are located in the first display area 101a. At least one first connection trace 107 of the plurality of first connection traces 107 is electrically connected to at least one second light-emitting unit 104 at one end, and is electrically connected to the dummy electrode pattern 106 and the second pixel circuit group 105 at the other end. That is, one end of each first connection trace 107 may be located in the second display area 101b, and the other end may be located in the first display area 101a. Thus, the second pixel circuit group 105 located in the first display area 101a can be electrically connected to the second light-emitting unit 104 located in the second display area 101b, and further the second pixel circuit group 105 provides a driving signal for the second light-emitting unit 104 connected thereto, and the driving signal is used to drive the second light-emitting unit 104 to emit light.

[0112] In the embodiment of the present application, the plurality of first connection traces 107 and the plurality of dummy electrode patterns 106 are located in different layers. That is, the plurality of first connection traces 107 and the plurality of dummy electrode patterns 106 can be respectively fabricated by two lithography processes.

[0113] Since the dummy electrode pattern 106 is provided in the first display area 101a, the overlapping capacitance between the area where the first light-emitting unit 102 is provided in the first display area 101a and the first connection trace 107, and the overlapping capacitance between the area where the dummy electrode pattern 106 is provided and the first connection trace 107 can be made consistent, ensuring the display effect of the display panel 10.

[0114] In summary, the embodiment of the present application provides a display panel, in which a dummy electrode pattern is provided in the first display area of the display panel, and the dummy electrode pattern and the first connection trace are located in different layers. Thus, it is convenient to make the overlapping capacitance between the area where each pixel circuit group in the first display area is located and the first connection trace consistent, and further the display effect of the display panel can be ensured.

[0115] Figure 4 is a partial schematic diagram of another display panel provided by the embodiment of the present application. Refer to Figure 4It can be seen that the display panel 10 may further include: a plurality of second connection traces 108. One end of at least one second connection trace 108 among the plurality of second connection traces 108 may be electrically connected to at least one second light-emitting unit 104, and the other end is electrically connected to the dummy electrode pattern 106 and the second pixel circuit group 105.

[0116] Among them, the plurality of second connection traces 108, the plurality of first connection traces 107, and the plurality of dummy electrode patterns 106 are all located in different layers. That is, any two of the following structures are located in different layers: the plurality of first connection traces 107, the plurality of second connection traces 108, and the plurality of dummy electrode patterns 106. The plurality of first connection traces 107, the plurality of second connection traces 108, and the plurality of dummy electrode patterns 106 need to be prepared by three lithography processes respectively.

[0117] Since the space of the display panel 10 is limited, the number of first connection traces 107 that can be provided in the same layer is limited. Therefore, by providing the plurality of first connection traces 107 and the plurality of second connection traces 108 located in different layers, a part of the second pixel circuit group 105 in the first display area 101a can be connected to a part of the second light-emitting units 104 in the second display area 101b through the first connection traces 107, so as to drive this part of the second light-emitting units 104 located in the second display area 101b to emit light. Moreover, another part of the second pixel circuit group 105 in the first display area 101a can be connected to another part of the second light-emitting units 104 in the second display area 101b through the second connection traces 108, so as to drive this other part of the second light-emitting units 104 located in the second display area 101b to emit light.

[0118] The solution of the embodiment of the present application can increase the number of second light-emitting units 104 that can be provided in the second display area 101b without increasing the number of first connection traces 107, and further ensure the display effect of the second display area 101b in the display panel 10. Moreover, since the number of second light-emitting units 104 that can be provided in the second display area 101b is relatively large, a larger-sized camera can be allowed to be provided in the second display area 101b, and the requirement for the manufacturing precision of the display panel 10 is relatively low.

[0119] Optionally, the materials of the first connection trace 107 and the second connection trace 108 may be transparent materials to avoid affecting the transmittance of the second display area 101b. For example, the materials of the first connection trace 107 and the second connection trace 108 may be indium tin oxide (ITO). Additionally, the extending directions of the plurality of first connection traces 107 and the plurality of second connection traces 108 may both be the second direction Y. The second direction Y may be the pixel row direction of the display panel 10.

[0120] It should be noted that the display panel 10 in the embodiments of the present application may further include a plurality of third connection traces. Moreover, any two of the following structures are located in different layers: the plurality of first connection traces 107, the plurality of second connection traces 108, the plurality of third connection traces, and the plurality of dummy electrode patterns 106. The plurality of first connection traces 107, the plurality of second connection traces 108, the plurality of third connection traces, and the plurality of dummy electrode patterns 106 need to be prepared by four lithography processes respectively. That is to say, the display panel 10 may include three layers of connection traces, and the three layers of connection traces are respectively: the plurality of first connection traces 107, the plurality of second connection traces 108, and the plurality of third connection traces. Of course, the display panel 10 may further include more layers of connection traces, and the embodiments of the present application do not limit this.

[0121] In the embodiments of the present application, the display panel 10 including two layers of connection traces is taken as an example for illustration, that is, the display panel 10 including the plurality of first connection traces 107 and the plurality of second connection traces 108 is taken as an example. The sum of the numbers of the plurality of first connection traces 107 and the plurality of second connection traces 108 included in the display panel 10 may be the same as the number of the dummy electrode patterns 106 included in the display panel 10 and correspond one by one. Each connection trace in the plurality of first connection traces 107 and the plurality of second connection traces 108 may be electrically connected to a corresponding one of the dummy electrode patterns 106.

[0122] In the embodiments of the present application, referring to Figure 1 , the orthographic projection of each dummy electrode pattern 106 on the substrate 101 may at least partially overlap with the orthographic projection of at least one second pixel circuit group 105 on the substrate 101. Among them, Figure 1In the present application, the same small square is used to represent two overlapping structures. For example, the same small square is used to represent the overlapping first light-emitting unit 102 and the first pixel circuit group 103, and they are labeled as 102 / 103. Another example is that the same small square is used to represent the overlapping second pixel circuit group 105 and the dummy electrode pattern 106, and they are labeled as 105 / 106. Optionally, the orthographic projection of each dummy electrode pattern 106 on the substrate 101 may at least partially overlap with the orthographic projection of a second pixel circuit group 105 on the substrate 101.

[0123] Moreover, the orthographic projection of each dummy electrode pattern 106 on the substrate 101 does not overlap with the orthographic projection of any first light-emitting unit 102 on the substrate 101. The non-overlap between the dummy electrode pattern 106 and the first light-emitting unit 102 can avoid the influence of the dummy electrode pattern 106 on the first light-emitting unit 102 and ensure the light-emitting effect of the first light-emitting unit 102.

[0124] In the embodiments of the present application, referring to Figure 1 and Figure 3 , the second display area 101b may include a central area 101b1 and an edge area 101b2 surrounding the central area 101b1. For example, Figure 3 schematically shows that the shape of the second display area 101b is rectangular, and the shape of the central area 101b1 of the second display area 101b is circular. Then the edge area 101b2 is the area in the rectangle except for the circular central area. Of course, the central area 101b1 and the edge area 101b2 of the second display area 101b may also be other shapes, which can be set according to the actual product requirements, and the embodiments of the present application do not limit this.

[0125] Optionally, the central area 101b may be used as an under-screen camera area. The second light-emitting unit 104 is arranged in the central area 101b1, and the second pixel circuit group 105 for driving the second light-emitting unit 104 to emit light is arranged in the first display area 101a. Thus, the central area 101b1 can have a high light transmittance to achieve the camera function, and can also emit light by connecting with the pixel circuit groups in other areas (the first display area 101a), without affecting the display function of the screen.

[0126] In the embodiments of the present application, referring to Figure 1, the second light-emitting units 104 in the second display area 101b can be controlled in a left-right half control manner, and are respectively controlled by the second pixel circuit groups 105 in the two first display areas 101a that are axisymmetric about the center line extending in the first direction X. For example, the second light-emitting units 104 located on the left side of the center line are controlled by the second pixel circuit group 105 in the first display area 101a on the left side of the center line, and the second light-emitting units 104 located on the right side of the center line are controlled by the second pixel circuit group 105 in the first display area 101a on the right side of the center line. Among them, the first direction X can be the pixel column direction of the display panel 10.

[0127] Reference Figure 4 It can be seen that the orthographic projections of the plurality of first connection traces 107 on the substrate 101 do not overlap with the orthographic projections of the plurality of second connection traces 108 on the substrate 101. Thus, the possibility of generating overlapping capacitance between the plurality of first connection traces 107 and the plurality of second connection traces 108 can be reduced, thereby avoiding signal crosstalk.

[0128] Exemplarily, the orthographic projections of the plurality of first connection traces 107 on the substrate 101 and the orthographic projections of the plurality of second connection traces 108 on the substrate 101 are staggered in the first direction X. Thus, the distance between the plurality of first connection traces 107 on the same layer along the first direction X and the distance between the plurality of second connection traces 108 on the same layer along the first direction X can be made larger, so that the connection traces on the same layer can be prevented from affecting each other and the reliability of signal transmission can be ensured. Of course, the orthographic projections of the plurality of first connection traces 107 on the substrate 101 and the orthographic projections of the plurality of second connection traces 108 on the substrate 101 can be arranged in other ways, and the embodiments of the present application do not limit this.

[0129] Figure 5 is a schematic diagram of a dummy electrode pattern provided by an embodiment of the present application. Reference Figure 5 , at least one dummy electrode pattern 106 includes: a main body portion 1061 and a first connection portion 1062, and the first connection portion 1062 can extend along the first direction X. Combining Figure 4 and Figure 5 , since the extending direction (the first direction X) of the first connection portion 1062 intersects with the extending direction (the second direction Y) of the connection traces (the first connection traces 107 and the second connection traces 108), there is an intersection between the first connection portion 1062 and at least one of the plurality of first connection traces 107 and the plurality of second connection traces 108.

[0130] Among them, the first connection portion 1062 is connected to at least one of the plurality of first connection traces 107 and the plurality of second connection traces 108 through a via at the intersection. Thus, the at least one connection trace can be electrically connected to the dummy electrode pattern 106. Moreover, the dummy electrode pattern 106 can also be electrically connected to the second pixel circuit group 105. Therefore, the at least one connection trace can be electrically connected to the second pixel circuit group 105 through the dummy electrode pattern 106.

[0131] Figure 6 It is a partial schematic diagram of another display panel provided by an embodiment of the present application. Figure 7 is Figure 6 a cross-sectional view along the AA direction. Refer to Figure 6 and Figure 7 It can be seen that each second pixel circuit group 105 may include: a source-drain metal layer located on the substrate 101. The source-drain metal layer includes a source electrode and a drain electrode arranged at intervals ( Figure 7 only the drain electrode A of one transistor in the second pixel circuit group 105 is shown in ). The display panel 10 may further include: a first insulating layer 109, a second insulating layer 110, and a third insulating layer 111.

[0132] Optionally, Figure 7 the first connection pattern 112 shown in is on the same layer as the plurality of first connection traces 107, and Figure 7 the second connection pattern 113 shown in is on the same layer as the plurality of second connection traces 108. Thus, the source-drain metal layer, the first insulating layer 109, the plurality of first connection traces 107, the second insulating layer 110, the plurality of second connection traces 108, the third insulating layer 111, and the dummy electrode pattern 106 are stacked in sequence in a direction away from the substrate 101. That is, the first insulating layer 109 is on the side of the source-drain metal layer away from the substrate 101, the plurality of first connection traces 107 are on the side of the first insulating layer 109 away from the substrate 101, the second insulating layer 110 is on the side of the plurality of first connection traces 107 away from the substrate 101, the plurality of second connection traces 108 are on the side of the second insulating layer 110 away from the substrate 101, the third insulating layer 111 is on the side of the plurality of second connection traces 108 away from the substrate 101, and the dummy electrode pattern 106 is on the side of the third insulating layer 111 away from the plurality of second connection traces 108.

[0133] In the embodiment of the present application, the plurality of dummy electrode patterns 106 at least include: a first dummy electrode pattern and a second dummy electrode pattern. Among them, the first dummy electrode pattern and the second dummy electrode pattern are two different dummy electrode patterns.

[0134] Figure 8It is a partial schematic diagram of the first connection trace and the second insulating layer provided by an embodiment of the present application. Refer to Figure 8 , the second insulating layer 110 may have a plurality of first vias ( Figure 8 One first via 110a is shown in ). And, the first via 110a may be used to expose a first connection trace 107 located on a side of the second insulating layer 110 close to the substrate 101. Figure 9 It is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application. Refer to Figure 9 , the third insulating layer 111 may have third vias 111a corresponding one-to-one to the plurality of first vias 110a ( Figure 9 One third via 111a is shown in ).

[0135] Among them, the orthographic projection of each first via 110a on the substrate 101 may at least partially overlap with the orthographic projection of the corresponding third via 111a on the substrate 101. For example, in combination with Figure 8 and Figure 9 , the orthographic projection of the third via 111a on the substrate 101 is located within the orthographic projection of the corresponding first via 110a on the substrate 101.

[0136] Figure 10 It is a schematic diagram of a first connection trace and a dummy electrode pattern provided by an embodiment of the present application. In combination with Figures 8 to 9 , at least a part of the first connection portion 1062 of the first dummy electrode pattern among the plurality of dummy electrode patterns 106 may be located within the third via 111a and the first via 110a, and is electrically connected to the first connection trace 107 through the third via 111a and the first via 110a.

[0137] Figure 11 It is a schematic diagram of a second connection trace and a second insulating layer provided by an embodiment of the present application. Refer to Figure 11 , the second insulating layer 110 may have a plurality of second vias 110b ( Figure 11 One second via 110b is shown in ). And, at least a part of each second connection trace 108 may be located within the second via 110b. Figure 12 It is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application. Refer to Figure 12 , the third insulating layer 111 may have fourth vias 111b corresponding one-to-one to the plurality of second vias 110b ( Figure 12 One fourth via 111b is shown in ). The fourth via 111b is used to expose a second connection trace 108.

[0138] Figure 13It is a schematic diagram of a second connection trace and a dummy electrode pattern provided by an embodiment of the present application. Combining Figures 11 to 13 , at least a part of the first connection portion 1062 of the second dummy electrode pattern among the plurality of dummy electrode patterns 106 may be located in the fourth via 111b and is electrically connected to the second connection trace 108 through the fourth via 111b.

[0139] In the embodiment of the present application, since the second connection trace 108 is located on the side of the second insulating layer 110 away from the substrate 101, whether the second via 110b is provided in the second insulating layer 110 does not affect the connection between the second connection trace 108 and the first connection portion 1062 of the second dummy electrode pattern. However, in order to save the manufacturing cost of the display panel 10, the second insulating layer 110 and the third insulating layer 111 may be fabricated using the same mask. Thus, at the position where the fourth via 111b is present in the third insulating layer 111, the second via 110b is also present at the corresponding position in the second insulating layer 110.

[0140] That is, combining Figures 11 to 13 , the orthographic projection of each second via 110b on the substrate 101 may at least partially overlap with the orthographic projection of the corresponding fourth via 111b on the substrate 101. For example, the orthographic projection of the fourth via 111b on the substrate 101 is located within the orthographic projection of the corresponding second via 110b on the substrate 101. Thus, the second dummy electrode pattern may be electrically connected to the portion of the second connection trace 108 located within the second via 110b.

[0141] Of course, if the manufacturing cost is not considered, the second insulating layer 110 may not need to be provided with a plurality of second vias 110b, and a plurality of second connection traces 108 may be directly formed on the side of the second insulating layer 110 away from the substrate 101.

[0142] According to the above description, the first connection portion 1062 of some of the plurality of dummy electrode patterns 106 (such as the first dummy electrode pattern) may be electrically connected to the first connection trace 107 through a via, and the first connection portion 1062 of another part of the dummy electrode patterns (such as the second dummy electrode pattern) may be electrically connected to the second connection trace 108 through a via.

[0143] Since the first connection portion 1062 of the first dummy electrode pattern is electrically connected to the first connection trace 107 through a via hole, there is an intersection between the first connection portion 1062 of the first dummy electrode pattern and the first connection trace 107, and the orthographic projection of this intersection on the substrate can overlap with the orthographic projection of the first connection portion 1062 of the first dummy electrode pattern on the substrate. Also, since the first connection portion 1062 of the second dummy electrode pattern is electrically connected to the second connection trace 108 through a via hole, there is an intersection between the first connection portion 1062 of the second dummy electrode pattern and the second connection trace 108, and the orthographic projection of this intersection on the substrate can overlap with the orthographic projection of the first connection portion 1062 of the second dummy electrode pattern on the substrate.

[0144] That is, the orthographic projection of the intersection on the substrate 101 can overlap with the orthographic projection of the first connection portion 1062 on the substrate 101.

[0145] Reference Figure 6 It can also be seen that the display panel 10 may further include: a plurality of second connection portions 114. The second connection portions 114 extend along the first direction X. Since the extending direction (the first direction X) of the second connection portions 114 intersects with the extending direction (the second direction Y) of the connection traces (the first connection trace 107 and the second connection trace 108), there is an intersection between the second connection portions 114 and at least one of the plurality of first connection traces 107 and the plurality of second connection traces 108. Thus, the second connection portions 114 and at least one of the plurality of first connection traces 107 and the plurality of second connection traces 108 are electrically connected through vias at the intersections, and the electrical connection between at least one of the connection traces and the second connection portions 114 can be achieved.

[0146] In the embodiment of the present application, the second connection portions 114 may be on the same layer as the source-drain metal layer of the second pixel circuit group 105. That is, the second connection portions 114 and the source-drain metal layer of the second pixel circuit group 105 may be prepared based on the same material and by the same patterning process.

[0147] To realize the connection between the second pixel circuit group 105 and at least one of the plurality of first connection traces 107 and the plurality of second connection traces 108, when preparing the second connection portions 114 and the source-drain metal layer, the second connection portions 114 and the drain of a transistor may be made into an integral structure. Thus, the electrical connection between at least one of the connection traces and the second pixel circuit group 105 can be achieved through the second connection portions 114.

[0148] In an embodiment of the present application, the second connection portion 114 and the dummy electrode pattern 106 are located in different layers. And the second connection portion 114 can be electrically connected to a dummy electrode pattern 106 through a via. That is, the signal transmitted in the dummy electrode pattern 106 can be the same as the signal transmitted in the second connection portion 114.

[0149] Figure 14 It is a schematic diagram of a second connection portion and a first insulating layer provided by an embodiment of the present application. Refer to Figure 14 , the first insulating layer 109 can have a plurality of fifth vias 109a ( Figure 14 One fifth via 109a is shown in ). And the fifth via 109a can be used to expose a second connection portion 114 located on the side of the first insulating layer 109 close to the substrate 101. Figure 15 It is a schematic diagram of a second connection portion and a first connection trace provided by an embodiment of the present application. Refer to Figure 15 , at least a part of the first connection trace 107 can be located in the fifth via 109a and is electrically connected to the second connection portion 114 through the fifth via 109a.

[0150] Figure 16 It is a schematic diagram of a second connection portion, a first insulating layer and a second insulating layer provided by an embodiment of the present application. Refer to Figure 16 , the first insulating layer 109 has a plurality of sixth vias 109b, and the second insulating layer 110 also has a plurality of sixth vias 110c. The plurality of sixth vias 109b in the first insulating layer 109 correspond to the plurality of sixth vias 110c in the second insulating layer 110 one by one. And each sixth via 109b in the first insulating layer 109 at least partially overlaps with a corresponding sixth via 110c in the second insulating layer 110.

[0151] For the convenience of description, the sixth via 109b in the first insulating layer 109 and a corresponding sixth via 110c in the second insulating layer 110 are collectively referred to as the sixth via. The sixth via (109b and 110c) is used to expose a second connection portion 114. Figure 17 It is a schematic diagram of a second connection trace and a second connection portion provided by an embodiment of the present application. Combining Figure 16 and Figure 17 , at least a part of the second connection portion 114 can be located in the sixth via and is electrically connected to the second connection trace 108 through the sixth via.

[0152] The second connecting portion 114 intersects with a connecting trace (the first connecting trace 107 or the second connecting trace 108), and the orthographic projection of the intersection on the substrate 101 may not overlap with the orthographic projection of any dummy electrode pattern 106 on the substrate 101 (for example Figure 6 the intersection w1 in Figure 6 ). Alternatively, the orthographic projection of the intersection on the substrate 101 is located within the orthographic projection of a dummy electrode pattern 106 on the substrate 101 (for example

[0153] Figure 18 is a partial schematic diagram of the first connecting trace and the second insulating layer provided by an embodiment of the present application. Refer to Figure 18 , the second insulating layer 110 may have a plurality of seventh vias 110d ( Figure 18 one seventh via 110d is shown in Figure 19 is a partial schematic diagram of a third insulating layer provided by an embodiment of the present application. Refer to Figure 19 , the third insulating layer 111 may have ninth vias 111c corresponding one-to-one to the plurality of seventh vias 110d ( Figure 19 one ninth via 111c is shown in

[0154] Among them, the orthographic projection of each seventh via 110d on the substrate 101 may at least partially overlap with the orthographic projection of the corresponding ninth via 111c on the substrate 101. For example, in combination with Figure 18 and Figure 19 , the orthographic projection of the ninth via 111c on the substrate 101 is located within the orthographic projection of the corresponding seventh via 110d on the substrate 101.

[0155] Figure 20 is a schematic diagram of a first connecting trace and a first electrode of a second light-emitting unit provided by an embodiment of the present application. In combination with Figures 18 to 20 , at least a part of the first electrode 1041 of at least one second light-emitting unit 104 may be located within the seventh via 110d and the ninth via 111c, and is electrically connected to the first connecting trace 107 through the seventh via 110d and the ninth via 111c.

[0156] Figure 21 is a schematic diagram of a second connecting trace and a second insulating layer provided by an embodiment of the present application. Refer to Figure 21 , the second insulating layer 110 may have a plurality of eighth vias 110e ( Figure 21An eighth via 110e is shown. And at least part of each second connection trace 108 can be located within the eighth via 110e. Figure 22 is a schematic diagram of another third insulating layer provided by an embodiment of the present application. Refer to Figure 22 , the third insulating layer 111 can have tenth vias 111d that correspond one-to-one with a plurality of eighth vias 110e ( Figure 22 in which a tenth via 111d is shown). The tenth via 111d is used to expose a second connection trace 108.

[0157] Figure 23 is a schematic diagram of a second connection trace and a first electrode of a second light-emitting unit provided by an embodiment of the present application. Combining Figures 21 to 23 , at least part of the first electrode 1041 of at least one second light-emitting unit 104 can be located within the tenth via 111d and is electrically connected to the second connection trace 108 through the tenth via 111d.

[0158] In the embodiment of the present application, since the second connection trace 108 is located on the side of the second insulating layer 110 away from the substrate 101, whether there is an eighth via 110e in the second insulating layer 110 does not affect the connection between the second connection trace 108 and the first electrode of the second light-emitting unit 104. However, in order to save the manufacturing cost of the display panel 10, the second insulating layer 110 and the third insulating layer 111 can be fabricated using the same mask. Thus, at the position where the third insulating layer 111 has the tenth via 111d, the second insulating layer 110 also has an eighth via 110e at the corresponding position.

[0159] That is to say, combining Figures 21 to 23 , the orthographic projection of each eighth via 110e on the substrate 101 can at least partially overlap with the orthographic projection of the corresponding tenth via 111d on the substrate 101. For example, the orthographic projection of the eighth via 110e on the substrate 101 is located within the orthographic projection of the corresponding tenth via 111d on the substrate 101. Thus, the first electrode 1041 of the second light-emitting unit 104 can be electrically connected to the part of the second connection trace 108 located within the eighth via 110e.

[0160] According to the above description, the first electrodes 1041 of some of the second light-emitting units 104 among the plurality of second light-emitting units 104 can be electrically connected to the first connection trace 107 through vias, and the first electrodes 1041 of another part of the second light-emitting units 104 can be electrically connected to the second connection trace 108 through vias.

[0161] Refer to Figure 7, the display panel 10 may further include: a plurality of first connection patterns 112 and a plurality of second connection patterns 113 corresponding to the plurality of first connection patterns 112 one by one. Figure 7 One first connection pattern 112 and one second connection pattern 113 are shown.

[0162] Figure 24 It is a schematic diagram of a first insulating layer and a first connection pattern provided by an embodiment of the present application. Figure 25 It is a schematic diagram of a second insulating layer and a second connection pattern provided by an embodiment of the present application. Figure 26 It is a schematic diagram of yet another third insulating layer provided by an embodiment of the present application. Refer to Figures 24 to 26 It can be seen that the first insulating layer 109 may have a plurality of eleventh vias 109c, the second insulating layer 110 may have a plurality of twelfth vias 110f corresponding to the plurality of eleventh vias 109c one by one, and the third insulating layer 111 has a plurality of thirteenth vias 111e corresponding to the plurality of twelfth vias 110f one by one. Among them, the orthographic projection of each eleventh via 109c on the substrate 101 overlaps at least partially with the orthographic projection of the corresponding twelfth via 110f on the substrate 101. The orthographic projection of each twelfth via 110f on the substrate 101 overlaps at least partially with the orthographic projection of the corresponding thirteenth via 111e on the substrate 101.

[0163] Combined with Figure 7 , and Figures 24 to 26 , each eleventh via 109c is used to expose the drain of a transistor in a second pixel circuit group 105. At least a part of a first connection pattern 112 is located in the eleventh via 109c and is electrically connected to the drain A through the eleventh via 109c. Each twelfth via 110f is used to expose a first connection pattern 112. At least a part of a second connection pattern 113 corresponding to the first connection pattern 112 may be located in the twelfth via 110f and is electrically connected to the first connection pattern 112 through the twelfth via 110f. Each thirteenth via 111e is used to expose a second connection pattern 113. At least a part of a dummy electrode pattern 106 is located in the thirteenth via 111e and is connected to the second connection pattern 113 through the thirteenth via 111e. That is to say, the dummy electrode pattern 106 can be connected to the drain A of the second pixel circuit group 105 through the second connection pattern 113 and the first connection pattern 112.

[0164] Optionally, the orthographic projection of the twelfth via 110f on the substrate 101 is located within the orthographic projection of the eleventh via 109c on the substrate 101, and the orthographic projection of the thirteenth via 111e on the substrate 101 is located within the orthographic projection of the twelfth via 110f on the substrate 101.

[0165] In an embodiment of the present application, the first pixel circuit group 103 may also include a source-drain metal layer located on the substrate 101. The source-drain metal layer includes a source electrode and a drain electrode that are spaced apart. Figure 27 It is a schematic structural diagram of a first light-emitting unit provided by an embodiment of the present application. Refer to Figure 27 , the first light-emitting unit 102 may include a first electrode a1, a light-emitting layer a2, and a second electrode a3 that are sequentially stacked in a direction away from the substrate 101. Among them, the first electrode a1 may be an anode, and the second electrode a3 may be a cathode. The drain electrode of the first pixel circuit group 103 may be electrically connected to the first electrode a1 of the first light-emitting unit 102.

[0166] Optionally, a plurality of dummy electrode patterns 106 may be in the same layer as the first electrode a1 in the first light-emitting unit 102. That is, the dummy electrode pattern 106 may be a dummy anode pattern. In this case, the connection schematic of the drain electrode of a transistor in the first pixel circuit group 103 to the first electrode a1 of the first light-emitting unit 102 may refer to the above Figure 7 . For example, by replacing the second pixel circuit group 105 in Figure 7 with the first pixel circuit group 103, and replacing the dummy electrode pattern 106 in Figure 7 with the first electrode a1 of the first light-emitting unit 102, Figure 7 it can be used to represent the connection relationship between the drain electrode of a transistor in the first pixel circuit group 103 and the first electrode a1 of the first light-emitting unit 102.

[0167] Refer to Figure 27 It can be seen that the first light-emitting unit 102 may further include a pixel defining layer a4 located between the first electrode a1 and the light-emitting layer a2. Refer to Figure 2 , Figure 4 and Figure 6 , the pixel defining layer a4 may have a plurality of openings a41, and each opening a41 may be used to expose the first electrode a1 of a first light-emitting unit 102. Moreover, the orthographic projection of the plurality of openings a41 on the substrate 101 does not overlap with the orthographic projection of any dummy electrode pattern 106 on the substrate 101.

[0168] By making the opening a41 of the pixel defining layer a4 expose the first electrode a1 of the first light-emitting unit 102, the first electrode a1 of the first light-emitting unit 102 can be in contact with the light-emitting layer a2 to achieve light emission. Since the orthographic projection of the plurality of openings a41 on the substrate 101 does not overlap with the orthographic projection of any dummy electrode pattern 106 on the substrate 101, no light is emitted at the dummy electrode pattern 106.

[0169] It should be noted that, for the sake of illustration, the light-emitting layer and the cathode layer are not shown in the top views provided in the embodiments of the present application. Only the opening a41 of the pixel definition layer a4 is used to distinguish the first electrode a1 of the first light-emitting unit 102 and the dummy electrode pattern 106. For example Figure 2 in Figure 2 , the pattern with the opening a41 of the pixel definition layer a4 is the first electrode a1, and the pattern without the opening a41 of the pixel definition layer a4 is the dummy electrode pattern 106.

[0170] In the embodiments of the present application, the multiple first light-emitting units 102 include: first light-emitting units of multiple first colors, first light-emitting units of multiple second colors, and first light-emitting units of multiple third colors. Among them, at least one first light-emitting unit of the first color, at least one first light-emitting unit of the second color, and at least one first light-emitting unit of the third color in the multiple first light-emitting units 102 form a light-emitting unit group b. Among them, the first color, the second color, and the third color can be the three primary colors. For example, the first color is red (R), the second color is green (G), and the third color is blue (B).

[0171] Moreover, the multiple dummy electrode patterns 106 form at least one dummy electrode pattern group c. The number of dummy electrode patterns 106 included in each dummy electrode pattern group c is equal to the number of first light-emitting units 102 included in a light-emitting unit group b.

[0172] Exemplarily, referring to Figure 28 , each light-emitting unit group b includes: one first light-emitting unit b1 of the first color, two first light-emitting units of the second color (b21 and b22), and one first light-emitting unit b3 of the third color. Among them, the two first light-emitting units of the second color (b21 and b22) can be collectively referred to as the first light-emitting unit pair b2 of the second color. That is to say, each light-emitting unit group b includes four first light-emitting units 102, and each dummy electrode pattern group c can also include four dummy electrode patterns 106.

[0173] In the embodiments of the present application, the multiple dummy electrode patterns 106 included in each dummy electrode pattern group c can correspond one-to-one to the multiple first light-emitting units 102 in a light-emitting unit group b, and the shape and area of each dummy electrode pattern 106 are the same as those of the first electrode a1 in the corresponding first light-emitting unit 102.

[0174] Since the dummy electrode pattern 106 has the same shape and area as the first electrode a1 in the corresponding first light-emitting unit 102, the overlapping area between the first electrode a1 in the first display area 101a and the connection trace can be made the same as the overlapping area between the dummy electrode pattern 106 and the connection trace. Furthermore, the overlapping capacitances between the first electrode a1 in the first display area 101a and the dummy electrode pattern 106 and the connection trace are made consistent, ensuring the display effect of the display panel 10. Herein, the first connection trace 107 and the second connection trace 108 are collectively referred to as connection traces.

[0175] In the embodiment of the present application, referring to Figure 29 , the multiple second light-emitting units 104 may also include: second light-emitting units of multiple first colors, second light-emitting units of multiple second colors, and second light-emitting units of multiple third colors. Among them, at least one second light-emitting unit of the first color, at least one second light-emitting unit of the second color, and at least one second light-emitting unit of the third color in the multiple second light-emitting units 104 may also form a light-emitting unit group b.

[0176] Among them, the number of dummy electrode patterns 106 included in each dummy electrode pattern group c may also be equal to the number of second light-emitting units 104 included in a light-emitting unit group b. By way of example, each light-emitting unit group b includes: one second light-emitting unit b1 of the first color, two second light-emitting units (b21 and b22) of the second color, and one second light-emitting unit b3 of the third color. Among them, the two second light-emitting units (b21 and b22) of the second color may be collectively referred to as the second-color second-light-emitting unit pair b2.

[0177] In the embodiment of the present application, referring to Figure 3 , the substrate 101 includes two first display areas 101a. The two first display areas 101a are respectively located on both sides of the second display area 101b. The substrate 101 further includes: a first peripheral area 101d and a second peripheral area 101e. The first peripheral area 101d and the second peripheral area 101e are respectively located on both sides of the two first display areas 101a. That is, the first peripheral area 101d, a first display area 101a, the second display area 101b, another first display area 101a, and the second peripheral area 101e are arranged along the second direction Y. For example, the first peripheral area 101d is located on the left side of the axis of the substrate 101 along the first direction X, and the second peripheral area 101e is located on the right side of the axis of the substrate 101 along the first direction X.

[0178] Figure 30 is a schematic structural diagram of another display panel provided by the embodiment of the present application. Referring to Figure 30It can be seen that the display panel 10 may further include: a first row driving circuit 115 located in the first peripheral region 101d and a second row driving circuit 116 located in the second peripheral region 101e. The first row driving circuit 115 is electrically connected to the first pixel circuit group 103 and the second pixel circuit group 105 in a first display area 101a. The second row driving circuit 116 is electrically connected to the first pixel circuit group 103 and the second pixel circuit group 105 in another first display area 101a. Among them, the first pixel circuit group 103 and the second pixel circuit group 105 electrically connected to the first row driving circuit 115 are located in a first display area 101a on the left side of the axis of the substrate 101 along the first direction X. The first pixel circuit group 103 and the second pixel circuit group 105 electrically connected to the second row driving circuit 116 are located in another first display area 101a on the right side of the axis of the substrate 101 along the first direction X.

[0179] For ease of understanding, a first display area 101a located on the left side of the axis of the substrate 101 along the first direction X may be referred to as the left first display area 101a, and another first display area 101a located on the right side of the axis of the substrate 101 along the first direction X may be referred to as the right first display area 101a. Refer to Figure 30 , the first row driving circuit 115 may be electrically connected to each pixel circuit group in the left first display area 101a, so as to provide a row driving signal for each pixel circuit group in the left first display area 101a. And the first row driving circuit 115 is not electrically connected to any pixel circuit group in the right first display area 101a. The second row driving circuit 116 may be electrically connected to each pixel circuit group in the right first display area 101a, so as to provide a row driving signal for each pixel circuit group in the right first display area 101a. And the second row driving circuit 116 is not electrically connected to any pixel circuit group in the left first display area 101a.

[0180] That is to say, in the embodiment of the present application, the pixel circuit groups in the left first display area 101a and the pixel circuit groups in the right first display area 101a are driven by different row driving circuits, and the row driving signals provided to the pixel circuit groups in the two first display areas 101a do not affect each other.

[0181] Refer to Figure 30 It can also be seen that the display panel 10 may further include: a plurality of first scanning signal lines 117 located in a first display area 101a, and a plurality of second scanning signal lines 118 located in another first display area 101a. Among them, the plurality of first scanning signal lines 117 and the plurality of second scanning signal lines 118 can both extend along the second direction Y.

[0182] The first row driving circuit 115 can be electrically connected to a plurality of first scanning signal lines 117, and through the plurality of first scanning signal lines 117, it is electrically connected to the first pixel circuit group 103 and the second pixel circuit group 105 in a first display area 101a. The second row driving circuit 116 can be electrically connected to a plurality of second scanning signal lines 118, and through the plurality of second scanning signal lines 118, it is electrically connected to the first pixel circuit group 103 and the second pixel circuit group 105 in another first display area 101a.

[0183] Among them, the plurality of first scanning signal lines 117 and the plurality of second scanning signal lines 118 can be on the same layer, and the orthographic projections of the plurality of first scanning signal lines 117 on the substrate 101 and the orthographic projections of the plurality of second scanning signal lines 118 on the substrate 101 are both outside the second display area 101b. That is to say, neither the plurality of first scanning signal lines 117 nor the plurality of second scanning signal lines 118 is located in the second display area 101b, thereby ensuring the transmittance of the second display area 101b.

[0184] In the embodiment of the present application, the number of the first scanning signal lines 117 included in the display panel 10 can be the same as the number of rows of pixel circuits included in the first pixel circuit group 103 and the second pixel circuit group 105 in a first display area 101a (the left first display area 101a). The number of the second scanning signal lines 118 included in the display panel 10 can be the same as the number of rows of pixel circuits included in the first pixel circuit group 103 and the second pixel circuit group 105 in another first display area 101a (the right first display area 101a).

[0185] Reference Figure 3 It can also be seen that the substrate 101 can further include: a third display area 101c and a third peripheral area 101f. The third display area 101c is located on the same side of the first display area 101a and the second display area 101b, and the third peripheral area 101f is located on the same side of the first display area 101a and the second display area 101b. Moreover, the first peripheral area 101d and the second peripheral area 101e are located on both sides of the third display area 101c along the second direction Y.

[0186] Reference Figure 3, the substrate 101 includes two first display areas 101a. The shapes of the first display area 101a and the second display area 101b are both rectangular. Among them, both the first display area 101a and the second display area 101b are located at the edge of the display area. The first display area 101a, the second display area 101b, and the third display area 101c are collectively referred to as the display area. The edges of the first display area 101a and the second display area 101b that are far from the third display area 101c are connected to the third peripheral area 101f. One edge of the second display area 101b extending along the second direction Y is connected to the third display area 101c, and the other edge is connected to the third peripheral area 101f. The two edges of the second display area 101b extending along the first direction X are respectively connected to the two first display areas 101a.

[0187] Reference Figure 1 , the display panel 10 may further include: a plurality of third light-emitting units 119 located in the third display area 101c, and a plurality of third pixel circuit groups 120 connected to the plurality of third light-emitting units 119 in a one-to-one correspondence. The first row driving circuit 115 located in the first peripheral area 101d and the second row driving circuit 116 located in the second peripheral area 101e are both connected to the third pixel circuit group 120 in the third display area 101c. That is, both the first row driving circuit 115 and the second row driving circuit 116 can provide row driving signals for the third pixel circuit group 120, and the third pixel circuit group 120 in the third display area 101c can be driven by two row driving circuits.

[0188] Exemplarily, the display panel 10 may include a plurality of third scanning signal lines 121. One end of each third scanning signal line 121 is connected to the first row driving circuit 115, the other end is connected to the second row driving circuit 116, and the third scanning signal is also connected to the third pixel circuit group 120.

[0189] Optionally, the density of the plurality of third light-emitting units 119 is greater than the density of the plurality of first light-emitting units 102 and greater than the density of the plurality of second light-emitting units 104. The density (i.e., pixel density) of the second light-emitting units 104 in the under-screen camera area (the central area 101b1 of the second display area 101b) is lower than the density of the third light-emitting units 119 in the normal display area (the third display area 101c), so the camera can be disposed below the low pixel density area that allows more light to pass through. The above "the density of the plurality of third light-emitting units 119 is greater than the density of the plurality of first light-emitting units 102 and greater than the density of the plurality of second light-emitting units 104" means that the number of third light-emitting units 119 is greater than the number of second light-emitting units 104 and greater than the number of first light-emitting units 102 under the same area.

[0190] In the embodiment of the present application, the third display area 101c is the main display area with a relatively high resolution (pixels per inch, PPI), that is, a relatively high density of third light-emitting units 119 for display are arranged in the third display area 101c. Each third light-emitting unit 119 corresponds to a third pixel circuit group 120, and each third light-emitting unit 119 is driven to emit light through a corresponding third pixel circuit group 120. The second display area 101b may allow the light incident from the display side of the display panel 10 to pass through the display panel 10 and reach the back side of the display panel 10, so as to enable the normal operation of components such as sensors located on the back side of the display panel 10. The embodiment of the present application is not limited thereto. For example, the second display area 101b may also allow the light emitted from the back side of the display panel 10 to pass through the display panel 10 and reach the display side of the display panel 10. The first display area 101a and the second display area 101b also include a plurality of light-emitting units for display. However, since the pixel circuit group for driving the light-emitting unit to emit light is usually opaque, in order to improve the transmittance of the central area 101b1 of the second display area 101b, the light-emitting unit in the second display area 101b and the pixel circuit group for driving the light-emitting unit may be physically separated. For example, the second pixel circuit group 105 connected to the light-emitting unit (such as Figure 1 the second light-emitting unit 104 in the second display area 101b) in the second display area 101b may be arranged in the first display area 101a. That is, the second pixel circuit group 105 will occupy a part of the space in the first display area 101a. And the remaining space in the first display area 101a is used to arrange the first light-emitting unit 102 and the first pixel circuit group 103 in the first display area 101a. For example Figure 1 each dot-filled square box in the first display area 101a represents a pixel circuit group. If the pixel circuit group represented by a certain filled square box is the first pixel circuit group 103, then the filled square box may also represent the first light-emitting unit 102. In this case, the first pixel circuit group 103 (or the first light-emitting unit 102) in the first display area 101a and the second pixel circuit group 105 connected to the second light-emitting unit 104 in the second display area 101b are arranged in an array in the first display area 101a. Thus, the resolution of the first display area 101a and the second display area 101b is lower than that of the third display area 101c, that is, the pixel density of the third display area 101c is greater than the pixel density of the first display area 101a and greater than the pixel density of the second display area 101b.

[0191] In the embodiment of the present application, refer to Figure 1 and Figure 30, the display panel 10 may further include: a plurality of data lines 122. When the shape of the second display area 101b is rectangular, the orthographic projection of the portion of each data line 122 located in the second display area 101b on the substrate 101 may be a straight line or a broken line, and is located in the area of the second display area 101b close to the first display area 101a. That is, the portion of each data line 122 located in the second display area 101b may be designed along the edge of the second display area 101b.

[0192] Optionally, in combination with Figure 31 and Figure 32 , the orthographic projection of the portion of each data line 122 located in the second display area 101b on the substrate 101 may include a first line segment 1221, a second line segment 1222, and a third line segment 1223 that are connected in sequence. Among them, the extension directions of the first line segment 1221 and the third line segment 1223 are both the second direction Y, and the extension direction of the second line segment 1222 is the first direction X. Moreover, the first line segment 1221 is located on the side of the second display area 101b close to the third display area 101c, the second line segment 1222 is located on the side of the second display area 101b close to the first display area 101a, and the third line segment 1223 is located on the side of the second display area 101b close to the third peripheral area 101f.

[0193] Referring to Figure 32 , each data line 122 may also be located in the third peripheral area 101f, and the portion of each data line 122 located in the third peripheral area 101f may be connected to the third line segment 1223 of the data line 122.

[0194] Figure 33 is a partial schematic diagram of a first connection trace and a second connection trace provided by an embodiment of the present application. Referring to Figure 33 It can be seen that the connection lines of the other ends of the plurality of first connection traces 107, and the connection lines of the other ends of the plurality of second connection traces 108 are both parallel to the edge of the first display area 101a away from the second display area 101b, and the distances between the connection lines of the other ends of the plurality of first connection traces 107, and the connection lines of the other ends of the plurality of second connection traces 108 and the edge of the first display area 101a away from the second display area 101b are both less than the distance threshold.

[0195] The other end of the first connection trace 107 can be the end of the two ends of the first connection trace 107 that is far from the second display area 101b. The other end of the second connection trace 108 can be the end of the two ends of the second connection trace 108 that is far from the second display area 101b. By designing the distance between the connection line of the other ends of the plurality of first connection traces 107 and the edge of the first display area 101a far from the second display area 101b to be small, and designing the distance between the connection line of the other ends of the plurality of second connection traces 108 and the edge of the first display area 101a far from the second display area 101b to be small, connection traces can exist everywhere in the first display area 101a. Thus, the overlapping capacitors everywhere in the first display area 101a can be made consistent, ensuring the uniformity of the display effect of the first display area 101a. Among them, Figure 33 The connection line of the other ends of the plurality of first connection traces 107 and the connection line of the other ends of the plurality of second connection traces 108 shown in

[0196] Optionally, the connection line of the other ends of the plurality of first connection traces 107, the connection line of the other ends of the plurality of second connection traces 108, and the edge of the first display area 101a far from the second display area 101b can all be substantially parallel to the first direction X. The connection line of the other ends of the plurality of first connection traces 107, the connection line of the other ends of the plurality of second connection traces 108, and the edge of the first display area 101a far from the second display area 101b are collinear. That is to say, the other ends of the plurality of first connection traces 107 and the other ends of the plurality of second connection traces 108 can both extend to the edge of the first display area 101a far from the second display area 101b.

[0197] In the embodiments of the present application, "substantially" means that an error range within 15% is allowed. For example, "substantially parallel" can mean that the included angle between the two is between 0 degrees and 30 degrees, such as it can be between 0 degrees and 10 degrees, 0 degrees and 15 degrees, etc.

[0198] In the embodiments of the present application, since the number of the first light-emitting units 102 that can emit light in the first display area 101a is small, while the number of the third light-emitting units 119 that can emit light in the third display area 101c is large, it may cause the display brightness of the first display area 101a to be lower than that of the third display area 101c. Thus, in order to improve the display brightness of the first display area 101a, each first light-emitting unit 102 can be driven by at least two pixel circuits, thereby improving the brightness of the first light-emitting unit 102 and ensuring the consistency of the display effects of the first display area 101a and the third display area 101c.

[0199] Optionally, referring to Figure 30, the first pixel circuit group 103 may include: a first pixel circuit 1031. The first pixel circuit 1031 in each first pixel circuit group 103 is configured to be electrically connected to at least one first light-emitting unit 102. The second pixel circuit group 105 may include: a second pixel circuit 1051. The second pixel circuit 1052 included in each second pixel circuit group 105 is configured to be electrically connected to at least one second light-emitting unit 104.

[0200] If the first pixel circuit group 103 only includes the first pixel circuit 1031 and does not include other pixel circuits, and the first pixel circuit is configured to be electrically connected to one first light-emitting unit 102, then the first light-emitting unit 102 can be driven by one pixel circuit. Correspondingly, if the second pixel circuit group 105 only includes the second pixel circuit 1051 and does not include other pixel circuits, and the second pixel circuit is configured to be electrically connected to one second light-emitting unit 104, then the second light-emitting unit 104 can be driven by one pixel circuit.

[0201] If the first pixel circuit group 103 only includes the first pixel circuit 1031 and does not include other pixel circuits, and the first pixel circuit is configured to be electrically connected to a plurality of first light-emitting units 102 (for example, two first light-emitting units 102), then the plurality of first light-emitting units 102 can be driven by the same pixel circuit. Correspondingly, if the second pixel circuit group 105 only includes the second pixel circuit 1051 and does not include other pixel circuits, and the second pixel circuit is configured to be electrically connected to a plurality of second light-emitting units 104 (for example, two second light-emitting units 104), then the plurality of second light-emitting units 104 can be driven by the same pixel circuit.

[0202] Optionally, referring to Figure 34 , each first pixel circuit group 103 may further include: at least one third pixel circuit 1032. At least two pixel circuits in each first pixel circuit group 103 are configured to be electrically connected to the same first light-emitting unit 103. Each second pixel circuit group 105 may further include: at least one fourth pixel circuit 1052. At least two pixel circuits in each second pixel circuit group 105 are configured to be electrically connected to the same second light-emitting unit 104.

[0203] If the first pixel circuit group 103 includes a first pixel circuit 1031 and a third pixel circuit 1032, and the first pixel circuit 1031 and the third pixel circuit 1032 are configured to be electrically connected to the same first light-emitting unit 102, then the first light-emitting unit 102 can be driven by two pixel circuits. Correspondingly, if the second pixel circuit 1051 and the fourth pixel circuit 1052 are configured to be electrically connected to one second light-emitting unit 104, then the second light-emitting unit 104 can be driven by two pixel circuits.

[0204] If the first pixel circuit group 103 includes a first pixel circuit 1031 and a plurality of third pixel circuits 1032, and the first pixel circuit 1031 and the plurality of third pixel circuits 1032 are configured to be electrically connected to the same first light-emitting unit 102, then the first light-emitting unit 102 can be driven by a plurality of pixel circuits. Correspondingly, if the second pixel circuit group 105 includes a second pixel circuit 1051 and a plurality of fourth pixel circuits 1052, and the second pixel circuit 1051 and the fourth pixel circuits 1052 are configured to be electrically connected to the same second light-emitting unit 104, then the second light-emitting unit 104 can be driven by a plurality of pixel circuits.

[0205] In the embodiments of the present application, the electrical connection between the pixel circuit and the light-emitting unit may mean that the pixel circuit is electrically connected to the first electrode of the light-emitting unit. For example, at least two pixel circuits in the first pixel circuit group 103 being configured to be electrically connected to the same first light-emitting unit 102 may mean that at least two pixel circuits in the first pixel circuit group 103 are configured to be electrically connected to the first electrode a1 of the same first light-emitting unit 102.

[0206] Optionally, taking the first pixel circuit group 103 including a first pixel circuit 1031 and a third pixel circuit 1032, and the second pixel circuit group 105 including a second pixel circuit 1051 and a fourth pixel circuit 1052 as an example for illustration.

[0207] Reference Figure 35 , the first electrode a1 of the first light-emitting unit 102 includes a first pattern 102-1 and a second pattern 102-2. The second pattern 102-2 can be used to be electrically connected to at least two pixel circuits in the first pixel circuit group 103. Among them, the second pattern 102-2 is the connection part between the first electrode a1 of the first light-emitting unit 102 and the first pixel circuit group 103.

[0208] The orthographic projection of the connection part (second pattern 102-2) between the first electrode a1 of the first light-emitting unit 102 and the first pixel circuit group 103 on the substrate 101 does not overlap with the orthographic projection of the plurality of first connection traces 107 on the substrate 101, and does not overlap with the orthographic projection of the plurality of second connection traces 108 on the substrate 101. Thus, it can be ensured that the connection part between the first electrode a1 and the first pixel circuit group 103 is not affected by the first connection traces 107 and the second connection traces 108, and the normal light emission of the first light-emitting unit 102 connected to the first pixel circuit group 103 can be ensured.

[0209] In an embodiment of the present application, in order to ensure the transmittance of the second display area 101b, usually the number of the second light-emitting units 104 provided in the second display area 101b is small. Therefore, the display brightness of the second display area 101b may be lower than that of the third display area 101c. Thus, in order to improve the display brightness of the second display area 101b, each second light-emitting unit 104 can be driven by at least two pixel circuits, so as to improve the brightness of the second light-emitting unit 104 and ensure the consistency of the display effects of the second display area 101b and the third display area 101c.

[0210] Reference Figure 35 , the dummy electrode pattern 106 includes a third pattern 106-1 and a fourth pattern 106-2. The fourth pattern 106-2 can be used to be electrically connected to at least two pixel circuits in the second pixel circuit group 105. Wherein, the fourth pattern 106-2 is the connection part of the dummy electrode pattern 106 and the first pixel circuit group 103.

[0211] The orthographic projection of the connection part (the fourth pattern 106-2) of the dummy electrode pattern 106 and the second pixel circuit group 105 on the substrate 101 does not overlap with the orthographic projection of the plurality of first connection traces 107 on the substrate 101, and does not overlap with the orthographic projection of the plurality of second connection traces 108 on the substrate 101. Thus, the connection part of the dummy electrode pattern 106 and the first pixel circuit group 103 will not be affected by the first connection traces 107 and the second connection traces 108, and it can be ensured that the second pixel circuit group 105 drives the second light-emitting unit 104 to emit light normally through the dummy electrode pattern 106.

[0212] In an embodiment of the present application, the structures of the first pixel circuit group 103 and the second pixel circuit group 105 may be the same. For example, both include two pixel circuits. The first pixel circuit group 103 and the second pixel circuit group 105 can both be referred to as a pixel circuit pair f. For the convenience of subsequent description, each of the two pixel circuits included in the first pixel circuit group 103 and the second pixel circuit group 105 can be referred to as a first pixel circuit and a second pixel circuit. That is, for the convenience of description, the third pixel circuit 1032 included in the first pixel circuit group 103 can be referred to as a second pixel circuit, the second pixel circuit 1051 included in the second pixel circuit group 105 can be referred to as a first pixel circuit, and the fourth pixel circuit 1052 included in the second pixel circuit group 105 can be referred to as a second pixel circuit.

[0213] Figure 36 is an equivalent circuit diagram of a first pixel circuit group or a second pixel circuit group provided in an embodiment of the present application. Reference Figure 36, at least two pixel circuits in the first pixel circuit group 103 are configured to be electrically connected to the same first light-emitting unit 102. At least two pixel circuits in the second pixel circuit group 105 are configured to be electrically connected to the same second light-emitting unit 104.

[0214] Optionally, the display panel 10 further includes a reset power signal line, a data signal line, a scan signal line, a power signal line, a reset control signal line, and a light-emitting control signal line located on the substrate 101. As Figure 36 shown, each pixel circuit (the first pixel circuit f1 and the second pixel circuit f2) includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. A first pole of the threshold compensation transistor T2 is connected to a first pole of the driving transistor T3, a second pole of the threshold compensation transistor T2 is connected to a gate of the driving transistor T3, a first pole of the first reset control transistor T7 is connected to the reset power signal line to receive a reset signal Vinit, a second pole of the first reset control transistor T7 is connected to the light-emitting unit, and a first pole of the data writing transistor T4 is connected to a second pole of the driving transistor T3. For example, as Figure 36 shown, the pixel circuit of each pixel unit further includes a storage capacitor C, a first light-emitting control transistor T6, a second light-emitting control transistor T5, and a second reset transistor T1. A gate of the data writing transistor T4 is electrically connected to the scan signal line to receive a scan signal Gate; a first pole of the storage capacitor C is electrically connected to the power signal line, a second pole of the storage capacitor C is electrically connected to a gate of the driving transistor T3; a gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive a compensation control signal; a gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive a reset control signal Reset; a first pole of the second reset transistor T1 is electrically connected to the reset power signal line to receive a reset signal Vinit, a second pole of the second reset transistor T1 is electrically connected to a gate of the driving transistor T3, and a gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive a reset control signal Reset; a gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive a light-emitting control signal EM; a first pole of the second light-emitting control transistor T5 is electrically connected to the power signal line, a second pole of the second light-emitting control transistor T5 is electrically connected to a second pole of the driving transistor T3, and a gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive a light-emitting control signal EM. The above-mentioned power signal line refers to a signal line for outputting a voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0215] Optionally, the scan signal and the compensation control signal can be the same, that is, the gates of the data writing transistor T3 and the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gates of the data writing transistor T3 and the threshold compensation transistor T2 can also be electrically connected to different signal lines respectively, that is, the gate of the data writing transistor T3 is electrically connected to the first scan signal line, and the gate of the threshold compensation transistor T2 is electrically connected to the second scan signal line, and the signals transmitted by the first scan signal line and the second scan signal line can be the same or different, so that the gates of the data writing transistor T3 and the threshold compensation transistor T2 can be separately controlled, increasing the flexibility of controlling the pixel circuit.

[0216] Optionally, the light emission control signals input to the first light emission control transistor T6 and the second light emission control transistor T5 can be the same, that is, the gates of the first light emission control transistor T6 and the second light emission control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. The gates of the first light emission control transistor T6 and the second light emission control transistor T5 can also be electrically connected to different light emission control signal lines respectively, and the signals transmitted by the different light emission control signal lines can be the same or different.

[0217] Optionally, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 can be the same, that is, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gates of the first reset transistor T7 and the second reset transistor T1 can also be electrically connected to different reset control signal lines respectively. At this time, the signals on the different reset control signal lines can be the same or different.

[0218] Such as Figure 36As shown, when the display panel 10 is working, in the first stage of the screen display, the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage, the same data signal Data is stored in the two N1 nodes of the two pixel circuits through two connected data writing transistors T4, two driving transistors T3 and two threshold compensation transistors T2 respectively connected to the two connected data writing transistors T4; in the third light-emitting stage, the second light-emitting control transistor T5, the driving transistor T3 and the first light-emitting control transistor T6 in the two pixel circuits (i.e., the pixel circuit pair f composed of the first pixel circuit f1 and / or the second pixel circuit f2) are all turned on to transmit the same data signal to the two N4 nodes. At this time, the N4 nodes of the two pixel circuits are connected together to commonly drive the same light-emitting unit B to emit light, which can achieve the purpose of increasing the current and brightness. Among them, the light-emitting unit B can be the first light-emitting unit 102 in the first display area 101a or the second light-emitting unit 104 in the second display area 101b.

[0219] It should be noted that in the embodiments of the present application, in addition to the pixel circuit shown as Figure 36 the 7T1C (i.e., seven transistors and one capacitor) structure, the pixel circuits included in the pixel circuit group may also be structures including other numbers of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure. The embodiments of the present application do not limit this. As long as the data writing transistors T4 of the two pixel circuits are connected together and the N4 nodes of the two pixel circuits are connected together to achieve the common driving of the same light-emitting unit to emit light.

[0220] Figure 37 is a partial schematic diagram of the active semiconductor layer of the pixel circuit in the first display area provided by the embodiments of the present application. As Figure 37 shown, the active semiconductor layer 123 can be formed by patterning a semiconductor material. The active semiconductor layer 123 can be used to fabricate the active layers of the above-mentioned second reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6 and first reset control transistor T7. The active semiconductor layer 123 includes the active layer patterns (channel regions) and doping region patterns (source / drain doping regions) of the transistors in each pixel unit, and the active layer patterns and doping region patterns of the transistors in the same pixel circuit are integrally arranged.

[0221] It should be noted that the active layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region can be made conductive through doping or the like to achieve electrical connection of each structure. That is, the active semiconductor layer 123 of each transistor of each sub-pixel is an integral pattern formed of p-type silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., the source region and the drain region) and an active layer pattern, and the active layers of different transistors are separated by a doping structure.

[0222] For example, the active semiconductor layer 123 can be made of amorphous silicon, polysilicon, oxide semiconductor material, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0223] Figure 38 It is a partial schematic diagram of the first conductive layer in the first display area provided by an embodiment of the present application. The display panel includes a gate insulating layer on the side of the active semiconductor layer 123 away from the substrate, which is used to insulate the above-mentioned active semiconductor layer 123 from the subsequently formed first conductive layer 124 (i.e., the gate metal layer). Figure 38 The first conductive layer 124 included in the display panel is shown. The first conductive layer 124 is disposed on the gate insulating layer, so as to be insulated from the active semiconductor layer 123. The first conductive layer 124 may include the second pole CC2 of the capacitor C, a plurality of scan signal lines g1 extending along the second direction Y, a plurality of reset control signal lines g2, and a plurality of light emission control signal lines g3. Of course, the first conductive layer 124 may further include the gates of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, and the first reset control transistor T7.

[0224] Among them, the gate of the data writing transistor T3 can be the overlapping part of the scan signal line g1 and the active semiconductor layer 123; the gate of the first light emission control transistor T6 can be a part of the overlapping part of the light emission control signal line g3 and the active semiconductor layer 123, and the gate of the second light emission control transistor T5 can be another part of the overlapping part of the light emission control signal line g3 and the active semiconductor layer 123. The gate of the second reset transistor T1 is a part of the overlapping part of the reset control signal line g2 and the active semiconductor layer 123, and the gate of the first reset control transistor T7 is another part of the overlapping part of the reset control signal line g2 and the active semiconductor layer 123. The threshold compensation transistor T2 can be a thin film transistor with a double-gate structure. The first gate of the threshold compensation transistor T2 can be the overlapping part of the scan signal line g1 and the active semiconductor layer 123, and the second gate of the threshold compensation transistor T2 can be the overlapping part of the protruding structure P protruding from the scan signal line g1 and the active semiconductor layer 123. The gate of the driving transistor T1 can be the second pole CC2 of the capacitor C.

[0225] It should be noted that, as the channel regions of the respective transistors, the active semiconductor layers 123 on both sides of each channel region are made conductive through processes such as ion doping to serve as the first pole and the second pole of the respective transistors. The source and drain of the transistor can be symmetric in structure, so there may be no physical difference between its source and drain. In the embodiments of the present application, in order to distinguish the transistors, except for the gate serving as the control pole, one of the poles is directly described as the first pole and the other as the second pole. Therefore, the first pole and the second pole of all or part of the transistors in the embodiments of the present application can be interchanged as needed.

[0226] Reference Figure 38 , the scan signal line g1, the reset control signal line g2, and the light emission control signal line g3 are arranged along the column direction Y. The scan signal line g1 is located between the reset control signal line g2 and the light emission control signal line g3.

[0227] In the first direction X, the second pole CC2 of the capacitor C (i.e., the gate of the driving transistor T1) is located between the scan signal line g1 and the light emission control signal line g3. The protruding structure P protruding from the scan signal line g1 is located on the side of the scan signal line g1 away from the light emission control signal line g3.

[0228] A first insulating layer is formed on the above-mentioned first conductive layer 124 to insulate the first conductive layer 124 from the second conductive layer 125 to be formed subsequently.

[0229] Figure 39 is a partial schematic diagram of the second conductive layer in the first display area provided by the embodiments of the present application. Reference Figure 39 , the second conductive layer 125 includes the first pole CC1 of the capacitor C and a plurality of reset power signal lines g4 extending along the second direction Y. The first pole CC1 of the capacitor C and the second pole CC2 of the capacitor C at least partially overlap to form the capacitor C.

[0230] Optionally, a second insulating layer is formed on the above-mentioned second conductive layer 125 to insulate the second conductive layer 125 from the source-drain metal layer 126 to be formed subsequently.

[0231] Figure 40 is a partial schematic diagram of the source-drain metal layer in the first display area provided by the embodiments of the present application. Figure 28 is a stacked schematic diagram of the active semiconductor layer, the first conductive layer, the second conductive layer, and the source-drain metal layer in the first display area provided by the embodiments of the present application. Reference Figure 40 and Figure 41, the source-drain metal layer 126 includes a data line 122 extending along the first direction X and a power supply signal line g5. The data line 122 is electrically connected to the second pole of the data writing transistor T2 through a via hole penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer. The power supply signal line g5 is electrically connected to the first pole of the second light-emitting control transistor T5 through a via hole penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer. The power supply signal line g5 and the data line 122 are alternately arranged along the second direction Y. The power supply signal line g5 is electrically connected to the first pole CC1 of the capacitor C through a via hole penetrating through the second insulating layer.

[0232] In an embodiment of the present application, a passivation layer and a planarization layer may be disposed on a side of the source-drain metal layer 126 away from the substrate 101 to protect the source-drain metal layer 126.

[0233] Reference Figure 41 , the first pixel circuit group 103 and the second pixel circuit group 105 may include two pixel circuits arranged along the second direction Y, that is, including a pair of pixel circuits f. The third pixel circuit group 120 does not include the pair of pixel circuits f (not shown), and only includes one pixel circuit. Two adjacent pixel circuits arranged along the second direction Y in the third pixel circuit group 120 respectively drive a third light-emitting unit 119 to emit light, and the two data writing transistors in the two adjacent pixel circuits are independent of each other and are respectively connected to different data lines.

[0234] In summary, the embodiment of the present application provides a display panel. A dummy electrode pattern is provided in the first display area of the display panel, and the dummy electrode pattern and the first connection trace are located in different layers. Thereby, it is convenient to make the overlapping capacitance between the regions where the respective pixel circuit groups in the first display area are located and the first connection trace consistent, and further, the display effect of the display panel can be ensured.

[0235] Figure 42 is a schematic structural diagram of a display device provided by an embodiment of the present application. Reference Figure 42 It can be seen that the display device may include: a power supply component 20 and the display panel 10 provided in the above embodiment. The power supply component 20 may be used to supply power to the display panel 10. Among them, the display device may be a curved display device.

[0236] Optionally, the display device may be an organic light-emitting diode (OLED) display panel, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function and a fingerprint recognition function.

[0237] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included within the protection scope of the present application.

Claims

1. A display panel, characterized in that, The display panel includes: a substrate substrate having adjacent first and second display regions; a plurality of first light-emitting units located in the first display region, the first light-emitting units including an anode, a light-emitting layer, and a cathode stacked in sequence in a direction away from the substrate substrate, the plurality of first light-emitting units including first light-emitting units of a plurality of first colors, first light-emitting units of a plurality of second colors, and first light-emitting units of a plurality of third colors, at least one first light-emitting unit of the first color, at least one first light-emitting unit of the second color, and at least one first light-emitting unit of the third color constituting a light-emitting unit group; a plurality of first pixel circuit groups located in the first display region, and each of the first pixel circuit groups being electrically connected to at least one of the first light-emitting units; a plurality of second light-emitting units located in the second display region; a plurality of second pixel circuit groups located in the first display region; a plurality of dummy electrode patterns located in the first display region, the dummy electrode patterns being on the same layer as the anode, the plurality of dummy electrode patterns constituting at least one dummy electrode pattern group, the number of dummy electrode patterns included in each dummy electrode pattern group being equal to the number of first light-emitting units included in one light-emitting unit group, the plurality of dummy electrode patterns included in each dummy electrode pattern group corresponding one-to-one to the plurality of first light-emitting units in one light-emitting unit group, and each dummy electrode pattern in the dummy electrode pattern group having the same shape and area as the anode in the corresponding first light-emitting unit in the light-emitting unit group; and a plurality of first connection traces, at least one of the plurality of first connection traces having one end electrically connected to at least one of the second light-emitting units and the other end electrically connected to the dummy electrode pattern and the second pixel circuit group; wherein the plurality of first connection traces and the plurality of dummy electrode patterns are on different layers.

2. The display panel according to claim 1, wherein The display panel further includes: a plurality of second connection traces; at least one of the plurality of second connection traces having one end electrically connected to at least one of the second light-emitting units and the other end electrically connected to the dummy electrode pattern and the second pixel circuit group; wherein the plurality of second connection traces, the plurality of first connection traces, and the plurality of dummy electrode patterns are all on different layers.

3. The display panel according to claim 2, wherein The sum of the number of the plurality of first connection traces and the number of the plurality of second connection traces included in the display panel is the same as the number of the dummy electrode patterns and corresponds one-to-one, and each of the plurality of first connection traces and the plurality of second connection traces is electrically connected to a corresponding one of the dummy electrode patterns.

4. The display panel according to claim 2, wherein At least one of the dummy electrode patterns includes a main body portion and a first connection portion, the first connection portion extending in a first direction, the first connection traces and the second connection traces both extending in a second direction, and the first direction intersecting the second direction; The first connection portion is electrically connected to at least one of the plurality of first connection traces and the plurality of second connection traces through a via at the intersection.

5. The display panel according to claim 4, wherein Each of the second pixel circuit groups includes: a source-drain metal layer located on the substrate, the source-drain metal layer including a source electrode and a drain electrode arranged at intervals; the display panel further includes: a first insulating layer, a second insulating layer, and a third insulating layer; The source-drain metal layer, the first insulating layer, the plurality of first connection traces, the second insulating layer, the plurality of second connection traces, the third insulating layer, and the dummy electrode pattern are stacked in sequence in a direction away from the substrate.

6. The display panel according to claim 5, wherein The plurality of dummy electrode patterns at least include: a first dummy electrode pattern and a second dummy electrode pattern; the second insulating layer has a plurality of first vias and a plurality of second vias, and the third insulating layer has a plurality of third vias corresponding to the plurality of first vias one by one, and a plurality of fourth vias corresponding to the plurality of second vias one by one; The orthographic projection of each of the first vias on the substrate at least partially overlaps with the orthographic projection of the corresponding third via on the substrate. Each of the first vias is used to expose one of the first connection traces. At least a part of the first connection portion in the first dummy electrode pattern is electrically connected to the first connection trace through the third via and the first via; At least a part of each of the second connection traces is located in the second via. Each of the fourth vias is used to expose one of the second connection traces. At least a part of the first connection portion in the second dummy electrode pattern is electrically connected to the second connection trace through the fourth via.

7. The display panel according to claim 4, wherein The orthographic projection of the intersection on the substrate overlaps with the orthographic projection of the first connection portion on the substrate.

8. The display panel according to claim 2, wherein The display panel further includes: a plurality of second connection portions, the second connection portions extend in a first direction, the first connection traces and the second connection traces both extend in a second direction, and the first direction intersects with the second direction; The second connection portion and the dummy electrode pattern are located in different layers, and the second connection portion is electrically connected to one of the dummy electrode patterns through a via. The second connection portion is also electrically connected to at least one of the plurality of first connection traces and the plurality of second connection traces through a via at the intersection.

9. The display panel according to claim 8, wherein, Each of the second pixel circuit groups includes: a source-drain metal layer located on the substrate, and the second connection portion is located in the same layer as the source-drain metal layer.

10. The display panel according to claim 9, wherein, The display panel further includes: a first insulating layer, a second insulating layer, and a third insulating layer; The source-drain metal layer, the first insulating layer, the plurality of first connection traces, the second insulating layer, the plurality of second connection traces, the third insulating layer, and the dummy electrode pattern are stacked in sequence in a direction away from the substrate.

11. The display panel according to claim 10, characterized in that, The first insulating layer has a plurality of fifth vias. Each of the fifth vias is used to expose one of the second connection portions. At least a part of one of the first connection traces is electrically connected to the second connection portion through one of the fifth vias; The first insulating layer and the second insulating layer have a plurality of sixth vias, each of the sixth vias being configured to expose one of the second connection portions, and at least a part of one of the second connection traces is electrically connected to the second connection portion through one of the sixth vias.

12. The display panel according to claim 8, wherein The orthographic projection of the intersection on the substrate does not overlap with the orthographic projection of any of the dummy electrode patterns on the substrate; Alternatively, the orthographic projection of the intersection on the substrate is located within the orthographic projection of one of the dummy electrode patterns on the substrate.

13. The display panel according to claim 2, wherein, Each of the second pixel circuit groups includes: a source-drain metal layer located on the substrate, the source-drain metal layer including a source electrode and a drain electrode arranged at intervals; the display panel further includes: a first insulating layer, a second insulating layer, and a third insulating layer; the source-drain metal layer, the first insulating layer, the plurality of first connection traces, the second insulating layer, the plurality of second connection traces, the third insulating layer, and the dummy electrode pattern are stacked in sequence in a direction away from the substrate. The second insulating layer has a plurality of seventh vias and a plurality of eighth vias, and the third insulating layer has a plurality of ninth vias corresponding to the plurality of seventh vias one by one, and a plurality of tenth vias corresponding to the plurality of eighth vias one by one; The orthographic projection of each of the seventh vias on the substrate at least partially overlaps with the orthographic projection of the corresponding ninth via on the substrate, each of the seventh vias being configured to expose one of the first connection traces, and a first electrode of at least one of the second light-emitting units is electrically connected to the first connection trace through the seventh via and the ninth via; At least a part of each of the second connection traces is located within the eighth via, each of the tenth vias being configured to expose one of the second connection traces, and a first electrode of at least one of the second light-emitting units is electrically connected to the second connection trace through the tenth via.

14. The display panel according to claim 13, wherein The first insulating layer has a plurality of eleventh vias, the second insulating layer has a plurality of twelfth vias corresponding to the plurality of eleventh vias one by one, and the third insulating layer has a plurality of thirteenth vias corresponding to the plurality of twelfth vias one by one; the orthographic projection of each of the eleventh vias on the substrate at least partially overlaps with the orthographic projection of the corresponding twelfth via on the substrate, and the orthographic projection of each of the twelfth vias on the substrate at least partially overlaps with the orthographic projection of the corresponding thirteenth via on the substrate; The display panel further includes: a plurality of first connection patterns and a plurality of second connection patterns corresponding to the plurality of first connection patterns one by one; Each of the eleventh vias is configured to expose the drain of a transistor in one of the second pixel circuit groups, and at least a portion of one of the first connection patterns is electrically connected to the drain through the eleventh via; each of the twelfth vias is configured to expose one of the first connection patterns, and at least a portion of one of the second connection patterns corresponding to one of the first connection patterns is electrically connected to the first connection pattern through the twelfth via; each of the thirteenth vias is configured to expose one of the second connection patterns, and at least a portion of a dummy electrode pattern is connected to the second connection pattern through the thirteenth via. Among them, the multiple first connection patterns and the multiple first connection traces are on the same layer, and the multiple second connection patterns and the multiple second connection traces are on the same layer.

15. The display panel according to any one of claims 2 to 14, characterized in that, The orthographic projection of the multiple first connection traces on the substrate does not overlap with the orthographic projection of the multiple second connection traces on the substrate.

16. The display panel according to claim 15, characterized in that, The orthographic projection of the multiple first connection traces on the substrate and the orthographic projection of the multiple second connection traces on the substrate are staggered in the second direction of the display panel.

17. The display panel according to any one of claims 1 to 14, characterized in that, The substrate includes: two of the first display areas, and the two first display areas are located on both sides of the second display area along the first direction; the substrate further includes: a first peripheral area and a second peripheral area, and the first peripheral area and the second peripheral area are respectively located on both sides of the two first display areas; the display panel further includes: a first row driving circuit located in the first peripheral area and a second row driving circuit located in the second peripheral area. The first row driving circuit is electrically connected to the first pixel circuit groups and the second pixel circuit groups in one of the first display areas, and the second row driving circuit is electrically connected to the first pixel circuit groups and the second pixel circuit groups in the other first display area.

18. The display panel according to claim 17, wherein The display panel further includes: multiple first scan signal lines located in one of the first display areas, and multiple second scan signal lines located in the other first display area. The first row driving circuit is electrically connected to the first pixel circuit groups and the second pixel circuit groups in one of the first display areas through the multiple first scan signal lines, and the second row driving circuit is electrically connected to the first pixel circuit groups and the second pixel circuit groups in the other first display area through the multiple second scan signal lines. Among them, the multiple first scan signal lines and the multiple second scan signal lines are on the same layer, and the orthographic projection of the multiple first scan signal lines on the substrate and the orthographic projection of the multiple second scan signal lines on the substrate are both outside the second display area.

19. The display panel according to claim 17, wherein The substrate further includes: a third display area located on the same side of the first display area and the second display area; the first peripheral area and the second peripheral area are located on both sides of the third display area along the first direction; the display panel further includes: multiple third light-emitting units located in the third display area, and multiple third pixel circuit groups connected to the multiple third light-emitting units in a one-to-one correspondence. Both the first row driving circuit and the second row driving circuit are connected to the third pixel circuit group in the third display area.

20. The display panel according to claim 19, wherein, The density of the plurality of third light emitting units is greater than the density of the plurality of first light emitting units and greater than the density of the plurality of second light emitting units.

21. The display panel according to any one of claims 1 to 14, characterized in that, The shape of the second display area is rectangular; the display panel further includes: a plurality of data lines; The orthographic projection of the portion of each data line located in the second display area on the substrate is a straight line or a broken line, and is located in the area of the second display area close to the first display area.

22. The display panel according to any one of claims 1 to 14, characterized in that, Each of the second light emitting units includes: a first electrode, a light emitting layer, and a second electrode stacked in sequence away from the substrate; Wherein, the plurality of dummy electrode patterns are on the same layer as the first electrode.

23. The display panel according to any one of claims 1 to 14, characterized in that, The orthographic projection of each dummy electrode pattern on the substrate at least partially overlaps with the orthographic projection of at least one of the second pixel circuit groups on the substrate, and the orthographic projection of each dummy electrode pattern on the substrate does not overlap with the orthographic projection of any of the first light emitting units on the substrate.

24. The display panel according to any one of claims 1 to 14, characterized in that, The orthographic projection of the connection between each dummy electrode pattern and the second pixel circuit group on the substrate does not overlap with the orthographic projection of the plurality of first connection traces on the substrate, and does not overlap with the orthographic projection of the plurality of second connection traces on the substrate.

25. A display device, characterized in that, The display device includes: a power supply component and the display panel according to any one of claims 1 to 24; The power supply component is used to supply power to the display panel.

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