Display device and electronic equipment

Abstract

The present invention relates to a display device and an electronic device. A second display area of ​​the display device has a lower pixel density than a first display area. A third metal layer is located above the first metal layer and the second metal layer. The occupancy rate of the third metal layer in the second display area is lower than that in the first display area. In a pixel unit, the first metal layer includes a first electrode area for controlling the amount of current in a driving transistor, the second metal layer includes a second electrode area and a third electrode area for supplying current to the driving transistor, and the third metal layer includes a main area for forming a capacitor included in a capacitive element to store a control voltage of the driving transistor, and an island area surrounded by the main area with a gap and connected to each other with a lower electrode area through a through-hole area.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] Organic light emitting diode (OLED) elements are current-driven self-luminous elements, and therefore do not require a backlight source. In addition, OLED elements have the advantages of achieving low power consumption, wide viewing angles, and high contrast; and are expected to contribute to the development of flat panel display devices.

[0003] The display area of ​​the OLED display device may include an area having a pixel density different from the pixel density of other areas. For example, some portable terminals such as smartphones and tablets include a photosensitive element such as a camera for taking photos below the display area. In order for the camera to receive external light, the camera is set below the area with a pixel density lower than the surrounding environment. Summary of the invention

[0004] Increasing the density of pixel circuits to achieve higher resolution may cause some of the following problems. One of them is that the power supply line becomes thinner (narrower) and has a higher resistance, which causes the anode power supply voltage (IR drop) to be uneven within the plane. Another problem is that the storage capacitor is closer to the wiring and crosstalk occurs due to capacitive coupling, causing the voltage of the storage capacitor to change from the expected value. At the same time, for the above-mentioned configuration of setting the photosensor behind the display area, the light transmittance required for the area above the photosensor is different from the light transmittance required for the remaining area.

[0005] One aspect of the present invention is a display device, comprising: a first display area, the first display area is configured to display an image; a second display area, the second display area is configured to display an image, and the second display area has a lower pixel density than the first display area; a first metal layer; a second metal layer, the second metal layer is located above the first metal layer; and a third metal layer, the third metal layer is located above the first metal layer and the second metal layer. The occupancy rate of the third metal layer in the second display area is lower than the occupancy rate of the third metal layer in the first display area. The first display area includes a plurality of first pixel units, each of the plurality of first pixel units includes: a light-emitting element, the light-emitting element includes an upper electrode area, a lower electrode area, and a light-emitting layer located between the upper electrode area and the lower electrode area; and a driving transistor, the driving transistor is configured to control the light emission of the light-emitting element. The first metal layer, the second metal layer, and the third metal layer are located below the lower electrode area. In each of the plurality of first pixel units, the first metal layer includes a first electrode area, the first electrode area is configured to control the amount of current in the channel of the driving transistor. In each of the plurality of first pixel units, the second metal layer includes a second electrode area and a third electrode area configured to supply current to the channel of the driving transistor. In each of the multiple first pixel units, the third metal layer includes: a main area, the main area is configured to be supplied with a power supply potential and to form a capacitor included in a first capacitor element with the second metal layer, the first capacitor element is configured to store a voltage that controls the driving transistor; and an island area, the island area is separated from the main area and surrounded by the main area with a gap, and the island area is interconnected with the lower electrode area through a through-hole area.

[0006] One aspect of the present invention is a display device, comprising: a first display area, the first display area is configured to display an image; a second display area, the second display area is configured to display an image, and the second display area has a lower pixel density than the first display area; a first metal layer; a second metal layer, the second metal layer is located above the first metal layer; and a third metal layer, the third metal layer is located above the first metal layer and the second metal layer. The pattern of the third metal layer in the second display area is different from the pattern of the third metal layer in the first display area. The first display area includes a plurality of first pixel units, each of the plurality of first pixel units includes: a light-emitting element, the light-emitting element includes an upper electrode area, a lower electrode area, and a light-emitting layer located between the upper electrode area and the lower electrode area; and a driving transistor, the driving transistor is configured to control the light emission of the light-emitting element. The first metal layer, the second metal layer, and the third metal layer are located below the lower electrode area. In each of the plurality of first pixel units, the first metal layer includes a first electrode area, the first electrode area is configured to control the amount of current in the channel of the driving transistor. In each of the plurality of first pixel units, the second metal layer includes a second electrode area and a third electrode area configured to supply current to the channel of the driving transistor. In each of the multiple first pixel units, the third metal layer includes: a main area, the main area is configured to be supplied with a power supply potential and to form a capacitor included in a first capacitor element with the second metal layer, the first capacitor element is configured to store a voltage that controls the driving transistor; and an island area, the island area is separated from the main area and surrounded by the main area with a gap, and the island area is interconnected with the lower electrode area through a through-hole area.

[0007] One aspect of the present invention improves the display quality of a display device.

[0008] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematically shows an example of a configuration of an OLED display device;

[0010] Figure 2 An example of a configuration of a pixel circuit and its control signal in one embodiment of the present specification is shown;

[0011] Figure 3 is a plan view schematically showing a device structure of a pixel unit;

[0012] Figure 4 Schematically shows the Figure 3 The cross-sectional structure of the section line IV-IV';

[0013] Figure 5Ashows a pattern of a layer included in a stacked structure of a TFT substrate;

[0014] Figure 5B shows a pattern of another layer included in the stacked structure of the TFT substrate;

[0015] Figure 5C shows a pattern of another layer included in the stacked structure of the TFT substrate;

[0016] Figure 5D shows patterns of some layers included in a stacked structure of a TFT substrate;

[0017] Figure 5E shows a pattern of another layer included in the stacked structure of the TFT substrate;

[0018] Fig. 5F shows a pattern of another layer included in the stacked structure of the TFT substrate;

[0019] Figure 5G shows a pattern of another layer included in the stacked structure of the TFT substrate;

[0020] Figure 6 schematically shows an example of a configuration of a display area;

[0021] Figure 7 schematically shows the layout of control lines on a TFT substrate;

[0022] Fig. 8A shows a first metal layer pattern, an intermediate conductive layer pattern, and a third metal layer pattern in another structural example of a pixel unit including a third metal layer;

[0023] Figure 8B Shows Fig. 8A The middle conductive layer pattern and the third metal layer pattern in the structural example shown;

[0024] Figure 8C In addition to Fig. 8A a second metal layer pattern outside the illustrated stacked structure;

[0025] Fig. 9 is a cross-sectional view schematically showing a cross-sectional structure of another structural example of a pixel unit;

[0026] Fig.10 is a cross-sectional view schematically showing a cross-sectional structure of a low-density region including a third metal layer having another pattern example. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely examples for implementing the present invention and are not intended to limit the technical scope of the present invention.

[0028] In the following description, a pixel is the smallest unit in a display area and is an element for emitting monochromatic light. It is also called a sub-pixel. A group of pixels of different colors (for example, red, blue, and green) constitute an element for displaying a mixed color point. This element may be called a primary pixel. When it is necessary to distinguish an element for emitting monochromatic light from an element for emitting mixed color light for the sake of clarity of description, the former is called a sub-pixel and the latter is called a primary pixel. The features of this specification are applicable to a monochrome display device whose display area is composed of monochrome pixels.

[0029] Describe a configuration example of a display device. The display area of ​​the display device includes an area with relatively low pixel density (also referred to as a low-density area or a low-resolution area) and an area with relatively high pixel density (also referred to as a normal area or a normal resolution area). The display area may include multiple low-density areas with a lower pixel density than the normal area, and these low-density areas may have different pixel densities. The light-emitting element of the pixel in the example described below is a current-driven element, such as an organic light-emitting diode (OLED) element.

[0030] Increasing the density of pixel circuits to achieve higher resolution may lead to some of the following problems. One of them is that the power line becomes thinner (narrower) and has a higher resistance, which leads to uneven anode power supply voltage (IR drop) within the plane. Another problem is that the storage capacitor is closer to the wiring, and crosstalk occurs due to capacitive coupling, so that the storage capacitor cannot maintain an accurate potential (meaning that the desired light cannot be obtained from the light-emitting element). Another problem is that in the case where the display device is a flexible display device, the thin metal wires arranged on the insulating layer or the polysilicon layer are easily broken when the substrate is bent.

[0031] The pixel unit of the display device in the embodiment of the present specification has a first metal layer including a gate electrode region, a second metal layer including a source / drain region, and a third metal layer located above these layers. The gate electrode region is a first electrode region for controlling the amount of current in the transistor channel. The source / drain electrode region is a second electrode region or a third electrode region for supplying current to the channel of the transistor.

[0032] The third metal layer is supplied with a power supply potential for the light-emitting element and forms a storage capacitor for driving the field effect transistor with the second metal layer. The display area includes a normal area and a low-density area, and the third metal layer has a different pattern between the normal area and the low-density area. This configuration reduces the IR drop (voltage drop) of the power supply potential and further provides the pixel unit therein with characteristics suitable for each display area.

[0033] Display device configuration

[0034] Reference Figure 1 The overall configuration of the display device in the embodiment of this specification is described. The elements in the drawings may be exaggerated in size or shape to facilitate clear understanding of the description. Hereinafter, an organic light emitting diode (OLED) display device is described as an example of a display device.

[0035] Figure 1 The configuration example of the OLED display device 10 is schematically shown. The OLED display device 10 includes a thin film transistor (TFT) substrate 100 on which an OLED element (light emitting element) is manufactured and a structural encapsulation unit 150 for encapsulating the OLED element. A control circuit is provided at the periphery of the cathode electrode region 114 outside the display region 125 of the TFT substrate 100, specifically, a scan driver 131, an emission driver 132, an electrostatic discharge protection circuit 133, a driver IC 134, and a demultiplexer 136.

[0036] The driver IC 134 is connected to an external device through a flexible printed circuit (FPC) 135. The scan driver 131 drives the scan lines on the TFT substrate 100. The emission driver 132 drives the emission control lines to control the light emission of the pixels. The electrostatic discharge protection circuit 133 protects the elements on the TFT substrate 100 from being damaged by electrostatic discharge. The driver IC 134 is mounted with, for example, an anisotropic conductive film (ACF).

[0037] The driver IC 134 provides power and control signals including timing signals to the scan driver 131 and the emission driver 132, and also provides power and data signals to the demultiplexer 136. The demultiplexer 136 serially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer greater than 1). The demultiplexer 136 changes the output data line of the data signal from the driver IC 134 d times in each scanning period to drive the data lines of d times the output pin of the driver IC 134.

[0038] Pixel circuit

[0039] Figure 2200 and its control signal configuration example in the embodiment of the present specification. The pixel circuit 200 is included in the Nth pixel circuit row (N is an integer). The pixel circuit 200 includes six transistors (TFT) P1 to P6, each of which has a gate, a source and a drain. All transistors P1 to P6 in this example are p-type TFTs.

[0040] The transistor P1 is a driving transistor for controlling the amount of current flowing to the OLED element E1. The source of the driving transistor P1 is connected to a power line 241 for transmitting a power supply potential VDD. The driving transistor P1 controls the amount of current to be supplied from the power line 241 to the OLED element E1 according to the voltage stored in the storage capacitor element C0. The storage capacitor element C0 maintains the written voltage throughout a frame period. The cathode of the OLED element E1 is connected to a power line 204 for transmitting a power supply potential VEE from a cathode power supply.

[0041] Figure 2 The storage capacitor C0 in the configuration example of is composed of a first capacitor C1 and a second capacitor C2 connected in series. One end of the storage capacitor C0 is supplied with an anode power supply potential VDD, and the other end is connected to the gate of the driving transistor P1.

[0042] The storage capacitor C0 is composed of capacitors C1 and C2 connected in series between a power line 241 for transmitting anode power supply potential VDD and the gate of the driving transistor P1. One end of the capacitor C1 is connected to the power line 241, and the other end of the capacitor C1 is connected to one end of the capacitor C2. The other end of the capacitor C2 is connected to the gate of the driving transistor P1. A source / drain of the transistor P4 and a source / drain of the transistor P2 are connected to the intermediate node between the capacitors C1 and C2.

[0043] The voltage of the storage capacitor element C0 is the voltage between the gate of the driving transistor P1 and the VDD power supply line 241. The source of the driving transistor P1 is connected to the VDD power supply line 241; the source potential is the anode power supply potential VDD. Therefore, the storage capacitor element C0 stores the gate-source voltage of the driving transistor P1.

[0044] The transistor P5 is an emission control switch transistor for controlling the supply of driving current to the OLED element E1 and the on / off of the light emission of the OLED element E1. The source of the transistor P5 is connected to the drain of the driving transistor P1. The transistor P5 turns on / off the current supply to the OLED element E1 connected to its drain. The gate of the transistor P5 is connected to the control signal line 232A, and the transistor P5 is controlled by the emission control signal Em input from the emission driver 132. The emission control signal is a selection signal for controlling the light emission of the OLED element E1.

[0045] The transistor P6 is used to supply the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of the transistor P6 is connected to the power supply line 242 for transmitting the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

[0046] The gate of transistor P6 is connected to control signal line 231A, and transistor P6 is controlled by selection signal S1. When transistor P6 is turned on by selection signal S1 from scan driver 131, transistor P6 supplies reset potential Vrst transmitted by power line 242 to the anode of OLED element E1. Transistors P5 and P6 also supply reset potential Vrst to the gate of driving transistor P1 through transistor P3.

[0047] Transistor P3 is a switching transistor (threshold compensation transistor) for writing a voltage for applying threshold calibration (threshold compensation) to the drive transistor P1 into the storage capacitor element C0, and is also a transistor for resetting the gate potential of the drive transistor P1. The source and drain of transistor P3 are connected to the gate and drain of the drive transistor P1. Therefore, when transistor P3 is turned on, the drive transistor P1 is diode-connected.

[0048] Transistor P4 is a switching transistor (threshold compensation transistor) for writing a voltage for applying threshold compensation to drive transistor P1 into storage capacitor C0. Transistor P4 controls whether to supply reference potential Vref to storage capacitor C0. One end of the source / drain of transistor P4 is connected to a power line 202 for transmitting reference potential Vref, and the other end is connected to an intermediate node between capacitor elements C1 and C2. The gate of transistor P4 is connected to control signal line 231B, and transistor P4 is controlled by a selection signal S1 input to its gate from scan driver 131.

[0049] Transistors P3, P6 and P4 are controlled by selection signal S1. Therefore, these transistors P3, P6 and P4 are turned on / off at the same time. During the period when these transistors are turned on, transistor P5 is turned on to reset the gate potential of driving transistor P1, and then turned off. When transistors P3 and P4 are turned on, transistor P1 is a diode-connected transistor. The threshold compensation voltage based on power supply potential VDD and reference potential Vref is written into storage capacitor element C0.

[0050] Transistor P2 is a switching transistor for selecting a pixel circuit to be supplied with a data signal and writing a data signal (data signal voltage) Vdata into the storage capacitor element C0. One end of the source / drain of transistor P2 is connected to the storage capacitor element C0, and the other end is connected to the data line 237 for transmitting the data signal Vdata.

[0051] The gate of transistor P2 is connected to a control signal line 231C for transmitting a selection signal S2 from the scan driver 131. Transistor P2 is controlled by the selection signal S2. The selection signal S2 is a signal different from the selection signal S1. For the pixel circuit 200, the selection signal S2 is a selection signal for controlling the supply of the data signal Vdata to the storage capacitor element C0. When transistor P2 is turned on, transistor P2 supplies the data signal Vdata supplied from the driver IC 134 through the data line 237 to the storage capacitor element C0.

[0052] The structure of the pixel unit

[0053] Hereinafter, the structure of a pixel unit in the display area 125 is described. Figure 3 3 is a plan view schematically showing a device structure of one pixel unit 300 . Figure 3 The schematic diagram shows a complete pixel unit 300 and a portion of an adjacent pixel unit. The pixel unit 300 is also called a pixel region. The pixel unit 300 has a reference Figure 2 Specifically, the pixel unit 300 is as follows: Figure 3 As shown in FIG. 1 , the light emitting element E1 includes six thin film transistors P1 to P6 and two capacitor elements C1 and C2. Figure 3 Remove from.

[0054] Figure 3 It also includes a VDD power line 241 for transmitting a power supply potential VDD and a power line 242 for transmitting a reset potential Vrst. The reference potential Vref may be the same as the anode power supply potential VDD. Figure 3 It includes control signal lines 231A and 231B for transmitting the selection signal S1, a control signal line 231C for transmitting the selection signal S2, and a control signal line 232A for transmitting the emission control signal Em. Figure 3 A data line 237 for transmitting a data signal Vdata is also included.

[0055] exist Figure 3 In FIG. 1 , a metal layer including power supply line 241 (a second metal layer described later) is shown by a dotted line. Parts of the same layer are represented by the same pattern. A layer is made of the same material by the same process. Each layer may be a single component layer made of a single material, or may have a multilayer structure consisting of a plurality of component layers made of different materials. Figure 3 In the figure, a via area (also called a contact area) is a conductive area arranged in a hole opened vertically through an insulator to connect different layers to each other, and the via area is represented by a filled square or a square with an X inside.

[0056] The square with an X inside represents a via region between a third metal layer and another conductive layer to be described later, and the filled square represents a via region between a second metal layer and another conductive layer. For example, via region 301 connects the third metal layer and VDD power supply line 241 to each other, and via region 311 connects the third metal layer and the anode electrode of OLED element E1 to each other.

[0057] The third metal layer includes a main region 361 occupying a large area of ​​the pixel unit 300 and an island region 362 disposed in an opening of the main region 361. The main region 361 fills all areas around the opening and occupies more than half of the area of ​​the pixel unit 300. The island region 362 is completely surrounded by a gap and is physically and electrically isolated from the main region 361.

[0058] Figure 4 Schematically shows the Figure 3 Cross-sectional structure along section line IV-IV'. Figure 4 The cross-sectional structure of the configuration of the pixel unit 300 including the flexible substrate of the TFT substrate 100, the driving TFT and OLED elements, and the structural packaging unit 150 is schematically shown. In the following description, the definitions of the upper side and the lower side correspond to the upper side and the lower side of the drawings.

[0059] The TFT substrate 100 includes a flexible substrate and a pixel circuit (TFT array) and an OLED element manufactured on the flexible substrate. The flexible substrate includes a polyimide layer 402, a silicon oxide layer (SiOx layer) 403, an amorphous silicon layer (a-Si layer) 404, and a polyimide layer 405 in order from the bottom. The silicon oxide layer 403 is formed on the polyimide layer 402 and is in direct contact with the polyimide layer 402. The amorphous silicon layer 404 is formed on the silicon oxide layer 403 and is in direct contact with the silicon oxide layer 403. The polyimide layer 405 is formed on the amorphous silicon layer 404 and is in direct contact with the amorphous silicon layer 404.

[0060] The TFT substrate 100 includes a silicon oxide layer 406, a transparent conductive layer 407, a silicon oxide layer 408, a silicon nitride layer (SiNx layer) 409, and a silicon oxide layer 410 in order from the bottom above the flexible substrate (polyimide layer 405). The transparent conductive layer 407 can be made of amorphous oxide (such as ITO or IZO) or amorphous silicon (a-Si). The pixel circuit (TFT array) and the OLED element are manufactured above the silicon oxide layer 410.

[0061] A silicon oxide layer 406 is formed between and in direct contact with the polyimide layer 405 and the transparent conductive layer 407. The silicon oxide layer 406 completely covers the polyimide layer 405. A silicon oxide layer 408 is formed over and in direct contact with the transparent conductive layer 407. A silicon nitride layer 409 is formed over and in direct contact with the silicon oxide layer 408. A silicon oxide layer 410 is formed over and in direct contact with the silicon nitride layer 409.

[0062] OLED elements are manufactured on the flexible substrate including the above-mentioned multiple layers. Each OLED element includes a lower electrode region (e.g., an anode electrode 438), an upper electrode region (e.g., a cathode electrode 432), and a multilayer organic light-emitting film 434 located between the cathode electrode 432 and the anode electrode 438. Multiple anode electrodes 438 are arranged on the same plane (e.g., arranged on the planarization film 431), and one multilayer organic light-emitting film 434 is arranged on one anode electrode 438. Figure 4 In the example shown in FIG. 1 , the cathode electrode 432 of one pixel is part of an unseparated conductive film covering the entire display area 125 .

[0063] Figure 4 Shown is an example of a top emission pixel structure, which includes a top emission type OLED element. The top emission pixel structure is configured in such a way that a cathode electrode 432 common to a plurality of pixels is disposed on the light emitting side (upper side of the figure). The cathode electrode 432 has a shape that completely covers the display area 125. The top emission pixel structure is characterized in that the anode electrode 438 has light reflectivity, while the cathode electrode 432 has light transmittance. Thus, a configuration is obtained in which light from the multilayer organic light emitting film 434 is transmitted toward the structural encapsulation unit 150. The cathode electrode 432 can be a translucent film disposed at an optimal optical distance from the anode electrode 438 to form a resonant structure.

[0064] The bottom emission pixel structure has a transparent anode electrode and a reflective cathode electrode to emit light to the outside through a flexible substrate. If both the anode electrode and the cathode electrode are made of a light-transmitting material, a transparent display device can be obtained. The structure of the flexible substrate of the present invention is applicable to OLED display devices of any of these types and also to display devices including light-emitting elements other than OLED.

[0065] The sub-pixels of a full-color OLED display device generally emit light of one color of red, green, and blue. A red sub-pixel, a green sub-pixel, and a blue sub-pixel constitute a main pixel. A pixel circuit including a plurality of thin-film transistors controls the light emission of the OLED element associated therewith. The OLED element is composed of an anode electrode in the lower electrode region, an organic light-emitting film, and a cathode electrode in the upper electrode region.

[0066] Each pixel unit 300 includes a pixel circuit including a driving transistor and a plurality of switching transistors. The pixel circuit is fabricated between the silicon oxide layer 410 and the anode electrode 438 and controls a current to be supplied to the anode electrode 438. Figure 4 The transistor P3 shown in FIG. 1 has a top gate structure. Other transistors also have a top gate structure.

[0067] The polysilicon layer is disposed above the silicon oxide layer 410 and is in direct contact with the silicon oxide layer 410. The polysilicon layer includes a channel 413 that determines the transistor characteristics of the transistor P3 at a position where a gate electrode region 417 is to be formed later. At both ends of the channel 413, source / drain regions 414 and 415 are disposed. The source / drain regions 414 and 415 are doped with high-concentration impurities to be electrically connected to the wiring layer above them. Figure 4 Also included is a source / drain region 412 of transistor P5.

[0068] A lightly doped drain (LDD) doped with low-concentration impurities may be disposed between the channel 413 and the source / drain region 414 and between the channel 413 and the source / drain region 415 . Figure 4 LDD is omitted to avoid complexity. The polysilicon layer also includes a region used as a part of wiring and electrodes.

[0069] Above the polysilicon layer, a first metal layer including a gate electrode region 417 and electrode regions 418 and 419 is provided via a gate insulating layer 416. The electrode region 418 includes a gate electrode region of the driving transistor P1 not shown. The first metal layer may be made of a metal having a high melting point such as W, Mo or Ta or an alloy of such a metal.

[0070] Interlayer insulating film 420 is arranged to cover the first metal layer. Interlayer insulating film 420 can be made of silicon oxide or silicon nitride. An intermediate conductive layer including electrode regions 421 and 422 is arranged above interlayer insulating film 420 and directly contacts interlayer insulating film 420. The intermediate conductive layer can be made of a low resistance semiconductor, a metal with a high melting point such as W, Mo or Ta, or an alloy of such a metal. The intermediate conductive layer increases the capacitance of the storage capacitor element C0 with a smaller area.

[0071] exist Figure 4In the example of FIG. 4 , the electrode region 421 overlaps with the electrode region 419 of the first metal layer in the stacking direction via the interlayer insulating film 420. The electrode region 422 overlaps with the electrode region 418 of the first metal layer in the stacking direction via the interlayer insulating film 420. A portion of the first capacitor C1 is formed between the electrode regions 421 and 419. The electrode region 419 is supplied with the anode power supply potential VDD. A portion of the second capacitor C2 is formed between the electrode regions 422 and 418.

[0072] The planarization film 424 is provided to cover the intermediate conductive layer and the interlayer insulating film 420. The planarization film 424 may be made of an organic or inorganic insulator and is in direct contact with the intermediate conductive layer and the interlayer insulating film 420.

[0073] A second metal layer including a source / drain electrode region 425 is disposed above the planarization film 424. The second metal layer may have a single-layer structure of aluminum or a multi-layer structure of Ti / Al / Ti. The source / drain electrode region 425 is connected to the source / drain region 414 of the polysilicon layer through a through-hole region disposed in a hole opened through the interlayer insulating film 420 and the gate insulating layer 416 in the stacking direction.

[0074] The second metal layer further includes an electrode region 426. The electrode region 426 is connected to the electrode region 422 of the intermediate conductive layer through a via region provided in a hole opened through the planarization film 424 in the stacking direction. These electrode regions are at the same potential.

[0075] The second metal layer further includes an electrode region 427. The electrode region 427 is opposed to the electrode region 421 of the intermediate conductive layer in the stacking direction with the interlayer insulating film 420 interposed therebetween. A portion of the first capacitive element C1 is formed between the electrode regions 427 and 421.

[0076] The second metal layer further includes an electrode region 428. The electrode region 428 is connected to the source / drain region 412 of the transistor P5 through a via region provided in a hole opening vertically downward through the planarization film 424, the interlayer insulating film 420, and the gate insulating layer 416.

[0077] Another planarization film 430 is provided to cover the second metal layer and the planarization film 424. The planarization film 430 may be made of an organic or inorganic insulator and is in direct contact with the second metal layer and the planarization film 424.

[0078] A third metal layer including a main region 361 and an island region 362 is disposed above the planarization film 430. The third metal layer may have a single-layer structure of aluminum or a multi-layer structure of Ti / Al / Ti; it is in direct contact with the planarization film 430. As described above, the island region 362 is isolated from the main region 361 and surrounded by the main region 361 with a gap therebetween. The main region 361 surrounds the island region 362, and there is a gap around the island region 362.

[0079] The main region 361 is connected to the electrode region 427 of the second metal layer through the through-hole region 301 extending vertically downward in the hole of the planarization film 430. The main region 361 is supplied with the anode power supply potential VDD through the electrode region 427.

[0080] When in the stacking direction ( Figure 4 When viewed in the vertical direction of the middle conductive layer, the main region 361 in this example covers the entire middle conductive layer. The main region 361 partially crosses the planarization film 430 and 424 and is opposite to a portion of the electrode regions 421 and 422 of the middle conductive layer. The main region 361 forms a portion of the first capacitive element C1 together with the electrode regions 421 and 422. In addition, the main region 361 partially crosses the planarization film 430 and is opposite to the electrode region 426 of the second metal layer. The main region 361 forms another portion of the first capacitive element C1 together with the electrode region 426.

[0081] As described above, the first capacitor element C1 in this example includes a capacitor between the electrode region 421 of the intermediate conductive layer and the electrode region 419 of the first metal layer, a capacitor between the electrode region 421 and the electrode region 427 of the second metal layer, a capacitor between the electrode regions 421 and 422 of the intermediate conductive layer and the main region 361 of the third metal layer, and a capacitor between the electrode region 426 of the second metal layer and the main region 361 of the third metal layer.

[0082] The electrode region 427 of the second metal layer is at the same potential as the main region 361 of the third metal layer. The electrode region 426 of the second metal layer is at the same potential as the electrode regions 421 and 422 of the intermediate conductive layer. The electrode regions 419 and 427 and the main region 361 are supplied with the anode power supply potential VDD. As can be understood from this description, the first capacitive element C1 includes a capacitor between the intermediate conductive layer and the third metal layer in addition to the capacitor between the intermediate conductive layer and the first metal layer.

[0083] The second capacitive element C2 is composed of a capacitor between the electrode region 422 of the intermediate conductive layer and the electrode region 418 of the first metal layer. The electrode region 418 extends to the gate of the driving transistor P1. From this description, it can be understood that the second capacitive element C2 is composed only of a capacitor between the intermediate conductive layer and the first metal layer.

[0084] As described above, the intermediate conductive layer forms a capacitor included in the second capacitive element C2 with the first metal layer, and forms a capacitor included in the first capacitive element C1 with the main region 361 , the second metal layer, and the first metal layer.

[0085] The main region 361 of the third metal layer occupies a large area of ​​the pixel unit 300 and covers the entire intermediate conductive layer including the electrode regions 421 and 422 of the storage capacitor element C0. Since the main region 361 is supplied with a constant anode power supply potential VDD, the voltage variation of the storage capacitor element C0 caused by crosstalk can be reduced. In addition, the power line obtains a larger area due to the main region 361, which reduces the possibility of breakage of the power line caused by bending and IR drop.

[0086] The island region 362 is connected to the electrode region 428 of the second metal layer through the via region 312 below the island region 362. The via region 312 extends through the planarization film 430 in the stacking direction and directly contacts the electrode region 428.

[0087] The planarization film 431 is provided to cover the third metal layer and the planarization film 430. The planarization film 431 may be made of an organic or inorganic insulator and is in direct contact with the third metal layer and the planarization film 430.

[0088] The anode electrode 438 is disposed above the planarization film 431. The anode electrode 438 is in direct contact with the planarization film 431. The anode electrode 438 is connected to the source / drain region 412 through the contact hole of the planarization film 431. The TFT of the pixel circuit is manufactured below the anode electrode 438. For example, the anode electrode 438 is composed of a middle reflective metal layer and a transparent conductive layer sandwiching the reflective metal layer. The anode electrode 438 may have a structure of ITO / Ag / ITO or IZO / Ag / IZO.

[0089] The anode electrode 438 is connected to the island region 362 of the third metal layer through the through-hole region below the anode electrode 438. The through-hole region extends through the planarization film 431 in the stacking direction and directly contacts the island region 362. The source / drain region 412, the electrode region 428 of the second metal layer, and the island region 362 supply a driving potential (anode potential) that determines the brightness (amount of light) of the light-emitting element. The island region 362 is away from the main region 361 to which the power supply potential VDD is supplied and is outside the main region 361. For this reason, the island region 362 can supply the driving potential to the anode electrode 438.

[0090] An insulating pixel defining layer (PDL) 437 is disposed over the anode electrode 438 to separate the OLED elements. Each OLED element is fabricated in an opening 436 of the pixel defining layer 437.

[0091] A multilayer organic light emitting film 434 is disposed above the anode electrode 438. The multilayer organic light emitting film 434 contacts the pixel defining layer 437 at the opening 436 of the pixel defining layer 437 and its periphery. The multilayer organic light emitting film 434 is formed by depositing an organic light emitting material of R, G or B color on the anode electrode 438.

[0092] The multilayer organic light-emitting film 434 is formed by vapor deposition of an organic light-emitting material in an area corresponding to a pixel through a metal mask. The multilayer organic light-emitting film 434 is composed of, for example, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer in order from the bottom. The stacked structure of the multilayer organic light-emitting film 434 is determined according to the design.

[0093] The cathode electrode 432 is disposed on the multilayer organic light emitting film 434. The cathode electrode 432 is a light-transmitting electrode. The cathode electrode 432 transmits a portion of the visible light from the multilayer organic light emitting film 434. The layer of the cathode electrode 432 is formed by vapor deposition of a metal such as Ag or Mg or an alloy thereof. If the resistance of the cathode electrode 432 is too high and the uniformity of the brightness of the emitted light is impaired, an additional auxiliary electrode layer is provided using a material such as a transparent electrode of ITO, IZO, ZnO or In2O3.

[0094] The stack of the anode electrode 438, the multilayer organic light emitting film 434, and the cathode electrode 432 formed in the opening 436 of the pixel defining layer 437 corresponds to an OLED element. The structural encapsulation unit 150 is disposed above the cathode electrode 432 and is in direct contact with the cathode electrode 432. The structural encapsulation unit (thin film encapsulation unit) 150 includes an inorganic insulator (e.g., SiNx or AlOx) layer 433, an organic planarization film 439, and another inorganic insulator (e.g., SiNx or AlOx) layer 435.

[0095] The touch screen film 453, the λ / 4 plate 454, the polarizing plate 455, and the resin cover lens 456 are placed on the structural packaging unit 150 in this order from the bottom. The λ / 4 plate 454 and the polarizing plate 455 are used to reduce the reflection of light from the outside. Figure 4 The stacked structure of the OLED display device described is an example; it can be omitted Figure 4 One or more layers in the Figure 4 For example, the intermediate conductive layer may be removed. If the intermediate conductive layer is removed, a storage capacitor is formed between the polysilicon layer doped with high concentration impurities and the gate electrode via the gate insulating layer 416.

[0096] FIG. 5A to FIG. 5G Patterns of some layers included in the stacked structure of the TFT substrate 100 are shown. FIG. 5A to FIG. 5GThe layers are ordered to show the order in which they are formed on the flexible substrate, starting from the bottom.

[0097] Figure 5A A semiconductor (eg, polysilicon) layer pattern 501 is schematically shown. The semiconductor layer pattern 501 includes a channel region having a high resistance. Some portions of the semiconductor layer pattern 501 are doped with impurities to become a low resistance region having a lower resistance than the channel region.

[0098] Figure 5B The first metal layer pattern 503 is schematically shown. As described above, the first metal layer includes a gate electrode region of a transistor and a wiring region and an electrode region for transmitting a power supply potential or a signal potential. Figure 5C The middle conductive layer pattern 505 is schematically shown. The middle conductive layer includes electrode regions 421 and 422 and a connection region 423 for connecting these electrode regions. The electrode regions 421 and 422 are a fifth electrode region and a fourth electrode region, respectively.

[0099] The width of the connection area 423 ( Figure 5C The length of the connection region 423 in the horizontal direction (in the horizontal direction) is smaller than the width of the electrode regions 421 and 422. Preferably, the width of the connection region 423 is as small as possible to minimize the impact of misalignment or variation in processing on the two storage capacitors, and therefore, the minimum value allowed by the manufacturing process is adopted. For example, the width of the connection region 423 can be 1 / 10 or less of the width of the electrode regions 421 and 422. As described above, the intermediate conductive layer is a component of the storage capacitor.

[0100] Figure 5D The stacked structure of the semiconductor layer pattern 501 , the first metal layer pattern 503 , and the intermediate conductive layer pattern 505 is schematically shown. Figure 5D Also included is a via region for interconnecting the second metal layer and the conductive layer below the second metal layer. The via region is represented by a filled square. Via region 531 interconnects the first metal layer and the second metal layer, and via region 551 interconnects the middle conductive layer and the second metal layer.

[0101] Figure 5E The second metal layer pattern 507 is schematically shown. Figure 5E The via regions 301 and 312 for connecting the second metal layer and the third metal layer to each other are also included. As described above, the via region 301 connects the main region 361 of the third metal layer to the second metal layer. The via region 312 connects the island region 362 of the third metal layer to the second metal layer. Fig. 5F The third metal layer pattern 509 is schematically shown. Fig. 5FIt also includes a through hole region 311 for connecting the third metal layer and the anode electrode of the OLED element E1 to each other. Fig. 5F As shown, the main region 361 fills all regions of the pixel unit except the island region 362 and the gap between the main region 361 and the island region 362 .

[0102] The main area 361 of one pixel unit 300 is a part of the unseparated metal sheet. The metal sheet includes the main areas 361 of a plurality of pixel units 300. As for the island area 362, one pixel unit 300 has one island area 362. The island area 362 is located in the opening 363 of the main area 361, and the entire outer end of the island area 362 is away from the inner end of the opening 363 of the main area 361.

[0103] Figure 5G The anode electrode 438 and the opening 436 of the pixel defining layer 437 are schematically shown. The light emitting region is located within the opening 436. As described above, the driving potential is supplied to the anode electrode 438 through the island region 362 of the third metal layer.

[0104] Display area configuration

[0105] Hereinafter, a configuration example of the display area 125 in the embodiment of the present specification is described. Figure 6 The configuration example of the display area 125 is schematically shown. The OLED display device 10 can be installed on a mobile terminal such as a smart phone or a tablet terminal. The display area 125 includes a normal area 461 with a normal pixel density and a low-density area 463 with N columns and M rows having a pixel density lower than that of the normal area 461. The normal area 461 is a first display area, and the low-density area 463 is a second display area.

[0106] One or more cameras 465 are disposed below (behind) the low-density area 463. The camera 465 is an example of a photoelectric sensor; other types of photoelectric sensors may be disposed below the low-density area 463. Figure 6 In the drawings, as an example, one of the multiple cameras is provided with reference numeral 465.

[0107] When observing the display area 125, the camera 465 is located behind the low-density area 463; each camera 465 takes a picture of an object in front of the camera using light that passes through the low-density area 463. In order not to interfere with the camera 465 taking pictures, the density of the pixel units (including the light-emitting elements and the pixel circuits) in the low-density area 463 is lower than the density of the pixel units in the surrounding normal area 461.

[0108] The controller not shown transmits the data of the photo taken by the camera 465 to the OLED display device 10. Figure 6An example of a low-density area in is an area under which a camera is provided, but features of the present specification are applicable to a display device including an area with a relatively low pixel density for other purposes. The frequency of light sensed by the photosensor is not limited to a specific value.

[0109] Wiring layout and third metal layer

[0110] Hereinafter, an example of a wiring layout of the OLED display device 10 is described. Figure 7 The layout of control lines on the TFT substrate 100 is schematically shown. Figure 7 The low-density region 463 in the configuration example includes an end of the display region 125; one side of the low-density region 463 is a part of one side of the display region 125. The remaining outer end of the low-density region 463 is located inside the display region 125 and is a boundary with the normal region 461.

[0111] Figure 7 The layout of the pixel circuit in the normal area 461 in the configuration example is a strip arrangement. Specifically, each pixel column (sub-pixel column) extending along the Y axis is composed of pixels (sub-pixels) of the same color. Each pixel row extending along the X axis is composed of red pixels, green pixels and blue pixels arranged in a loop. The low-density area 463 has such a configuration that some pixels are removed from the pixel layout of the normal area 461. The blank area in the low-density area 463 does not include any pixel circuit including an OLED element, but only includes wiring.

[0112] A plurality of scan lines 106 extend from the scan driver 131 along the X axis. A plurality of emission control lines 107 extend from the emission driver 132 along the X axis. Figure 7 , one of the scan lines and one of the emission control lines are provided with reference numerals 106 and 107, respectively. Figure 7 The scanning line 106 in the configuration example of transmits selection signals of pixels in the normal area 461 and the low-density area 463. The emission control line 107 transmits emission control signals of the normal area 461 and the low-density area 463.

[0113] The driver IC 134 transmits a control signal for the scan driver 131 through the wiring 711 and transmits a control signal for the emission driver 132 through the wiring 713. The driver IC 134 controls the timing of the scan signal (selection pulse) from the scan driver 131 and the emission control signal from the emission driver 132 based on image data (image signal) from the outside.

[0114] The driver IC 134 supplies the data signals of the sub-pixels in the normal area 461 and the low-density area 463 to the demultiplexer 136 through the wiring 705. Figure 7 , as an example, one of the wirings is provided with reference numeral 705. The driver IC 134 determines the data signal of each sub-pixel in the normal area 461 and the low-density area 463. The data signal of one sub-pixel is determined according to the gray level of one or more sub-pixels of image data (one frame) from the outside.

[0115] The demultiplexer 136 serially outputs one output of the driver IC 134 to N data lines (N is an integer greater than 1) during a scanning period. Figure 7 In FIG. 1 , as an example, one data line among a plurality of data lines extending along the Y axis is provided with reference numeral 105 .

[0116] Figure 7 The layout of the anode power supply line pattern on the TFT substrate 100 is also schematically shown. Figure 7 As shown, the TFT substrate 100 includes an anode power supply line pattern 801. The anode power supply line pattern 801 supplies an anode power supply potential to the pixel circuits in the normal region 461 and the low-density region 463.

[0117] The anode power supply line pattern 801 includes a rectangular surrounding portion and a wiring portion inside the surrounding portion. In the wiring portion, wirings extending along the Y axis are arranged side by side along the X axis. Some wirings extend through the normal area 461 and the low-density area 463. The anode power supply line pattern 801 transmits the anode power supply potential VDD to the pixel circuits of each sub-pixel in the normal area 461 and the low-density area 463. The anode power supply line pattern 801 may be different from Figure 7 For example, the anode power supply line pattern 801 may be developed like a grid including a plurality of wirings extending along the X-axis in addition to the wiring portion extending along the Y-axis.

[0118] Figure 7 The third metal layer 591 is also schematically shown. The anode power supply potential VDD is supplied to the main area of ​​the third metal layer 591 from the anode power supply line pattern 801. In this example, the third metal layer 591 is provided in the normal area 461, but not provided in the low-density area 463. Since the third metal layer 591 is removed from the low-density area 463 (not provided in the low-density area 463), but provided only outside the low-density area 463, the reduction of light that passes through the low-density area 463 and reaches the camera 465 behind the low-density area 463 can be made small.

[0119] Unlike the configuration in which the low density region 463 is located within the opening of the third metal layer, the third metal layer 591 may be partially located in the low density region 463. The third metal layer 591 in the low density region 463 has a pattern different from that in the normal region 461.

[0120] The occupancy rate of the third metal layer 591 in the low-density region 463 is lower than that in the normal region 461. This configuration reduces the reduction of light reaching the camera 465. The occupancy rate in the region is a value obtained by dividing the area of ​​the region filled with the third metal layer 591 by the area of ​​the entire region.

[0121] In one example, the pixel circuits in the normal region 461, the pixel circuits in the low-density region 463, and the pixel units have the same outer dimensions. The pixel units in the normal region 461 have a reference Figure 3 to Figure 5G The structure of the description.

[0122] However, the low density region 463 does not include the third metal layer 591, and therefore, the pixel cells in the low density region 463 have a configuration such that the third metal layer is Figure 3 to Figure 5G The structure described is removed from the structure. To do this, Figure 4 The through-hole area 311 shown in the figure is in direct contact with the electrode area 428 of the second metal layer. In other words, the anode electrode 438 is connected to the second metal layer through the through-hole area extending vertically downward rather than through the third metal layer. The pixel unit in the low-density area 463 may include a third metal layer. For example, the third metal layer may have only an island pattern at the position of the through-hole area 311. This configuration makes the contact resistance from the driving TFT to the anode electrode equal between the low-density area and the high-density area (normal area). The occupancy rate of the third metal layer in the pixel unit (pixel area) in the low-density area 463 is lower than the occupancy rate of the third metal layer in the normal area 461.

[0123] The driver IC 134 includes a DC-DC converter to generate a plurality of power supply potentials and supplies the power supply potentials to the OLED display panel. The driver IC 134 outputs an anode power supply potential VDD to the anode power supply line pattern 801 and outputs a cathode power supply potential VSS to the cathode electrode 432.

[0124] Figure 7 The cathode electrode layer not shown in the figure has the shape of one sheet and completely covers the normal area 461 and the low-density area 463. The cathode electrode of each pixel in these areas 461 and 463 is a part of the one sheet of the cathode electrode layer.

[0125] Other configuration examples

[0126] Hereinafter, another structure of the pixel unit in the normal display area 461 is described. Figure 3 to Figure 5GIn the described structural example, when viewed in the stacking direction, the main area of ​​the third metal layer covers the entire intermediate conductive layer in the pixel unit. In another configuration example of the pixel unit, the main area only covers a portion of the intermediate conductive layer. The capacitance of the first capacitive element C1 can be adjusted by adjusting the area of ​​the main area covering the intermediate conductive layer.

[0127] Fig. 8A 5 shows a first metal layer pattern 503, an intermediate conductive layer pattern 505, and a third metal layer pattern 820 in another structural example of a pixel unit including a third metal layer. Figure 3 to Figure 5G Compared with the structure described above, the first metal layer pattern 503 and the middle conductive layer pattern 505 are the same, and the third metal layer pattern 820 is different.

[0128] Figure 8B Shows Fig. 8A The intermediate conductive layer pattern 505 and the third metal layer pattern 820 in the structural example shown. The third metal layer pattern 820 in the pixel unit is composed of a main region 821 and an island region 822. The island region 822 is located in the opening of the main region 821.

[0129] The island region 822 is surrounded by a gap for isolating the island region 822 from the main region 821. The area of ​​the gap is larger than that of the aforementioned structural example. Therefore, the occupancy rate of the third metal layer in the pixel unit is lower than that in the aforementioned structural example. The electrode region 421 of the intermediate conductive layer is located in the gap between the main region 821 and the island region 822; it does not overlap with the third metal layer pattern 820 in the stacking direction. However, the entire electrode region 422 of the intermediate conductive layer overlaps with (is covered by) the third metal layer pattern 820 in the stacking direction.

[0130] The middle conductive layer pattern 505 includes a connection region 423 connecting the two electrode regions 421 and 422 in the Y-axis direction (first direction). Preferably, the width ( Figure 8B The length in the X-axis direction (second direction) of the intermediate conductive layer is smaller than the width of the electrode regions 421 and 422; the minimum value allowed by the manufacturing process is adopted. Therefore, the capacitance change of the storage capacitor caused by the alignment error in the Y-axis direction of the intermediate conductive layer can be minimized.

[0131] like Figure 8B As shown, distances L1 and L2 are defined between the end of the electrode region 421 of the middle conductive layer and the end (inner end of the opening) of the main region 821 of the third metal layer. In one example, these distances L1 and L2 are equal. This configuration reduces the impact of alignment errors.

[0132] Figure 8C Apart from Fig. 8AIn addition to the stacked structure shown, a second metal layer pattern 850 is also shown. Since the present embodiment is configured so that the third metal layer does not overlap with the electrode region 421 of the intermediate conductive layer, a through hole region 825 for connecting the second metal layer pattern 850 and the third metal layer pattern 820 is provided at a different position than in the aforementioned structural example. The through hole region 825, like the through hole region 301 in the aforementioned structural example, interconnects the main region 821 of the third metal layer and the electrode region (wiring region) of the second metal layer for transmitting the anode power supply potential VDD.

[0133] Fig. 9 Schematically shows the cross-sectional structure of the pixel unit. Figure 4 The electrode region 421 of the intermediate conductive layer is not covered by the third metal layer pattern and is located inside the opening. Since the through hole region connecting the second metal layer and the third metal layer is set at different positions, this example does not include Figure 4 The through hole area 301 and the electrode area 427 of the second metal layer.

[0134] Like in Figure 4 As in the structural example in FIG. 1 , a portion of the first capacitor element C1 is formed between the main region 821 of the third metal layer and the electrode region 426 of the second metal layer, and another portion of the first capacitor element C1 is formed between the main region 821 and the electrode region 422 of the intermediate conductive layer. The second capacitor element C2 is formed only between the intermediate conductive layer and the first metal layer.

[0135] Another application example of the third metal layer is described. The example described below uses the third metal layer as a pinhole matrix layer. The pinhole matrix layer includes a pinhole array, which includes a plurality of pinholes arranged in two dimensions. The pinholes transmit only light entering from a certain point of the object in a specific direction.

[0136] Fig.10 4 is a cross-sectional view schematically showing a cross-sectional structure of the low-density region 463. In the low-density region 463, the third metal layer functions as a matrix pinhole image sensing (MAPIS) layer 593. The MAPIS layer 593 is a pinhole matrix layer.

[0137] The structure encapsulation unit 471 is placed to cover the OLED element E1. The touch screen film 453, the polarizing plate 455 and the cover lens 456 are placed on the structure encapsulation unit 471 in order from the bottom. The third metal layer pattern in the normal area 461 is consistent with the reference Figure 3 to Figure 5G or FIG. 8A to FIG. 9 The third metal layer pattern described is the same. It can be understood from this specification that the pattern of the third metal layer in the low-density area 463 is different from the pattern of the third metal layer in the normal area 461.

[0138] exist Fig.10 In the embodiment, the CMOS sensor 901 of the photoelectric sensor is arranged below (behind) the MAPIS layer 593. For example, Fig.10 The configuration example shown in can function as a fingerprint sensor. The finger 902 to be imaged reflects light from the OLED element E1. The light from the finger 902 forms an image on the CMOS sensor 901 through the pinhole array of the MAPIS layer 593. The fingerprint image captured by the CMOS sensor 901 is transmitted to a controller not shown. The controller compares the acquired fingerprint image with the fingerprint data of the registered user to authenticate the user.

[0139] The MAPIS layer 593 is supplied with the anode power supply potential VDD. The MAPIS layer 593 partially forms one or more capacitors included in the storage capacitor element. All areas of the MAPIS layer 593 except the pinhole are filled with metal. In one example, the occupancy rate of the MAPIS layer 593 in the pixel unit is higher than the occupancy rate of the third metal layer in the pixel unit in the normal area 461. As shown in this configuration example and other configuration examples, the third metal layer having different patterns in different areas of the display area 125 can provide the photosensor behind the third metal layer with light suitable for the purpose of the area.

[0140] As described above, the embodiments of the present invention have been described; however, the present invention is not limited to the aforementioned embodiments. Those skilled in the art can easily modify, add or convert each element in the aforementioned embodiments within the scope of the present invention. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, or the configuration of one embodiment can be incorporated into the configuration of another embodiment.

Claims

1. A display device, comprising: a first display area, the first display area being configured to display an image; a second display area, the second display area being configured to display an image, the second display area having a lower pixel density than the first display area; A first metal layer; a second metal layer, the second metal layer being located above the first metal layer; as well as a third metal layer, the third metal layer being located above the first metal layer and the second metal layer, The occupancy rate of the third metal layer in the second display area is lower than the occupancy rate of the third metal layer in the first display area. The first display area includes a plurality of first pixel units, and each of the plurality of first pixel units includes: A light emitting element, the light emitting element comprising an upper electrode region, a lower electrode region, and a light emitting layer located between the upper electrode region and the lower electrode region; and a driving transistor configured to control light emission of the light emitting element, Wherein, the first metal layer, the second metal layer, and the third metal layer are located below the lower electrode region, Wherein, in each of the plurality of first pixel units, the first metal layer includes a first electrode region, and the first electrode region is configured to control the amount of current in the channel of the driving transistor, wherein, in each of the plurality of first pixel units, the second metal layer includes a second electrode region and a third electrode region, the second electrode region and the third electrode region are configured to supply current to the channel of the driving transistor, and Wherein, in each of the plurality of first pixel units, the third metal layer includes: a main region configured to be supplied with a power supply potential and to form with the second metal layer a capacitor included in a first capacitance element configured to store a voltage for controlling the drive transistor; and An island region is spaced apart from the main region and surrounded by the main region with a gap therebetween, and the island region is connected to the lower electrode region through a through-hole region.

2. The display device according to claim 1, further comprising an intermediate conductive layer between the first metal layer and the second metal layer, in, In each of the plurality of first pixel units, the intermediate conductive layer is configured to form, with the first metal layer, a capacitor included in a second capacitive element different from the first capacitive element, and In each of the plurality of first pixel units, the intermediate conductive layer is configured to form a capacitor included in the first capacitive element with the main region.

3. The display device according to claim 2, wherein: In each of the plurality of first pixel units, the main region covers all regions of the intermediate conductive layer when viewed in a stacking direction.

4. The display device according to claim 2, in, In each of the plurality of first pixel units, the intermediate conductive layer includes a fourth electrode region, a fifth electrode region, and a connection region connecting the fourth electrode region and the fifth electrode region in a first direction, wherein, when viewed in the stacking direction, the entire fourth electrode region is covered by the third metal layer, wherein, when viewed in the stacking direction, the fifth electrode region is located in a gap between the main region and the island region, and The connection region has a smaller length than the fourth electrode region and the fifth electrode region in a second direction perpendicular to the first direction.

5. The display device according to claim 2, in, In each of the plurality of first pixel units, the intermediate conductive layer includes a fourth electrode region and a fifth electrode region, wherein, when viewed in the stacking direction, the entire fourth electrode region is covered by the third metal layer, wherein, when viewed in the stacking direction, the fifth electrode region is located in a gap between the main region and the island region, and Wherein, the distances between the two sides of the fifth electrode region and the main region are equal.

6. The display device according to claim 1, wherein: The main area fills all areas of the first pixel unit except the island area and the gap.

7. The display device according to claim 1, wherein: The second display area does not include the third metal layer.

8. A display device, comprising: a first display area, the first display area being configured to display an image; a second display area, the second display area being configured to display an image, the second display area having a lower pixel density than the first display area; A first metal layer; a second metal layer, the second metal layer being located above the first metal layer; as well as a third metal layer, the third metal layer being located above the first metal layer and the second metal layer, wherein a pattern of the third metal layer in the second display area is different from a pattern of the third metal layer in the first display area, The first display area includes a plurality of first pixel units, and each of the plurality of first pixel units includes: A light emitting element, the light emitting element comprising an upper electrode region, a lower electrode region, and a light emitting layer located between the upper electrode region and the lower electrode region; and a driving transistor configured to control light emission of the light emitting element, Wherein, the first metal layer, the second metal layer, and the third metal layer are located below the lower electrode region, Wherein, in each of the plurality of first pixel units, the first metal layer includes a first electrode region, and the first electrode region is configured to control the amount of current in the channel of the driving transistor, wherein, in each of the plurality of first pixel units, the second metal layer includes a second electrode region and a third electrode region, the second electrode region and the third electrode region are configured to supply current to the channel of the driving transistor, and Wherein, in each of the plurality of first pixel units, the third metal layer includes: a main region configured to be supplied with a power supply potential and to form with the second metal layer a capacitor included in a first capacitance element configured to store a voltage for controlling the drive transistor; and An island region is spaced apart from the main region and surrounded by the main region with a gap therebetween, and the island region is connected to the lower electrode region through a through-hole region.

9. The display device according to claim 8, wherein: The third metal layer includes a pinhole array in the second display area.

10. An electronic device comprising: The display device according to claim 1 or 8; as well as A photoelectric sensor is disposed below the second display area.

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