Semiconductor structure and method of manufacturing the same, integrated circuit and method of manufacturing the same

Abstract

Disclosed are a semiconductor structure and a manufacturing method thereof, and an integrated circuit and a manufacturing method thereof. The semiconductor structure comprises: a substrate, the substrate having a first doping type; an epitaxial layer on the substrate, the epitaxial layer having a second doping type, the first doping type and the second doping type being opposite; a base region, an emitter region and a collector region in the epitaxial layer, wherein the base region and the collector region are isolated from each other, the emitter region is in contact with the base region and is isolated from the collector region, the base region has the first doping type, and the emitter region and the collector region have the second doping type; a first isolation structure and a second isolation structure on the epitaxial layer, the first isolation structure isolates the base region and the collector region, and the second isolation structure isolates a side of the emitter region from the base region. In the application, the second isolation structure isolates the side of the emitter region from the base region, which can reduce the parasitic capacitance between the emitter region and the base region and improve the characteristic frequency of the semiconductor structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and more specifically, relates to a semiconductor structure and its manufacturing method, and an integrated circuit and its manufacturing method. Background Technology

[0002] The main characteristics that distinguish high-frequency transistors from ordinary transistors are their small transistor size, low breakdown voltage, and extremely high characteristic frequency, making them difficult to manufacture. They are generally used in high-frequency broadband low-noise amplifiers such as VHF (Very High Frequency) wireless communication, UHF (Ultra High Frequency) wireless communication, CATV (Cable Television), wireless remote control, and RF modules. These applications are mostly used under low voltage, small signal, low current, and low noise conditions.

[0003] To achieve the highest characteristic frequency, the parasitic capacitance of the transistor must be minimized, and the junction depth of its emitter and base regions must be made as shallow as possible. Traditional high-frequency transistors typically employ polycrystalline emitter technology to reduce the emitter junction depth and increase the frequency.

[0004] In existing high-frequency transistors, the emitter region is formed within the intrinsic base region. The bottom and sidewalls of this emitter region are in contact with the intrinsic base region but far from the extrinsic base region. However, the pad oxide layer under the emitter region in high-frequency transistors is either a low-pressure chemical vapor deposition oxide layer (LPTEOS) or a plasma-enhanced chemical vapor deposition oxide layer (PETEOS). The emitter junction has a side-side EB (emitter / base) PN junction, resulting in a large parasitic capacitance of the side-side EB junction, which affects the characteristic frequency Ft of the high-frequency transistor. Furthermore, the formation process of the extrinsic base region and emitter region uses a non-self-aligned process, leading to a higher base resistance, further affecting the characteristic frequency Ft of the high-frequency transistor. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor structure and its manufacturing method, an integrated circuit and its manufacturing method, to reduce the parasitic capacitance of the side EB junction of the semiconductor structure and increase the characteristic frequency of the semiconductor structure.

[0006] According to a semiconductor structure provided by the present invention, the structure includes: a substrate having a first doping type; an epitaxial layer on the substrate having a second doping type, wherein the first doping type and the second doping type are opposite; a base region, an emitter region, and a collector region located in the epitaxial layer, wherein the base region and the collector region are isolated from each other, the emitter region is in contact with the base region and isolated from the collector region, the base region having a first doping type, and the emitter region and the collector region having a second doping type; a first isolation structure and a second isolation structure located on the epitaxial layer, wherein the first isolation structure isolates the base region and the collector region, and the second isolation structure isolates the side of the emitter region from the base region.

[0007] Preferably, the first isolation structure and the second isolation structure are field oxide layers or shallow trench structures.

[0008] Preferably, the base region includes an intrinsic base region and an intrinsic base region, wherein the doping concentration of the intrinsic base region is higher than that of the intrinsic base region.

[0009] Preferably, the non-intrinsic base region is located on one side of the intrinsic base region and contacts the intrinsic base region, and the intrinsic base region surrounds the emitter region and contacts the emitter region.

[0010] Preferably, the collector region is located on the side of the intrinsic base region away from the non-intrinsic base region.

[0011] Preferably, the semiconductor structure further includes a buried layer located between the substrate and the epitaxial layer, the buried layer having a second doping type.

[0012] Preferably, the current collector region includes: a first implantation region located on the surface of the epitaxial layer; and a second implantation region located between the first implantation region and the buried layer, wherein the second implantation region contacts the buried layer to connect the first implantation region and the buried layer; wherein the first implantation region and the second implantation region have a second doping type, and the doping concentration of the second implantation region is less than the doping concentration of the first implantation region.

[0013] Preferably, the semiconductor structure further includes an emitter polycrystalline silicon located above the emitter region.

[0014] Preferably, when the first isolation structure is a field oxide layer, the thickness of the first isolation structure is [missing information].

[0015] Preferably, when the second isolation structure is a field oxide layer, the thickness of the second isolation structure is

[0016] Preferably, the semiconductor structure further includes: an interlayer dielectric layer located on the epitaxial layer, the first isolation structure, and the second isolation structure; a first contact hole, a second contact hole, and a third contact hole penetrating the interlayer dielectric layer; a base, an emitter, and a collector located on the interlayer dielectric layer; wherein the base is in contact with the base region through the first contact hole, the emitter is in contact with the emitter region through the second contact hole, and the collector is in contact with the collector region through the third contact hole.

[0017] Preferably, the semiconductor structure further includes: a third isolation structure that penetrates the epitaxial layer and extends into the substrate; wherein a portion of the first isolation structure is located above the third isolation structure.

[0018] Preferably, the first doping type is P-type and the second doping type is N-type.

[0019] Preferably, the semiconductor structure is a high-frequency transistor.

[0020] According to a second aspect of the present invention, an integrated circuit is provided, comprising at least one of the semiconductor structures described above.

[0021] Preferably, the integrated circuit is a BICMOS circuit or a BCD circuit.

[0022] According to a third aspect of the present invention, a method for manufacturing a semiconductor structure is provided, comprising: forming an epitaxial layer on a substrate having a first doping type and the epitaxial layer having a second doping type, wherein the first doping type and the second doping type are opposite; forming a first isolation structure on the epitaxial layer; forming a base region in the epitaxial layer and forming a second isolation structure on the epitaxial layer; forming a collector region and an emitter region in the epitaxial layer, wherein the first isolation structure isolates the base region and the collector region from each other, the emitter region is in contact with the base region and isolated from the collector region, the base region having a first doping type, and the emitter region and the collector region having a second doping type; wherein the second isolation structure isolates the side of the emitter region from the base region.

[0023] Preferably, the first isolation structure and the second isolation structure are field oxide layers or shallow trench structures.

[0024] Preferably, the step of forming the first isolation structure includes: forming a pad oxide layer and a first silicon nitride layer on the epitaxial layer; etching the first silicon nitride layer to form a first isolation region; performing local silicon oxidation in the first isolation region to form the first isolation structure; removing the first silicon nitride layer and performing sacrificial oxidation on the pad oxide layer.

[0025] Preferably, the step of forming the second isolation structure includes: forming a second silicon nitride layer on the pad oxide layer; etching the second silicon nitride layer to form a second isolation region; performing local silicon oxidation in the second isolation region to form the second isolation structure; and removing the second silicon nitride layer.

[0026] Preferably, the step of forming the first isolation structure includes: forming a first shallow trench in the epitaxial layer; and filling the first shallow trench with an oxide layer to form the first isolation structure.

[0027] Preferably, forming a base region in the epitaxial layer includes: forming photoresist on the epitaxial layer, exposing and developing the photoresist to form a base region window; performing ion implantation of a first conductivity type in the base region window to form an intrinsic base region, and removing the photoresist.

[0028] Preferably, the step of forming the second isolation structure includes: forming a second shallow trench in the epitaxial layer; and filling the second shallow trench with an oxide layer to form the second isolation structure.

[0029] Preferably, forming the base region further includes: performing ion implantation on one side of the intrinsic base region to form an intrinsic base region; wherein the doping concentration of the intrinsic base region is higher than the doping concentration of the intrinsic base region; the intrinsic base region is located on one side of the intrinsic base region and in contact with the intrinsic base region, and the intrinsic base region surrounds the emitter region and is in contact with the emitter region.

[0030] Preferably, the collector region is located on the side of the intrinsic base region away from the non-intrinsic base region.

[0031] Preferably, before forming the epitaxial layer, the method further includes forming a buried layer on a substrate, the buried layer having a second doping type, and the epitaxial layer being located on the substrate and the buried layer.

[0032] Preferably, forming the current collector region includes: forming photoresist on the epitaxial layer and exposing and developing the photoresist to form a current collector region window; performing ion implantation on the current collector region window to form a first implantation region, the first implantation region having a second doping type; forming the current collector region further includes: before forming the first implantation region, forming a second implantation region in the epitaxial layer, the second implantation region contacting the buried layer to connect the first implantation region and the buried layer; wherein the second implantation region has a second doping type, and the doping concentration of the second implantation region is less than the doping concentration of the first implantation region.

[0033] Preferably, the step of forming the emitter region includes: forming photoresist on the first isolation structure and the second isolation structure, and exposing and developing the photoresist to form an emitter region window; performing polycrystalline deposition on the epitaxial layer of the emitter region window to form an emitter polycrystalline layer; performing ion implantation of the emitter polycrystalline layer with a second conductivity type; and low-temperature push-junction to push the ions of the second conductivity type in the polycrystalline layer into the intrinsic base region to form the emitter region.

[0034] Preferably, when the first isolation structure is a field oxide layer, the thickness of the first isolation structure is [missing information].

[0035] Preferably, when the second isolation structure is a field oxide layer, the thickness of the second isolation structure is [missing information].

[0036] Preferably, the method for manufacturing the semiconductor structure further includes: forming an interlayer dielectric layer on the epitaxial layer, the first isolation structure, and the second isolation structure; forming a first contact hole, a second contact hole, and a third contact hole penetrating the interlayer dielectric layer, wherein the first contact hole contacts the base region, the second contact hole contacts the emitter region, and the third contact hole contacts the collector region; and forming a base, an emitter, and a collector on the interlayer dielectric layer, wherein the base contacts the first contact hole, the emitter contacts the second contact hole, and the collector contacts the third contact hole.

[0037] Preferably, before forming the first isolation structure, the method further includes: forming a third isolation structure, the third isolation structure penetrating the epitaxial layer and extending into the substrate; wherein a portion of the first isolation structure is located above the third isolation structure.

[0038] Preferably, the first doping type is P-type and the second doping type is N-type.

[0039] Preferably, the semiconductor structure is a high-frequency transistor.

[0040] Preferably, when forming the base region and the collector region, the first isolation structure serves as a barrier layer for ion implantation; when forming the emitter region, the second isolation structure serves as a barrier layer for ion implantation and a barrier layer for ion diffusion during annealing.

[0041] According to a fourth aspect of the present invention, a method for manufacturing an integrated circuit is provided, comprising at least the method for manufacturing a semiconductor structure as described above.

[0042] Preferably, the integrated circuit is a BICMOS circuit or a BCD circuit.

[0043] According to the semiconductor structure and manufacturing method thereof, and the integrated circuit and manufacturing method thereof according to embodiments of the present invention, multiple first isolation structures and multiple second isolation structures are formed by two LOCOS local silicon oxidation processes. The first isolation structure isolates the base region and collector region in the epitaxial layer, and the second isolation structure isolates the side of the emitter region from the base region. This can reduce the parasitic capacitance between the emitter region and the base region and improve the characteristic frequency of the semiconductor structure.

[0044] Furthermore, the collector region includes a first injection region and a second injection region, wherein the second injection region is in contact with the buried layer, the first injection region is located above the second injection region, and the doping concentration of the second injection region is less than that of the first injection region, which can reduce the series resistance of the collector region.

[0045] Furthermore, the base region includes an intrinsic base region and an intrinsic base region, with a certain distance between the emitter region and the intrinsic base region. The intrinsic base region can reduce the base region resistance and increase the frequency. The distance between the emitter region and the intrinsic base region is determined by the second isolation structure, which increases the stability of the base region resistance.

[0046] Furthermore, the base region and collector region are formed by ion implantation, and the first isolation structure can be used as a barrier layer for ion implantation; the intriguing base region is formed by ion implantation, and the second isolation structure can be used as a barrier layer for ion implantation and a barrier layer for ion diffusion during annealing, forming a self-aligned process, which can reduce the base region resistance of the semiconductor structure, thereby increasing the characteristic frequency of the semiconductor structure. Attached Figure Description

[0047] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0048] Figure 1 This diagram illustrates a semiconductor structure provided according to a first embodiment of the present invention.

[0049] Figure 2 A schematic diagram of a semiconductor structure provided according to a second embodiment of the present invention is shown;

[0050] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention is shown;

[0051] Figures 4a-4g The diagram shows the structural schematics of each step in the semiconductor structure manufacturing method provided in the first embodiment of the present invention. Detailed Implementation

[0052] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0053] This invention can be presented in various forms, some of which will be described below.

[0054] Figure 1 A schematic diagram of a semiconductor structure according to a first embodiment of the present invention is shown. This semiconductor structure is, for example, a high-frequency transistor, and the high-frequency transistor is, for example, a high-frequency NPN transistor. See also... Figure 1 The semiconductor structure 200 includes a substrate 201, a buried layer 202 on the substrate 201, an epitaxial layer 203 on the substrate 201 and the buried layer 202, a base region, a collector region, and an emitter region 211 in the epitaxial layer 203, a first isolation structure 205, a second isolation structure 210, and an interlayer dielectric layer (ILD) 213 on the surface of the epitaxial layer 203. In this embodiment, the substrate 201 can be any suitable type of semiconductor substrate, such as a silicon substrate, a germanium-silicon substrate, etc. The substrate 201 has a first doping type; the buried layer 202 and the epitaxial layer 203 have a second doping type, which is the opposite of the first doping type. This embodiment of the invention uses P-type doping as the first doping type and N-type doping as the second doping type as an example for illustration, but it is not limited to this.

[0055] The buried layer 202 is located between the substrate 201 and the epitaxial layer 203, and is located in the active region AA.

[0056] In this embodiment, the base region includes an intrinsic base region 207 and an intrinsic base region 209. The doping type of the intrinsic base region 207 and the intrinsic base region 209 is a first doping type. The doping concentration of the intrinsic base region 209 is higher than that of the intrinsic base region 207.

[0057] The extrinsic base region 209 is located on one side of the intrinsic base region 207 and is in contact with the intrinsic base region 207. The intrinsic base region 207 surrounds the emitter region 211 and is in contact with the emitter region 211. The emitter region 211 is separated from the extrinsic base region 209 by a certain distance. The extrinsic base region 209 can reduce the base resistance and increase the frequency of the semiconductor structure. The distance between the emitter region 211 and the extrinsic base region 209 is determined by the second isolation structure 210, which increases the stability of the base resistance.

[0058] The collector region is located on the side of the intrinsic base region 207 away from the non-intrinsic base region 209.

[0059] The first isolation structure 205 isolates the base region and the collector region, and the second isolation structure 210 isolates the side of the emitter region 211 from the base region.

[0060] In this embodiment, the first isolation structure 205 and the second isolation structure 210 are field oxide layers, both formed using the LOCOS local oxidation process. The thickness of the first isolation structure 205 is... The thickness of the second isolation structure 210 is

[0061] Specifically, the first isolation structure 205 isolates the intrinsic base region 207 from the collector region, and the second isolation structure 210 isolates the side of the emitter region 211 from the intrinsic base region 207. That is, the sidewall of the emitter region 211 is in contact with the second isolation structure 210, but not with the intrinsic base region 207.

[0062] The collector region includes at least a first implantation region 208, which is located on the surface of the epitaxial layer 203. The first implantation region 208 is isolated from the intrinsic base region 207 by a first isolation structure 205. The first implantation region 208 is doped with a second doping type. In a preferred embodiment, the collector region further includes a second implantation region 206, which is located between the first implantation region 208 and the buried layer 202, and contacts both the first implantation region 208 and the buried layer 202 to connect them. The second implantation region 206 is doped with a second doping type. The doping concentration of the second implantation region 206 is lower than that of the first implantation region 208.

[0063] The emitter region 211 is doped with a second doping type. The emitter region 211 is formed using a polycrystalline process. Specifically, photoresist is coated onto the second isolation structure 210, and the emitter region window is exposed and developed to reveal the surface of the intrinsic base region 207 and part of the surface of the second isolation structure 210. Before polycrystalline silicon deposition, the emitter region window is cleaned to remove the native oxide layer on its surface. Then, polycrystalline silicon is immediately deposited in the furnace tube. The thickness of the deposited polycrystalline silicon is [missing information]. To obtain polysilicon with a second type of conductivity, impurities are implanted into it. To ensure low leakage current in the device, arsenic (As) is typically used. + Implantation. After doping, a low-temperature annealing process below 1000°C is used to implant the As into the polycrystalline silicon. + Impurities are appropriately pushed into the intrinsic base region 207 to form the emitter region 211. Then, the polysilicon is etched using photolithography and etching methods to retain the polysilicon on the emitter region 211, forming the emitter polysilicon 212. The thickness of the emitter polysilicon 212 is...

[0064] The semiconductor structure further includes an interlayer dielectric layer (ILD) 213 covering the epitaxial layer 203, the first isolation structure 205, the second isolation structure 210, and the emitter polycrystalline 212, and a first contact hole 214, a second contact hole 215, and a third contact hole 216 penetrating the interlayer dielectric layer 213. The first contact hole 214 contacts the non-intrinsic base region 209, the second contact hole 215 contacts the emitter region 211 (emitter polycrystalline 212), and the third contact hole 216 contacts the first injection region 208 of the collector region.

[0065] The first contact hole 214, the second contact hole 215, and the third contact hole 216 are used to lead out the corresponding electrodes.

[0066] The semiconductor structure further includes a base 217, an emitter 218, and a collector 219 located on the interlayer dielectric layer 213. The base 217 is electrically connected to the intrinsic base region 209 via a first contact hole 214. The emitter 218 is electrically connected to the emitter region 211 via a second contact hole 215 and an emitter polycrystalline structure 212. The collector 219 is electrically connected to the first injection region 208 of the collector region via a third contact hole 216. The base 217, emitter 218, and collector 219 are all metal layers, such as aluminum, aluminum-copper, or aluminum-silicon-copper, but are not limited to these.

[0067] In a preferred embodiment, the base 217, emitter 218, and collector 219 comprise a titanium-titanium nitride layer, a metal layer, and a titanium nitride layer stacked sequentially from bottom to top, which can reduce the reflectivity of the metal layer and facilitate photolithography.

[0068] In a preferred embodiment, the semiconductor structure further includes a third isolation structure 204 that penetrates the epitaxial layer 203 and extends into the substrate 201. The third isolation structure 204 is doped with a first doping type.

[0069] This invention also provides an integrated circuit comprising the semiconductor structure described above. The integrated circuit is, for example, a bipolar and complementary metal-oxide-semiconductor (BiCMOS) circuit or a bipolar CMOS DMOS (BCD) circuit.

[0070] The semiconductor structure and integrated circuit of the present invention include a plurality of first isolation structures and a plurality of second isolation structures. The first isolation structures isolate the base region and the collector region in the epitaxial layer, and the second isolation structures isolate the side of the emitter region from the base region. This can reduce the parasitic capacitance between the emitter region and the base region and improve the characteristic frequency of the semiconductor structure.

[0071] Furthermore, the collector region includes a first injection region and a second injection region, wherein the second injection region is in contact with the buried layer, the first injection region is located above the second injection region, and the doping concentration of the second injection region is less than that of the first injection region, which can reduce the series resistance of the collector region.

[0072] Furthermore, the base region includes an intrinsic base region and an intrinsic base region, with a certain distance between the emitter region and the intrinsic base region. The intrinsic base region can reduce the base region resistance and increase the frequency. The distance between the emitter region and the intrinsic base region is determined by the second isolation structure, which increases the stability of the base region resistance.

[0073] Furthermore, the base region and collector region are formed by ion implantation, and the first isolation structure can be used as a barrier layer for ion implantation. The intriguing base region is formed by ion implantation, and the second isolation structure can be used as a barrier layer for ion implantation and a barrier layer for ion diffusion during annealing, forming a self-aligned process. This can reduce the base region resistance of the semiconductor structure, thereby increasing the characteristic frequency of the semiconductor structure.

[0074] Figure 2 A schematic diagram of a semiconductor structure provided according to a second embodiment of the present invention is shown. Compared with the first embodiment, both the first isolation structure 205 and the second isolation structure 210 in this embodiment are shallow trench structures.

[0075] In this embodiment, the first isolation structure 205 and the second isolation structure 210 are formed using a shallow trench STI process.

[0076] The first isolation structure 205 includes a first shallow trench STI1 and an oxide layer located in the first shallow trench, and the second isolation structure 210 includes a second shallow trench STI2 and an oxide layer located in the second shallow trench.

[0077] This invention also provides an integrated circuit comprising the semiconductor structure described above. The integrated circuit is, for example, a bipolar and complementary metal-oxide-semiconductor (BiCMOS) circuit or a bipolar CMOS DMOS (BCD) circuit.

[0078] The semiconductor structure and integrated circuit of the present invention include a plurality of first isolation structures and a plurality of second isolation structures. The first isolation structures isolate the base region and the collector region in the epitaxial layer, and the second isolation structures isolate the side of the emitter region from the base region. This can reduce the parasitic capacitance between the emitter region and the base region and improve the characteristic frequency of the semiconductor structure.

[0079] Furthermore, the collector region includes a first injection region and a second injection region, wherein the second injection region is in contact with the buried layer, the first injection region is located above the second injection region, and the doping concentration of the second injection region is less than that of the first injection region, which can reduce the series resistance of the collector region.

[0080] Furthermore, the base region includes an intrinsic base region and an intrinsic base region, with a certain distance between the emitter region and the intrinsic base region. The intrinsic base region can reduce the base region resistance and increase the frequency of the semiconductor structure. The distance between the emitter region and the intrinsic base region is determined by the second isolation structure, which increases the stability of the base region resistance.

[0081] Furthermore, the base region and collector region are formed by ion implantation, and the first isolation structure can be used as a barrier layer for ion implantation. The intriguing base region is formed by ion implantation, and the second isolation structure can be used as a barrier layer for ion implantation and a barrier layer for ion diffusion during annealing, forming a self-aligned process. This can reduce the base region resistance of the semiconductor structure, thereby increasing the characteristic frequency of the semiconductor structure.

[0082] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention is shown. Figures 4a-4g This diagram illustrates the structural steps of the semiconductor structure manufacturing method provided in the first embodiment of the present invention. Figure 3 As shown, the method for manufacturing the semiconductor structure includes the following steps.

[0083] In step S01, an epitaxial layer is formed on the substrate.

[0084] See Figure 4a An epitaxial layer 203 is formed on the substrate 201.

[0085] In this embodiment, the substrate 201 can be any suitable type of semiconductor substrate, such as a silicon substrate, a germanium-silicon substrate, etc. The substrate 201 has a first doping type; the epitaxial layer 203 has a second doping type, which is the opposite of the first doping type. This embodiment of the invention uses P-type doping as the first doping type and N-type doping as the second doping type as an example for illustration, but it is not limited to this. The thickness of the epitaxial layer 203 is, for example, 1µm to 2µm.

[0086] In a preferred embodiment, after forming the epitaxial layer 203, the method further includes forming a third isolation structure 204, which penetrates the epitaxial layer 203 and extends into the substrate 201. The third isolation structure 204 is doped with a first doping type, with implanted ions such as boron and an implantation dose of, for example, 7E13–8E14 cm⁻¹. -2 .

[0087] In a preferred embodiment, prior to forming the epitaxial layer 203, a buried layer 202 is also formed on the substrate 201, the buried layer 202 being located between the substrate 201 and the epitaxial layer 203. Further, photolithography, implantation, and annealing are performed on the substrate 201 to form the buried layer 202, with implanted ions such as antimony (Sb). + The injection dose is, for example, 5E14~2E15cm. -2 This gives the buried layer 202 a second doping type.

[0088] In a preferred embodiment, after forming the buried layer 202, the method further includes: forming a second implantation region 206 in the epitaxial layer 203, the second implantation region 206 extending from the surface of the epitaxial layer 203 to the surface of the buried layer 202 to contact the buried layer 202. The second implantation region 206 is doped with a second doping type, the implanted ion is, for example, phosphorus, and the implantation dose is, for example, 1E15 to 5E15 cm⁻¹. -2 .

[0089] In step S02, a first isolation structure 205 is formed on the epitaxial layer, wherein the first isolation structure 205 defines the regions of the collector region and the base region for isolating the collector region and the base region from each other.

[0090] See Figure 4a The steps for forming the first isolation structure 205 include: forming a pad oxide layer 220 and a first silicon nitride layer (not shown) on the epitaxial layer 203; etching the first silicon nitride layer to form a first isolation region; performing LOCOS silicon local oxidation in the first isolation region to form the first isolation structure 205; removing the first silicon nitride layer and performing sacrificial oxidation on the pad oxide layer 220 region. The first isolation structure 205 defines the base region and the collector region, and isolates the base region and the collector region from each other. If the first isolation structure 205 is a shallow trench structure, a first shallow trench is formed in the epitaxial layer 203, and then an oxide layer is filled in the first shallow trench to form the first isolation structure.

[0091] In step S03, a base region is formed in the epitaxial layer and a second isolation structure 210 is formed on the epitaxial layer, the second isolation structure 210 defining the region of the emitter region 211.

[0092] See Figure 4b The formation of a base region in the epitaxial layer 203 includes: forming photoresist on the epitaxial layer 203, and exposing and developing the photoresist to form a base region window; performing ion implantation on the base region window to form an intrinsic base region 207, and removing the photoresist. The intrinsic base region 207 is located below the surface of the epitaxial layer 203.

[0093] In this embodiment, the intrinsic base region 207 is doped with the first doping type, and the implanted ion is, for example, boron, with an implantation dose of, for example, 1E13 to 1E14 cm⁻¹. -2 .

[0094] Further, a second silicon nitride layer 221 is deposited on the pad oxide layer 220, and the second silicon nitride layer 221 is etched to form a second isolation region 222.

[0095] See Figure 4c In the second isolation structure region 222, LOCOS silicon local oxidation is performed to form the second isolation structure 210, and then the second silicon nitride layer 221 is removed. The thickness of the second isolation structure 210 is... The second isolation structure 210 isolates the side of the emitter region from the intrinsic base region 207 and defines the emitter region window. If the second isolation structure 210 is a shallow trench structure, a second shallow trench is formed in the epitaxial layer 203, and then an oxide layer is filled in the second shallow trench to form the second isolation structure.

[0096] In step S04, a collector region and an emitter region are formed in the epitaxial layer, wherein the first isolation structure isolates the base region and the collector region from each other, and the emitter region is in contact with the base region and isolated from the collector region.

[0097] See Figure 4d A photoresist is formed on the epitaxial layer 203, and the photoresist is exposed and developed to form a collector region window; ion implantation is performed on the collector region window to form a first implantation region 208, the first implantation region 208 having a second doping type.

[0098] In a preferred embodiment, forming the base region further includes: performing ion implantation on one side of the intrinsic base region 207 to form an intrinsic base region 209, wherein the doping type of the intrinsic base region 209 is a first doping type.

[0099] Wherein, the doping concentration of the non-intrinsic base region 209 is higher than that of the intrinsic base region 207; the non-intrinsic base region 209 is located on one side of the intrinsic base region 207 and is in contact with the intrinsic base region 207, and the intrinsic base region 207 surrounds the emitter region 211 and is in contact with the emitter region 211.

[0100] See Figures 4e-4f Photoresist 223 is coated on the epitaxial layer and exposed and developed to form the emission region window 224, and the emission region 211 is formed in the epitaxial layer of the fourth region (see...). Figure 4f The emission region 211 is located below the surface of the epitaxial layer 203 between the second isolation structures 210.

[0101] In this embodiment, the emitter region 211 is formed using a polycrystalline process. Specifically, photoresist 223 is coated on the first isolation structure 205, the pad oxide layer 220, and the second isolation structure 210, and the emitter window 224 is exposed and developed. Before polycrystalline silicon deposition, the natural oxide layer on the surface of the emitter window 224 is cleaned, and then the silicon is immediately deposited in the furnace tube. The thickness of the polycrystalline silicon deposition is... To minimize leakage current in polycrystalline silicon, arsenic (As) is typically used for implanting impurities of the second conductivity type. + The injection dose is, for example, 2E15–2E16 cm. -2 After doping, a low-temperature annealing process below 1000℃ is used to remove the As implanted in the polycrystalline silicon. + Impurities are appropriately pushed into the intrinsic base region 207 to form the emitter region 211. Then, the polysilicon is etched using photolithography and etching methods to retain the polysilicon on the emitter region 211, forming the emitter polysilicon 212. The thickness of the emitter polysilicon 212 is...

[0102] The emitter region 211 is separated from the intrinsic base region 209 by a certain distance. The intrinsic base region 209 can reduce the base region resistance and increase the frequency of the semiconductor structure. The distance between the emitter region 211 and the intrinsic base region 209 is determined by the second isolation structure 210, which increases the stability of the base region resistance.

[0103] In step S05, an interlayer dielectric layer is formed, and a first contact hole, a second contact hole, and a third contact hole are formed penetrating the interlayer dielectric layer, as well as a base, an emitter, and a collector located on the interlayer dielectric layer.

[0104] See Figure 4g An interlayer dielectric layer 213 is deposited on the epitaxial layer 203, the first isolation structure 205, the second isolation structure 210 and the emitter polycrystalline layer 212, and contact hole photolithography and etching are performed to form a first contact hole 214, a second contact hole 215 and a third contact hole 216 penetrating the interlayer dielectric layer 213, and a base 217, an emitter 218 and a collector 219 are formed on the interlayer dielectric layer 213.

[0105] In this embodiment, the first contact hole 214, the second contact hole 215, and the third contact hole 216 are used to lead out corresponding electrodes. The base 217 is electrically connected to the intrinsic base region 209 through the first contact hole 214, the emitter 218 is electrically connected to the emitter region 211 through the second contact hole 215 and the emitter polycrystalline 212, and the collector 219 is electrically connected to the first injection region 208 of the collector region through the third contact hole 216. The base 217, emitter 218, and collector 217 are all metal layers, such as aluminum, aluminum-copper, or aluminum-silicon-copper, but are not limited thereto.

[0106] In a preferred embodiment, the base 217, emitter 218, and collector 219 comprise a titanium-titanium nitride layer, a metal layer, and a titanium nitride layer stacked sequentially from bottom to top, which can reduce the reflectivity of the metal layer and facilitate photolithography.

[0107] Furthermore, the formation order of the first injection region 208 and the non-intrinsic base region 209 in the collector region is not limited to the above.

[0108] Specifically, an etching mask with a predetermined opening is formed on the interlayer dielectric layer 213. Then, the interlayer dielectric layer 213 is etched using the etching mask to remove the interlayer dielectric layer 213 corresponding to the predetermined opening of the etching mask, forming a first contact hole 214 that penetrates the interlayer dielectric layer 213 in the thickness direction to reach the intrinsic base region 209, a second contact hole 215 that reaches the emitter polycrystalline structure 212 above the emitter region 211, and a third contact hole 216 that reaches the first implantation region 208 of the collector region. Then, conductive layers are filled into the first contact hole 214, the second contact hole 215, and the third contact hole 216, and the base 217, emitter 218, and collector 217 are formed above the first contact hole 214, the second contact hole 215, and the third contact hole 216, respectively.

[0109] According to the semiconductor structure and manufacturing method thereof, and the integrated circuit and manufacturing method thereof according to embodiments of the present invention, multiple first isolation structures and multiple second isolation structures are formed by two LOCOS local silicon oxidation processes. The first isolation structure isolates the base region and collector region in the epitaxial layer, and the second isolation structure isolates the side of the emitter region from the base region. This can reduce the parasitic capacitance between the emitter region and the base region and improve the characteristic frequency of the semiconductor structure.

[0110] Furthermore, the collector region includes a first injection region and a second injection region, wherein the second injection region is in contact with the buried layer, the first injection region is located above the second injection region, and the doping concentration of the second injection region is less than that of the first injection region, which can reduce the series resistance of the collector region.

[0111] Furthermore, the base region includes an intrinsic base region and an intrinsic base region, with a certain distance between the emitter region and the intrinsic base region. The intrinsic base region can reduce the base region resistance and increase the frequency of the semiconductor structure. The distance between the emitter region and the intrinsic base region is determined by the second isolation structure, which increases the stability of the base region resistance.

[0112] Furthermore, the base region and collector region are formed by ion implantation, and the first isolation structure can be used as a barrier layer for ion implantation. The intriguing base region is formed by ion implantation, and the second isolation structure can be used as a barrier layer for ion implantation and a barrier layer for ion diffusion during annealing, forming a self-aligned process. This can reduce the base region resistance of the semiconductor structure, thereby increasing the characteristic frequency of the semiconductor structure.

[0113] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate having a first doping type; An epitaxial layer located on a substrate, the epitaxial layer having a second doping type, the first doping type being the opposite of the second doping type; The epitaxial layer contains a base region, an emitter region, and a collector region, wherein the base region and the collector region are isolated from each other, the emitter region is in contact with the base region and isolated from the collector region, the base region has a first doping type, and the emitter region and the collector region have a second doping type; A first isolation structure and a second isolation structure are located on the epitaxial layer. The first isolation structure isolates the base region and the collector region, and the second isolation structure isolates the side of the emitter region from the base region. The base region includes an intrinsic base region and an intrinsic base region. The intrinsic base region is located on one side of the intrinsic base region and contacts the intrinsic base region. The intrinsic base region surrounds the emitter region and contacts the emitter region. The collector region is located on the side of the intrinsic base region away from the non-intrinsic base region.

2. The semiconductor structure according to claim 1, characterized in that, The first isolation structure and the second isolation structure are field oxide layers or shallow trench structures.

3. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the non-intrinsic base region is higher than that of the intrinsic base region.

4. The semiconductor structure according to claim 1, characterized in that, Also includes: A buried layer, located between the substrate and the epitaxial layer, has a second doping type.

5. The semiconductor structure according to claim 4, characterized in that, The current collection area includes: The first injection region is located on the surface of the epitaxial layer; A second injection region is located between the first injection region and the buried layer, and the second injection region contacts the buried layer to connect the first injection region and the buried layer. The first injection region and the second injection region have a second doping type, and the doping concentration of the second injection region is less than the doping concentration of the first injection region.

6. The semiconductor structure according to claim 1, characterized in that, Also includes: Emitter polycrystalline silicon is located above the emitter region.

7. The semiconductor structure according to claim 2, characterized in that, When the first isolation structure is a field oxide layer, the thickness of the first isolation structure is 5000Å~10000Å.

8. The semiconductor structure according to claim 2, characterized in that, When the second isolation structure is a field oxide layer, the thickness of the second isolation structure is 1500 Å to 4000 Å.

9. The semiconductor structure according to claim 1, characterized in that, Also includes: An interlayer dielectric layer located on the epitaxial layer, the first isolation structure, and the second isolation structure; The first contact hole, the second contact hole, and the third contact hole penetrate the interlayer dielectric layer; The base, emitter, and collector are located on the interlayer dielectric layer; The base is in contact with the base region through the first contact hole, the emitter is in contact with the emitter region through the second contact hole, and the collector is in contact with the collector region through the third contact hole.

10. The semiconductor structure according to claim 1, wherein, Also includes: A third isolation structure extends through the epitaxial layer and into the substrate; Part of the first isolation structure is located above the third isolation structure.

11. The semiconductor structure according to claim 1, wherein, The first doping type is P-type, and the second doping type is N-type.

12. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure is a high-frequency transistor.

13. An integrated circuit, characterized in that, It includes at least one semiconductor structure as described in any one of claims 1-12.

14. The integrated circuit according to claim 13, characterized in that, The integrated circuit is a BICMOS circuit or a BCD circuit.

15. A method for manufacturing a semiconductor structure, characterized in that, include: An epitaxial layer is formed on a substrate having a first doping type and the epitaxial layer having a second doping type, wherein the first doping type and the second doping type are opposite. A first isolation structure is formed on the epitaxial layer; A base region is formed in the epitaxial layer and a second isolation structure is formed on the epitaxial layer; A collector region and an emitter region are formed in an epitaxial layer, wherein the first isolation structure isolates the base region and the collector region from each other, the emitter region is in contact with the base region and isolated from the collector region, the base region has a first doping type, and the emitter region and the collector region have a second doping type; The second isolation structure isolates the side of the emitter region from the base region. The base region includes an intrinsic base region and an intrinsic base region. The intrinsic base region is located on one side of the intrinsic base region and contacts the intrinsic base region. The intrinsic base region surrounds the emitter region and contacts the emitter region. The collector region is located on the side of the intrinsic base region away from the non-intrinsic base region.

16. The manufacturing method according to claim 15, characterized in that, The first isolation structure and the second isolation structure are field oxide layers or shallow trench structures.

17. The manufacturing method according to claim 16, characterized in that, The steps to form the first isolation structure include: A pad oxide layer and a first silicon nitride layer are formed on the epitaxial layer; The first silicon nitride layer is etched to form a first isolation region; A first isolation structure is formed by localized silicon oxidation in the first isolation region; The first silicon nitride layer is removed, and the pad oxide layer is subjected to sacrificial oxidation.

18. The manufacturing method according to claim 17, wherein, The steps for forming the second isolation structure include: A second silicon nitride layer is formed on the oxide layer of the padding layer; The second silicon nitride layer is etched to form a second isolation region; A second isolation structure is formed by localized silicon oxidation in the second isolation region. Remove the second silicon nitride layer.

19. The manufacturing method according to claim 16, characterized in that, The steps to form the first isolation structure include: A first shallow trench is formed in the epitaxial layer; An oxide layer is filled into the first shallow trench to form a first isolation structure.

20. The manufacturing method according to claim 15, characterized in that, The formation of base regions in the epitaxial layer includes: Photoresist is formed on the epitaxial layer, and the photoresist is exposed and developed to form a base region window; Ion implantation of the first conductivity type is performed in the base region window to form the intrinsic base region, and the photoresist is removed.

21. The manufacturing method according to claim 19, wherein, The steps for forming the second isolation structure include: A second shallow trench is formed in the epitaxial layer; An oxide layer is filled into the second shallow trench to form a second isolation structure.

22. The manufacturing method according to claim 20, wherein, The formation of the base region also includes: An intrinsic base region is formed by ion implantation on one side of the intrinsic base region; The doping concentration of the non-intrinsic base region is higher than that of the intrinsic base region.

23. The manufacturing method according to claim 15, wherein, Before the formation of the epitaxial layer, the following is also included: A buried layer is formed on a substrate, the buried layer having a second doping type, and the epitaxial layer is located on the substrate and the buried layer.

24. The manufacturing method according to claim 23, wherein, The formation of the current collector region includes: Photoresist is formed on the epitaxial layer, and the photoresist is exposed and developed to form a collector area window; Ion implantation is performed in the current collector window to form a first implantation region, the first implantation region having a second doping type; The formation of the current collector region also includes: Before forming the first injection region, a second injection region is formed in the epitaxial layer, the second injection region contacting the buried layer to connect the first injection region and the buried layer; The second implantation region has a second doping type, and the doping concentration of the second implantation region is less than the doping concentration of the first implantation region.

25. The manufacturing method according to claim 15, wherein, The steps to form the launch zone include: Photoresist is formed on the first isolation structure and the second isolation structure, and the photoresist is exposed and developed to form the emission region window; Polycrystalline emitter is formed by polycrystalline deposition on the epitaxial layer of the emitter region window; The emitter polycrystalline material is subjected to ion implantation of a second conductivity type; Low-temperature push junctions push ions of the second conductivity type within the polycrystalline material into the intrinsic base region to form the emission region.

26. The manufacturing method according to claim 16, wherein, When the first isolation structure is a field oxide layer, the thickness of the first isolation structure is 5000Å~10000Å.

27. The manufacturing method according to claim 16, wherein, When the second isolation structure is a field oxide layer, the thickness of the second isolation structure is 1500 Å to 4000 Å.

28. The manufacturing method according to claim 15, wherein, Also includes: An interlayer dielectric layer is formed on the epitaxial layer, the first isolation structure, and the second isolation structure; A first contact hole, a second contact hole, and a third contact hole are formed that penetrate the interlayer dielectric layer, wherein the first contact hole contacts the base region, the second contact hole contacts the emitter region, and the third contact hole contacts the collector region; A base, an emitter, and a collector are formed on the interlayer dielectric layer, wherein the base is in contact with a first contact hole, the emitter is in contact with a second contact hole, and the collector is in contact with a third contact hole.

29. The manufacturing method according to claim 15, wherein, Before the formation of the first isolation structure, it also includes: A third isolation structure is formed, which penetrates the epitaxial layer and extends into the substrate; Part of the first isolation structure is located above the third isolation structure.

30. The manufacturing method according to claim 15, wherein, The first doping type is P-type, and the second doping type is N-type.

31. The manufacturing method according to claim 15, wherein, The semiconductor structure is a high-frequency transistor.

32. The manufacturing method according to claim 15, characterized in that, When forming the base region and the collector region, the first isolation structure serves as a barrier layer for ion implantation; When the emission region is formed, the second isolation structure serves as a barrier layer for ion implantation and a barrier layer for ion diffusion during annealing.

33. A method for manufacturing an integrated circuit, characterized in that, It includes at least a method for manufacturing a semiconductor structure as described in any one of claims 15-32.

34. The method for manufacturing an integrated circuit according to claim 33, characterized in that, The integrated circuit is a BICMOS circuit or a BCD circuit.

Images