Surrounding gate field effect transistor

Abstract

The present invention is a surround gate field effect transistor, comprising a substrate, at least one channel layer, a source electrode, a drain electrode, a gate electrode, at least one dielectric layer and an insulating layer; the channel layer is located above the substrate and comprises a first layer and a second layer, the first layer is formed of a first two-dimensional semiconductor material, the second layer is formed of a second two-dimensional semiconductor material and covers the surface of the first layer, the energy gap of the second two-dimensional semiconductor material is smaller than the energy gap of the first two-dimensional semiconductor material, two ends of the channel layer are respectively connected to the source electrode and the drain electrode, the gate electrode is located between the source electrode and the drain electrode and surrounds the channel layer, the dielectric layer is between the gate electrode and the channel layer, and the insulating layer is between the gate electrode and the source electrode and between the gate electrode and the drain electrode. Thereby, the present invention can effectively improve the carrier mobility of the two-dimensional semiconductor material channel layer to improve the performance of the surround gate field effect transistor.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to a gate all around field effect transistor. Background Art

[0002] A field effect transistor is a common semiconductor device, having three electrodes: a source, a drain and a gate, and a channel layer connecting the source and the drain. Current flows through the channel layer, and the conductivity of the channel layer depends on the electric field generated by the voltage between the gate and the source. Therefore, the source-drain current can be controlled by the gate-source voltage, serving as a switching device, and its applications are quite extensive.

[0003] In order to improve the performance of field effect transistor devices, there is a trend towards three-dimensional stacking, resulting in the so-called gate all around FET. However, as the device size becomes smaller and smaller, the thickness of the channel layer is bound to be reduced to a few nanometers. Since traditional three-dimensional semiconductor materials such as silicon have many surface dangling bonds, the influence of these dangling bonds on carrier mobility will be significantly increased, causing the carriers or current that can pass through the channel layer under the same voltage to be significantly reduced. To increase the passing current, the voltage has to be increased, but this does not meet the requirements of low power consumption or low voltage. Therefore, attempts are currently being made to use two-dimensional semiconductor materials without surface dangling bonds to fabricate semiconductor devices, hoping to maintain high-performance operation even when the size is reduced. However, two-dimensional semiconductor materials still have limitations in terms of performance as the channel layer. Therefore, how to further improve the efficiency of gate all around field effect transistors has become an urgent issue in the industry. Summary of the Invention

[0004] An object of the present invention is to provide a gate all around field effect transistor, which can effectively improve the carrier mobility of the channel layer of two-dimensional semiconductor materials, thereby enhancing the efficiency of the gate all around field effect transistor.

[0005] To achieve the above object, the wrap-around gate field effect transistor of the present invention includes a substrate, at least one channel layer, a source electrode, a drain electrode, a gate electrode, at least one dielectric layer, and an insulating layer; the channel layer is located above the substrate and includes a first layer and a second layer, the first layer is formed of a first two-dimensional semiconductor material, the second layer is formed of a second two-dimensional semiconductor material and covers the surface of the first layer, the energy gap of the second two-dimensional semiconductor material is smaller than the energy gap of the first two-dimensional semiconductor material, the channel layer has a first end and a second end opposite to each other, the source electrode is connected to the first end of the channel layer, the drain electrode is connected to the second end of the channel layer, the gate electrode is located between the source electrode and the drain electrode and surrounds the channel layer, the dielectric layer is between the gate electrode and the channel layer, and the insulating layer includes a first isolation portion and a second isolation portion, the first isolation portion is between the gate electrode and the source electrode, and the second isolation portion is between the gate electrode and the drain electrode.

[0006] In some embodiments, the channel layer further includes a third layer formed of a third two-dimensional semiconductor material and covering the surface of the second layer, and the energy gap of the third two-dimensional semiconductor material is greater than the energy gap of the second two-dimensional semiconductor material.

[0007] In some embodiments, the second two-dimensional semiconductor material is tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2), or zirconium diselenide (ZrSe2), and the third two-dimensional semiconductor material is tungsten disulfide (WS2), gallium selenide (GaSe), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2), or zirconium diselenide (ZrSe2).

[0008] In some embodiments, the material of the substrate is silicon (Si), silicon with grown silicon dioxide (SiO2 / Si), sapphire, quartz, silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), mica sheet, or silicon with grown silicon nitride (SiN x / Si).

[0009] In some embodiments, the first two-dimensional semiconductor material is tungsten disulfide (WS2), gallium selenide (GaSe), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2) or zirconium diselenide (ZrSe2), and the second two-dimensional semiconductor material is tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2) or zirconium diselenide (ZrSe2).

[0010] In some embodiments, the insulating layer further includes a bottom portion located between the substrate and the gate, between the substrate and the source, and between the substrate and the drain.

[0011] In some embodiments, the bottom of the insulating layer is connected to the first isolation portion and the second isolation portion.

[0012] In some embodiments, the insulating layer further includes a top portion located above the gate and connected to the first isolation portion and the second isolation portion.

[0013] Thereby, the present invention can effectively improve the carrier mobility of the two-dimensional semiconductor material channel layer to improve the performance of the surround gate field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a perspective view of a surround gate field effect transistor according to a first preferred embodiment of the present invention;

[0015] Figure 2 is Figure 1 a cross-sectional view along the A-A cutting line in;

[0016] Figure 3 is Figure 1 a cross-sectional view along the B-B cutting line in;

[0017] Figures 4a - 4b is an energy level diagram of a channel layer of a surround gate field effect transistor according to a first preferred embodiment of the present invention;

[0018] Figure 5 is a cross-sectional view of a surround gate field effect transistor according to a second preferred embodiment of the present invention;

[0019] Figure 6 is a cross-sectional view of a surround gate field effect transistor according to a third preferred embodiment of the present invention.

[0020]

Symbolic Explanation

[0021] 1, 1a, 1b Surrounding Gate Field Effect Transistor

[0022] 10 Substrate

[0023] 20, 20b Channel Layer 21 First Layer 22 Second Layer

[0024] 23 Third Layer 24, 24b First End

[0025] 25, 25b Second End a Curve

[0026] b Dashed Line 26 First Two - Dimensional Potential Well

[0027] 28 Second Two - Dimensional Potential Well

[0028] 30, 30a, 30b Source 32, 32a, 32b Drain 34 Gate

[0029] 40, 40a Dielectric Layer

[0030] 44 Insulating Layer 46 First Isolation Portion 48 Second Isolation Portion

[0031] 50 Bottom 52 Top Detailed Embodiment

[0032] The technical content and features of the present invention are described in detail below through three preferred embodiments in conjunction with the accompanying drawings, as Figures 1 - 3 shown. The surrounding gate field effect transistor 1 provided by the first preferred embodiment of the present invention includes a substrate 10, three channel layers 20, a source 30, a drain 32, a gate 34, three dielectric layers 40, and an insulating layer 44.

[0033] The material of the substrate 10 is a three - dimensional material, i.e., silicon (Si). In other embodiments, the material of the substrate 10 can be sapphire, quartz, silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), mica sheet, silicon with grown silicon dioxide (SiO2 / Si), silicon with grown silicon nitride (SiN x / Si), or other amorphous insulating materials.

[0034] These channel layers 20 are located above the substrate 10 and are arranged at intervals vertically. In the vertical direction, each of the channel layers 20 includes a first layer 21, a second layer 22, and a third layer 23. The first layer 21 is formed of a first two-dimensional semiconductor material. The second layer 22 is formed of a second two-dimensional semiconductor material and covers the upper surface of the first layer 21. The third layer 23 is formed of a third two-dimensional semiconductor material and covers the upper surface of the second layer 22. The energy gap of the second two-dimensional semiconductor material is smaller than the energy gap of the first two-dimensional semiconductor material. The energy gap of the third two-dimensional semiconductor material is larger than the energy gap of the second two-dimensional semiconductor material. In the horizontal direction, each of the channel layers 20 has a relative first end 24 (located at Figure 2 the left side) and a second end 25 (located at Figure 2 the right side).

[0035] The thickness of the first layer 21 is about less than 3 nm. The first two-dimensional semiconductor material is tungsten disulfide (WS2), and the energy gap between its valence band and conduction band is 2.0 eV. The thickness of the second layer 22 is about less than 4 nm. The second two-dimensional semiconductor material is indium selenide (InSe), and the energy gap between its valence band and conduction band is 1.4 eV, which is narrower than the energy gap of the first two-dimensional semiconductor material. Thus, when the Fermi level is balanced, a two-dimensional electron gas (2DEG) similar to that commonly seen at the AlGaN / GaN interface can be formed, so that a first two-dimensional potential well 26 is formed in the second layer 22 adjacent to the first layer 21, and the carrier mobility therein can be effectively improved. As Figure 4a shown, Figure 2 the channel layer 20 in CBM is rotated counterclockwise by 90° to show the change in the conduction band energy level, where the vertical axis is the energy level, curve a is the lower edge of the conduction band (E f ,conduction band min.), and the dashed line b is the Fermi energy level (E Figure 4bAs shown, making the channel layer 20 have two potential wells with high carrier mobility can further improve the carrier mobility of the channel layer 20 (or super-channel). In addition, if the surface of the channel layer of a general semiconductor device is oxidized under the influence of the environment during the manufacturing process, the carrier mobility will be significantly reduced, affecting the device's on-current (I on ). Since the carriers transmitted by the super-channel of the present invention are transmitted through a two-dimensional potential well with a lower potential energy, and the two-dimensional potential well is located deep inside the channel layer 20, it is less affected by the oxidation of the channel layer surface. This is another advantage of the super-channel.

[0036] The first layer 21 and the second layer 22 can be selected from other two-dimensional semiconductor materials, as long as the energy gap of the second two-dimensional semiconductor material is narrower than that of the first two-dimensional semiconductor material. For example, the first two-dimensional semiconductor material can be tungsten disulfide (WS2), gallium selenide (GaSe), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2) or zirconium diselenide (ZrSe2). The second two-dimensional semiconductor material can be tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2) or zirconium diselenide (ZrSe2). The energy gaps of the above two-dimensional semiconductor materials are listed in Table 1. The first two-dimensional semiconductor material / the second two-dimensional semiconductor material can be combined in various ways, such as but not limited to: tungsten disulfide (WS2) / indium selenide (InSe), gallium selenide (GaSe) / indium selenide (InSe), tungsten diselenide (WSe2) / indium selenide (InSe), molybdenum disulfide (MoS2) / indium selenide (InSe), molybdenum diselenide (MoSe2) / indium selenide (InSe), molybdenum disulfide (MoS2) / molybdenum ditelluride (MoTe2), gallium selenide (GaSe) / molybdenum ditelluride (MoTe2), molybdenum diselenide (MoSe2) / molybdenum ditelluride (MoTe2), tungsten disulfide (WS2) / molybdenum ditelluride (MoTe2), tungsten diselenide (WSe2) / molybdenum ditelluride (MoTe2), molybdenum disulfide (MoS2) / tungsten ditelluride (WTe2), gallium selenide (GaSe) / tungsten ditelluride (WTe2), molybdenum diselenide (MoSe2) / tungsten ditelluride (WTe2), tungsten disulfide (WS2) / tungsten ditelluride (WTe2) or tungsten diselenide (WSe2) / tungsten ditelluride (WTe2). These combinations can all form the aforementioned super-channel.

[0037] Table 1

[0038]

[0039]

[0040] In addition, the third layer 23 can also be made of other two-dimensional semiconductor materials, as long as the energy gap of the third two-dimensional semiconductor material is wider than that of the second two-dimensional semiconductor material, and the third two-dimensional semiconductor material and the first two-dimensional semiconductor material can be the same or different materials. For example, the third two-dimensional semiconductor material can be tungsten disulfide (WS2), gallium selenide (GaSe), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2), or zirconium diselenide (ZrSe2). The combination of the second two-dimensional semiconductor material and the third two-dimensional semiconductor material can vary, such as but not limited to: indium selenide (InSe) / tungsten disulfide (WS2), indium selenide (InSe) / gallium selenide (GaSe), indium selenide (InSe) / tungsten diselenide (WSe2), indium selenide (InSe) / molybdenum disulfide (MoS2), indium selenide (InSe) / molybdenum diselenide (MoSe2), molybdenum ditelluride (MoTe2) / molybdenum disulfide (MoS2), molybdenum ditelluride (MoTe2) / gallium selenide ( / GaSe), molybdenum ditelluride (MoTe2) / molybdenum diselenide (MoSe2), molybdenum ditelluride (MoTe2) / tungsten disulfide (WS2), molybdenum ditelluride (MoTe2) / tungsten diselenide (WSe2), tungsten ditelluride (WTe2) / molybdenum disulfide (MoS2), tungsten ditelluride (WTe2) / gallium selenide (GaSe), tungsten ditelluride (WTe2) / molybdenum diselenide (MoSe2), tungsten ditelluride (WTe2) / tungsten disulfide (WS2), or tungsten ditelluride (WTe2) / tungsten diselenide (WSe2). If for cost or other considerations, the third layer 23 can also be omitted, as Figure 4a shown.

[0041] The source electrode 30 is connected to the first end portion 24 of these channel layers 20. In this embodiment, the source electrode 30 is a block made of a metal or a semi-metal material and is connected to the end of the first end portion 24 of these channel layers 20 to form an edge contact. The material of the source electrode 30 can be a metal such as tungsten (W), molybdenum (Mo), or a semi-metal such as bismuth (Bi), antimony (Sb), or an alloy thereof to achieve ohmic contact.

[0042] The drain 32 is connected to the second end 25 of these channel layers 20. In this embodiment, the drain 32 is a block of metal or semimetal material and is connected to the end of the second end 25 of these channel layers 20 to form an edge contact. The material of the drain 32 can be a metal such as tungsten (W), molybdenum (Mo), or a semimetal such as bismuth (Bi), antimony (Sb), or an alloy thereof to achieve ohmic contact.

[0043] The gate 34 is located between the source 30 and the drain 32 and surrounds these channel layers 20. The material of the gate 34 is aluminum (Al), copper (Cu), nickel (Ni), tantalum (Ta), vanadium (V), zirconium (Zr), hafnium (Hf), titanium (Ti), molybdenum (Mo), tungsten (W), cobalt (Co), gold (Au), tungsten nitride (WN x ), titanium nitride (TiN x ), molybdenum nitride (MoN x ), tantalum nitride (TaN x ), tantalum silicon nitride (TaSi x N y ), or other suitable materials, where 0.5 ≤ x ≤ 1 and y < 2.

[0044] These dielectric layers 40 are between the gate 34 and these channel layers 20 and are composed of Figure 3 It can be seen that each of these dielectric layers 40 surrounds and coats each of these channel layers 20 and separates these channel layers 20 from the gate 34. The material of the dielectric layer 40 is aluminum oxide (Al2O3), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), hafnium dioxide (HfO2), hafnium silicate (HfSiO4), lanthanum oxide (La2O3), tantalum pentoxide (Ta2O5), hafnium zirconium oxide (Hf x Zr 1-x O4), lanthanum aluminate (LaAlO x ), hafnium aluminum oxide ((HfO2) x (Al2O3) 1-x ), or other suitable materials with a high dielectric constant, where 0.5 ≤ x < 1.

[0045] The insulating layer 44 includes a first isolation portion 46, a second isolation portion 48, a bottom portion 50, and a top portion 52. The first isolation portion 46 is between the gate 34 and the source 30 and surrounds and coats the dielectric layers 40 to prevent short - circuiting between the gate 34 and the source 30; the second isolation portion 48 is between the gate 34 and the drain 32 and surrounds and coats the dielectric layers 40 to prevent short - circuiting between the gate 34 and the drain 32; the bottom portion 50 is between the substrate 10 and the gate 34, between the substrate 10 and the source 30, and between the substrate 20 and the drain 32. The bottom portion 50 is connected to the first isolation portion 46 and the second isolation portion 48, and the bottom portion 50 serves as an etch stop layer during the manufacturing process; the top portion 52 is above the gate 34 and is connected to the first isolation portion 46 and the second isolation portion 48. The top portion 52 serves as a mask to protect the gate 34, the first isolation portion 46, and the second isolation portion 48 from being affected by etching during the manufacturing process, but it can also be removed in the later stage of the process as needed. The material of the insulating layer 44 is mainly silicon oxide, and the insulating layer 44 can be composed of one or more layers of different materials.

[0046] Since the surround - gate field - effect transistor 1 uses the multi - layer structure of the first layer 21, the second layer 22, and the third layer 23 as the channel layer 20, compared with the channel layer of a known two - dimensional semiconductor material with a single - layer structure, it has a significantly higher carrier mobility, forming a so - called super channel, and the thickness is only a few nanometers, generally less than 10 nm. Therefore, the surround - gate field - effect transistor 1 of the present invention not only reduces the size but also maintains high - performance operation.

[0047] As Figure 5 shown, it is the surround - gate field - effect transistor 1a provided by the second preferred embodiment of the present invention. Its structure is substantially the same as that of the first preferred embodiment, and the difference is that the two ends of the dielectric layer 40a are etched and shrunk during the manufacturing process, so that the subsequently grown source 30a and drain 32a not only form an edge contact with the ends of the first and second ends 24, 25 of the channel layer 20, but also form a surface contact with the upper and lower surfaces of the first and second ends 24, 25. Since the thickness of the channel layer 20 is very thin (only about 10 nm), this can greatly increase the contact area with the source 30a and the drain 32a, making the electrical connection between them more reliable.

[0048] Another as Figure 6As shown, the wrap-around gate field-effect transistor 1b provided by the third preferred embodiment of the present invention has a structure substantially the same as that of the first preferred embodiment, except that the length of the channel layer 20b in the horizontal direction is relatively shortened, so that the end of the first end portion 24b is recessed inward from the surface of the first isolation portion 46 of the insulating layer 44, and the end of the second end portion 25b is recessed inward from the surface of the second isolation portion 48 of the insulating layer 44. In this way, the source electrode 30b extends into the dielectric layer 44 and contacts the end of the first end portion 24a, and the drain electrode 32b extends into the dielectric layer 44 and contacts the end of the second end portion 25b, forming an edge contact. In this way, the object of the present invention can also be achieved.

[0049] Based on the design concept of the present invention, the structure and materials of the wrap-around gate field-effect transistor 1 can have other variations. For example, the number of the channel layers 20 can be increased or decreased as needed, and at least one channel layer 20 is sufficient. The above-mentioned first two-dimensional semiconductor material, second two-dimensional semiconductor material, and third two-dimensional semiconductor material are all binary compounds, but ternary compounds can also be used. For example: MoS 2-x Se x 、MoS 2-x Te x or WS 2-x Se x . All such easily conceivable variations should be covered by the scope of the claims of the present invention.

Claims

1. A wrap-around gate field-effect transistor, characterized in that, Comprising: A substrate; At least one channel layer located above the substrate. The channel layer includes a first layer and a second layer. The first layer is formed of a first two-dimensional semiconductor material, and the second layer is formed of a second two-dimensional semiconductor material and covers the surface of the first layer. The energy gap of the second two-dimensional semiconductor material is smaller than that of the first two-dimensional semiconductor material. The channel layer has a first end and a second end opposite to each other; A source electrode connected to the first end of the channel layer; A drain electrode connected to the second end of the channel layer; A gate electrode located between the source electrode and the drain electrode and surrounding the channel layer; At least one dielectric layer interposed between the gate electrode and the channel layer; and An insulating layer including a first isolation portion and a second isolation portion. The first isolation portion is interposed between the gate electrode and the source electrode, and the second isolation portion is interposed between the gate electrode and the drain electrode.

2. The wraparound gate field effect transistor according to claim 1, characterized in that The channel layer further includes a third layer formed of a third two-dimensional semiconductor material and covering the surface of the second layer. The energy gap of the third two-dimensional semiconductor material is greater than that of the second two-dimensional semiconductor material.

3. The wrap-around gate field effect transistor according to claim 2, characterized in that, The second two-dimensional semiconductor material is tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2), or zirconium diselenide (ZrSe2). The third two-dimensional semiconductor material is tungsten disulfide (WS2), gallium selenide (GaSe), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2), or zirconium diselenide (ZrSe2).

4. The surround gate field effect transistor according to claim 1, wherein The substrate is made of silicon (Si), silicon with grown silicon dioxide (SiO2 / Si), sapphire, quartz, silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), mica sheet, or silicon with grown silicon nitride (SiN x / Si).

5. The wrap-around gate field effect transistor according to any one of claims 1 to 4, wherein The first two-dimensional semiconductor material is tungsten disulfide (WS2), gallium selenide (GaSe), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2), or zirconium diselenide (ZrSe2). The second two-dimensional semiconductor material is tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), indium selenide (InSe), molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), hafnium disulfide (HfS2), hafnium diselenide (HfSe2), zirconium disulfide (ZrS2), or zirconium diselenide (ZrSe2).

6. The wraparound gate field effect transistor according to claim 1, characterized in that The insulating layer further includes a bottom portion located between the substrate and the gate electrode, between the substrate and the source electrode, and between the substrate and the drain electrode.

7. The wrap-around gate field effect transistor according to claim 6, wherein The bottom of the insulating layer is connected to the first isolation portion and the second isolation portion.

8. The wraparound gate field effect transistor according to claim 1, 6 or 7, characterized in that, The insulating layer further includes a top portion located above the gate electrode and connected to the first isolation portion and the second isolation portion.

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