A method for improving PWM resolution

Abstract

The application provides a method for improving PWM resolution, adopts a lookup table method to realize resolution PWM adjustment output, and the resolution is less than 0.1%. In the looked-up table, the full sequence of frequency division coefficients is arranged in a cycle with the frequency division coefficient sub-sequence as a period, and the frequency division coefficient sub-sequence adopts a first arithmetic sequence. The full sequence of high level is composed of multiple different high level sub-sequences, all high level values in the same high level sub-sequence are the same, and the values form a second arithmetic sequence with the values of the adjacent high level sub-sequences. Each frequency division coefficient sub-sequence corresponds to a high level sub-sequence. The increasing and decreasing change directions of the above-mentioned first arithmetic sequence and the second arithmetic sequence are opposite. The application improves the resolution of PWM without improving the frequency of the main clock, the output is stable, the MCU occupation is low, and the application is simple, convenient and easy to use. Without reducing the output frequency of PWM, the energy storage inductance and filter capacitance are reduced, and the circuit board area is reduced.

Description

Technical Field

[0001] This invention relates to a method for improving PWM resolution at a given master clock frequency, and belongs to the field of electronic technology. Background Technology

[0002] The resolution of a PWM circuit depends on the master clock frequency and the PWM output frequency. Generally, to improve the output resolution of a PWM circuit, the master clock frequency should be increased or the output frequency decreased. However, the master clock frequency of some commonly used, cost-effective MCUs is fixed. Increasing the master clock frequency requires using a more expensive MCU with a higher master clock frequency, increasing system cost. Furthermore, increasing the system master clock frequency may also cause electromagnetic compatibility issues. Additionally, decreasing the PWM output frequency leads to poorer stability of the PWM control output voltage or current, requiring more complex filtering circuits, which also increases cost and processing difficulty.

[0003] Patent application CN105375907A discloses a waveform encoding method and system for improving the resolution of PWM signals. This PWM encoding scheme can improve PWM resolution by adjusting the ratio of N and N+1 in the PWM output pulse. However, in this method, the MCU needs to constantly adjust the output of the two encodings, causing jitter in the output signal and increasing the overhead of the MCU.

[0004] Patent application CN107846221A discloses a method for improving DAC accuracy by incorporating PWM principles. Patent application CN108398976A discloses a method for generating high-precision voltage based on pulse width modulation. Patent application CN111490760A discloses a method, device, and equipment for high-precision analog output from a microcontroller based on PWM waveforms. These patents all employ similar methods to patent CN105375907A and suffer from similar technical problems.

[0005] Those skilled in the art are dedicated to improving them, or to providing new methods that differ from them, in an attempt to solve these technical problems. Summary of the Invention

[0006] The technical problem to be solved by this invention is: to improve the PWM resolution at a given master clock frequency, existing methods cannot guarantee the original output frequency, resulting in output jitter and high MCU usage.

[0007] To address the aforementioned technical problems, this invention provides a method for improving PWM resolution by employing a lookup table method to achieve PWM output adjustment with a resolution of less than 0.1%.

[0008] In the table being searched, the full sequence of frequency division coefficients is arranged cyclically with the frequency division coefficient subsequence as one period, and the frequency division coefficient subsequence adopts the first arithmetic sequence;

[0009] In the table being looked up, the full high-level sequence consists of multiple different high-level subsequences. All high-level values ​​in the same high-level subsequence are the same, and they form a second arithmetic sequence with the values ​​of adjacent high-level subsequences.

[0010] Each frequency division coefficient subsequence corresponds to a high-level subsequence;

[0011] The first arithmetic sequence and the second arithmetic sequence have opposite directions of increase and decrease.

[0012] In some embodiments, the method for improving PWM resolution includes the following steps:

[0013] Determine the frequency division coefficient subsequence: The number of frequency division coefficients in the frequency division coefficient subsequence is N, where N is equal to or greater than 2, and the frequency division coefficient subsequence is a decreasing arithmetic sequence;

[0014] Determine the complete sequence of frequency division coefficients: Circularly arrange the subsequences of frequency division coefficients with each subsequence as a period to obtain the complete sequence of frequency division coefficients;

[0015] Determine the high-level base sequence: The high-level base sequence adopts an increasing arithmetic sequence;

[0016] Determine the complete high-level sequence: Repeat each value in the high-level base sequence N times to obtain the complete high-level sequence;

[0017] The duty cycle is obtained from the full sequence of frequency division coefficients and the full sequence of high-level signals, and the resolution is then obtained.

[0018] In some embodiments, the middle number of the frequency division coefficient subsequence is an integer power of 10.

[0019] In some embodiments, N=5, and the duty cycle resolution is 0.02%.

[0020] In some embodiments, the frequency division coefficient subsequence is 1004, 1002, 1000, 998, 996.

[0021] In some embodiments, N = 10, and the duty cycle resolution is 0.01%.

[0022] In some embodiments, the frequency division coefficient subsequence is: 1004, 1003, 1002, 1001, 1000, 999, 998, 997, 996, 995.

[0023] In some embodiments, the frequency division coefficient subsequence is: 1005, 1004, 1003, 1002, 1001, 1000, 999, 998, 997, 996.

[0024] The beneficial effects of this invention are:

[0025] (1) This invention improves the resolution of PWM without increasing the master clock frequency, with stable output, low MCU usage, and simple, convenient and easy-to-use software structure.

[0026] (2) Not reducing the output frequency of PWM helps to reduce the energy storage inductor and filter capacitor, and reduce the circuit board area. Attached Figure Description

[0027] Figure 1 This is the list of values ​​used in the lookup table method in the comparative example of this invention.

[0028] Figure 2 This is a list of values ​​used in the lookup table method in a preferred embodiment of the present invention.

[0029] Figure 3 This is a circuit diagram of a preferred embodiment of the present invention, which uses PWM to control the light source to emit light. Detailed Implementation

[0030] The terms "first," "second," and similar words used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms "an" or "a" and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. In the description of this patent, unless otherwise stated, "a plurality of" means two or more.

[0031] This invention provides a method for improving PWM resolution by using a lookup table method to achieve PWM output adjustment with varying resolution. Specifically, different duty cycles are determined by a series of varying high-level signals and frequency division coefficients. These duty cycles are arranged in an increasing or decreasing order, and adjacent duty cycles are close in magnitude; this is the so-called resolution.

[0032] In the table being looked up, the full sequence of frequency division coefficients is arranged cyclically with each frequency division coefficient subsequence as a period. Each full sequence of frequency division coefficients includes at least two frequency division coefficient subsequences. Each frequency division coefficient subsequence includes at least two frequency division coefficient values. Preferably, each frequency division coefficient subsequence has 5 or 10 frequency division coefficient values, which are arranged in an arithmetic sequence. Preferably, the median of the frequency division coefficients is an integer power of 10, for example, the frequency division coefficient subsequences are: (1) 1004, 1002, 1000, 998, 996; or (2) 1004, 1003, 1002, 1001, 1000, 999, 998, 997, 996, 995. A frequency division coefficient subsequence is an arithmetic sequence, which is called the first arithmetic sequence for ease of description.

[0033] In the table being looked up, the full high-level sequence is divided into multiple distinct high-level subsequences, with all high-level values ​​within the same subsequence being identical. Alternatively, the full high-level sequence can be viewed as an extension of a high-level base sequence, where each value in the base sequence is repeated the same number of times, resulting in a high-level subsequence. The high-level base sequence is an arithmetic sequence, which, for ease of description, is referred to as the second arithmetic sequence.

[0034] The first and second arithmetic sequences change in opposite directions. For example, if the frequency division coefficient subsequence is an increasing arithmetic sequence, then the high-level basis sequence is a decreasing arithmetic sequence, and their quotient changes increasingly. If the frequency division coefficient subsequence is a decreasing arithmetic sequence, then the high-level basis sequence is an increasing arithmetic sequence, and their quotient changes decreasingly.

[0035] In this invention, the frequency division factor is adjusted simultaneously with the duty cycle, thus improving the resolution. The resolution is improved to 0.01% (duty cycle change rate is 0.01%) by fine-tuning the frequency division factor.

[0036] The method provided by this invention can achieve PWM output adjustment of resolution through table lookup in software implementation, avoiding the high MCU occupancy problem caused by the MCU constantly adjusting two different duty cycles in the prior art, and avoiding low-frequency jitter of the output signal.

[0037] This invention improves the output resolution of PWM without reducing the PWM output frequency. The invention employs a fixed PWM division coefficient and high-level ratio, reducing MCU overhead and providing the advantage of stable output signal. Simultaneously, software control is simpler and easier to implement.

[0038] Figure 1This is a circuit diagram of the PWM power supply used in this invention. The power supply is input via VIN, and the MCU controls the PWM output. After adjusting the output current, it is provided to a terminal that requires high precision and stability in current regulation, thereby accurately controlling the LED's illumination.

[0039] This invention is not limited to PWM power supplies, but can also be widely used in various PWM encoding systems such as PWM_ADC, which has practical convenience and social benefits.

[0040] The following examples further illustrate the present invention in detail.

[0041] Comparative Example

[0042] In typical PWM control, assuming the system's highest clock frequency is 30MHz, and to satisfy signal stability, the PWM output frequency needs to be 30KHz. Therefore, the PWM frequency division factor is 30M / 30K = 1000.

[0043] Duty cycle refers to the proportion of on-time relative to the total time within a pulse cycle. The duty cycle value is determined by the proportion of high-level pulses. The duty cycle is calculated by dividing the number of high-level pulses (numerator) by the frequency division factor (denominator). To allow for variation in the duty cycle, the frequency division factor is usually fixed, while the number of high-level pulses varies systematically. The difference between adjacent duty cycles calculated in this way is the resolution.

[0044] When adjusting the duty cycle to regulate the output voltage, the PWM frequency division factor is usually fixed, such as... Figure 1 The PWM frequency division factor is kept constant at 1000, and the sum of the number of high-level and low-level levels is 1000. The number of high-level levels can take any value between 1 and 999. If the number of high-level levels changes continuously from 1 to 999, then the system resolution is 1 / 1000, or 0.1%. Figure 1 This is a portion of the data, with the high level increasing sequentially from 94 to 116, and the duty cycle difference between adjacent levels being 0.1%, thus the minimum resolution can only be 0.1%.

[0045] Example 1

[0046] The encoding scheme employed in this invention can improve the resolution of PWM regulation without increasing the system master clock frequency. By adjusting the duty cycle and simultaneously adjusting the frequency division factor, the resolution is improved. The resolution is increased to 0.01% (duty cycle change rate is 0.01%) by fine-tuning the frequency division factor.

[0047] In the comparative examples above, the number of high-level levels changes continuously with minimal variation, while the frequency division coefficient remains fixed. Therefore, this invention considers slightly varying the frequency division coefficient around a reference frequency division coefficient, resulting in a repetitive but unchanging number of high-level levels. In other words, it is equivalent to... Figure 1 A single row in the list is expanded into multiple rows. When comparing these rows, the numerator remains constant while the denominator changes, and the changes occur from large to small. This further subdivides a duty cycle and improves resolution.

[0048] The PWM regulation scheme used in this invention is as follows: Figure 2 As shown:

[0049] The entire sequence of frequency division coefficients cycles continuously in periods of 10, with the frequency division coefficients decreasing sequentially within the same cycle. In this embodiment, the cyclic subsequence of frequency division coefficients is: 1004, 1003, 1002, 1001, 1000, 999, 998, 997, 996, 995. The entire sequence of frequency division coefficients is obtained by continuously cycling through the above cyclic subsequence. Figure 1 In the table, the above cyclic subsequence repeats twice. The loop sections at the beginning and end of the table may be incomplete, but they must still conform to the cyclical pattern. The frequency division coefficient cyclic subsequence expands around the basic frequency division coefficient of 1000, thus ensuring a relatively stable output frequency. The output frequency fluctuates narrowly around 30kHz, with a maximum of 30.15 and a minimum of 29.88, which is within the allowable operating range.

[0050] exist Figure 2 In this process, the high-level full sequence is divided into several subsequences. Each value in each subsequence is the same, and the increment between adjacent subsequences is in the opposite direction to the increment of the frequency division coefficient. The number of values ​​in each high-level subsequence is equal to the number of values ​​in the same frequency division coefficient cycle, and they correspond one-to-one. Figure 2 This includes a cyclic subsequence of frequency division coefficients: 1004, 1003, 1002, 1001, 1000, 999, 998, 997, 996, 995. The corresponding high-level number is 100, meaning there are ten 100s. Above the high level of 100 are ten 99s, and below 100 are ten 101s, all of which also match this cyclic subsequence of frequency division coefficients.

[0051] The duty cycle is the high level divided by the frequency division factor, and the result is as follows: Figure 2 As shown in the diagram, it is clear that the difference between two adjacent duty cycles is 0.01%, meaning the resolution is 0.01%.

[0052] Example 2

[0053] The difference between this embodiment and Embodiment 1 lies in the cyclic sequence of the frequency division coefficients. In this embodiment, the cyclic subsequence of the frequency division coefficients—1005, 1004, 1003, 1002, 1001, 1000, 999, 998, 997, 996—is based on Embodiment 1, with one numerical position shifted. Thus, the cyclic sequence of the frequency division coefficients still expands around the basic frequency division coefficient of 1000, and the two numbers are essentially the same. This ensures that the output frequency remains relatively stable, fluctuating within a narrow range around 30kHz.

[0054] The cyclic subsequence of the frequency division coefficient can also be: 1006, 1005, 1004, 1003, 1002, 1001, 1000, 999, 998, 997, or 1003, 1002, 1001, 1000, 999, 998, 997, 996, 995, 994. Although it is still an extension around the basic frequency division coefficient of 1000, the numbers at both ends of the same cyclic subsequence of frequency division coefficient differ more, and the maximum or minimum output frequency offset of 30kHz is also greater.

[0055] In this embodiment, the entire high-level sequence is exactly the same as in Embodiment 1. The duty cycle is the high level divided by the frequency division factor. Although the absolute value of the duty cycle is not exactly the same as in Embodiment 1, the difference between two adjacent duty cycles is still 0.01%, that is, the resolution is also 0.01%.

[0056] Example 3

[0057] In Examples 1 and 2, there are 10 values ​​in a cyclic subsequence of a frequency division coefficient. In this example, the corresponding number of values ​​is reduced to 5.

[0058] In this embodiment, the entire sequence of frequency division coefficients cycles continuously in a period of 5 numbers, with the frequency division coefficients decreasing sequentially within the same cycle. In this embodiment, the cyclic subsequence of frequency division coefficients is: 1004, 1002, 1000, 998, 996. This cyclic sequence is repeated continuously to obtain the complete sequence of frequency division coefficients. The cyclic sections at the beginning and end of the table may be incomplete, but they must still conform to the cyclical pattern. The cyclic sequence of frequency division coefficients expands around the basic frequency division coefficient of 1000, thus ensuring a relatively stable output frequency with a narrow fluctuation around 30kHz, which is within acceptable limits.

[0059] The high-level sequence is divided into several subsequences, each with the same value. The increment between adjacent subsequences is in the opposite direction to the frequency division coefficient. The number of values ​​in each high-level subsequence corresponds one-to-one with the number of values ​​within the same frequency division coefficient cycle. The corresponding high-level number is 100, meaning there are five 100s. Above 100 are five 99s, and below 100 are five 101s, each corresponding to a frequency division coefficient cycle: 1004, 1002, 1000, 998, and 996.

[0060] In this embodiment, the difference between two adjacent duty cycles is 0.02%, that is, the resolution is 0.02%, which is slightly worse than the resolution in Embodiment 1, but still finer than the 0.1% in the prior art.

[0061] Example 4

[0062] In Examples 1 and 2, there are 10 values ​​in a cyclic subsequence of a frequency division coefficient. In this example, the corresponding number of values ​​is reduced to 2.

[0063] The entire sequence of frequency division coefficients cycles continuously in two-digit periods, with the frequency division coefficients decreasing sequentially within the same period. In this embodiment, the cyclic sequence of frequency division coefficients is 1000, 995. The frequency division coefficients are obtained by continuously cycling through this sequence. The cyclic sections at the beginning and end of the table may be incomplete, but they must still conform to the cyclical pattern. The cyclic sequence of frequency division coefficients expands around the basic frequency division coefficient of 1000, thus keeping the output frequency basically stable, fluctuating around 30kHz.

[0064] The high-level sequence is divided into several subsequences, each with the same value. The increments between adjacent subsequences are opposite to the direction of the frequency division coefficient. The number of values ​​in each high-level subsequence corresponds one-to-one with the number of values ​​within the same frequency division coefficient cycle. The corresponding high-level number is 100, meaning there are two 100s. Looking at Table 1, the high level above 100 consists of two 99s, and the high level below 100 consists of two 101s, each corresponding to a frequency division coefficient cycle: 1000 and 995.

[0065] Duty cycle is the high level divided by the frequency division factor. In this embodiment, the difference between two adjacent duty cycles is 0.05%, that is, the resolution is 0.05%, which is worse than the resolution in embodiment 3, but still finer than the 0.1% in the prior art.

[0066] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A method for improving PWM resolution, characterized in that, A lookup table method is used to achieve PWM output adjustment for resolution less than 0.1%; In the table being searched, the full sequence of frequency division coefficients is arranged cyclically with the frequency division coefficient subsequence as one period, and the frequency division coefficient subsequence adopts the first arithmetic sequence; In the table being looked up, the full high-level sequence consists of multiple different high-level subsequences. All high-level values ​​in the same high-level subsequence are the same, and they form a second arithmetic sequence with the values ​​of adjacent high-level subsequences. Each of the frequency division coefficient subsequences corresponds to a high-level subsequence; The first arithmetic sequence and the second arithmetic sequence have opposite directions of increase and decrease.

2. The method for improving PWM resolution according to claim 1, characterized in that, Includes the following steps: Determine the frequency division coefficient subsequence: the number of frequency division coefficients in the frequency division coefficient subsequence is N, N is equal to or greater than 2, and the frequency division coefficient subsequence is a decreasing arithmetic sequence; Determine the complete sequence of frequency division coefficients: The complete sequence of frequency division coefficients is obtained by cyclically arranging the subsequences of frequency division coefficients as one period; Determine the high-level base sequence: The high-level base sequence adopts an increasing arithmetic sequence; Determine the high-level full sequence: Repeat each value in the high-level base sequence N times to obtain the high-level full sequence; The duty cycle is obtained from the full sequence of the frequency division coefficients and the full sequence of the high level, and the resolution is obtained.

3. The method for improving PWM resolution according to claim 2, characterized in that, The middle number of the frequency division coefficient subsequence is an integer power of 10.

4. The method for improving PWM resolution according to claim 3, characterized in that, With N=5, the duty cycle resolution is 0.02%.

5. The method for improving PWM resolution according to claim 4, characterized in that, The frequency division coefficient subsequence is 1004, 1002, 1000, 998, 996.

6. The method for improving PWM resolution according to claim 3, characterized in that, With N=10, the duty cycle resolution is 0.01%.

7. The method for improving PWM resolution according to claim 6, characterized in that, The frequency division coefficient subsequence is: 1004, 1003, 1002, 1001, 1000, 999, 998, 997, 996, 995.

8. The method for improving PWM resolution according to claim 6, characterized in that, The frequency division coefficient subsequence is: 1005, 1004, 1003, 1002, 1001, 1000, 999, 998, 997, 996.

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