Shift register, gate drive circuit, display panel and driving method thereof

Abstract

A shift register, a gate driving circuit, a display panel and a driving method thereof. The shift register (100) comprises: an input circuit (110) configured to input the potential of an input signal terminal (CN) to a pull-up node (PU) under the control of a signal of an input control terminal (STV); an output circuit (120) configured to provide a signal of a clock signal terminal (CK) to an output signal terminal (OUT) under the control of the potential of the pull-up node (PU); a first control circuit (130) configured to provide the potential of a first control signal terminal (CKB) to a pull-down node (PD), and to provide the potential of a reference signal terminal (VGL) to the pull-down node (PD) according to the potential of the pull-up node (PU); and a second control circuit (140) connected to the pull-down node (PD), a second control signal terminal (EN), an output signal terminal (OUT) and a reference signal terminal (VGL), and configured to pull down the potential of the output signal terminal (OUT) in a display phase and pull up the potential of the output signal terminal (OUT) in a power-off phase under the control of the potentials of the pull-down node (PD) and the second control signal terminal (EN).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display panel and a driving method thereof. Background Art

[0002] In a display device, a gate drive circuit is usually used to drive multiple sub-pixels for display. For example, when the display device is turned on, the gate drive circuit in the display device is powered on, so that the gate drive circuit generates a gate drive signal, and the gate drive signal is provided to multiple sub-pixels, so that the sub-pixels are turned on for display. When the display device is turned off, the gate drive circuit is powered off, and the gate drive circuit usually includes multiple shift registers connected in cascade to generate multiple output signals that are shifted in sequence as gate drive signals. However, conventional gate drive circuits are prone to display anomalies when powered on. Summary of the invention

[0003] An embodiment of the present disclosure provides a shift register, comprising:

[0004] An input circuit connected to an input signal terminal, an input control terminal and a pull-up node of the shift register, and configured to input the potential of the input signal terminal to the pull-up node under the control of a signal of the input control terminal;

[0005] an output circuit connected to the pull-up node, the clock signal terminal and the output signal terminal, and configured to provide the signal of the clock signal terminal to the output signal terminal under the control of the potential of the pull-up node;

[0006] a first control circuit connected to a first control signal terminal, the pull-up node, a pull-down node of the shift register, and a reference signal terminal, and configured to provide a potential of the first control signal terminal to the pull-down node, and provide a potential of the reference signal terminal to the pull-down node according to a potential of the pull-up node; and

[0007] The second control circuit is connected to the pull-down node, the second control signal terminal, the output signal terminal and the reference signal terminal, and is configured to pull down the potential of the output signal terminal in the display stage and pull up the potential of the output signal terminal in the power-off stage under the control of the potential of the pull-down node and the second control signal terminal.

[0008] For example, the second control circuit includes:

[0009] a pull-down sub-circuit connected to the pull-down node, the output signal terminal and the reference signal terminal, and configured to provide the potential of the reference signal terminal to the output signal terminal under the control of the potential of the pull-down node; and

[0010] The lower electronic circuit is connected to the second control signal terminal, the pull-down node, the output signal terminal and the reference signal terminal, and is configured to provide the potential of the second control signal terminal to the output signal terminal and provide the potential of the reference signal terminal to the pull-down node under the control of the signal of the second control signal terminal.

[0011] For example, the lower electronic circuit includes a first transistor and a second transistor, wherein,

[0012] The gate and the first electrode of the first transistor are connected to the second control signal terminal, and the second electrode of the first transistor is connected to the output signal terminal; and

[0013] A gate of the second transistor is connected to the second control signal terminal, a first electrode of the second transistor is connected to the reference signal terminal, and a second electrode of the second transistor is connected to the pull-down node.

[0014] For example, the pull-down subcircuit includes a third transistor and a first capacitor, wherein:

[0015] The gate of the third transistor is connected to the pull-down node, the first electrode of the third transistor is connected to the reference signal terminal, and the second electrode of the third transistor is connected to the output signal terminal; and

[0016] A first terminal of the first capacitor is connected to the pull-down node, and a second terminal of the first capacitor is connected to the reference signal terminal.

[0017] For example, the pull-down subcircuit further includes a fourth transistor, a gate of the fourth transistor is connected to the output signal terminal, a first electrode of the fourth transistor is connected to the reference signal terminal, and a second electrode of the fourth transistor is connected to the pull-down node.

[0018] For example, the second control circuit includes a fifth transistor and a second capacitor, wherein:

[0019] The gate of the fifth transistor is connected to the pull-down node, the first electrode of the fifth transistor is connected to the second control signal terminal, and the second electrode of the fifth transistor is connected to the output signal terminal; and

[0020] A first terminal of the second capacitor is connected to the pull-down node, and a second terminal of the second capacitor is connected to the reference signal terminal.

[0021] For example, the shift register further includes: a noise reduction circuit connected to the input control terminal, the pull-down node and the reference signal terminal, and configured to provide the potential of the reference signal terminal to the pull-down node under the control of the signal of the input control terminal.

[0022] For example, the noise reduction circuit includes a sixth transistor, a gate of the sixth transistor is connected to the input control terminal, a first electrode of the sixth transistor is connected to the reference signal terminal, and a second electrode of the sixth transistor is connected to the pull-down node.

[0023] For example, the shift register further includes: a reset circuit connected to a reset control terminal, a reset signal terminal and the pull-up node, and configured to provide the potential of the reset signal terminal to the pull-up node under the control of a signal of the reset control terminal.

[0024] For example, the pull-up node includes a first pull-up node connected to the input circuit and a second pull-up node connected to the output circuit, and the first control circuit includes a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor, wherein,

[0025] The gate and the first electrode of the seventh transistor are connected to the first control signal terminal, and the second electrode of the seventh transistor is connected to the pull-down node;

[0026] The gate of the eighth transistor is connected to the pull-down node, the first electrode of the eighth transistor is connected to the reference signal terminal, and the second electrode of the eighth transistor is connected to the first pull-up node;

[0027] The gate of the ninth transistor is connected to the first pull-up node, the first electrode of the ninth transistor is connected to the reference signal terminal, and the second electrode of the ninth transistor is connected to the pull-down node; and

[0028] A gate of the tenth transistor is connected to a power signal terminal, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the second pull-up node.

[0029] For example, the input circuit includes an eleventh transistor, a gate of the eleventh transistor is connected to the input control terminal, a first electrode of the eleventh transistor is connected to the input signal terminal, and a second electrode of the eleventh transistor is connected to the pull-up node.

[0030] For example, the output circuit includes a twelfth transistor and a third capacitor, wherein:

[0031] The gate of the twelfth transistor is connected to the pull-up node, the first electrode of the twelfth transistor is connected to the clock signal terminal, and the second electrode of the twelfth transistor is connected to the output signal terminal; and

[0032] A first end of the third capacitor is connected to the pull-up node, and a second end of the third capacitor is connected to the output signal terminal.

[0033] For example, the reset circuit includes a thirteenth transistor, a gate of the thirteenth transistor is connected to the reset control terminal, a first electrode of the thirteenth transistor is connected to the reset signal terminal, and a second electrode of the thirteenth transistor is connected to the pull-up node.

[0034] For example, the shift register also includes a total reset circuit connected to the total reset signal terminal, the pull-up node and the reference signal terminal, and is configured to provide the potential of the reference signal terminal to the pull-up node under the control of the signal of the total reset signal terminal.

[0035] For example, the total reset circuit includes a fourteenth transistor, a gate of the fourteenth transistor is connected to the total reset signal terminal, a first electrode of the fourteenth transistor is connected to the reference signal terminal, and a second electrode of the fourteenth transistor is connected to the pull-up node.

[0036] The embodiment of the present disclosure further provides a gate driving circuit, comprising N stages of cascaded shift registers, each of which is the above-mentioned shift register, wherein:

[0037] The input signal terminal of each shift register is connected to receive an input signal, the reset signal terminal is connected to receive a reset signal, and the second control signal terminal is connected to receive a second control signal;

[0038] The input control terminal of the n-th shift register is connected to the output signal terminal of the ni-th shift register, and the reset control terminal of the n-th shift register is connected to the output signal terminal of the n+j-th shift register; and

[0039] The N-stage cascaded shift registers are divided into at least one group, each group includes K-stage cascaded shift registers, the clock signal ends of the K-stage cascaded shift registers are respectively connected to receive K clock signals, and the first control signal ends of the K-stage cascaded shift registers are respectively connected to receive the K clock signals, wherein N, K, n, i and j are all integers, 1≤n≤N, 1<K≤N.

[0040] For example, i=j=4, K=8, the K clock signals include a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal and an eighth clock signal, and in each group of shift registers:

[0041] The clock signal terminal of the first stage shift register is connected to receive the first clock signal, and the first control signal terminal of the first stage shift register is connected to receive the fifth clock signal;

[0042] The clock signal terminal of the second stage shift register is connected to receive the second clock signal, and the first control signal terminal of the second stage shift register is connected to receive the sixth clock signal;

[0043] The clock signal terminal of the third-stage shift register is connected to receive the third clock signal, and the first control signal terminal of the third-stage shift register is connected to receive the seventh clock signal;

[0044] The clock signal terminal of the fourth-stage shift register is connected to receive the fourth clock signal, and the first control signal terminal of the fourth-stage shift register is connected to receive the eighth clock signal;

[0045] The clock signal terminal of the fifth-stage shift register is connected to receive the fifth clock signal, and the first control signal terminal of the fifth-stage shift register is connected to receive the first clock signal;

[0046] The clock signal terminal of the sixth-stage shift register is connected to receive the sixth clock signal, and the first control signal terminal of the sixth-stage shift register is connected to receive the second clock signal;

[0047] The clock signal terminal of the seventh-stage shift register is connected to receive the seventh clock signal, and the first control signal terminal of the seventh-stage shift register is connected to receive the third clock signal;

[0048] The clock signal terminal of the eighth stage shift register is connected to receive the eighth clock signal, and the first control signal terminal of the eighth stage shift register is connected to receive the fourth clock signal.

[0049] For example, i=j=2, K=4, the K clock signals include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, and in each group of shift registers:

[0050] The clock signal terminal of the first stage shift register is connected to receive the first clock signal, and the first control signal terminal of the first stage shift register is connected to receive the third clock signal;

[0051] The clock signal terminal of the second stage shift register is connected to receive the second clock signal, and the first control signal terminal of the second stage shift register is connected to receive the fourth clock signal;

[0052] The clock signal terminal of the third-stage shift register is connected to receive the third clock signal, and the first control signal terminal of the third-stage shift register is connected to receive the first clock signal;

[0053] The clock signal terminal of the fourth-stage shift register is connected to receive the fourth clock signal, and the first control signal terminal of the fourth-stage shift register is connected to receive the second clock signal.

[0054] An embodiment of the present disclosure further provides a display panel, comprising:

[0055] a plurality of sub-pixels arranged in an array; and

[0056] At least one of the above-mentioned gate driving circuits, wherein the N-stage shift registers in the gate driving circuit are respectively connected to a plurality of rows of sub-pixels in the array.

[0057] For example, the display panel includes two gate driving circuits, and the two gate driving circuits are respectively located on both sides of the array of the plurality of sub-pixels along a first direction, wherein the first direction is a row direction of the array.

[0058] For example, the display panel includes a gate driving circuit, wherein i_j=2, K=4, and the odd-numbered shift register and the even-numbered shift register in the gate driving circuit are respectively located on both sides of the array of the plurality of sub-pixels along the first direction.

[0059] For example, the shift register includes an input circuit, a first control circuit, a second control circuit and an output circuit, wherein the input circuit, the first control circuit, the second control circuit and the output circuit are arranged in sequence along a first direction, and a size of each of the input circuit, the first control circuit, the second control circuit and the output circuit in the second direction is 0.8-1.4 times a size of the sub-pixel in the second direction, wherein the first direction is a row direction of the array, and the second direction is perpendicular to the first direction.

[0060] For example, the display panel also includes a multiplexing circuit, which is connected to M columns of sub-pixels in the array. The multiplexing circuit is configured to multiplex the received m input data signals into M output data signals under the control of a first selection signal and a second selection signal and provide them to the M columns of sub-pixels respectively, where m and M are integers greater than 1, and M is an integer multiple of m.

[0061] An embodiment of the present disclosure further provides a driving method of the above-mentioned gate driving circuit, comprising:

[0062] In the display stage, an input signal of a first level is provided to the gate driving circuit, and each shift register outputs a gate driving signal at a respective output signal terminal based on the input signal under the control of the potential of the respective input control terminal;

[0063] In the power-off stage, a second control signal of a first level and an input signal of a second level are provided to the gate drive circuit, each shift register provides the second control signal of the first level to its respective output signal terminal, and each shift register provides the input signal of the second level to its respective pull-up node under the control of the potential of its respective input control terminal.

[0064] For example, the second control circuit of each shift register includes a pull-down sub-circuit and a lower electronic circuit, wherein:

[0065] In the display phase, the pull-down subcircuit of each shift register provides the potential of the reference signal terminal of the shift register to the output signal terminal of the shift register under the control of the potential of the pull-down node of the shift register; and

[0066] In the power-down phase, the lower electronic circuit of each shift register provides a second control signal of a first level at the second control signal terminal of the shift register to the output signal terminal of the shift register and provides the potential of the reference signal terminal of the shift register to the pull-down node of the shift register.

[0067] For example, the second control circuit of each shift register includes a fifth transistor and a second capacitor, wherein:

[0068] In the display stage, a second control signal of a second level is provided to the gate driving circuit, and the second control circuit of each shift register provides the second control signal of the second level to the output signal terminal of the shift register under the control of the potential of the pull-down node of the shift register;

[0069] In the power-down stage, K clock signals maintaining the first level are provided to the gate drive circuit, and the first control circuit of each shift register provides the clock signal of the first level received at the first control signal terminal of the shift register to the pull-down node of the shift register, and the potential of the pull-down node causes the second control circuit of the shift register to provide the second control signal of the first level to the output signal terminal of the shift register.

[0070] For example, in the display stage, K sequentially shifted clock signals are provided to the gate drive circuit, and each shift register outputs a gate drive signal at its own output signal terminal based on the input signal and the received clock signal under the control of the potential of its own input control terminal, wherein the k+1th clock signal is shifted by a unit scan time relative to the kth clock signal, wherein k is an integer, 1≤k≤K-1, and the unit scan time is the time required for the gate drive circuit to scan a row of pixels.

[0071] For example, in the gate driving circuit, i=j=4 and K=8, and in the display period, the K clock signals are periodic signals with a duty cycle of 25% and a pulse width of 2 times the unit scanning time.

[0072] For example, in the gate driving circuit, i=j=2 and K=4, and in the display period, the K clock signals are periodic signals with a duty cycle of 50% and a pulse width of 2 times the unit scanning time.

[0073] For example, in the gate driving circuit, i=j=4 and K=8, and in the display period, the K clock signals are periodic signals with a duty cycle of 12.5% ​​and a pulse width of a unit scanning time.

[0074] For example, in the gate driving circuit, i=j=2 and K=4, and in the display period, the K clock signals are periodic signals with a duty cycle of 25% and a pulse width of a unit scanning time. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 A block diagram of a shift register according to an embodiment of the present disclosure is shown.

[0076] Figure 2A A circuit diagram of a shift register according to an embodiment of the present disclosure is shown.

[0077] Figure 2B A circuit diagram of a shift register according to another embodiment of the present disclosure is shown.

[0078] Figure 2C A circuit diagram of a shift register according to another embodiment of the present disclosure is shown.

[0079] Figure 2D A circuit diagram of a shift register according to another embodiment of the present disclosure is shown.

[0080] Figure 3 A circuit diagram of a shift register according to another embodiment of the present disclosure is shown.

[0081] Figure 4 A circuit diagram of a shift register according to another embodiment of the present disclosure is shown.

[0082] Figure 5 A schematic diagram of a gate driving circuit according to an embodiment of the present disclosure is shown.

[0083] Figure 6 A schematic diagram of a gate driving circuit according to another embodiment of the present disclosure is shown.

[0084] Fig. 7A A schematic diagram of a display panel according to an embodiment of the present disclosure is shown.

[0085] Figure 7B Shows Fig. 7A A schematic diagram of the layout of the display panel.

[0086] Figure 7C Shows Figure 7B Schematic diagram of the layout of the shift register in .

[0087] Figure 8A schematic diagram of a display panel according to another embodiment of the present disclosure is shown.

[0088] Fig. 9 A schematic diagram of a display panel according to another embodiment of the present disclosure is shown.

[0089] Fig.10 A schematic diagram of a display panel according to another embodiment of the present disclosure is shown.

[0090] Fig.11 A schematic diagram of a display panel according to another embodiment of the present disclosure is shown.

[0091] Fig.12 A circuit diagram of a multiplexing circuit according to an embodiment of the present disclosure is shown.

[0092] Fig.13 A signal timing diagram of a shift register in a display phase according to an embodiment of the present disclosure is shown.

[0093] Fig.14 A signal timing diagram of a gate driving circuit in a display stage according to an embodiment of the present disclosure is shown.

[0094] Fig.15 A signal timing diagram of a gate driving circuit in a display stage according to another embodiment of the present disclosure is shown.

[0095] Fig.16 The working timing diagram of the gate driving circuit according to the embodiment of the present disclosure is shown.

[0096] Fig.17 FIG. 4 shows an operation timing diagram of a gate driving circuit according to another embodiment of the present disclosure.

[0097] Fig.18 FIG. 4 shows a timing diagram of a gate driving circuit in a power-on phase according to another embodiment of the present disclosure.

[0098] Fig.19A A signal timing diagram of a display panel according to an embodiment of the present disclosure is shown.

[0099] Fig.19B A schematic diagram showing a signal waveform of a display panel according to an embodiment of the present disclosure is shown.

[0100] Fig.19C A simulation diagram of a signal waveform of a display panel according to an embodiment of the present disclosure is shown.

[0101] Fig. 20 A signal timing diagram of a display panel according to another embodiment of the present disclosure is shown.

[0102] Figures 21A to 21C Shows Fig. 20 Signal simulation diagram of an embodiment of the present invention.

[0103] Fig. 22 A signal waveform diagram of a display panel according to another embodiment of the present disclosure is shown.

[0104] Figures 23A to 23C Shows Fig. 22 Signal simulation diagram of an embodiment of the present invention.

[0105] Fig.24 A flow chart of a driving method of a gate driving circuit according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0106] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only used for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0107] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by those skilled in the art. The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0108] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0109] In addition, in the description of the embodiments of the present disclosure, the terms "first level" and "second level" are only used to distinguish the difference in amplitude between the two levels. For example, the following description is taken as an example that the "first level" is a high level and the "second level" is a low level. Those skilled in the art will appreciate that the present disclosure is not limited thereto.

[0110] The transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other devices with the same characteristics. Preferably, the thin film transistors used in the embodiments of the present disclosure may be oxide semiconductor transistors or low temperature polycrystalline silicon (LTPS, Low Temperature Poly-silicon) thin film transistors. Since the source and drain of the thin film transistor used here are symmetrical, the source and drain can be interchanged. In the embodiments of the present disclosure, one of the source and the drain is referred to as the first pole, and the other of the source and the drain is referred to as the second pole. In the following examples, an N-type thin film transistor is used as an example for description. Those skilled in the art can understand that the embodiments of the present disclosure can obviously be applied to the case of a P-type thin film transistor.

[0111] Figure 1 A block diagram of a shift register according to an embodiment of the present disclosure is shown.

[0112] like Figure 1 As shown, the shift register 100 includes an input circuit 110 , an output circuit 120 , a first control circuit 130 and a second control circuit 140 .

[0113] The input circuit 110 is connected to the input signal terminal CN, the input control terminal STV and the pull-up node PU. The input circuit 110 can input the potential of the input signal terminal CN to the pull-up node PU under the control of the signal of the input control terminal STV.

[0114] The output circuit 120 is connected to the pull-up node PU, the clock signal terminal CK, and the output signal terminal OUT. The output circuit 120 can provide the signal of the clock signal terminal CK to the output signal terminal OUT under the control of the potential of the pull-up node PU.

[0115] The first control circuit 130 is connected to the first control signal terminal CKB, the pull-up node PU, the pull-down node PD and the reference signal terminal VGL. The first control circuit 130 can provide the potential of the first control signal terminal CKB to the pull-down node PD, and provide the potential of the reference signal terminal VGL to the pull-down node PD according to the potential of the pull-up node PU.

[0116] The second control circuit 140 is connected to the pull-down node PD, the second control signal terminal EN, the output signal terminal OUT and the reference signal terminal VGL. Under the control of the potential of the pull-down node PD and the second control signal terminal EN, the second control circuit 140 can pull down the potential of the output signal terminal OUT in the display phase and pull up the potential of the output signal terminal OUT in the power-off phase.

[0117] Typically, during the power-off process, the shift register places all signal terminals (such as the input control terminal, the input signal terminal, the first control signal terminal, the clock signal terminal, the reference signal terminal, etc.) at a valid level (such as a high level), so that a high level is output at the output signal terminal, thereby achieving charge release.

[0118] The embodiment of the present disclosure can control the pull-up and pull-down of the potential of the output signal terminal based on the signal of the second control signal terminal by setting a second control circuit connected to the separate second control signal terminal, so that the shift register can realize charge release without placing all signal terminals at a valid level (e.g., a high level) when powered off. Since all signal terminals do not need to be placed at a valid level when powered off, the level of the pull-up node can be set as needed during the power-off stage, for example, the pull-up node can be set to an invalid level (e.g., a low level), so that when the shift register is powered on again, it will not generate an unexpected output during the power-on period due to the power-on process not supporting the reset of the pull-up node.

[0119] Figure 2A A circuit diagram of a shift register according to an embodiment of the present disclosure is shown.

[0120] like Figure 2A As shown, the shift register 200A includes an input circuit 210, an output circuit 220, a first control circuit 230 and a second control circuit 240. The above descriptions of the input circuit 110, the output circuit 120, the first control circuit 130 and the second control circuit 140 are also applicable to the input circuit 210, the output circuit 220, the first control circuit 230 and the second control circuit 240, respectively.

[0121] The input circuit 210 includes an eleventh transistor T11 , a gate of the eleventh transistor T11 is connected to the input control terminal STV, a first electrode of the eleventh transistor T11 is connected to the input signal terminal CN, and a second electrode of the eleventh transistor T11 is connected to the pull-up node PU.

[0122] The output circuit 220 includes a twelfth transistor T12 and a third capacitor C3. The gate of the twelfth transistor T12 is connected to the pull-up node PU, the first electrode of the twelfth transistor T12 is connected to the clock signal terminal CK, and the second electrode of the twelfth transistor T12 is connected to the output signal terminal OUT. The first end of the third capacitor C3 is connected to the pull-up node PU, and the second end of the third capacitor C3 is connected to the output signal terminal OUT.

[0123] The first control circuit 230 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The gate and the first electrode of the seventh transistor T7 are connected to the first control signal terminal CKB, and the second electrode of the seventh transistor T7 is connected to the pull-down node PD. The gate of the eighth transistor T8 is connected to the pull-down node PD, the first electrode of the eighth transistor T8 is connected to the reference signal terminal VGL, and the second electrode of the eighth transistor T8 is connected to the pull-up node PU. The gate of the ninth transistor T9 is connected to the pull-up node PU, the first electrode of the ninth transistor T9 is connected to the reference signal terminal VGL, and the second electrode of the ninth transistor T9 is connected to the pull-down node PD.

[0124] exist Figure 2A In the embodiment, the shift register 200A further includes a reset circuit 250. The reset circuit 250 includes a thirteenth transistor T13, the gate of the thirteenth transistor T13 is connected to the reset control terminal RST, the first electrode of the thirteenth transistor T13 is connected to the reset signal terminal CNB, and the second electrode of the thirteenth transistor T13 is connected to the pull-up node PU. The reset circuit 250 and the input circuit 210 can be used interchangeably to realize forward scanning and reverse scanning. For example, in the case of forward scanning, a high level signal is applied to the input signal terminal CN, a low level signal is applied to the reset signal terminal CNB, the input circuit 210 provides a high level input to the pull-up node PU based on the high level of the input signal terminal CN, and the reset circuit 250 resets the pull-up node PU to a low level based on the low level of the reset signal terminal CNB. In the case of reverse scanning, a low level signal is applied to the input signal terminal CN, a high level signal is applied to the reset signal terminal CNB, the reset circuit 250 provides a high level input to the pull-up node PU based on the high level of the reset signal terminal CNB, and the input circuit 210 resets the pull-up node PU to a low level based on the low level of the input signal terminal CN.

[0125] Figure 2B A circuit diagram of a shift register according to another embodiment of the present disclosure is shown. Figure 2B The shift register 200B is similar to the above-mentioned shift register 200A. For the sake of simplicity, the following mainly describes in detail the differences.

[0126] Similar to the shift register 200A, the shift register 200B includes an input circuit 210, an output circuit 220, a first control circuit 230' and a reset circuit 250. Figure 2AUnlike the shift register 200A, the shift register 200B has two pull-up nodes, namely, a first pull-up node PU1 and a second pull-up node PU2. The first pull-up node PU1 is connected to the input circuit 210, and the second pull-up node PU2 is connected to the output circuit 220. In addition to the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9, the first control circuit 230' further includes a tenth transistor T10 connected between the first pull-up node PU1 and the second pull-up node PU2. Figure 2B As shown, the gate of the tenth transistor T10 is connected to the power signal terminal VGH, the first electrode of the tenth transistor T10 is connected to the first pull-up node PU1, and the second electrode of the tenth transistor T10 is connected to the second pull-up node PU2. The gate and the first electrode of the seventh transistor T7 are connected to the first control signal terminal CKB, and the second electrode of the seventh transistor T7 is connected to the pull-down node PD. The gate of the eighth transistor T8 is connected to the pull-down node PD, the first electrode of the eighth transistor T8 is connected to the reference signal terminal VGL, and the second electrode of the eighth transistor T8 is connected to the first pull-up node PU1. The gate of the ninth transistor T9 is connected to the first pull-up node PU1, the first electrode of the ninth transistor T9 is connected to the reference signal terminal VGL, and the second electrode of the ninth transistor T9 is connected to the pull-down node PD. When the power signal terminal VGH is at a high level, the tenth transistor T10 is turned on, thereby electrically connecting the first pull-up node PU1 to the second pull-up node PU2; when the power signal terminal VGH is at a low level, the tenth transistor T10 is turned off, thereby electrically isolating the first pull-up node PU1 from the second pull-up node PU2. By providing the tenth transistor T10, the first pull-up node PU1 and the second pull-up node PU2 can be electrically isolated or connected as needed, thereby preventing the potential of the second pull-up node PU2 for controlling the output circuit 320 from being affected by other circuits when necessary.

[0127] exist Figure 2B In the shift register 200B, the second control circuit includes a pull-down sub-circuit 2401 and a lower electronic circuit 2402 .

[0128] The pull-down sub-circuit 2401 is connected to the pull-down node PD, the output signal terminal OUT, and the reference signal terminal VGL. The pull-down sub-circuit 2401 can provide the potential of the reference signal terminal VGL to the output signal terminal OUT under the control of the potential of the pull-down node PD. Figure 2B In the embodiment, the pull-down sub-circuit 2401 includes a third transistor T3 and a first capacitor C1. The gate of the third transistor T3 is connected to the pull-down node PD, the first electrode of the third transistor T3 is connected to the reference signal terminal VGL, and the second electrode of the third transistor T3 is connected to the output signal terminal OUT. The first end of the first capacitor C1 is connected to the pull-down node PD, and the second end of the first capacitor C1 is connected to the reference signal terminal VGL.

[0129] The lower electronic circuit 2402 is connected to the second control signal terminal EN, the pull-down node PD, the output signal terminal OUT and the reference signal terminal VGL. Under the control of the signal of the second control signal terminal EN, the lower electronic circuit 2402 can provide the potential of the second control signal terminal EN to the output signal terminal OUT and provide the potential of the reference signal terminal VGL to the pull-down node PD. Figure 2B , the lower electronic circuit 2402 may include a first transistor T1 and a second transistor T2. The gate and the first electrode of the first transistor T1 are connected to the second control signal terminal EN, and the second electrode of the first transistor T1 is connected to the output signal terminal OUT. The gate of the second transistor T2 is connected to the second control signal terminal EN, the first electrode of the second transistor T2 is connected to the reference signal terminal VGL, and the second electrode of the second transistor T2 is connected to the pull-down node PD.

[0130] In some embodiments, Figure 2B As shown, the pull-down sub-circuit 2401 may further include a fourth transistor T4, the gate of the fourth transistor T4 is connected to the output signal terminal OUT, the first electrode of the fourth transistor T4 is connected to the reference signal terminal VGL, and the second electrode of the fourth transistor T4 is connected to the pull-down node PD. When the output signal terminal OUT is at a high level, the fourth transistor T4 is turned on, thereby pulling the pull-down node PD down to the low level of the reference signal terminal VGL. The fourth transistor T4 plays a role in further stabilizing the potential of the pull-down node PD.

[0131] In some embodiments, Figure 2B As shown, the shift register 200B further includes a total reset circuit 270. The total reset circuit 270 is connected to the total reset signal terminal RESET, the first pull-up node PU1 and the reference signal terminal VGL. The total reset circuit 370 can provide the potential of the reference signal terminal VGL to the first pull-up node PU1 under the control of the signal of the total reset signal terminal RESET. Figure 2B In the embodiment, the total reset circuit 270 includes a fourteenth transistor T14, a gate of the fourteenth transistor T14 is connected to the total reset signal terminal RESET, a first electrode of the fourteenth transistor T14 is connected to the reference signal terminal VGL, and a second electrode of the fourteenth transistor T14 is connected to the first pull-up node PU1. When the total reset signal terminal RESET is at a high level, the fourteenth transistor T14 is turned on, thereby resetting the first pull-up node PU1 to a low level at the reference signal terminal VGL.

[0132] Figure 2C 2 is a circuit diagram of a shift register according to another embodiment of the present disclosure. Similar to the shift register 200B, the shift register 200C includes an input circuit 210 , an output circuit 220 , a first control circuit 230 ′, a reset circuit 250 and a total reset circuit 270 .

[0133] Different from the shift register 200B, the second control circuit 240' of the shift register 200C includes a fifth transistor T5 and a second capacitor C2. The gate of the fifth transistor T5 is connected to the pull-down node PD, the first electrode of the fifth transistor T5 is connected to the second control signal terminal EN, and the second electrode of the fifth transistor T5 is connected to the output signal terminal OUT. The first end of the second capacitor C2 is connected to the pull-down node PD, and the second end of the second capacitor C2 is connected to the reference signal terminal VGL.

[0134] Figure 2D A circuit diagram of a shift register according to another embodiment of the present disclosure is shown. Figure 2D The shift register 200D is similar to the shift register 200B, and the difference lies at least in the structure of the second control circuit 240 ″ and the fact that it also includes a noise reduction circuit 260.

[0135] like Figure 2D As shown, the noise reduction circuit 260 is connected to the input control terminal STV, the pull-down node PD and the reference signal terminal VGL. The noise reduction circuit 260 can provide the potential of the reference signal terminal VGL to the pull-down node PD under the control of the signal of the input control terminal STV. Figure 2D In the embodiment, the noise reduction circuit 260 includes a sixth transistor T6, a gate of the sixth transistor T6 is connected to the input control terminal STV, a first electrode of the sixth transistor T6 is connected to the reference signal terminal VGL, and a second electrode of the sixth transistor T6 is connected to the pull-down node PD.

[0136] exist Figure 2D In the embodiment, the second control circuit 240" includes a third transistor T3, a fourth transistor T4 and a first capacitor C1. The gate of the third transistor T3 is connected to the pull-down node PD, the first electrode of the third transistor T3 is connected to the second control signal terminal EN, and the second electrode of the third transistor T3 is connected to the output signal terminal OUT. The first end of the first capacitor C1 is connected to the pull-down node PD, and the second end of the first capacitor C1 is connected to the reference signal terminal VGL. The gate of the fourth transistor T4 is connected to the output signal terminal OUT, the first electrode of the fourth transistor T4 is connected to the reference signal terminal VGL, and the second electrode of the fourth transistor T4 is connected to the pull-down node PD. Of course, the embodiments of the present disclosure are not limited to this. In some embodiments, the first electrode of the third transistor T3 can be connected to the reference signal terminal VGL instead of the second control signal terminal EN.

[0137] Figure 3 A circuit diagram of a shift register according to another embodiment of the present disclosure is shown. Figure 3 The shift register 300 is similar to the above-mentioned shift register 200A. For the sake of simplicity, the following mainly describes in detail the differences.

[0138] Similar to shift register 200A, shift register 300 includes an input circuit 310, an output circuit 320, a first control circuit 330 and a reset circuit 350. The above description of input circuit 210, output circuit 220, first control circuit 230 and reset circuit 250 also applies to input circuit 310, output circuit 320, first control circuit 330 and reset circuit 350.

[0139] and Figure 2A Unlike the shift register 200A, the shift register 300 has two pull-up nodes, namely, a first pull-up node PU1 and a second pull-up node PU2. The first pull-up node PU1 is connected to the input circuit 310, and the second pull-up node PU2 is connected to the output circuit 320. In addition to the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9, the first control circuit further includes a tenth transistor T10 connected between the first pull-up node PU1 and the second pull-up node PU2. Figure 3 As shown, the gate of the tenth transistor T10 is connected to the power signal terminal VGH, the first electrode of the tenth transistor T10 is connected to the first pull-up node PU1, and the second electrode of the tenth transistor T10 is connected to the second pull-up node PU2. The gate and the first electrode of the seventh transistor T7 are connected to the first control signal terminal CKB, and the second electrode of the seventh transistor T7 is connected to the pull-down node PD. The gate of the eighth transistor T8 is connected to the pull-down node PD, the first electrode of the eighth transistor T8 is connected to the reference signal terminal VGL, and the second electrode of the eighth transistor T8 is connected to the first pull-up node PU1. The gate of the ninth transistor T9 is connected to the first pull-up node PU1, the first electrode of the ninth transistor T9 is connected to the reference signal terminal VGL, and the second electrode of the ninth transistor T9 is connected to the pull-down node PD. When the power signal terminal VGH is at a high level, the tenth transistor T10 is turned on, thereby electrically connecting the first pull-up node PU1 to the second pull-up node PU2; when the power signal terminal VGH is at a low level, the tenth transistor T10 is turned off, thereby electrically isolating the first pull-up node PU1 from the second pull-up node PU2. By providing the tenth transistor T10, the first pull-up node PU1 and the second pull-up node PU2 can be electrically isolated or connected as needed, thereby preventing the potential of the second pull-up node PU2 for controlling the output circuit 320 from being affected by other circuits when necessary.

[0140] exist Figure 3 In the embodiment, the second control circuit includes a pull-down sub-circuit 3401 and a lower electronic circuit 3402 .

[0141] The pull-down sub-circuit 3401 is connected to the pull-down node PD, the output signal terminal OUT, and the reference signal terminal VGL. The pull-down sub-circuit 3401 can provide the potential of the reference signal terminal VGL to the output signal terminal OUT under the control of the potential of the pull-down node PD. Figure 3 In the embodiment, the pull-down sub-circuit 3401 includes a third transistor T3 and a first capacitor C1. The gate of the third transistor T3 is connected to the pull-down node PD, the first electrode of the third transistor T3 is connected to the reference signal terminal VGL, and the second electrode of the third transistor T3 is connected to the output signal terminal OUT. The first end of the first capacitor C1 is connected to the pull-down node PD, and the second end of the first capacitor C1 is connected to the reference signal terminal VGL.

[0142] The lower electronic circuit 3402 is connected to the second control signal terminal EN, the pull-down node PD, the output signal terminal OUT and the reference signal terminal VGL. Under the control of the signal of the second control signal terminal EN, the lower electronic circuit 3402 can provide the potential of the second control signal terminal EN to the output signal terminal OUT and provide the potential of the reference signal terminal VGL to the pull-down node PD. Figure 3 , the lower electronic circuit 3402 may include a first transistor T1 and a second transistor T2. The gate and the first electrode of the first transistor T1 are connected to the second control signal terminal EN, and the second electrode of the first transistor T1 is connected to the output signal terminal OUT. The gate of the second transistor T2 is connected to the second control signal terminal EN, the first electrode of the second transistor T2 is connected to the reference signal terminal VGL, and the second electrode of the second transistor T2 is connected to the pull-down node PD.

[0143] In some embodiments, Figure 3 As shown, the pull-down sub-circuit 3401 may further include a fourth transistor T4, the gate of the fourth transistor T4 is connected to the output signal terminal OUT, the first electrode of the fourth transistor T4 is connected to the reference signal terminal VGL, and the second electrode of the fourth transistor T4 is connected to the pull-down node PD. When the output signal terminal OUT is at a high level, the fourth transistor T4 is turned on, thereby pulling the pull-down node PD down to the low level of the reference signal terminal VGL. The fourth transistor T4 plays a role in further stabilizing the potential of the pull-down node PD.

[0144] In some embodiments, Figure 3 As shown, the shift register further includes a noise reduction circuit 360. The noise reduction circuit 360 is connected to the input control terminal STV, the pull-down node PD and the reference signal terminal VGL. The noise reduction circuit 360 can provide the potential of the reference signal terminal VGL to the pull-down node PD under the control of the signal of the input control terminal STV. Figure 3 In the embodiment, the noise reduction circuit includes a sixth transistor T6, a gate of the sixth transistor T6 is connected to the input control terminal STV, a first electrode of the sixth transistor T6 is connected to the reference signal terminal VGL, and a second electrode of the sixth transistor T6 is connected to the pull-down node PD.

[0145] In the absence of the noise reduction circuit 360, when the input control terminal STV is at a high level, the eleventh transistor T11 is turned on, and the high level at the input signal terminal CN is input to the first pull-up node PU1, thereby turning on the ninth transistor T9. During this period, the high level at the first control signal terminal CKB turns on the seventh transistor T7, and the seventh transistor T7 and the ninth transistor T9 form a DC path. Since the channel width-to-length ratio W / L of the ninth transistor T9 is at least twice the channel width-to-length ratio W / L of the seventh transistor, the resistance of the seventh transistor T7 is greater than the resistance of the ninth transistor T9, and the pull-down node PD is at an intermediate level under the action of the resistance voltage divider, which is close to but greater than the low level at the reference signal terminal VGL. The intermediate level at the pull-down node PD causes the eighth transistor T8 to turn on, thereby pulling down the potential of the first pull-up node PU1.

[0146] By setting the noise reduction circuit 360, when the input control terminal STV is at a high level, the sixth transistor T6 is turned on, so that the low level of the reference signal terminal VGL is used to further pull down the potential of the pull-down node PD, thereby alleviating or avoiding the above-mentioned problem of affecting the potential of the first pull-up node PU1 due to the potential of the pull-down node PD not being low enough, and improving the competition relationship between the pull-up node PU and the pull-down node PD.

[0147] In some embodiments, Figure 3 As shown, the shift register 300 further includes a total reset circuit 370. The total reset circuit 370 is connected to the total reset signal terminal RESET, the first pull-up node PU1 and the reference signal terminal VGL. The total reset circuit 370 can provide the potential of the reference signal terminal VGL to the first pull-up node PU1 under the control of the signal of the total reset signal terminal RESET. Figure 3 In the embodiment, the total reset circuit 370 includes a fourteenth transistor T14, a gate of the fourteenth transistor T14 is connected to the total reset signal terminal RESET, a first electrode of the fourteenth transistor T14 is connected to the reference signal terminal VGL, and a second electrode of the fourteenth transistor T14 is connected to the first pull-up node PU1. When the total reset signal terminal RESET is at a high level, the fourteenth transistor T14 is turned on, thereby resetting the first pull-up node PU1 to a low level at the reference signal terminal VGL.

[0148] Figure 4 A circuit diagram of a shift register according to another embodiment of the present disclosure is shown. Figure 4 The shift register 400 is Figure 3 The present invention is similar to the shift register 300 of FIG. 1 , and the difference lies at least in the second control circuit 440. For the sake of simplicity, the following will mainly describe the difference in detail.

[0149] Similar to the shift register 300, the shift register 400 includes an input circuit 410, an output circuit 420, a first control circuit 430, a reset circuit 450, a noise reduction circuit 460 and a total reset circuit 470. The above description of the input circuit 310, the output circuit 320, the first control circuit 330, the reset circuit 350, the noise reduction circuit 360 and the total reset circuit 370 also applies to the input circuit 410, the output circuit 420, the first control circuit 430, the reset circuit 450, the noise reduction circuit 460 and the total reset circuit 470.

[0150] Different from the shift register 300, the second control circuit 440 of the shift register 400 includes a fifth transistor T5 and a second capacitor C2. The gate of the fifth transistor T5 is connected to the pull-down node PD, the first electrode of the fifth transistor T5 is connected to the second control signal terminal EN, and the second electrode of the fifth transistor T5 is connected to the output signal terminal OUT. The first end of the second capacitor C2 is connected to the pull-down node PD, and the second end of the second capacitor C2 is connected to the reference signal terminal VGL.

[0151] Figure 5 A schematic diagram of a gate driving circuit according to an embodiment of the present disclosure is shown.

[0152] like Figure 5 As shown, the gate driving circuit 500 includes N stages of cascaded shift registers. For ease of description, Figure 5 8 shift registers GOA1 to GOA8 are shown, however, the embodiments of the present disclosure are not limited thereto, and the number of shift registers can be set as required. Each shift register GOA1 to GOA8 can be implemented by a shift register of any of the above embodiments, such as shift registers 100, 200A, 200B, 200C, 200D, 300 or 400.

[0153] The input signal terminal CN of each shift register GOA1 to GOA8 is connected to receive the input signal CN, the reset signal terminal CNB is connected to receive the reset signal CNB, and the second control signal terminal EN is connected to receive the second control signal EN. It should be noted here that since the input signal terminal CN of each shift register receives the same input signal, in order to simplify the description, the input signal and the input signal terminal are represented by the same reference numeral CN herein. For the same reason, the reset signal terminal and the reset signal are both represented by CNB, and the second control signal terminal EN and the second control signal are both represented by EN.

[0154] According to an embodiment of the present disclosure, the input control terminal STV of the nth stage shift register is connected to the output signal terminal OUT of the nith stage shift register, and the reset control terminal RST of the nth stage shift register is connected to the output signal terminal OUT of the n+jth stage shift register.

[0155] exist Figure 5 , i=j=4, the input control terminal STV of the n-th shift register is connected to the output signal terminal OUT of the n-4-th shift register, and the reset control terminal RST of the n-th shift register is connected to the output signal terminal OUT of the n+4-th shift register. For example, the output signal terminal OUT of the first-stage shift register GOA1 is connected to the input control terminal STV of the fifth-stage shift register GOA5, and the output signal terminal OUT of the second-stage shift register GOA2 is connected to the input control terminal STV of the sixth-stage shift register GOA6, and so on. The reset control terminal RST of the first-stage shift register GOA1 is connected to the output signal terminal OUT of the fifth-stage shift register GOA5, and the reset control terminal RST of the second-stage shift register GOA2 is connected to the output signal terminal OUT of the sixth-stage shift register GOA6, and so on. The input signal terminals STV of the first-stage to fourth-stage shift registers GOA1 to GOA4 are respectively connected to receive the start signals STV1 to STV4.

[0156] According to an embodiment of the present disclosure, N-stage cascaded shift registers are divided into at least one group, each group includes K-stage cascaded shift registers, the clock signal terminals CK of the K-stage cascaded shift registers are respectively connected to receive K clock signals, and the first control signal terminals CKB of the K-stage cascaded shift registers are respectively connected to receive the K clock signals, wherein N, K, n, i and j are all integers, 1≤n≤N, 1<K≤N. Figure 5 In the embodiment, K=8, each group of shift registers includes 8 shift registers, for example, the first to eighth stage shift registers GOA1 to GOA8 are grouped together and connected to 8 clock signals CK1 to CK8 respectively.

[0157] exist Figure 5In the group of shift registers GOA1 to GOA8 shown, the clock signal terminal CK of the first-stage shift register GOA1 is connected to receive the first clock signal CK1, and the first control signal terminal CKB of the first-stage shift register GOA1 is connected to receive the fifth clock signal CK5; the clock signal terminal CK of the second-stage shift register GOA2 is connected to receive the second clock signal CK2, and the first control signal terminal CKB of the second-stage shift register GOA2 is connected to receive the sixth clock signal CK6; the clock signal terminal CK of the third-stage shift register GOA3 is connected to receive the third clock signal CK3, and the first control signal terminal CKB of the third-stage shift register GOA3 is connected to receive the seventh clock signal CK7; the clock signal terminal CK of the fourth-stage shift register GOA4 is connected to receive the fourth clock signal CK4, and the first control signal terminal CKB of the fourth-stage shift register GOA4 is connected to receive the The clock signal terminal CK of the fifth-stage shift register GOA5 is connected to receive the fifth clock signal CK5, and the first control signal terminal CKB of the fifth-stage shift register GOA5 is connected to receive the first clock signal CK1; the clock signal terminal CK of the sixth-stage shift register GOA6 is connected to receive the sixth clock signal CK6, and the first control signal terminal CKB of the sixth-stage shift register GOA6 is connected to receive the second clock signal CK2; the clock signal terminal CK of the seventh-stage shift register GOA7 is connected to receive the seventh clock signal CK7, and the first control signal terminal CKB of the seventh-stage shift register GOA7 is connected to receive the third clock signal CK3; the clock signal terminal CK of the eighth-stage shift register GOA8 is connected to receive the eighth clock signal CK8, and the first control signal terminal CKB of the eighth-stage shift register GOA8 is connected to receive the fourth clock signal CK4. The second group of shift registers GOA9 to GOA16 are respectively connected to receive clock signals CK1 to CK8 in a manner similar to GOA1 to GOA8, and so on.

[0158] The other signal terminals (if any) of the shift registers GOA1 to GOA8 of the gate drive circuit 500 are respectively connected to receive signals for the signal terminals, for example, the power signal terminal VGH of each level of the shift registers GOA1 to GOA8 is connected to receive the power signal, the reference signal terminal VGL is connected to receive the reference signal, and the general reset signal terminal RESET is connected to receive the general reset signal.

[0159] Figure 6 A schematic diagram of a gate driving circuit according to another embodiment of the present disclosure is shown. Figure 6 The gate drive circuit 600 and Figure 5 The gate driving circuit 500 is similar to the gate driving circuit 500 of FIG. 1 , and the difference is at least that i=j=2 and K=4. In order to simplify the description, the difference will be mainly described in detail below.

[0160] like Figure 6 As shown, the input control terminal STV of the n-th shift register is connected to the output signal terminal OUT of the n-2-th shift register, and the reset control terminal RST of the n-th shift register is connected to the output signal terminal OUT of the n+2-th shift register. For example, the output signal terminal OUT of the first-stage shift register GOA1 is connected to the input control terminal STV of the third-stage shift register GOA3, and the output signal terminal OUT of the second-stage shift register GOA2 is connected to the input control terminal STV of the fourth-stage shift register GOA4, and so on. The reset control terminal RST of the first-stage shift register GOA1 is connected to the output signal terminal OUT of the third-stage shift register GOA3, and the reset control terminal RST of the second-stage shift register GOA2 is connected to the output signal terminal OUT of the fourth-stage shift register GOA4, and so on. The input signal terminals STV of the first-stage shift register GOA1 and the second-stage shift register GOA2 are connected to receive the start signals STV1 and STV2, respectively.

[0161] The gate drive circuit 600 is controlled by four clock signals CK1 to CK4, and the adjacent four-stage shift registers are connected as a group to receive the clock signals CK1 to CK4. For example, in the first group of shift registers GOA1 to GOA4, the clock signal terminal CK of the first-stage shift register GOA1 is connected to receive the first clock signal CK1, and the first control signal terminal CKB of the first-stage shift register GOA1 is connected to receive the third clock signal CK3; the clock signal terminal CK of the second-stage shift register GOA2 is connected to receive the second clock signal CK2, and the first control signal terminal CKB of the second-stage shift register GOA2 is connected to receive the fourth clock signal CK4; the clock signal terminal CK of the third-stage shift register GOA3 is connected to receive the third clock signal CK3, and the first control signal terminal CKB of the third-stage shift register GOA3 is connected to receive the first clock signal CK1; the clock signal terminal CK of the fourth-stage shift register GOA4 is connected to receive the fourth clock signal CK4, and the first control signal terminal CKB of the fourth-stage shift register GOA4 is connected to receive the second clock signal CK2. The second group of shift registers GOA2 to GOA8 are connected to receive clock signals CK1 to CK4, respectively, in a similar manner to the first group of shift registers GOA1 to GOA4.

[0162] Fig. 7A A schematic diagram of a display panel according to an embodiment of the present disclosure is shown.

[0163] like Fig. 7AAs shown, the display panel 700 includes a plurality of sub-pixels Pix arranged in an array and a gate driving circuit 710. The gate driving circuit 710 can be implemented by the gate driving circuit of any of the above embodiments, and the multi-stage shift registers in the gate driving circuit 710 are respectively connected to a plurality of rows of sub-pixels Pix in the array. Fig. 7A In the display area 720, a plurality of sub-pixels Pix are located, and the plurality of sub-pixels Pix are arranged in an N×M array, and N rows of sub-pixels Pix are respectively connected to N gate signal lines G1 to GN, and M columns of sub-pixels Pix are respectively connected to M data lines D1 to DM, and N output signals generated by the N-stage shift register in the gate drive circuit 710 are respectively provided to the gate lines G1 to GN. Of course, the embodiments of the present disclosure are not limited thereto, and the sub-pixels Pix can be arranged in other forms of arrays as needed, and the rows and columns of sub-pixels Pix can be connected to the gate lines and data lines in different ways, and the output signal terminal of the gate drive circuit 710 can be connected to the gate lines in different ways. For example, one gate line can connect two rows of sub-pixels, or two gate lines can connect one row of sub-pixels. For another example, each output signal terminal in the gate drive circuit 710 can be connected to one gate line or multiple gate lines, and so on.

[0164] Figure 7B Shows Fig. 7A A schematic diagram of the layout of the display panel. Figure 7B As shown, the gate driving circuit 710 can be composed of the above-mentioned gate driving circuit, and the N shift registers GOA1 to GOAN in the gate driving circuit 710 are shifted along the y direction (the column direction of the sub-pixel array, also referred to as the second direction, Figure 7B The gate lines G1 to GN are arranged in a one-to-one correspondence, and are connected to the sub-pixels Pix in the display area 720. Figure 7B As shown, the size of each shift register GOA1 to GOAN in the y direction may be 0.8-1.4 times the size of the sub-pixel Pix in the y direction. Preferably, the size of each shift register GOA1 to GOAN in the y direction is substantially the same as the size of the sub-pixel Pix in the y direction (in Figure 7B Here, the so-called size may refer to the size of the projection on the base substrate of the display panel. Figure 7B In FIG. 1 , the distance spanned by the projection of each shift register GOA1 to GOAN on the substrate of the display panel in the y direction can represent the size d of the shift register in the y direction. Figure 7B As shown, the distance spanned by the projection of the sub-pixel Pix on the substrate in the y direction may represent the size d of the sub-pixel Pix in the y direction.

[0165] Figure 7C Shows Figure 7BA schematic diagram of the layout of the shift register in FIG. Figure 7C As shown, the shift register can be implemented by the shift register of any of the above embodiments, for example, including the above input circuit 110, the first control circuit 130, the second control circuit 140 and the output circuit 120. The input circuit 110, the first control circuit 130, the second control circuit 140 and the output circuit 120 are arranged in sequence along the x direction (the row direction of the sub-pixel array, also referred to as the first direction, which is perpendicular to the y direction). Figure 7C In FIG. 1 , the size of each of the input circuit 110 , the first control circuit 130 , the second control circuit 140 and the output circuit 120 in the y direction is d, which is the same as the size d of the sub-pixel in the y direction. Figure 7C In the figure, the shift register disposed on the left side of the display area 720 is used as an example for illustration, and the input circuit 110, the first control circuit 130, the second control circuit 140 and the output circuit 120 are arranged from left to right, so as to gradually approach the display area 720 in this order. Similarly, in the case where the shift register is located on the right side of the display area 720, the input circuit 110, the first control circuit 130, the second control circuit 140 and the output circuit 120 are arranged from right to left, so as to gradually approach the display area 720 in this order. By sequentially arranging the input sub-circuit 110, the first control circuit 130, the second control circuit 140 and the output circuit 120 along the x direction, the arrangement size of each shift register unit in the y direction can be minimized in the y direction, and the number of shift register units in the y direction can be increased under the premise of ensuring the width-to-length ratio of each TFT in the shift register, which is beneficial to improve the resolution of the display panel and the narrow frame of the display panel in the y direction.

[0166] exist Figure 7B and Figure 7C In the figure, the projection of the shift register and the input circuit 110, the first control circuit 130, the second control circuit 140 and the output circuit 120 included therein on the substrate substrate is shown as a substantially rectangular shape, and its size in the y direction is represented by the side length of the rectangle in the y direction. However, the embodiments of the present disclosure are not limited thereto, and the projection of the shift register and the input circuit, the first control circuit, the second control circuit and the output circuit therein on the substrate substrate can be designed into other shapes, even irregular shapes, as long as its size in the y direction is substantially the same as the size of the sub-pixel in the y direction.

[0167] Figure 8 A schematic diagram of a display panel according to another embodiment of the present disclosure is shown. Figure 8 The display panel 800 and Fig. 7A The display panel 700 is similar to the display panel 800, and the difference is at least that the display panel 800 includes two gate driving circuits 810A and 810B. In order to simplify the description, the following will mainly describe the differences in detail. Figure 8 As shown, the display panel 800 includes a display area 820. The above description of the display area 720 is also applicable to the display area 820. The gate drive circuits 810A and 810B are connected along the x direction (the row direction of the sub-pixel array, also referred to as the first direction). Figure 8 The gate driving circuits 810A and 810B are respectively implemented by the above-mentioned gate driving circuit 500. For the sake of simplicity, Figure 8 Only the cascade connection between the shift registers GOA1 to GOAN is shown, and the connection between the clock signal and other control signals and the shift registers is omitted. Figure 8 As shown, the output signal end of the first-stage shift register GOA1 in the gate driving circuit 810A is connected to the gate line G1 for the first row of sub-pixels from the left, and the output signal end of the first-stage shift register GOA1 in the gate driving circuit 810B is connected to the gate line G1 for the first row of sub-pixels from the right; in a similar manner, the second-stage shift registers GOA2 of the gate driving circuits 810A and 810B are connected to the gate line G1 from the left and right sides, respectively, and so on. In this way, it is possible to apply gate driving signals to the gate lines from both sides, and for large-size display panels, it is possible to alleviate signal attenuation caused by the long gate line routing.

[0168] Fig. 9 A schematic diagram of a display panel according to another embodiment of the present disclosure is shown. Fig. 9 The display panel 900 and Figure 8 The display panel 800 is similar to the display panel 800, including a display area 920 and gate driving circuits 910A and 910B respectively located on both sides of the display area 920. Different from the display panel 800, the gate driving circuits 910A and 910B in the display panel 900 are each implemented by the above-mentioned gate driving circuit 600. For simplicity, Fig. 9 Only the cascade connection between the shift registers GOA1 to GOAN is shown, and the connection between the clock signal and other control signals and the shift registers is omitted. Figure 8 , Fig. 9 The shift registers GOA1 to GOAN of the gate driving circuit 910A are respectively connected to the gate lines G1 to GN from the left side, and the shift registers GOA1 to GOAN of the gate driving circuit 910B are respectively connected to the gate lines G1 to GN from the right side.

[0169] Fig.10 A schematic diagram of a display panel according to another embodiment of the present disclosure is shown. Fig. 7A Similar to the display panel 700, Fig.10The display panel 1000 includes a gate driving circuit and a plurality of sub-pixels located in a display area 1020. The gate driving circuit adopts the structure of the gate driving circuit 500, wherein the odd-numbered shift registers GOA1, GOA3, ... GOA(N-1) ( Fig.10 1010A) is arranged on one side of the display area 1020 along the x direction ( Fig.10 The even-numbered shift registers GOA2, GOA4, ... GOAN ( Fig.10 1010B) is arranged on the other side of the display area 1020 along the x direction ( Fig.10 For simplicity, Fig.10 Only the cascade connection between the shift registers GOA1 to GOAN is shown, and the connection between the clock signal and other control signals and the shift registers is omitted. Fig.10 As shown, the odd-numbered shift registers GOA1, GOA3, ...GOA(N-1) are respectively connected to the gate lines G1, G3, ...G(N-1) from the left, and the even-numbered shift registers GOA2, GOA4, ...GOAN are respectively connected to the gate lines G2, G4, ...GN from the right.

[0170] Fig.11 FIG. 2 shows a schematic diagram of a display panel according to another embodiment of the present disclosure. Fig.10 , Fig.11 The display panel 1100 includes a plurality of sub-pixels Pix located in a display area 1120 and a gate driving circuit 1110 connected to the plurality of sub-pixels Pix. The gate driving circuit 1100 may adopt the above reference Figures 8 to 10 The arbitrary method described is connected to the sub-pixel Pix. Fig.11 In the display panel 1100, the display panel 1100 further includes a multiplexing circuit 1130. The multiplexing circuit 1130 is connected to M columns of sub-pixels in the sub-pixel array through M data lines D1 to DM. The multiplexing circuit 1130 is, for example, connected to a data driving circuit (e.g., a driving IC) to receive m input data signals Data1 to Datam. The multiplexing circuit 1130 can multiplex the received m input data signals Data1 to Datam into M output data signals under the control of a first selection signal MUX1 and a second selection signal MUX2, and provide them to the data lines D1 to DM, and then to the M columns of sub-pixels Pix. m and M are integers greater than 1, and M is an integer multiple of m, such as twice.

[0171] Fig.12 FIG. 2 shows a circuit diagram of a multiplexing circuit according to an embodiment of the present disclosure. Fig.12 As shown, the multiplexing circuit includes a plurality of multiplexing units M1, M2, ..., Fig.12For the sake of simplicity, two multiplexing units M1 and M2 are shown. Fig.12 In , M / m=2, each multiplexing unit of the multiplexing circuit 1130 can multiplex a received input data signal into two output data signals and provide them to two data lines respectively, thereby realizing one-to-two multiplexing. For example, the multiplexing unit M1 multiplexes the received input data signal Data1 into two output data signals and provides them to data lines D1 and D2 respectively, and the multiplexing unit M2 multiplexes the received input data signal Data2 into two output data signals and provides them to data lines D3 and D4 respectively. Fig.12 In the embodiment, each multiplexing unit includes transistors Tm1 and Tm2. For example, in the multiplexing unit M1, the gate of transistor Tm1 is connected to the first selection signal line to receive the first selection signal MUX1, the first electrode is connected to receive the input data signal Data1, and the second electrode is connected to the data line D1; the gate of transistor Tm2 is connected to the second selection signal line to receive the second selection signal MUX2, the first electrode is connected to receive the input data signal Data1, and the second electrode is connected to the data line D2. When the first selection signal MUX1 is at a high level, transistor Tm1 is turned on, thereby providing the received input data signal Data1 to the data line D1; when the second selection signal MUX2 is at a high level, transistor Tm2 is turned on, thereby providing the input data signal Data1 to the data line D2. Other multiplexing units work in a similar manner and will not be described in detail here.

[0172] Fig.13 A signal timing diagram of a shift register in a display phase according to an embodiment of the present disclosure is shown. Fig.13 The signal timing sequence is applicable to the shift register of any of the above embodiments. Figure 3 Take the shift register 300 as an example. Fig.13 In the display stage, the input signal terminal CN and the power signal terminal VGH maintain a high level, and the reset signal terminal RST and the reference signal terminal RST maintain a low level.

[0173] In time period P1, the input control terminal STV is at a high level, and the eleventh transistor T11 is turned on, thereby inputting the high level of the input signal terminal CN to the first pull-up node PU1. The high level of the power signal terminal VGH turns on the tenth transistor T10, so that the second pull-up node PU2 is at a high level. The high level of the second pull-up node PU2 turns on the twelfth transistor T12. At this time, since the clock signal at the clock signal terminal CK is at a low level, the output signal terminal OUT is at a low level. The first control signal terminal CKB is at a high level, the seventh transistor T7 is turned on, and the high level of the first pull-up node PU1 turns on the ninth transistor T9, thereby using the low level of the reference signal terminal VGL to pull down the potential of the pull-down node PD. At this time, if there is no noise reduction circuit 360, as analyzed above, the potential at the pull-down node PD (such as Fig.13 The denoising circuit 360 is provided, and the high level of the input control terminal STV can turn on the sixth transistor T6, thereby further pulling down the potential of the pull-down node PD by using the potential of the reference signal terminal VGL (such as Fig.13 In the “PD (with noise reduction)” Fig.13 It can be seen that, compared with the case where there is no noise reduction circuit 360 , the potential of the pull-down node PD is reduced.

[0174] In period P2, the input control terminal STV and the first control signal terminal CKB become low level, the eleventh transistor T11 and the seventh transistor T7 are turned off, and the first pull-up node PU1 and the second pull-up node PU2 maintain a high level due to the presence of the third capacitor C3. At this time, since the seventh transistor T7 is turned off and the ninth transistor T9 is turned on, the potential of the pull-down node PD becomes further lower.

[0175] In period P3, the clock signal terminal CK is at a high level, and since the twelfth transistor T12 is in the on state, the high level of the clock signal terminal CK is provided to the output signal terminal OUT. The bootstrap effect of the third capacitor C3 further increases the potential of the second pull-up node PU2.

[0176] In period P4, the clock signal terminal CK changes to a low level, and the twelfth transistor T12 in the on state makes the output signal terminal OUT also change to a low level. The bootstrap effect of the third capacitor C3 reduces the potential of the second pull-up node PU2.

[0177] In period P5, the reset control terminal RST is at a high level, thereby providing the low level at the reset signal terminal CNB to the first pull-up node PU1, and the turned-on tenth transistor T10 causes the second pull-up node PU2 to also become a low level. The first control signal terminal CKB is at a high level, and the seventh transistor T7 is turned on, thereby causing the pull-down node PD to become a high level. The high level of the pull-down node PD turns on the third transistor T3, thereby pulling the output signal terminal OUT down to the low level of the reference signal terminal VGL.

[0178] In the above process, the second control signal terminal EN maintains a low level, and the first transistor T1 and the second transistor are in the off state.

[0179] Although the above description uses the shift register 300 as an example to illustrate the signal timing sequence, the above signal timing sequence is also applicable to other shift registers of the embodiment of the present disclosure. For example, for the shift register 400, it can be based on Fig.13 The signal timing works in a similar manner to the above, except that, in period P5, the second control signal terminal is at a low level, and the high level of the pull-down node PD turns on the fifth transistor T5, thereby pulling the output signal terminal OUT down to the low level of the reference signal terminal VGL.

[0180] Fig.14 A signal timing diagram of a gate driving circuit in a display stage according to an embodiment of the present disclosure is shown. Fig.14 The signal timing of is applicable to the gate driving circuit 500. Fig.14 As shown, eight clock signals CK1 to CK8 that are sequentially shifted are provided to the gate drive circuit 500. Each shift register GOA1 to GOAN in the gate drive circuit 500 may be, for example, configured as described above. Fig.13 The gate drive signals generated by the shift registers GOA1 to GOAN are respectively provided to the gate lines G1 to GN connected thereto. Fig.14In the figure, the clock signals CK1 to CK8 are periodic signals with a duty cycle of 12.5% ​​and a pulse width of a unit scan time, wherein the k+1th clock signal is shifted relative to the kth clock signal by a unit scan time, wherein k is an integer, 1≤k≤7. The so-called unit scan time here refers to the time required for the gate drive circuit to scan a row of pixels. Taking a display panel with an 8K resolution as an example, the sub-pixels in the display area of ​​the display panel are arranged in a 7680×4320 array. When the refresh frequency is 60Hz, the scan time for 1 frame is 1 / 60 seconds, that is, the time spent scanning 4320 rows of sub-pixels is 1 / 60 seconds, then the time spent scanning each row of sub-pixels (i.e., the unit scan time) H=1 / 60÷4320≈3.7μs. Similarly, when the refresh rate is 120Hz, the unit scan time H is approximately 1.85μs.

[0181] Fig.15 A signal timing diagram of a gate driving circuit in a display stage according to another embodiment of the present disclosure is shown. Fig.15 The signal timing of is applicable to the gate driving circuit 600. Fig.15 As shown, four clock signals CK1 to CK4 that are sequentially shifted are provided to the gate drive circuit 600. Each shift register GOA1 to GOAN in the gate drive circuit 600 can be, for example, configured as described above. Fig.13 The gate drive signals generated by the shift registers GOA1 to GOAN are respectively provided to the gate lines G1 to GN connected thereto. Fig.15 In the figure, the clock signals CK1 to CK4 are periodic signals with a duty cycle of 25% and a pulse width of a unit scan time, wherein the k+1th clock signal is shifted by a unit scan time relative to the kth clock signal, wherein k is an integer, 1≤k≤3.

[0182] Fig.16 The working timing diagram of the gate driving circuit according to the embodiment of the present disclosure is shown. Fig.16 The working timing diagram is applicable to the gate driving circuit of any of the above embodiments, and the above shift register 300 is used in the gate driving circuit. Fig.16 The working sequence of the gate drive circuit covers the power-on stage, display stage and power-off stage. For example, when the gate drive circuit is turned on, it enters the power-on stage; after the power-on is completed, it enters the display stage. The various shift registers in the gate drive circuit follow the above reference Fig.13 The described method works to drive sub-pixels for display; when the gate drive circuit needs to be turned off, it enters the power-down stage.

[0183] In the display stage, the second control signal is at a low level, so that the second control signal terminal EN of each shift register is at a low level. Figure 3 , the low level of the second control signal terminal EN turns off the first transistor T1 and the second transistor T2, thus not affecting the display operation of the shift register.

[0184] In the power-off stage, the second control signal and the power signal provided to the gate drive circuit are high level, so that the second control signal terminal EN and the power signal terminal VGH of each shift register are high level respectively. Other signals provided to the gate drive circuit, such as the total reset signal, input signal, reset signal, start signal STV1 to STVx (for example Figure 5 STV1 to STV4 in, or Figure 6 The STV1 and STV2 in the shift register, the K clock signals and the reference signal are all at low level, so that the total reset signal terminal RESET, the input signal terminal CN, the reset signal terminal CNB, the clock signal terminal CK, the first control signal terminal CKB and the reference signal terminal VGL of each shift register are all at low level. In each shift register, the reference Figure 3 , the high level of the second control signal terminal EN turns on the first transistor T1 and the second transistor T2, so that the high level at the second control signal terminal EN is provided to the output signal terminal to output a high-level output signal, and the low level at the reference signal terminal VGL is provided to the pull-down node PD. Since each shift register GOA1 to GOAN in the gate drive circuit outputs a high level, the cascade connection makes the input control terminal STV and the reset control terminal RST of each shift register both high, the eleventh transistor T11 and the thirteenth transistor T13 are turned on, so that the low level at the input signal terminal CN and the reset signal terminal CNB is provided to the pull-up node PU1. Since the power supply signal terminal VGH is at a high level, the tenth transistor T10 is turned on, so that the second pull-up node PU2 is also at a low level. In the above manner, the gate drive circuit is powered off, so that the output signal terminal OUT of each shift register is at a high level, the first pull-up node PU1 and the second pull-up node PU2 are at a high level, and the pull-down node is at a low level.

[0185] By setting the pull-up node (e.g., the first pull-up node PU1 and the second pull-up node PU2) to a low level during the power-off phase, when the gate drive circuit is powered on again, there will be no unexpected output due to the inability to set the pull-up node to a low level during the power-on process. In this way, the power-on process does not necessarily have to have the function of pulling the pull-up node to a low level, which relaxes the restrictions on power-on. For example, Fig.16 In the power-on phase, all signals provided to the gate drive circuit are at the ground level, such as an intermediate level between the high level and the low level, so that each signal terminal of each shift register is at the ground level. Fig.16 In the embodiment, power-on operation may not be required, and the gate drive circuit may enter the display stage for display driving after startup. Of course, the embodiments of the present disclosure are not limited thereto, and other signal timings may be used to perform power-on operation in the power-on stage, which will be further described in detail below.

[0186] Fig.17 FIG. 4 shows an operation timing diagram of a gate driving circuit according to another embodiment of the present disclosure. Fig.17 The working timing diagram is applicable to the gate driving circuit of any of the above embodiments, and the above shift register 400 is used in the gate driving circuit. Fig.17 The working sequence and Fig.16 Similar, the difference is at least in the power-off stage. In order to simplify the description, the following will mainly describe the difference in detail.

[0187] In the display phase, similar to Fig.16 , the second control signal is at a low level, so that the second control signal terminal EN of each shift register is at a low level. Figure 4 When the pull-down node PD is at a high level, the fifth transistor T5 is turned on, and the low level of the second control signal terminal EN is provided to the output signal terminal OUT to play the role of pulling down the potential of the output signal terminal OUT.

[0188] In the power-off stage, the second control signal, the power signal and the K clock signals provided to the gate drive circuit are at a high level, so that the second control signal terminal EN, the power signal terminal VGH, the clock signal terminal CK and the first control signal terminal CKB of each shift register are at a high level. Other signals provided to the gate drive circuit, such as the total reset signal, the input signal, the reset signal, the start signal STV1 to STVx (for example Figure 5 STV1 to STV4 in, or Figure 6 The STV1 and STV2 in the shift register and the reference signal are all low level, so that the total reset signal terminal RESET, the input signal terminal CN, the reset signal terminal CNB and the reference signal terminal VGL of each shift register are all low level. In each shift register, the reference Figure 4, the high level of the first control signal terminal CKB turns on the seventh transistor T7, so that the pull-down node PD is at a high level. The high level of the pull-down node PD turns on the fifth transistor T5, thereby providing the high level at the second control signal terminal EN to the output signal terminal OUT. Since the output signal terminals OUT of each shift register output a high level, the cascade connection makes the input control terminal STV and the reset control terminal RST of each shift register both high levels, thereby providing the low levels of the input signal terminal CN and the reset signal terminal CNB to the first pull-up node PU1. Since the power signal terminal VGH is at a high level, the tenth transistor T10 is turned on, and the second pull-up node PU2 is also at a low level. Through Fig.17 The power-off process makes the pull-up nodes PU1 and PU2 of each shift register at a low level and the pull-down node PD at a high level.

[0189] Although the above reference Fig.16 and Fig.17 A specific power-on timing sequence is described, but the embodiments of the present disclosure are not limited thereto, and other signal timing sequences may be used in the power-on stage as required, for example Fig.18 power-on sequence.

[0190] Fig.18 FIG. 2 shows a timing diagram of a gate drive circuit in a power-on phase according to another embodiment of the present disclosure. Fig.18 As shown, in the power-on stage, the total reset signal, K clock signals and power supply signal provided to the gate drive circuit are at a high level, so that the total reset signal terminal RESET, the clock signal terminal CK, the first control signal terminal CKB and the power supply signal terminal VGH of each shift register are at a high level. Other signals provided to the gate drive circuit, such as the input signal, the second control signal, the reset signal, the start signal STV1 to STVx (x is equal to 2 or 4), and the reference signal are at a low level, so that the input signal terminal CN, the second control signal terminal EN, the reset signal terminal CNB and the reference signal terminal VGL of each shift register are at a low level. Reference Figure 3 and Figure 4 , the high level of the total reset signal terminal RESET turns on the fourteenth transistor T14, thereby pulling down the first pull-up node PU1 to the low level of the reference signal terminal VGL. Since the power signal terminal VGH is at a high level, the tenth transistor T10 is turned on, so that the second pull-up node PU2 is also at a low level. The high level of the first control signal terminal CKB turns on the seventh transistor T7, so that the pull-down node PD is at a high level. Through this power-on process, the pull-up node can be reset to a low level, and the pull-down node can be reset to a high level, so that the pull-up node is pulled down again before entering the display stage, further alleviating the problem of affecting the signal output in the display stage due to the abnormal potential of the pull-up node.

[0191] Fig.19AThe signal timing diagram of the display panel according to the embodiment of the present disclosure is shown. The signal timing diagram of FIG19 is applicable to the display panel of any of the above embodiments, such as the above reference Fig.11 The display panel 1100 described below will be Fig.11 The signal timing of 19A is explained with reference to the display panel 1100.

[0192] refer to Fig.11 , the gate drive circuit 1110 provides gate drive signals to multiple rows of sub-pixels in the array through multiple gate lines G1 to GN under the control of K clock signals, so as to turn on at least one row of sub-pixels in the multiple rows of sub-pixels. The multiplexing circuit 1130 multiplexes the received m input data signals into M output data signals under the control of the first selection signal MUX1 and the second selection signal MUX2, and provides them to the data lines D1 to DM respectively, and thus to the M columns of sub-pixels in the array, so that the turned-on at least one row of sub-pixels emits light based on the received output data signals, wherein m and M are integers greater than 1, and M is an integer multiple of m. Fig.19A In the embodiment of the present invention, M=2m, that is, each multiplexing unit of the multiplexing circuit 1130 multiplexes one input data signal into two output data signals and provides them to two data lines respectively.

[0193] like Fig.19A As shown, in the period P1, the gate line G1 is at a high level, and the first row of sub-pixels is turned on. In the first sub-period of the period P1, the first selection signal line MUX1 is at a high level, and the multiplexing circuit 1130 provides the received m input data signals to the data lines D_o (including D1, D3, D5...) of the m odd columns, so that the m sub-pixels in the first row of sub-pixels turned on and located in the odd columns emit light. Then, in the second sub-period of the period P1, the high level of the second selection signal line MUX2 arrives, and the multiplexing circuit 1130 provides the received m input data signals to the data lines D_e (including D2, D4, D6...) of the m even columns, so that the m sub-pixels in the first row of sub-pixels turned on and located in the even columns emit light. In a similar manner, in time period P2, the gate line G2 of the second row of sub-pixels is at a high level, the second row of sub-pixels is turned on, the first selection signal MUX1 and the second selection signal MUX2 are successively at high levels, so that data is first written to the sub-pixels located in odd columns in the second row of sub-pixels, and then data is written to the sub-pixels located in even columns in the second column of sub-pixels, and so on.

[0194] Fig.19B FIG. 2 is a schematic diagram showing a signal waveform of a display panel according to an embodiment of the present disclosure. Fig.19B As shown in the above reference Figures 13 to 15Under the described signal timing, the pulse width of the gate drive signal GATE (i.e., the time length from the starting point of the rising edge of the gate drive signal GATE to the ending point of the falling edge) is H, where H represents the unit scanning time. The gate drive signal GATE can represent any level of gate drive signal in the gate drive circuit, such as any one of G1 to GN mentioned above. In a high level pulse of the gate drive signal GATE, there is a first time interval GAP1 between the starting point of the rising edge of the gate drive signal GATE and the starting point of the rising edge of the first selection signal MUX1, a second time interval GAP2 between the ending point of the falling edge of the second selection signal MUX2 and the starting point of the falling edge of the gate drive signal GATE, and a third time interval GAP3 between the ending point of the falling edge of the first selection signal MUX1 and the starting point of the rising edge of the second selection signal MUX2.

[0195] Generally, the longer the high level time of the first selection signal MUX1 and the second selection signal MUX2 is, the longer the time left for the sub-pixel to charge. Therefore, during the time when a row of sub-pixels is turned on, that is, during the period when the gate drive signal GATE is at a high level, it is desirable to minimize the rising time Tr (the time from the starting point to the end point of the rising edge) and the falling time Tf (the time from the starting point to the end point of the falling edge) of GAP1, GAP2 and the gate drive signal GATE.

[0196] However, in adopting Figures 13 to 15 The signal timing described is as follows: Fig.19C As shown in the signal simulation diagram, the rising time Tr of the gate drive signal GATE is relatively large, so that the gate drive signal GATE has not reached the desired high level within a certain period of time after the first selection signal MUX1 becomes a high level, resulting in incomplete opening of the sub-pixel. This makes the sub-pixel charging rate corresponding to the first selection signal MUX1 lower than the sub-pixel charging rate corresponding to the second selection signal MUX2. The so-called charging rate here is the ratio of the data voltage actually reached by the sub-pixel to the expected data voltage.

[0197] Fig. 20 A signal timing diagram of a display panel according to another embodiment of the present disclosure is shown. Fig. 20 The signal timing diagram is applicable to the gate driving circuit using four clock signals, such as the gate driving circuit 600. Fig. 20 The signal timing and Fig.15 Similarly, the difference is at least that the four clock signals CK1 to CK4 are periodic signals with a duty cycle of 50% and a pulse width of 2H. The first selection signal MUX1 and the second selection signal MUX2 are periodic signals with a duty cycle of 50% and a pulse width less than m / M*H. In this embodiment, M=2m, and the pulse width of the first selection signal MUX1 and the second selection signal MUX2 is less than 1 / 2*H.

[0198] In the period P1 , the gate driving signal G1 is at a high level, and the first row of sub-pixels are turned on. This process is also called a pre-charging stage.

[0199] In period P2, the gate drive circuit G1 maintains a high level, and the first selection signal MUX1 and the second selection signal MUX2 successively become high levels, thereby writing the data signal for the first row to the turned-on sub-pixels in the first row. During period P2, the gate drive signal G2 is also high, pre-charging the sub-pixels in the second row, during which the high levels of the first selection signal MUX1 and the second selection signal MUX2 cause the data signal for the first row to be written to the sub-pixels in the second row. However, the pre-charging process does not substantially affect the normal display of the sub-pixels in the second row, because in period P3 after period P2, the data signal for the second row will be written to the sub-pixels in the second row in a manner similar to that described above.

[0200] Through the above pre-charging, the high level duration of the gate drive signal is increased, so that the sub-pixel charging rates corresponding to the first selection signal MUX1 and the second selection signal MUX2 are consistent. However, for products with larger size and higher resolution, such as 31.58K products, the above pre-charging solution may have some problems. Figures 21A to 21C Let’s analyze and explain this.

[0201] FIG. 21A to FIG. 21C Shows Fig. 20 Signal simulation diagram of an embodiment of the present invention.

[0202] Referring to the structure of the gate driving circuit 600, when the output signal terminal OUT of the third-stage shift register GOA3 is at a high level, the pull-up node PU of the first-stage shift register GOA1 is discharged, so that the third transistor T3 of the first-stage shift register GOA1 is turned off, and at the same time, the CKB of the first-stage shift register GOA1 charges the pull-down node PD, so that the fourth transistor T4 is turned on. In the first-stage shift register GOA1, when the third transistor T3 is turned off but the fourth transistor T4 is not turned on, the output signal terminal OUT is in a floating state. At this time, the output signal terminal OUT is affected by the coupling capacitance between the pull-down node PD and the potential increases, such as Fig.21A As shown by the dotted line in the first-stage shift register GOA1, after the fourth transistor T4 is turned on, the potential of the output signal terminal OUT continues to drop. Since the channel width-to-length ratio W / L of the fourth transistor T4 is small and the discharge capacity is weak, the discharge time of the output signal terminal OUT is long, so the falling time Tf of the generated gate drive signal G1 is large, as shown in FIG. Fig.21A shown.

[0203] In addition, for an 8K display panel with a resolution of 7680×4320, if Figure 6 The cascade scheme of 4 clock signals, each clock signal drives 1080 rows of pixels. In this case, Fig. 21B As shown in the charging simulation waveform, among the multiple shift registers controlled by the same clock signal line (e.g., the clock signal line providing the clock signal CK1), there is a large difference between the rising edge of the gate drive signal on the gate line of the shift register far from the clock signal line (e.g., the gate line Gx connected to the output signal end of the last stage shift register controlled by CK1) and the rising edge of the gate line of the shift register close to the clock signal line (e.g., the gate line G1 connected to the output signal end of the first stage shift register controlled by CK1). If the process fluctuations of the signal line width and the signal line material film thickness in the process cause large fluctuations in the RC load on the gate line, the difference may be even greater, and may even cause the product to display abnormally with split screens.

[0204] like Fig. 21C As shown in the simulation waveform diagram, for 8K display products, Fig. 20 The driving scheme achieves a sub-pixel charging rate of less than 95%.

[0205] Fig. 22 A signal waveform diagram of a display panel according to another embodiment of the present disclosure is shown. Fig. 20 The signal timing diagram is applicable to the gate driving circuit 500 using 8 clock signals, such as the gate driving circuit 600. Fig. 22 The signal timing and Fig. 22 Similarly, the difference is at least that the eight clock signals are periodic signals with a duty cycle of 25% and a pulse width of 2H. The first selection signal MUX1 and the second selection signal MUX2 are periodic signals with a duty cycle of 50% and a pulse width less than 1 / 2*H.

[0206] Figures 23A to 23C Shows Fig. 22 Signal simulation diagram of the embodiment. Fig.23A It can be seen that by adopting Figure 5 The cascade scheme of the eight clock signals, such as the falling edge of the gate drive signal G1 controlled by the clock signal CK1 and the rising edge of the gate drive signal G5 controlled by the clock signal CK5, does not overlap. Fig.21A , the falling time Tf of the gate drive signal G1 to GN is small. Fig. 23B It can be seen that for the above 8K display products, if a cascade solution of 8 clock signals is adopted, each clock signal drives 540 rows of pixels, compared with Fig. 21B , the rising edge difference of the gate drive signal on different gate lines (such as G1 and Gx) controlled by the same clock signal line is reduced. Fig.23C It can be seen that using Fig. 22 The driving method can achieve a sub-pixel charging rate of 96%.

[0207] References FIG. 19A to FIG. 23C The signal waveform described is the signal waveform of the display panel in the display stage. The signal waveform of the display panel in the power-on stage and the power-off stage can be selected as needed. For example, the above reference Figures 16 to 18 The power-on sequence and power-off sequence in any embodiment of the present invention.

[0208] Fig.24 A flow chart of a driving method of a gate driving circuit according to an embodiment of the present disclosure is shown. The method is applicable to the gate driving circuit of any of the above embodiments.

[0209] In step S2401, in the display stage, an input signal of a first level is provided to the gate driving circuit, and each shift register outputs a gate driving signal at its own output signal terminal OUT based on the input signal under the control of the potential of its own input control terminal STV.

[0210] In step S2402, in the power-off stage, a second control signal of a first level and an input signal of a second level are provided to the gate drive circuit, each shift register provides the second control signal of the first level to its respective output signal terminal OUT, and each shift register provides the input signal of the second level to its respective pull-up node PU under the control of the potential of its respective input control terminal STV.

[0211] For example, in the case where the second control circuit of each shift register includes a pull-down sub-circuit and a lower electronic circuit, for example, in the case of adopting the shift register 300, in the display stage, the pull-down sub-circuit of each shift register provides the potential of the reference signal terminal VGL of the shift register to the output signal terminal OUT of the shift register under the control of the potential of the pull-down node PD of the shift register; in the power-off stage, the lower electronic circuit of each shift register provides the second control signal of the first level at the second control signal terminal EN of the shift register to the output signal terminal OUT of the shift register and provides the potential of the reference signal terminal VGL of the shift register to the pull-down node PD of the shift register.

[0212] For example, in the case where the second control circuit of each shift register includes a fifth transistor T5 and a second capacitor C2, for example, in the case of using the shift register 400, in the display stage, a second control signal of a second level is provided to the gate drive circuit, and the second control circuit of each shift register provides the second control signal of the second level to the output signal terminal OUT of the shift register under the control of the potential of the pull-down node PD of the shift register; in the power-off stage, K clock signals maintaining the first level are provided to the gate drive circuit, and the first control circuit of each shift register provides the clock signal of the first level received at the first control signal terminal CKB of the shift register to the pull-down node PD of the shift register, and the potential of the pull-down node PD causes the second control circuit of the shift register to provide the second control signal of the first level to the output signal terminal OUT of the shift register.

[0213] In some embodiments, during the display stage, K sequentially shifted clock signals are provided to the gate drive circuit, and each shift register outputs a gate drive signal at its respective output signal terminal OUT based on the input signal and the received clock signal under the control of the potential of its respective input control terminal STV, wherein the k+1th clock signal is shifted by the unit scan time relative to the kth clock signal, wherein k is an integer, 1≤k≤K-1, and the unit scan time is the time required for the gate drive circuit to scan a row of pixels.

[0214] Those skilled in the art can understand that the embodiments described above are exemplary and can be improved by those skilled in the art. The structures described in various embodiments can be freely combined without causing conflicts in structure or principle.

[0215] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art can clearly understand that various changes and modifications can be made without departing from the scope and spirit of the appended claims, and the present disclosure is not limited to the implementation methods of the exemplary embodiments listed in the specification.

Claims

1. A shift register, comprising: An input circuit connected to an input signal terminal, an input control terminal and a pull-up node of the shift register, and configured to input the potential of the input signal terminal to the pull-up node under the control of a signal of the input control terminal; an output circuit connected to the pull-up node, the clock signal terminal and the output signal terminal, and configured to provide the signal of the clock signal terminal to the output signal terminal under the control of the potential of the pull-up node; a first control circuit connected to a first control signal terminal, the pull-up node, a pull-down node of the shift register, and a reference signal terminal, and configured to provide a potential of the first control signal terminal to the pull-down node, and to provide a potential of the reference signal terminal to the pull-down node according to a potential of the pull-up node; as well as a second control circuit connected to the pull-down node, the second control signal terminal, the output signal terminal and the reference signal terminal, and configured to pull down the potential of the output signal terminal in a display phase and pull up the potential of the output signal terminal in a power-down phase under the control of the potentials of the pull-down node and the second control signal terminal; Wherein, the second control circuit comprises: a pull-down subcircuit connected to the pull-down node, the output signal terminal and the reference signal terminal, and configured to provide the potential of the reference signal terminal to the output signal terminal under the control of the potential of the pull-down node; The pull-down subcircuit includes a third transistor, a first capacitor and a fourth transistor, wherein: The gate of the third transistor is connected to the pull-down node, the first electrode of the third transistor is connected to the reference signal terminal, and the second electrode of the third transistor is connected to the output signal terminal; A first terminal of the first capacitor is connected to the pull-down node, and a second terminal of the first capacitor is connected to the reference signal terminal; and A gate of the fourth transistor is connected to the output signal terminal, a first electrode of the fourth transistor is connected to the reference signal terminal, and a second electrode of the fourth transistor is connected to the pull-down node.

2. The shift register according to claim 1, wherein: The second control circuit further includes: The lower electronic circuit is connected to the second control signal terminal, the pull-down node, the output signal terminal and the reference signal terminal, and is configured to provide the potential of the second control signal terminal to the output signal terminal and provide the potential of the reference signal terminal to the pull-down node under the control of the signal of the second control signal terminal.

3. The shift register according to claim 2, wherein: The lower electronic circuit comprises a first transistor and a second transistor, wherein, The gate and the first electrode of the first transistor are connected to the second control signal terminal, and the second electrode of the first transistor is connected to the output signal terminal; and A gate of the second transistor is connected to the second control signal terminal, a first electrode of the second transistor is connected to the reference signal terminal, and a second electrode of the second transistor is connected to the pull-down node.

4. The shift register according to claim 1, wherein: The second control circuit includes a fifth transistor and a second capacitor, wherein: The gate of the fifth transistor is connected to the pull-down node, the first electrode of the fifth transistor is connected to the second control signal terminal, and the second electrode of the fifth transistor is connected to the output signal terminal; and A first terminal of the second capacitor is connected to the pull-down node, and a second terminal of the second capacitor is connected to the reference signal terminal.

5. The shift register according to claim 1, further comprising: The noise reduction circuit is connected to the input control terminal, the pull-down node and the reference signal terminal, and is configured to provide the potential of the reference signal terminal to the pull-down node under the control of the signal of the input control terminal.

6. The shift register according to claim 5, wherein: The noise reduction circuit includes a sixth transistor, a gate of the sixth transistor is connected to the input control terminal, a first electrode of the sixth transistor is connected to the reference signal terminal, and a second electrode of the sixth transistor is connected to the pull-down node.

7. The shift register according to claim 1, further comprising: The reset circuit is connected to the reset control terminal, the reset signal terminal and the pull-up node, and is configured to provide the potential of the reset signal terminal to the pull-up node under the control of the signal of the reset control terminal.

8. The shift register according to claim 1, wherein: The pull-up node includes a first pull-up node connected to the input circuit and a second pull-up node connected to the output circuit, and the first control circuit includes a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor, wherein, The gate and the first electrode of the seventh transistor are connected to the first control signal terminal, and the second electrode of the seventh transistor is connected to the pull-down node; The gate of the eighth transistor is connected to the pull-down node, the first electrode of the eighth transistor is connected to the reference signal terminal, and the second electrode of the eighth transistor is connected to the first pull-up node; The gate of the ninth transistor is connected to the first pull-up node, the first electrode of the ninth transistor is connected to the reference signal terminal, and the second electrode of the ninth transistor is connected to the pull-down node; and A gate of the tenth transistor is connected to a power signal terminal, a first electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the tenth transistor is connected to the second pull-up node.

9. The shift register according to claim 1, wherein: The input circuit includes an eleventh transistor, a gate of the eleventh transistor is connected to the input control terminal, a first electrode of the eleventh transistor is connected to the input signal terminal, and a second electrode of the eleventh transistor is connected to the pull-up node.

10. The shift register according to claim 1, wherein: The output circuit includes a twelfth transistor and a third capacitor, wherein: The gate of the twelfth transistor is connected to the pull-up node, the first electrode of the twelfth transistor is connected to the clock signal terminal, and the second electrode of the twelfth transistor is connected to the output signal terminal; and A first end of the third capacitor is connected to the pull-up node, and a second end of the third capacitor is connected to the output signal terminal.

11. The shift register according to claim 7, wherein: The reset circuit includes a thirteenth transistor, a gate of the thirteenth transistor is connected to the reset control terminal, a first electrode of the thirteenth transistor is connected to the reset signal terminal, and a second electrode of the thirteenth transistor is connected to the pull-up node.

12. The shift register according to claim 1 further includes a total reset circuit, which is connected to the total reset signal terminal, the pull-up node and the reference signal terminal, and is configured to provide the potential of the reference signal terminal to the pull-up node under the control of the signal of the total reset signal terminal.

13. The shift register according to claim 12, wherein: The general reset circuit includes a fourteenth transistor, a gate of the fourteenth transistor is connected to the general reset signal terminal, a first electrode of the fourteenth transistor is connected to the reference signal terminal, and a second electrode of the fourteenth transistor is connected to the pull-up node.

14. A gate drive circuit, comprising N stages of cascaded shift registers, each of which is a shift register according to any one of claims 1 to 13, wherein: The input signal terminal of each shift register is connected to receive an input signal, the reset signal terminal is connected to receive a reset signal, and the second control signal terminal is connected to receive a second control signal; The input control terminal of the n-th shift register is connected to the output signal terminal of the ni-th shift register, and the reset control terminal of the n-th shift register is connected to the output signal terminal of the n+j-th shift register; and The N-stage cascaded shift registers are divided into at least one group, each group includes K-stage cascaded shift registers, the clock signal ends of the K-stage cascaded shift registers are respectively connected to receive K clock signals, and the first control signal ends of the K-stage cascaded shift registers are respectively connected to receive the K clock signals, wherein N, K, n, i and j are all integers, 1≤n≤N, 1<K≤N.

15. The gate driving circuit according to claim 14, wherein: i=j=4, K=8, the K clock signals include a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal and an eighth clock signal, in each group of shift registers: The clock signal terminal of the first stage shift register is connected to receive the first clock signal, and the first control signal terminal of the first stage shift register is connected to receive the fifth clock signal; The clock signal terminal of the second stage shift register is connected to receive the second clock signal, and the first control signal terminal of the second stage shift register is connected to receive the sixth clock signal; The clock signal terminal of the third-stage shift register is connected to receive the third clock signal, and the first control signal terminal of the third-stage shift register is connected to receive the seventh clock signal; The clock signal terminal of the fourth-stage shift register is connected to receive the fourth clock signal, and the first control signal terminal of the fourth-stage shift register is connected to receive the eighth clock signal; The clock signal terminal of the fifth-stage shift register is connected to receive the fifth clock signal, and the first control signal terminal of the fifth-stage shift register is connected to receive the first clock signal; The clock signal terminal of the sixth-stage shift register is connected to receive the sixth clock signal, and the first control signal terminal of the sixth-stage shift register is connected to receive the second clock signal; The clock signal terminal of the seventh-stage shift register is connected to receive the seventh clock signal, and the first control signal terminal of the seventh-stage shift register is connected to receive the third clock signal; The clock signal terminal of the eighth stage shift register is connected to receive the eighth clock signal, and the first control signal terminal of the eighth stage shift register is connected to receive the fourth clock signal.

16. The gate driving circuit according to claim 14, wherein: i=j=2, K=4, the K clock signals include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, in each group of shift registers: The clock signal terminal of the first stage shift register is connected to receive the first clock signal, and the first control signal terminal of the first stage shift register is connected to receive the third clock signal; The clock signal terminal of the second stage shift register is connected to receive the second clock signal, and the first control signal terminal of the second stage shift register is connected to receive the fourth clock signal; The clock signal terminal of the third-stage shift register is connected to receive the third clock signal, and the first control signal terminal of the third-stage shift register is connected to receive the first clock signal; The clock signal terminal of the fourth-stage shift register is connected to receive the fourth clock signal, and the first control signal terminal of the fourth-stage shift register is connected to receive the second clock signal.

17. A driving method of a gate driving circuit according to any one of claims 14 to 16, comprising: In the display stage, an input signal of a first level is provided to the gate driving circuit, and each shift register outputs a gate driving signal at a respective output signal terminal based on the input signal under the control of the potential of the respective input control terminal; In the power-off stage, a second control signal of a first level and an input signal of a second level are provided to the gate drive circuit, each shift register provides the second control signal of the first level to its respective output signal terminal, and each shift register provides the input signal of the second level to its respective pull-up node under the control of the potential of its respective input control terminal.

18. The driving method according to claim 17, wherein: The second control circuit of each shift register includes a pull-down sub-circuit and a lower electronic circuit, wherein, In the display phase, the pull-down subcircuit of each shift register provides the potential of the reference signal terminal of the shift register to the output signal terminal of the shift register under the control of the potential of the pull-down node of the shift register; and In the power-down phase, the lower electronic circuit of each shift register provides a second control signal of a first level at the second control signal terminal of the shift register to the output signal terminal of the shift register and provides the potential of the reference signal terminal of the shift register to the pull-down node of the shift register.

19. The driving method according to claim 17, wherein: The second control circuit of each shift register includes a fifth transistor and a second capacitor, wherein: In the display stage, a second control signal of a second level is provided to the gate driving circuit, and the second control circuit of each shift register provides the second control signal of the second level to the output signal terminal of the shift register under the control of the potential of the pull-down node of the shift register; In the power-down stage, K clock signals maintaining the first level are provided to the gate drive circuit, and the first control circuit of each shift register provides the clock signal of the first level received at the first control signal terminal of the shift register to the pull-down node of the shift register, and the potential of the pull-down node causes the second control circuit of the shift register to provide the second control signal of the first level to the output signal terminal of the shift register.

20. The driving method according to claim 17, wherein: In the display stage, K sequentially shifted clock signals are provided to the gate drive circuit, and each shift register outputs a gate drive signal at its own output signal terminal based on the input signal and the received clock signal under the control of the potential of its own input control terminal, wherein the k+1th clock signal is shifted by a unit scan time relative to the kth clock signal, wherein k is an integer, 1≤k≤K-1, and the unit scan time is the time required for the gate drive circuit to scan a row of pixels.

21. The driving method according to claim 20, wherein: In the gate driving circuit, i=j=4 and K=8. In the display stage, the K clock signals are periodic signals with a duty cycle of 25% and a pulse width of 2 times the unit scanning time.

22. The driving method according to claim 20, wherein: In the gate driving circuit, i=j=2 and K=4. In the display stage, the K clock signals are periodic signals with a duty cycle of 50% and a pulse width of 2 times the unit scanning time.

23. The driving method according to claim 20, wherein: In the gate driving circuit, i=j=4 and K=8. In the display stage, the K clock signals are periodic signals with a duty cycle of 12.5% ​​and a pulse width of a unit scanning time.

24. The driving method according to claim 20, wherein: In the gate driving circuit, i=j=2 and K=4. In the display stage, the K clock signals are periodic signals with a duty cycle of 25% and a pulse width of a unit scanning time.

25. A display panel comprising: a plurality of sub-pixels arranged in an array; as well as At least one gate driving circuit as claimed in any one of claims 14 to 16, wherein the N-stage shift registers in the gate driving circuit are respectively connected to multiple rows of sub-pixels in the array.

26. The display panel according to claim 25, wherein: The display panel comprises two gate driving circuits, and the two gate driving circuits are respectively located at two sides of the array of the plurality of sub-pixels along a first direction, wherein the first direction is a row direction of the array.

27. The display panel according to claim 25, wherein: The display panel comprises a gate driving circuit, wherein i=j=2, K=4, and the odd-numbered shift register and the even-numbered shift register in the gate driving circuit are respectively located on both sides of the array of the plurality of sub-pixels along a first direction.

28. The display panel according to any one of claims 25 to 27, wherein: The shift register comprises an input circuit, a first control circuit, a second control circuit and an output circuit, wherein the input circuit, the first control circuit, the second control circuit and the output circuit are arranged in sequence along a first direction, and the size of each of the input circuit, the first control circuit, the second control circuit and the output circuit in the second direction is 0.8-1.4 times the size of the sub-pixel in the second direction, wherein the first direction is the row direction of the array, and the second direction is perpendicular to the first direction.

29. The display panel according to any one of claims 25 to 27 further includes a multiplexing circuit, which is connected to M columns of sub-pixels in the array, and is configured to multiplex the received m input data signals into M output data signals under the control of a first selection signal and a second selection signal and provide them to the M columns of sub-pixels respectively, wherein m and M are integers greater than 1, and M is an integer multiple of m.

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