Semiconductor structure and its fabrication method

Abstract

This application provides a semiconductor structure and its fabrication method. In the semiconductor structure, a semiconductor substrate, a heterojunction, and an in-situ insulating layer are distributed from bottom to top. The in-situ insulating layer has a groove, and a transition layer is located at least on the in-situ insulating layer. A p-type semiconductor layer is located in the gate region within the groove and on the transition layer. An n-type ion-doped layer is located on the p-type semiconductor layer in the gate region, and / or on the source region of the heterojunction, and / or on the drain region of the heterojunction. The in-situ insulating layer and the transition layer can reduce the gate leakage current formed by channel leakage to the gate in the device. Therefore, the thickness of the barrier layer in the heterojunction can be smaller, and the threshold voltage can be increased. In addition, it can reduce the sheet resistance, increase the concentration of two-dimensional electron gas, improve the gate's control capability over the channel, and increase the operating current. The n-type ion-doped layer allows the source, drain, and gate to directly form an ohmic contact layer, avoiding high-temperature annealing.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As a typical representative of third-generation semiconductor materials, group III nitrides, with their wide bandgap semiconductors, have excellent properties such as large bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructures. They are very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.

[0003] For example, AlGaN / GaN heterojunctions have strong spontaneous polarization and piezoelectric polarization, resulting in a high concentration of two-dimensional electron gas (2DEG) at the AlGaN / GaN interface. They are widely used in semiconductor structures such as high electron mobility transistors (HEMTs).

[0004] Enhancement-mode devices have a wide range of applications in power electronics due to their normally-off nature. There are many ways to implement enhancement-mode devices, such as by using a p-type semiconductor at the gate to deplete the two-dimensional electron gas. Summary of the Invention

[0005] However, the inventors of this application have discovered that enhancement-mode devices implemented by placing a p-type semiconductor at the gate have a lower threshold voltage, and this method requires etching the p-type semiconductor outside the gate region, but etching inevitably leads to etching losses. Furthermore, the ohmic contact layer requires high-temperature annealing to form, which affects the performance of the semiconductor structure.

[0006] To address the above problems, a first aspect of the present invention provides a semiconductor structure comprising:

[0007] Semiconductor substrate, heterojunction, and in-situ insulating layer distributed from bottom to top;

[0008] A groove penetrating the in-situ insulating layer;

[0009] At least a transition layer located on the in-situ insulating layer;

[0010] A p-type semiconductor layer located within the groove and on the transition layer, in the gate region;

[0011] A heavily doped n-type ion layer located on the p-type semiconductor layer in the gate region, and / or on the source region of the heterojunction, and / or on the drain region of the heterojunction.

[0012] Optionally, the material of the n-type ion heavily doped layer includes a group III nitride material.

[0013] Optionally, the transition layer is also located within the groove.

[0014] Optionally, the non-gate region on the transition layer also has the p-type semiconductor layer.

[0015] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top.

[0016] Optionally, the n-type ion-doped layer contacts the channel layer or the barrier layer.

[0017] Optionally, the heterojunction comprises a group III nitride material.

[0018] Optionally, the in-situ insulating layer is a single-layer structure, and the material of the single-layer structure includes one or more of SiN and AlN; or the in-situ insulating layer is a multilayer structure, and the multilayer structure includes, from bottom to top, a SiN layer and an AlN layer, an AlN layer and a SiN layer, or a SiN layer, an AlN layer and a SiN layer.

[0019] Optionally, the transition layer is a single-layer structure, and the material of the single-layer structure includes one or a mixture of AlN, SiAlN, and AlGaN; or the transition layer is a stacked structure, and the stacked structure includes at least two layers selected from AlN, SiAlN, and AlGaN.

[0020] Optionally, the semiconductor structure further includes: a gate on an n-type ion heavily doped layer located in the gate region, a source on an n-type ion heavily doped layer located in the source region, and a drain on an n-type ion heavily doped layer located in the drain region.

[0021] A second aspect of the present invention provides a method for fabricating a semiconductor structure, comprising:

[0022] A semiconductor substrate is provided, on which a heterojunction is formed;

[0023] An in-situ insulating layer is formed on the heterojunction;

[0024] A groove is formed that penetrates the in-situ insulating layer;

[0025] A transition layer and a p-type semiconductor layer are sequentially formed within the groove and on the in-situ insulating layer;

[0026] An n-type ion heavily doped layer is formed on the p-type semiconductor layer of the gate region, and / or on the source region of the heterojunction, and / or on the drain region of the heterojunction.

[0027] Optionally, the material of the n-type ion heavily doped layer includes a group III nitride material.

[0028] Optionally, the fabrication method further includes: patterning the p-type semiconductor layer and retaining the p-type semiconductor layer in the gate region.

[0029] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top.

[0030] Optionally, the n-type ion-doped layer contacts the channel layer or the barrier layer.

[0031] Optionally, the heterojunction comprises a group III nitride material.

[0032] Optionally, the in-situ insulating layer is a single-layer structure, and the material of the single-layer structure includes one or more of SiN and AlN; or the in-situ insulating layer is a multilayer structure, and the multilayer structure includes, from bottom to top, a SiN layer and an AlN layer, an AlN layer and a SiN layer, or a SiN layer, an AlN layer and a SiN layer.

[0033] Optionally, the transition layer is a single-layer structure, and the material of the single-layer structure includes one or a mixture of AlN, SiAlN, and AlGaN; or the transition layer is a stacked structure, and the stacked structure includes at least two layers selected from AlN, SiAlN, and AlGaN.

[0034] Optionally, the fabrication method further includes: forming a gate on an n-type ion heavily doped layer in the gate region, forming a source on an n-type ion heavily doped layer in the source region, and forming a drain on an n-type ion heavily doped layer in the drain region.

[0035] A third aspect of the present invention provides a method for fabricating a semiconductor structure, comprising:

[0036] A semiconductor substrate is provided, on which a heterojunction is formed;

[0037] An in-situ insulating layer and a transition layer are sequentially formed on the heterojunction;

[0038] A groove is formed that penetrates the in-situ insulating layer and the transition layer;

[0039] A p-type semiconductor layer is formed within the groove and on the transition layer;

[0040] An n-type ion heavily doped layer is formed on the p-type semiconductor layer of the gate region, and / or on the source region of the heterojunction, and / or on the drain region of the heterojunction.

[0041] Optionally, the material of the n-type ion heavily doped layer includes a group III nitride material.

[0042] Optionally, the fabrication method further includes: patterning the p-type semiconductor layer and retaining the p-type semiconductor layer in the gate region.

[0043] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top.

[0044] Optionally, the n-type ion-doped layer contacts the channel layer or the barrier layer.

[0045] Optionally, the heterojunction comprises a group III nitride material.

[0046] Optionally, the in-situ insulating layer is a single-layer structure, and the material of the single-layer structure includes one or more of SiN and AlN; or the in-situ insulating layer is a multilayer structure, and the multilayer structure includes, from bottom to top, a SiN layer and an AlN layer, an AlN layer and a SiN layer, or a SiN layer, an AlN layer and a SiN layer.

[0047] Optionally, the transition layer is a single-layer structure, and the material of the single-layer structure includes one or a mixture of AlN, SiAlN, and AlGaN; or the transition layer is a stacked structure, and the stacked structure includes at least two layers selected from AlN, SiAlN, and AlGaN.

[0048] Optionally, the fabrication method further includes: forming a gate on an n-type ion heavily doped layer in the gate region, forming a source on an n-type ion heavily doped layer in the source region, and forming a drain on an n-type ion heavily doped layer in the drain region.

[0049] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0050] 1) The semiconductor structure of the present invention includes: a semiconductor substrate, a heterojunction, an in-situ insulating layer, a transition layer, a p-type semiconductor layer, and an n-type ion-heavily doped layer. The semiconductor substrate, heterojunction, and in-situ insulating layer are distributed from bottom to top. The in-situ insulating layer has a groove. The transition layer is located at least on the in-situ insulating layer outside the groove. The p-type semiconductor layer is located in the gate region within the groove and on the transition layer. The n-type ion-heavily doped layer is located on the p-type semiconductor layer in the gate region, and / or on the source region of the heterojunction, and / or on the drain region of the heterojunction. The transition layer facilitates the formation of the p-type semiconductor layer outside the groove during the process. The in-situ insulating layer and the transition layer can reduce the gate leakage current formed by channel leakage to the gate in the device. Therefore, the thickness of the barrier layer in the heterojunction can be smaller, thereby increasing the threshold voltage. Furthermore, due to the in-situ insulating layer, the sheet resistance can be reduced, the concentration of the two-dimensional electron gas can be increased, the gate's control over the channel can be improved, and the operating current can be increased.

[0051] The transition layer serves two purposes: firstly, it prevents the selective growth of p-type semiconductors on the in-situ insulating layer, thereby improving the quality of the p-type semiconductor layer; secondly, it prevents atoms (such as Si atoms) in the in-situ insulating layer from diffusing into the p-type semiconductor layer and affecting it.

[0052] The n-type ion-doped layer allows the source to directly form an ohmic contact layer with the source region of the heterojunction, the drain to form an ohmic contact layer with the drain region of the heterojunction, and the gate to form an ohmic contact layer with the p-type semiconductor layer of the gate region, thus avoiding high-temperature annealing.

[0053] 2) In the optional scheme, the heterojunction includes a channel layer and a barrier layer from bottom to top. Specifically, a) the channel layer and the barrier layer can each have one layer; or b) the channel layer and the barrier layer can each have multiple layers, which are alternately distributed; or c) one channel layer and two or more barrier layers to meet different functional requirements.

[0054] 3) In an optional embodiment, the heterojunction includes a group III nitride material. Group III nitride materials may include any one or a combination of GaN, AlGaN, and AlInGaN. The semiconductor structure of this invention has strong compatibility with existing HEMT devices.

[0055] 4) In the optional embodiment, the p-type semiconductor layer includes a group III nitride material. The transition layer material includes at least one of AlN, SiAlN, and AlGaN. The group III nitride material may include any one or a combination of GaN, AlGaN, and AlInGaN. The transition layer is formed using an in-situ growth process, which can improve the quality of the subsequent p-type semiconductor layer.

[0056] 5) In an optional scheme, the non-gate region on the transition layer also has a p-type semiconductor layer. In other words, the p-type semiconductor layer on the transition layer can be patterned, retaining only the p-type semiconductor layer in the gate region to consume the excess two-dimensional electron gas below the gate; due to the presence of the in-situ insulating layer and the transition layer, the p-type semiconductor layer in the non-gate region can also be left unpatterned, and the p-type semiconductor layers in both the gate region and the non-gate region are retained in the semiconductor structure.

[0057] 6) In the optional scheme, the source and drain are connected to the channel layer or the barrier layer to meet the requirements of different semiconductor structures. Attached Figure Description

[0058] Figure 1 This is a schematic diagram of the semiconductor structure according to the first embodiment of the present invention;

[0059] Figure 2 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention;

[0060] Figures 3 to 5 yes Figure 2A schematic diagram of the intermediate structure corresponding to the process in the document;

[0061] Figure 6 This is a schematic diagram of the semiconductor structure according to the second embodiment of the present invention;

[0062] Figure 7 This is a schematic diagram of the semiconductor structure according to the third embodiment of the present invention;

[0063] Figure 8 This is a flowchart of a method for fabricating a semiconductor structure according to the third embodiment of the present invention;

[0064] Figure 9 This is a schematic diagram of the semiconductor structure according to the fourth embodiment of the present invention;

[0065] Figure 10 This is a schematic diagram of the semiconductor structure according to the fifth embodiment of the present invention;

[0066] Figure 11 This is a flowchart of a method for fabricating a semiconductor structure according to the fifth embodiment of the present invention;

[0067] Figure 12 yes Figure 11 A schematic diagram of the intermediate structure corresponding to the process in the document;

[0068] Figure 13 This is a schematic diagram of the semiconductor structure according to the sixth embodiment of the present invention;

[0069] Figure 14 This is a schematic diagram of the semiconductor structure according to the seventh embodiment of the present invention;

[0070] Figure 15 This is a schematic diagram of the semiconductor structure according to the eighth embodiment of the present invention.

[0071] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below:

[0072] Semiconductor structures 1, 2, 3, 4, 5, 6, 7, 8; Semiconductor substrate 10

[0073] Heterojunction 11 In-situ insulating layer 12

[0074] Groove 13 Transition layer 14

[0075] p-type semiconductor layer 15 n-type ion heavily doped layer 16

[0076] Gate 17a Source 17b

[0077] Drain 17c, Channel layer 11a

[0078] Barrier layer 11b Detailed Implementation

[0079] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0080] Figure 1 This is a schematic diagram of the semiconductor structure according to the first embodiment of the present invention.

[0081] Reference Figure 1 As shown, semiconductor structure 1 includes:

[0082] Semiconductor substrate 10, heterojunction 11 and in-situ insulating layer 12 distributed from bottom to top;

[0083] The groove 13 penetrating the in-situ insulating layer 12 (refer to) Figure 4 (as shown);

[0084] Transition layer 14 located within the groove 13 and on the in-situ insulating layer 12;

[0085] p-type semiconductor layer 15 located on transition layer 14;

[0086] The p-type semiconductor layer 15 located in the gate region, and the n-type ion heavily doped layer 16 located in the source and drain regions of the heterojunction 11;

[0087] Gate 17a located on the n-type ion heavily doped layer 16 in the gate region, source 17b located on the n-type ion heavily doped layer 16 in the source region, and drain 17c located on the n-type ion heavily doped layer 16 in the drain region.

[0088] The semiconductor substrate 10 can be made of sapphire, silicon carbide, silicon, GaN, or diamond.

[0089] The heterojunction 11 may include a channel layer 11a and a barrier layer 11b from bottom to top. A two-dimensional electron gas can be formed at the interface between the channel layer 11a and the barrier layer 11b. In one alternative embodiment, the channel layer 11a is an intrinsic GaN layer, and the barrier layer 11b is an n-type AlGaN layer. In other alternative embodiments, the combination of the channel layer 11a and the barrier layer 11b can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. In addition, besides Figure 1 The channel layer 11a and barrier layer 11b shown each have one layer; the channel layer 11a and barrier layer 11b may also have multiple layers, which are alternately distributed; or one channel layer 11a and two or more barrier layers 11b to form a multi-barrier structure.

[0090] A nucleation layer and a buffer layer (not shown) may also be present between the heterojunction 11 and the semiconductor substrate 10. The nucleation layer may be made of materials such as AlN or AlGaN, and the buffer layer may be made of at least one of AlN, GaN, AlGaN, and AlInGaN. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction 11, and the semiconductor substrate 10. The buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0091] The in-situ insulating layer 12 is an insulating layer formed by an in-situ growth process. One of the functions of the in-situ insulating layer 12 is to connect the gate 17a and the barrier layer 11b outside the electrically insulating groove 13. In the HEMT structure, the in-situ insulating layer 12 can also suppress the current collapse effect.

[0092] In one alternative, the in-situ insulating layer 12 is a single-layer structure, and the material of the single-layer structure includes one or a mixture of SiN and AlN. In another alternative, the in-situ insulating layer 12 is a multilayer structure, which may include, from bottom to top, a SiN layer and an AlN layer, an AlN layer and a SiN layer, or a SiN layer, an AlN layer and a SiN layer, etc.

[0093] The transition layer 14 can be formed using an in-situ growth process. In one option, the transition layer 14 is a single-layer structure, and the material of this single-layer structure may include one or more mixtures of AlN, SiAlN, and AlGaN. In another option, the transition layer 14 is a stacked structure, and this stacked structure may include at least two layers selected from AlN, SiAlN, and AlGaN. The transition layer 14 made of the above materials can solve the problem that p-type group III nitride materials cannot be grown on the in-situ insulating layer 12, thus allowing a p-type semiconductor layer 15 to be formed outside the groove 13.

[0094] The p-type semiconductor layer 15 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN, wherein the p-type dopant ions can be magnesium ions to deplete the two-dimensional electron gas below the gate region to form an enhancement-mode device.

[0095] Figure 1 In the illustrated embodiment, the p-type semiconductor layer 15 has a recessed region at the corresponding groove 13, and a portion of the gate 17a is located in this recessed region. In some embodiments, the upper surface of the p-type semiconductor layer 15 and the lower surface of the gate 17a may also be flat.

[0096] Figure 1In this structure, the source 17b and drain 17c are connected to the barrier layer 11b, and ohmic contacts are formed between the source 17b and the barrier layer 11b, and between the drain 17c and the barrier layer 11b, using n-type ion heavily doped layers 16. An ohmic contact is also formed between the gate 17a and the p-type semiconductor layer 15 using n-type ion heavily doped layers 16. The source 17b, drain 17c, and gate 17a can be made of metal, such as existing conductive materials like Ti / Al / Ni / Au or Ni / Au. The n-type ion heavily doped layers 16 enable the source 17b to directly form ohmic contact layers with the source region of the heterojunction 11, the drain 17c to the drain region of the heterojunction 11, and the gate 17a to the p-type semiconductor layer 15 of the gate region without high-temperature annealing.

[0097] In some embodiments, an n-type ion heavily doped layer 16 may also be provided on the p-type semiconductor layer 15 of the gate region, and on at least one of the source region and drain region of the heterojunction 11. The p-type semiconductor layer 15 and gate 17a of the gate region without the n-type ion heavily doped layer 16, the source region and source 17b of the heterojunction 11 without the n-type ion heavily doped layer 16, or the drain region and drain 17c of the heterojunction 11 without the n-type ion heavily doped layer 16 are formed into an ohmic contact layer by high-temperature annealing.

[0098] In the n-type ion heavily doped layer 16, the n-type ions can be at least one of Si ions, Ge ions, Sn ions, Se ions, or Te ions. For different n-type ions, the doping concentration can be greater than 1E19 / cm. 3 The n-type ion-doped layer 16 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN.

[0099] In the semiconductor structure 1 described above, the in-situ insulating layer 12 and the transition layer 14 reduce the gate leakage current formed by the channel leakage to the gate 17a. Therefore, the thickness of the barrier layer 11b in the heterojunction 11 can be smaller, thereby reducing the threshold voltage. In addition, due to the provision of the in-situ insulating layer 12, the surface resistance can be reduced and the concentration of two-dimensional electron gas can be increased, thereby improving the gate's control capability over the channel and increasing the operating current.

[0100] To verify the technical effect of the present invention, taking a barrier layer 11b with a thickness of 5nm as an example, a comparison was made between the 5nm Al0.25GaN barrier layer / GaN channel layer semiconductor structure and the 5nm in-situ SiN layer / 5nm Al0.25GaN barrier layer / GaN channel layer semiconductor structure. It was found that the sheet resistance (surface resistance) between the source 17b and drain 17c can be reduced from 2300Ω / □ to 325Ω / □, and the two-dimensional electron gas concentration in the heterojunction 11 can be reduced from 2.4E12 / cm². 2 Increased to 1.03E13 / cm2 .

[0101] Furthermore, in existing AlGaN barrier layer / GaN channel layer HEMT structures, the thickness of the barrier layer 11b needs to be 15nm to 25nm to ensure a sufficient concentration of two-dimensional electron gas. In this application, a sufficient concentration of two-dimensional electron gas can be generated when the thickness of the barrier layer 11b is in the range of 1nm to 15nm; preferably, the thickness of the barrier layer 11b can be controlled to be below 10nm.

[0102] Figure 2 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention; Figures 3 to 5 yes Figure 2 The diagram shows the intermediate structure corresponding to the process flow.

[0103] First, refer to Figure 2 Step S1 and Figure 3 As shown, a semiconductor substrate 10 is provided, and a heterojunction 11 is formed on the semiconductor substrate 10.

[0104] The semiconductor substrate 10 can be made of sapphire, silicon carbide, silicon, GaN, or diamond.

[0105] The heterojunction 11 may include a channel layer 11a and a barrier layer 11b from bottom to top. In one alternative embodiment, the channel layer 11a is an intrinsic GaN layer, and the barrier layer 11b is an n-type AlGaN layer. In other alternative embodiments, the combination of the channel layer 11a and the barrier layer 11b may also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. The formation process of the channel layer 11a and the barrier layer 11b may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0106] Apart from Figure 1The channel layer 11a and barrier layer 11b shown each have one layer; the channel layer 11a and barrier layer 11b may also have multiple layers, which are alternately distributed; or one channel layer 11a and two or more barrier layers 11b to form a multi-barrier structure.

[0107] Before forming the heterojunction 11 on the semiconductor substrate 10, a nucleation layer and a buffer layer (not shown) may be formed sequentially. The nucleation layer may be made of materials such as AlN or AlGaN, and the buffer layer may be made of at least one of AlN, GaN, AlGaN, and AlInGaN. The method for forming the buffer layer may be the same as the method for forming the heterojunction 11. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction 11, and the semiconductor substrate 10. The buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0108] test Figure 3 The sheet resistor (surface resistance) of the example structure shown has a value of 2300Ω / □.

[0109] Next, refer to Figure 2 Step S2 and Figure 4 As shown, an in-situ insulating layer 12 is formed on the heterojunction 11.

[0110] The in-situ insulating layer 12 is an insulating layer formed by an in-situ growth process. In one option, the in-situ insulating layer 12 is a single-layer structure, and the material of this single-layer structure includes one or more mixtures of SiN and AlN. In another option, the in-situ insulating layer 12 is a multilayer structure, which, from bottom to top, may include: a SiN layer and an AlN layer, an AlN layer and a SiN layer, or a SiN layer, an AlN layer and a SiN layer, etc.

[0111] Then, refer to Figure 2 Step S3 and Figure 4 As shown, a groove 13 is formed that penetrates the in-situ insulating layer 12.

[0112] The groove 13 can be formed using either dry etching or wet etching. Specifically, a patterned mask layer is first formed on the in-situ insulating layer 12. The mask layer can be a photoresist layer, and patterning is performed using a pre-exposure followed by development process. The dry etching gas can be CF4, C3F8, etc., and the wet etching solution can be hot phosphoric acid.

[0113] test Figure 4 The sheet resistor (surface resistance) of the example structure shown has a value of 325Ω / □.

[0114] Next, refer to Figure 2 Step S4 and Figure 5As shown, a transition layer 14 and a p-type semiconductor layer 15 are sequentially formed in the groove 13 and on the in-situ insulating layer 12.

[0115] The transition layer 14 can be formed using an in-situ growth process. In one alternative, the transition layer 14 is a single-layer structure, and the material of this single-layer structure may include one or more mixtures of AlN, SiAlN, and AlGaN. In another alternative, the transition layer 14 is a stacked structure, and the stacked structure may include at least two layers selected from AlN, SiAlN, and AlGaN.

[0116] The p-type semiconductor layer 15 includes a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN, wherein the p-type dopant ions can be magnesium ions. The formation process of the p-type semiconductor layer 15 can refer to the formation process of the channel layer 11a and the barrier layer 11b.

[0117] In this embodiment, the p-type semiconductor layer 15 has a recessed region at the corresponding groove 13. In some embodiments, the upper surface of the p-type semiconductor layer 15 may also be flat.

[0118] Then, refer to Figure 2 Step S5 and Figure 1 As shown, an n-type ion heavily doped layer 16 is formed on the p-type semiconductor layer 15 in the gate region and on the source and drain regions of the heterojunction 11.

[0119] The n-type ion heavily doped layer 16 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN, wherein the n-type dopant ion can be at least one of Si ions, Ge ions, Sn ions, Se ions, or Te ions. The formation process of the n-type ion heavily doped layer 16 can refer to the formation process of the channel layer 11a and the barrier layer 11b, and n-type ions can be doped while growing, or n-type ions can be implanted after epitaxial growth.

[0120] In some embodiments, an n-type ion-doped layer 16 may also be formed on the p-type semiconductor layer 15 in the gate region and on at least one of the source and drain regions of the heterojunction 11.

[0121] Next, refer to Figure 2 Step S6 and Figure 1 As shown, a gate 17a is formed on an n-type ion heavily doped layer 16 in the gate region, a source 17b is formed on an n-type ion heavily doped layer 16 in the source region, and a drain 17c is formed on an n-type ion heavily doped layer 16 in the drain region.

[0122] The source 17b, drain 17c, and gate 17a can be made of metal, such as existing conductive materials like Ti / Al / Ni / Au and Ni / Au, and are formed using physical vapor deposition or chemical vapor deposition methods.

[0123] In this embodiment, since the p-type semiconductor layer 15 has a recessed region at the corresponding groove 13, a portion of the gate 17a is located in the recessed region. In some embodiments, the upper surface of the p-type semiconductor layer 15 and the lower surface of the gate 17a may also be flat.

[0124] Figure 6 This is a schematic diagram of the semiconductor structure according to the second embodiment of the present invention.

[0125] Reference Figure 6 and Figure 1 As shown, the semiconductor structure 2 in this embodiment is largely the same as the semiconductor structure 1 in embodiment 1, except that: the source 17b and the drain 17c are in contact with the channel layer 11a, and ohmic contacts are formed between the source 17b and the channel layer 11a and between the drain 17c and the channel layer 11a using an n-type ion heavily doped layer 16.

[0126] Correspondingly, the fabrication method of semiconductor structure 2 in this embodiment is largely the same as that of semiconductor structure 1 in embodiment 1, except that: in step S5, when forming the n-type ion heavily doped layer 16 on the source and drain regions of the heterojunction 11, the p-type semiconductor layer 15, transition layer 14, in-situ insulating layer 12, and barrier layer 11b in the source and drain regions are removed, exposing the channel layer 11a. The n-type ion heavily doped layer 16 allows the source 17b and channel layer 11a, and the drain 17c and channel layer 11a to directly form ohmic contact layers without high-temperature thermal annealing.

[0127] In some embodiments, the source 17b and drain 17c contact the channel layer 11a, and an ohmic contact is formed between the source 17b and the channel layer 11a, or between the drain 17c and the channel layer 11a, using an n-type ion heavily doped layer 16. An ohmic contact layer can be formed between the channel layer 11a and the source 17b, or between the channel layer 11a and the drain 17c, without the n-type ion heavily doped layer 16, through high-temperature annealing.

[0128] Figure 7 This is a schematic diagram of the semiconductor structure according to the third embodiment of the present invention. Figure 8 This is a flowchart of a method for fabricating a semiconductor structure according to the third embodiment of the present invention.

[0129] Reference Figure 7 , Figure 1 and Figure 6As shown, the semiconductor structure 3 of this embodiment is largely the same as the semiconductor structures 1 and 2 of embodiments 1 and 2, the only difference being that: on the transition layer 14, only the gate region has a p-type semiconductor layer 15.

[0130] Correspondingly, refer to Figure 8 and Figure 2 As shown, the fabrication method of semiconductor structure 3 in this embodiment is largely the same as that of semiconductor structures 1 and 2 in embodiments 1 and 2, except that step S4' further includes a step of patterning the p-type semiconductor layer 15. In other words, step S4' includes: sequentially forming a transition layer 14 and a p-type semiconductor layer 15 in the groove 13 and on the in-situ insulating layer 12; patterning the p-type semiconductor layer 15, retaining only the p-type semiconductor layer 15 in the gate region.

[0131] The patterned p-type semiconductor layer 15 can be achieved using dry etching or wet etching. Compared to the scheme of patterning the p-type semiconductor layer 15 directly formed on the barrier layer 11b, the in-situ insulating layer 12 and the transition layer 14 can prevent over-etching damage to the barrier layer 11b during the patterning process.

[0132] Figure 9 This is a schematic diagram of the semiconductor structure according to the fourth embodiment of the present invention. (Refer to...) Figure 9 , Figure 1 , Figure 6 and Figure 7 As shown, the semiconductor structure 4 in this embodiment is largely the same as the semiconductor structures 1, 2, and 3 in embodiments 1, 2, and 3, with the only difference being that the semiconductor structure 4 is an intermediate semiconductor structure and does not have a gate 17a, a source 17b, and a drain 17c.

[0133] Correspondingly, the method for fabricating the semiconductor structure 4 in this embodiment is roughly the same as the method for fabricating the semiconductor structures 1, 2, and 3 in embodiments 1, 2, and 3, with the only difference being that step S6 is omitted.

[0134] Semiconductor structure 4 can also be used for the production and sale of semi-finished products.

[0135] Figure 10 This is a schematic diagram of the semiconductor structure according to the fifth embodiment of the present invention. Figure 11 This is a flowchart of a method for fabricating a semiconductor structure according to the fifth embodiment of the present invention. Figure 12 yes Figure 11 The diagram shows the intermediate structure corresponding to the process flow.

[0136] Reference Figure 10 As shown, semiconductor structure 5 includes:

[0137] The semiconductor substrate 10, heterojunction 11, in-situ insulating layer 12 and transition layer 14 are distributed from bottom to top;

[0138] A groove 13 penetrating the in-situ insulating layer 12 and the transition layer 14;

[0139] p-type semiconductor layer 15 located within the groove 13 and on the transition layer 14;

[0140] The p-type semiconductor layer 15 located in the gate region, and the n-type ion heavily doped layer 16 located in the source and drain regions of the heterojunction 11;

[0141] Gate 17a located on the n-type ion heavily doped layer 16 in the gate region, source 17b located on the n-type ion heavily doped layer 16 in the source region, and drain 17c located on the n-type ion heavily doped layer 16 in the drain region.

[0142] Reference Figure 10 , Figure 12 and Figure 1 As shown, the semiconductor structure 5 of this embodiment is largely the same as the semiconductor structure 1 of embodiment 1, except that the groove 13 penetrates the in-situ insulating layer 12 and the transition layer 14, that is, the transition layer 14 is located only on the in-situ insulating layer 12 outside the groove 13.

[0143] Correspondingly, refer to Figure 11 , Figure 12 and Figure 2 As shown, the fabrication method of the semiconductor structure 5 in this embodiment is largely the same as the fabrication method of the semiconductor structure 1 in embodiment 1, with the only difference being: step S2' includes: sequentially forming an in-situ insulating layer 12 and a transition layer 14 on the heterojunction 11; step S3' includes: forming a groove 13 penetrating the in-situ insulating layer 12 and the transition layer 14; step S4" includes: forming a p-type semiconductor layer 15 in the groove 13 and on the transition layer 14.

[0144] Figure 10 In this configuration, the source 17b and drain 17c are connected to the barrier layer 11b, and ohmic contacts are formed between the source 17b and the barrier layer 11b, and between the drain 17c and the barrier layer 11b, using n-type ion heavily doped layers 16. An ohmic contact is also formed between the gate 17a and the p-type semiconductor layer 15 using n-type ion heavily doped layers 16. The n-type ion heavily doped layers 16 enable the source 17b to directly form ohmic contact layers with the source region of the heterojunction 11, the drain 17c to the drain region of the heterojunction 11, and the gate 17a to the p-type semiconductor layer 15 of the gate region without high-temperature annealing.

[0145] In some embodiments, an n-type ion heavily doped layer 16 may also be provided on the p-type semiconductor layer 15 of the gate region, and on at least one of the source region and drain region of the heterojunction 11. The p-type semiconductor layer 15 and gate 17a of the gate region without the n-type ion heavily doped layer 16, the source region and source 17b of the heterojunction 11 without the n-type ion heavily doped layer 16, or the drain region and drain 17c of the heterojunction 11 without the n-type ion heavily doped layer 16 are formed into an ohmic contact layer by high-temperature annealing.

[0146] In the semiconductor structure 5 described above, the in-situ insulating layer 12 and the transition layer 14 reduce the gate leakage current formed by the channel leakage to the gate 17a. Therefore, the thickness of the barrier layer 11b in the heterojunction 11 can be smaller, thereby reducing the threshold voltage. In addition, due to the provision of the in-situ insulating layer 12, the surface resistance can be reduced and the concentration of two-dimensional electron gas can be increased, thereby improving the gate's control capability over the channel and increasing the operating current.

[0147] Furthermore, in existing AlGaN barrier layer / GaN channel layer HEMT structures, the thickness of the barrier layer 11b needs to be 15nm to 25nm to ensure a sufficient concentration of two-dimensional electron gas. In this application, a sufficient concentration of two-dimensional electron gas can be generated when the thickness of the barrier layer 11b is in the range of 1nm to 15nm; preferably, the thickness of the barrier layer 11b can be controlled to be below 10nm.

[0148] Figure 13 This is a schematic diagram of the semiconductor structure according to the sixth embodiment of the present invention.

[0149] Reference Figure 13 and Figure 10 As shown, the semiconductor structure 6 in this embodiment is largely the same as the semiconductor structure 5 in embodiment 5, except that: the source 17b and the drain 17c are in contact with the channel layer 11a, and ohmic contacts are formed between the source 17b and the channel layer 11a, and between the drain 17c and the channel layer 11a using an n-type ion heavily doped layer 16.

[0150] Correspondingly, the fabrication method of the semiconductor structure 6 in this embodiment is largely the same as that of the semiconductor structure 5 in embodiment 5, except that: in step S5, when forming the n-type ion heavily doped layer 16 on the source and drain regions of the heterojunction 11, the p-type semiconductor layer 15, transition layer 14, in-situ insulating layer 12, and barrier layer 11b in the source and drain regions are removed to expose the channel layer 11a. The n-type ion heavily doped layer 16 allows the source 17b and the channel layer 11a, and the drain 17c and the channel layer 11a to form ohmic contact layers directly without high-temperature thermal annealing.

[0151] In some embodiments, the source 17b and drain 17c contact the channel layer 11a, and an ohmic contact is formed between the source 17b and the channel layer 11a, or between the drain 17c and the channel layer 11a, using an n-type ion heavily doped layer 16. An ohmic contact layer can be formed between the channel layer 11a and the source 17b, or between the channel layer 11a and the drain 17c, without the n-type ion heavily doped layer 16, through high-temperature annealing.

[0152] Figure 14 This is a schematic diagram of the semiconductor structure according to the seventh embodiment of the present invention.

[0153] Reference Figure 14 , Figure 10 and Figure 13 As shown, the semiconductor structure 7 of this embodiment is largely the same as the semiconductor structures 5 and 6 of embodiments 5 and 6, the only difference being that: on the transition layer 14, only the gate region has a p-type semiconductor layer 15.

[0154] Correspondingly, the fabrication method of the semiconductor structure 7 in this embodiment is largely the same as the fabrication methods of the semiconductor structures 5 and 6 in embodiments 5 and 6, with the only difference being that step S4" further includes the step of patterning the p-type semiconductor layer 15. In other words, step S4" includes: forming the p-type semiconductor layer 15 in the groove 13 and on the transition layer 14; patterning the p-type semiconductor layer 15, retaining only the p-type semiconductor layer 15 in the gate region.

[0155] The patterned p-type semiconductor layer 15 can be achieved using dry etching or wet etching. Compared to the scheme of patterning the p-type semiconductor layer 15 directly formed on the barrier layer 11b, the in-situ insulating layer 12 and the transition layer 14 can prevent over-etching damage to the barrier layer 11b during the patterning process.

[0156] Figure 15 This is a schematic diagram of the semiconductor structure according to the eighth embodiment of the present invention. (Refer to...) Figure 15 , Figure 10 , Figure 13 and Figure 14 As shown, the semiconductor structure 8 in this embodiment 8 is largely the same as the semiconductor structures 5, 6, and 7 in embodiments 5, 6, and 7, with the only difference being that the semiconductor structure 8 is an intermediate semiconductor structure and does not have a gate 17a, a source 17b, and a drain 17c.

[0157] Correspondingly, the method for fabricating the semiconductor structure 8 in this embodiment is roughly the same as the method for fabricating the semiconductor structures 5, 6, and 7 in embodiments 5, 6, and 7, with the only difference being that step S6 is omitted.

[0158] Semiconductor structure 8 can also be produced and sold as a semi-finished product.

[0159] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The semiconductor substrate (10), heterojunction (11), and in-situ insulating layer (12) are distributed from bottom to top; A groove (13) penetrating the in-situ insulating layer (12); At least a transition layer (14) located on the in-situ insulating layer (12); A p-type semiconductor layer (15) located within the groove (13) and on the transition layer (14) in the gate region; The p-type semiconductor layer (15) located on the gate region, the source region of the heterojunction (11), and the drain region of the heterojunction (11) are heavily doped with n-type ions. The transition layer (14) is used to prevent atoms in the in-situ insulating layer (12) from diffusing into the p-type semiconductor layer (15).

2. The semiconductor structure according to claim 1, characterized in that, The transition layer (14) is also located within the groove (13).

3. The semiconductor structure according to claim 1, characterized in that, The non-gate region on the transition layer (14) also has the p-type semiconductor layer (15).

4. The semiconductor structure according to claim 1, characterized in that, The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top.

5. The semiconductor structure according to claim 4, characterized in that, The n-type ion-doped layer (16) contacts the channel layer (11a) or the barrier layer (11b).

6. The semiconductor structure according to claim 1, characterized in that, The in-situ insulating layer (12) is a single-layer structure, and the material of the single-layer structure includes one or more of SiN and AlN; or the in-situ insulating layer (12) is a multilayer structure, and the multilayer structure includes, from bottom to top: SiN layer and AlN layer, AlN layer and SiN layer, or SiN layer, AlN layer and SiN layer. And / or the transition layer (14) is a single-layer structure, the material of which includes one or a mixture of AlN, SiAlN, and AlGaN; or the transition layer (14) is a stacked structure, the stacked structure including at least two layers of AlN, SiAlN, and AlGaN.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a gate (17a) on the n-type ion heavily doped layer (16) in the gate region, a source (17b) on the n-type ion heavily doped layer (16) in the source region, and a drain (17c) on the n-type ion heavily doped layer (16) in the drain region.

8. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate (10) is provided, on which a heterojunction (11) is formed; An in-situ insulating layer (12) is formed on the heterojunction (11); A groove (13) is formed that penetrates the in-situ insulating layer (12); A transition layer (14) and a p-type semiconductor layer (15) are sequentially formed in the groove (13) and on the in-situ insulating layer (12); On the p-type semiconductor layer (15) in the gate region, on the source region of the heterojunction (11), and on the drain region of the heterojunction (11), an n-type ion heavily doped layer (16) is formed. The transition layer (14) is used to prevent atoms in the in-situ insulating layer (12) from diffusing into the p-type semiconductor layer (15).

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Also includes: The p-type semiconductor layer (15) is patterned, while the p-type semiconductor layer (15) of the gate region is retained.

10. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The n-type ion-doped layer (16) contacts the channel layer (11a) or the barrier layer (11b).

12. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The in-situ insulating layer (12) is a single-layer structure, and the material of the single-layer structure includes one or more of SiN and AlN; or the in-situ insulating layer (12) is a multilayer structure, and the multilayer structure includes, from bottom to top: SiN layer and AlN layer, AlN layer and SiN layer, or SiN layer, AlN layer and SiN layer. And / or the transition layer (14) is a single-layer structure, the material of which includes one or a mixture of AlN, SiAlN, and AlGaN; or the transition layer (14) is a stacked structure, the stacked structure including at least two layers of AlN, SiAlN, and AlGaN.

13. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate (10) is provided, on which a heterojunction (11) is formed; An in-situ insulating layer (12) and a transition layer (14) are sequentially formed on the heterojunction (11); A groove (13) is formed that penetrates the in-situ insulating layer (12) and the transition layer (14); A p-type semiconductor layer (15) is formed in the groove (13) and on the transition layer (14); On the p-type semiconductor layer (15) in the gate region, on the source region of the heterojunction (11), and on the drain region of the heterojunction (11), an n-type ion heavily doped layer (16) is formed. The transition layer (14) is used to prevent atoms in the in-situ insulating layer (12) from diffusing into the p-type semiconductor layer (15).

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, Also includes: The p-type semiconductor layer (15) is patterned, while the p-type semiconductor layer (15) of the gate region is retained.

15. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top.

16. The method for fabricating a semiconductor structure according to claim 15, characterized in that, The n-type ion-doped layer (16) contacts the channel layer (11a) or the barrier layer (11b).

17. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The in-situ insulating layer (12) is a single-layer structure, and the material of the single-layer structure includes one or more of SiN and AlN; or the in-situ insulating layer (12) is a multilayer structure, and the multilayer structure includes, from bottom to top: SiN layer and AlN layer, AlN layer and SiN layer, or SiN layer, AlN layer and SiN layer. And / or the transition layer (14) is a single-layer structure, the material of which includes one or a mixture of AlN, SiAlN, and AlGaN; or the transition layer (14) is a stacked structure, the stacked structure including at least two layers of AlN, SiAlN, and AlGaN.

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