Method for manufacturing a chip package unit

Abstract

The application provides a preparation method of a chip packaging unit, comprising the following steps: providing a lead frame for pre-packaging a periphery of a base island and an inner pin section of a pin, wherein a first pin connected with the base island is insulated from other second pins; welding a chip on the base island of the lead frame; performing a ball welding test; after the ball welding test is completed and test abnormalities do not exceed a preset index, performing plasma cleaning and then encapsulating the base island and the inner pin section of the pin to obtain a semi-finished product; electroplating tin on exposed areas of the semi-finished product; packaging and forming and cutting into a single form to obtain the chip packaging unit; the chip packaging unit can be welded and tested simultaneously to monitor a ball welding process; meanwhile, the influence of subsequent cutting stress on the final product is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a chip packaging unit. Background Technology

[0002] A traditional semiconductor packaging unit includes: a lead frame 10', a chip 101', and metal wires (102', 103'), such as Figure 1 As shown, in the fabrication of a semiconductor packaging unit, the lead frame comprises multiple identical and interconnected basic units. Each basic unit includes a base island 2', a pin 3', and a connecting rib 4'. During the fabrication process, the lead frame utilizes stamping or etching methods to ultimately retain the functional areas required by the product. The base island 2' and pin 3' extend from different areas of the same lead frame and are separated from each other by gaps to form different functional partitions. Silver is then plated in the areas requiring ball bonding. During the packaging process, chip scribing, die mounting, and ball bonding are performed to connect one electrode on the bottom surface of the chip to the base island. The chip surface is connected to the pin via metal wires. After encapsulation, electroplating, and shaping or cutting, an independent single semiconductor packaging unit is finally formed. Finally, testing separates good and defective products.

[0003] Traditional semiconductor packaging and testing processes mainly include the following steps:

[0004] S1. The lead frame manufacturing process completes the lead frame shape required for the product, forming several base islands and pin integration;

[0005] S2. After the packaging and testing plant processes the incoming wafers into individual chips, the individual chips are bonded to the lead frame base islands with solder to perform die assembly. One electrode of the chip (such as the drain electrode of a common MOS chip) is transferred to the base islands of the lead frame through solder to be amplified to the extended area.

[0006] S3. The polarity of the chip's upper surface (such as the G and S poles of a common MOS chip) is connected to the pins of the lead frame via ball bonding, thereby expanding the functional area of ​​the polarity to the extended area through the pins.

[0007] S4. After assembly, the lead frame, chip, solder, and metal wire are encapsulated by a molding compound to encapsulate the base island, solder, chip, and pins in each basic unit of the entire lead frame to prevent oxidation.

[0008] S5. The base island extension and pin extension outside the molding compound, as solder contact points for the terminal circuit board assembly, need to be tin-plated to obtain stable solderability.

[0009] S6. The packaging form is formed and cut into individual pieces;

[0010] S7. Each product undergoes full electrical performance testing on a testing machine, and good and defective products are separated. Good products are shipped to the circuit board assembly plant for use on the board, while defective products are analyzed by the packaging plant to determine which process caused the defect.

[0011] Traditional processes show that by the time testing begins, 80% of the product is already assembled. Numerous anomalies can arise during assembly, some explicit and others implicit. In summary, traditional semiconductor packaging testing has the following drawbacks:

[0012] 1. In the chip packaging stage, the unit functions of the product are connected together by the lead frame, and the independent functions of the product cannot be realized yet.

[0013] 2. It is impossible to perform electrical performance testing on the product during the packaging stage;

[0014] 3. Traditional packaging and testing methods cannot accurately determine the cause of defects and the process to which they belong. The accumulation of process problems makes it difficult to find the cause of defects.

[0015] In view of this, it is necessary to provide a new method for fabricating chip packaging units to solve the above problems. Summary of the Invention

[0016] The purpose of this invention is to provide a method for preparing a chip packaging unit.

[0017] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: a method for preparing a chip packaging unit, comprising the following steps:

[0018] A lead frame is provided, wherein a first pin connected to the base island on the lead frame is insulated from other second pins;

[0019] The chip is soldered onto the base island of the lead frame;

[0020] Ball welding tests were performed simultaneously with welding.

[0021] After the ball bonding test is completed and the test abnormalities do not exceed the preset index, plasma cleaning is performed and the base island and the inner pin section of the pin are encapsulated to obtain a semi-finished product.

[0022] The exposed areas of the semi-finished product are electroplated with tin;

[0023] The chips are packaged, shaped, and cut into individual units to obtain chip packaging units;

[0024] Electrical performance tests were performed on the chip packaging unit.

[0025] As a further improved technical solution of the present invention, "performing ball welding test while welding" specifically includes the following steps:

[0026] The lead frame with the chip is placed on the ball bonding test device, so that one test probe contacts the outer pin segment of the second pin or the connecting rib of the outer pin segment connecting multiple second pins, and another test probe contacts the heat sink located on the side of the base island away from the pin, and the test probe is turned on at the same time.

[0027] Solder the two ends of the first wire to the G electrode bonding pad on the chip and the inner pin segment of the second pin corresponding to the G electrode, respectively.

[0028] After soldering one end of the second wire to the S-polar bonding pad on the chip, test it.

[0029] After soldering the other end of the second wire to the inner pin segment of the second pin corresponding to the S pole, test it.

[0030] After soldering the two ends of the third wire to the S-type bonding pad on the chip and the inner pin segment of the second pin corresponding to the S-type, test it.

[0031] The welding and testing process with the third conductor continues, as well as the welding and testing of other conductors on the S-pole bonding area and the inner pin segment of the second pin corresponding to the S-pole on the electrical connection chip.

[0032] After testing, an accumulated number of test anomalies will be recorded. If the number of anomalies exceeds the preset threshold, the ball welding machine will alarm and stop.

[0033] As a further improvement of the present invention, the "cumulative test anomaly" specifically means that the test anomaly is fed back to the ball welding machine and recorded on the electronic map.

[0034] As a further improvement of the present invention, the preset index is the PPM index.

[0035] As a further improvement of the present invention, "electroplated tin on the exposed area of ​​the semi-finished product" specifically includes the following steps:

[0036] The exposed areas of the heatsink and the first pin are simultaneously electroplated with tin;

[0037] The exposed areas of the second pins spaced apart from the base island and the connecting ribs of the outer pin segments connecting multiple second pins are simultaneously electroplated with tin.

[0038] As a further improvement of the present invention, the thickness of the electroplated layer formed on the second pin and the connecting rib is between 8μm and 20μm.

[0039] As a further improvement of the present invention, "providing a lead frame" includes the following steps: pre-encapsulating the periphery of the base island and the inner pin segment of the pin together.

[0040] As a further improvement of the present invention, "providing a lead frame" specifically includes the following steps:

[0041] A basic frame with a lead frame shape is formed;

[0042] Multiple sub-units are formed on the basic frame. Each sub-unit has a heat sink, a base island, a first pin connected to the base island, a connecting rib, and at least two second pins spaced apart from the base island.

[0043] The periphery of the base island, the inner pin segment of the first pin, and the inner pin segment of the second pin are pre-encapsulated together, with the inner pin segment of the second pin exposed.

[0044] Plastic stamping removes the connecting ribs between the first and second pins, as well as the end of the first pin furthest from the base island.

[0045] Cleaning;

[0046] After cleaning, the inner pin section of the second pin is electroplated.

[0047] As a further improved technical solution of the present invention, the front side of the first package body, which pre-encapsulates the periphery of the base island, the inner pin segment of the first pin, and the inner pin segment of the second pin together, is coplanar with the front side of the base island, and the back side of the first package body is coplanar with the back side of the heat sink.

[0048] As a further improvement of the present invention, the thickness of the electroplated layer formed after "electroplating the inner pin segment of the second pin" is between 2μm and 8μm.

[0049] The beneficial effects of this invention are as follows: In the lead frame of this invention, the first pin and the second pin are insulated from each other. At the same time, a first package is provided at one end of the base island near the pin and at one end of the plurality of pins near the base island. This facilitates simultaneous soldering and testing on the lead frame with the chip, enabling monitoring of the ball soldering process, timely detection of abnormalities in the ball soldering process, and early implementation of process control measures. In addition, the process of cutting the connecting ribs connecting the first pin and the second pin, as well as the connecting ribs at the end of the first pin away from the base island, is moved forward to the lead frame factory, reducing the impact of subsequent rib cutting stress on the final product. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the lead frame structure in the prior art.

[0051] Figures 2-11 This is a step diagram illustrating the fabrication method of the chip packaging unit in this invention.

[0052] Figure 12This is a schematic diagram of the ball welding test device in this invention. Detailed Implementation

[0053] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. Please refer to the accompanying drawings for further details. Figures 1 to 12 The figures shown represent preferred embodiments of the present invention. However, it should be noted that these embodiments are not intended to limit the present invention. Equivalent modifications or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0054] Please refer to Figures 2-11 As shown, the present invention also provides a method for fabricating a chip packaging unit 40, comprising the following steps:

[0055] A1: As Figures 2-5 As shown, a lead frame 10 is provided, wherein the first pin 3 connected to the base island 1 on the lead frame 10 is insulated from other second pins 4;

[0056] A2: As Figure 6 As shown, chip 30 is soldered onto the base island 1 of the lead frame 10 described above;

[0057] A3: As Figure 7 As shown, ball welding tests were performed while welding was being carried out;

[0058] A4: As Figure 8 As shown, after the ball bonding test is completed and the test abnormality does not exceed the preset index, plasma cleaning is performed and the base island 1 and the inner pin section of the pin are encapsulated to obtain a semi-finished product.

[0059] A5: As Figures 9-10 As shown, the exposed areas of the semi-finished product are electroplated with tin;

[0060] A6: As Figure 11 As shown, the chip is packaged and cut into individual pieces to obtain chip packaging unit 40;

[0061] A7: Perform electrical performance testing on chip packaging unit 40.

[0062] Specifically, please refer to Figure 5As shown, the lead frame 10 obtained in step A1 includes at least one encapsulation unit. Each encapsulation unit includes a base island 1, a plurality of pins arranged side-by-side and spaced apart on one side of the base island 1, and a heat sink 2 extending from the back of the base island 1 away from the pins. The plurality of pins includes a first pin 3 connected to the base island 1 and at least two second pins 4 spaced apart from the base island 1. The lead frame 10 also includes connecting ribs 5 connecting the outer pin segments of the at least two second pins 4, and a first encapsulation body 6 for encapsulating the periphery of the base island 1 and the inner pin segments of the plurality of pins. The first encapsulation body 6 has a spacer for the inner pin segments of the second pins 4 to... The exposed window, namely the first package 6 which encapsulates the periphery of the base island 1 and the inner pin segment of the plurality of pins, can fix and insulate the second pin 4 to the base island 1. Simultaneously, the first pin 3 and the second pin 4 are mutually insulated, facilitating simultaneous soldering and testing on the lead frame 10 with the chip 30. This allows for monitoring of the ball soldering process, timely detection of abnormalities, and early implementation of process control measures. Furthermore, by moving the process of cutting the connecting ribs between the first pin 3 and the second pin 4, as well as the connecting rib at the end of the first pin 3 furthest from the base island 1, to the lead frame factory, the impact of subsequent rib cutting stress on the final product is reduced. It is understood that the inner pin segment refers to the portion of the structure where a pin is located inside the first package 6, and the outer pin segment refers to the portion of the structure where a pin is located outside the first package 6.

[0063] It is understood that the first package 6 can fix the second pin 4 and at the same time insulate the second pin 4 from the base island 1.

[0064] Of course, this is not a limitation. It is understood that the lead frame 10 may not include the first package 6, and the second pin 4, which is insulated from the first pin 3, may be fixed and insulated from the base island by means of a film.

[0065] In one specific embodiment, the plurality of pins includes a first pin 3 connected to the base island 1, and two second pins 4 disposed on opposite sides of the first pin 3 and insulated from each other. Of course, this is not a limitation, and the number and relative position of the first pin 3 and the second pins 4 can be adjusted according to the specific requirements of the final chip packaging unit.

[0066] Furthermore, the first package 6 includes a first package segment located on the base island 1 near one end of the pin, and two second package segments extending from the opposite ends of the first package segment in a direction away from the pin. The two second package segments are respectively packaged on opposite sides of the base island 1, increasing the contact area between the first package 6 and the base island 1, enhancing their connection strength, and thereby enhancing the fixing strength of the second pin 4.

[0067] In one specific embodiment, the front side of the first package 6 is coplanar with the front side of the base island 1, and the back side of the first package 6 is coplanar with the back side of the heat sink 2. Increasing the thickness of the first package 6 can increase the strength of the first package 6, making it less prone to breakage, and at the same time, enhance the insulation effect.

[0068] Furthermore, the inner pin segment of the second pin 4 has a first electroplated layer 7, the thickness of which is between 2μm and 8μm, so as to facilitate the subsequent electrical connection between the second pin 4 and the chip 30 by ball bonding the end of the wire.

[0069] Further, please refer to Figures 2-5 As shown, step A1 includes the following steps:

[0070] A11: As Figure 2 As shown, a base frame with a lead frame shape is formed, and multiple sub-units are formed on the base frame. Each sub-unit has a heat sink 2, a base island 1, a first pin 3 connected to the base island 1, a connecting rib, and at least two second pins 4 spaced apart from the base island 1.

[0071] A12: As Figure 3 As shown, the periphery of the base island 1, the inner pin segment of the first pin 3, and the inner pin segment of the second pin 4 are pre-encapsulated together, and the inner pin segment of the second pin 4 is exposed.

[0072] A13: As Figure 4 As shown, the connecting ribs between the first pin 3 and the second pin 4, as well as the end of the first pin 3 away from the base island 1, are removed by stamping.

[0073] A14: Cleaning;

[0074] A15: As Figure 5 As shown, the inner pin section of the second pin 4 is electroplated after cleaning.

[0075] In step A12, the periphery of the base island 1 and the inner pin segment of the pin are pre-encapsulated together to achieve an insulating connection between the base island 1 and the second pin 4, as well as between the first pin 3 and the second pin 4. Thus, after the connecting rib is removed in the subsequent step A13, the second pin 4 can also be fixed together with the base island 1.

[0076] The first package 6 is defined as the pre-encapsulated part of the periphery of the base island 1, the inner pin segment of the first pin 3, and the inner pin segment of the second pin 4. The first package 6 has the functions of fixing and insulating, and can fix and insulate the second pin 4 from the base island 1. At the same time, the first pin 3 and the second pin 4 are mutually insulated, which facilitates testing while soldering on the lead frame 10 with chip 30.

[0077] Specifically, the front side of the first package 6 is coplanar with the front side of the base island 1, and the back side of the first package 6 is coplanar with the back side of the heat sink 2. Increasing the thickness of the first package 6 can increase the strength of the first package 6, making it less prone to breakage, and at the same time, enhance the insulation effect.

[0078] It is understood that the first package 6 can fix the second pin 4, thereby preventing the second pin 4 from detaching from the base island 1 after the connecting rib between the first pin 3 and the second pin 4 is removed by stamping in step A13.

[0079] In step A13, the connecting ribs between the first pin 3 and the second pin 4, as well as the end of the first pin 3 furthest from the base island 1, are removed by stamping. This insulates the first pin 3 and the second pin 4 from each other, facilitating subsequent solder ball testing. At this point, the remaining connecting ribs 5 are only connected to the second pin 4.

[0080] Furthermore, in step A15, the electroplated layer formed after “electroplated the inner pin segment of the second pin 4” is the first electroplated layer 7 mentioned above, and its thickness is between 2μm and 8μm.

[0081] Further, step A3 specifically involves placing the lead frame 10 with the chip 30 on the ball bonding test device 20, and then performing testing while bonding.

[0082] Specifically, the ball bonding test device 20 is used to perform tests during the ball bonding process of the lead frame 10 with chip 30. It can monitor the ball bonding process, detect abnormalities in the ball bonding process in a timely manner, and take process control measures as early as possible. At the same time, it avoids the interference of multiple process problems superimposed when troubleshooting packaging test abnormalities after the chip packaging unit is completed.

[0083] Please refer to Figure 12As shown, the ball bonding test apparatus 20 includes an infeed device 201 for placing the lead frame 10 with chip 30 to be tested, a ball bonding track 202 connected to the outlet of the infeed device 201, a ball bonding device 203 disposed in the ball bonding area of ​​the ball bonding track 202, a detection device 204 disposed in the ball bonding area to obtain the bonding position during bonding, a test probe 205 located in the ball bonding area and insulated from the ball bonding track 202, an outlet device 206 connected to the outlet end of the ball bonding track 202, and a control system 207. The infeed device 201, ball bonding track 202, ball bonding device 203, detection device 204, test probe 205, and outlet device 206 are all communicatively connected to the control system 207.

[0084] The control system 207 can be a computer, but is not limited to that.

[0085] Furthermore, the ball welding track 202 includes a track body and a clamping device 208 disposed on the track body. The clamping device 208 is used to position the lead frame 10 on the track body, which can improve the accuracy of subsequent ball welding.

[0086] It is understood that the ball-bonding track 202 in the ball-bonding area is insulated from other parts of the ball-bonding track 202, so that after the lead frame 10 is located in the ball-bonding area, the lead frame 10 is insulated from other parts of the ball-bonding track 202, enabling ball-bonding processes and testing.

[0087] Specifically, the ball-welding track 202 further includes a fixing plate disposed on one side of the track body and insulated from the track body. The test probe 205 is movably connected to the fixing plate in the vertical direction. Thus, when the test probe 205 moves upward, the distance between it and the track body can be increased, allowing the lead frame 10 to enter between the test probe 205 and the track body, facilitating the adjustment of the position of the test probe 205 on the lead frame 10. When the test probe 205 moves downward, it can contact the preset position of the lead frame 10, facilitating subsequent testing.

[0088] Furthermore, there are two test probes 205. During testing, one of the two test probes 205 contacts the outer pin segment of the second pin 4 or the connecting rib 5 connecting the outer pin segment of the second pin 4, and the other contacts the heat sink 2 located on the side of the base island 1 away from the pin.

[0089] In one specific embodiment, the two test probes 205 are arranged at intervals along the traveling direction of the ball welding track 202. Of course, this is not a limitation, and the two test probes 205 can also be arranged at intervals along the vertical direction.

[0090] Furthermore, the ball welding track 202 also includes a ball welding pressure plate heating block 209 disposed on the track body to assist the ball welding process during ball welding.

[0091] Furthermore, the "testing while welding" step A3 above specifically includes the following steps:

[0092] A31: Place the lead frame 10 with chip 30 on the ball bonding test device 20, so that one test probe 205 contacts the outer pin segment of the connecting rib 5 or the second pin 4, and the other test probe 205 contacts the heat sink 2 located on the side of the base island 1 away from the pin, and turn on the test probe 205 at the same time.

[0093] A32: Solder the two ends of the first wire to the G electrode bonding area on the chip 30 and the inner pin segment of the second pin 4 corresponding to the G electrode, respectively;

[0094] A33: Test after soldering one end of the second wire to the S-polarity bonding area on chip 30;

[0095] A34: After soldering the other end of the second wire to the inner pin segment of the second pin 4 corresponding to the S pole, test it;

[0096] A35: Solder the two ends of the third wire to the S-pole bonding pad on chip 30 and the inner pin segment of the second pin 4 corresponding to the S-pole, and then test.

[0097] A36: The welding and testing process with the third conductor continues, and the welding and testing of the S-polar bonding area on the electrical connection chip 30 and the other conductors of the inner pin segment of the second pin 4 corresponding to the S-polarity are carried out.

[0098] After testing, an accumulated number of test anomalies will be recorded. If the number of anomalies exceeds the preset threshold, the ball welding machine will alarm and stop.

[0099] It is understandable that there is only one wire between the second pin 4 corresponding to the G terminal and the chip 30, namely the first wire. Therefore, the first wire is connected first. After soldering one end of the second wire to the S terminal bonding pad on the chip 30 to form an electrical circuit, a test is performed to confirm the quality of the solder joint of the first wire and the solder joint connecting the second wire to the S terminal bonding pad on the chip 30.

[0100] In step A34, after soldering the other end of the second wire to the inner pin segment of the second pin 4 corresponding to the S pole, a test is performed. At this time, both ends of the second wire are soldered, and the quality of the solder joint between the second wire and the inner pin segment of the second pin 4 corresponding to the S pole can be confirmed.

[0101] In step A35, after both ends of the third wire are soldered, a test is performed to check the connection of the third wire. If an abnormality occurs, the electrical data can be used to preliminarily determine which solder joint is the problem. For example, if "short" appears, it means that the solder joint connecting the third wire and the chip 30 is abnormal.

[0102] In this embodiment, there are three wires that are electrically connected to the S-polar bonding area on the chip 30 and the inner pin segment of the second pin 4 corresponding to the S-polar, namely the second wire, the third wire, and the fourth wire. In step S6, after both ends of the fourth wire are soldered, a test is performed to test the connection of the fourth wire. If an abnormality occurs, it is possible to preliminarily determine which solder joint is the problem through electrical data. For example, if "short" appears, it means that the solder joint connecting the fourth wire and the chip 30 is abnormal.

[0103] Furthermore, "cumulative test anomalies" specifically refers to: reporting test anomalies to the ball welding machine and recording them on the electronic map.

[0104] Specifically, the preset index is the PPM defect index, which can also be used as one of the acceptance indicators for the ball welding test device 20.

[0105] The ball bonding test method in this invention performs the test during the ball bonding process, which can monitor the ball bonding process, detect abnormalities in the ball bonding process in a timely manner, and take process control measures as early as possible. At the same time, it avoids the interference of multiple process problems superimposed when troubleshooting packaging test abnormalities after the completion of chip packaging unit 40 in traditional methods.

[0106] Specifically, in step A4, CEL-9220 material cakes are used for encapsulation.

[0107] Furthermore, step A5 specifically includes the following steps:

[0108] The exposed areas of the first pin 3 and the heat sink 2 are simultaneously electroplated with tin;

[0109] The exposed areas of the second pin 4 and the connecting rib 5 are simultaneously electroplated with tin.

[0110] It is understood that the first pin 3 is electrically connected to the base island 1, and the heat sink 2 is electrically connected to the base island 1. Thus, the first pin 3 is electrically connected to the heat sink 2. The second pin 4 and the connecting rib 5 are mutually insulated from the base island 1 and the first pin 3. Therefore, it is necessary to perform tin plating in steps.

[0111] Meanwhile, in the tin plating step, the exposed areas of the first pin 3 and the heat sink 2 can be tin-plated simultaneously first, and then the exposed areas of the second pin 4 and the connecting rib 5 can be tin-plated simultaneously; or the exposed areas of the second pin 4 and the connecting rib 5 can be tin-plated simultaneously first, and then the exposed areas of the first pin 3 and the heat sink 2 can be tin-plated simultaneously.

[0112] Specifically, the thickness of the electroplated layer formed after electroplating the exposed areas of the second pin 4 and the connecting rib 5 is between 8μm and 20μm.

[0113] Furthermore, the electrical performance tests in step A7 include, but are not limited to, heat dissipation, resistance, withstand voltage, thermal resistance, open circuit, and short circuit. Appropriate electrical performance tests can be selected based on the specific requirements of chip 30.

[0114] Compared with the prior art, the chip packaging unit preparation method of the present invention can perform testing during the ball bonding process, monitor the ball bonding process, detect abnormalities in the ball bonding process in a timely manner, and take process control measures as early as possible. At the same time, it avoids the interference of multiple process problems superimposed when troubleshooting the cause of packaging test abnormalities after the completion of the chip packaging unit 40 in the traditional method.

[0115] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0116] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a chip packaging unit, characterized in that: The preparation method includes the following steps: A lead frame is provided, wherein a first pin connected to the base island on the lead frame is insulated from other second pins; The chip is soldered onto the base island of the lead frame; Ball welding tests were performed simultaneously with welding. After the ball bonding test is completed and the test abnormalities do not exceed the preset index, plasma cleaning is performed and the base island and the inner pin section of the pin are encapsulated to obtain a semi-finished product. The exposed areas of the semi-finished product are electroplated with tin; The chips are packaged, shaped, and cut into individual units to obtain chip packaging units; Perform electrical performance testing on the chip packaging unit; The "providing a lead frame" specifically includes the following steps: A basic frame with a lead frame shape is formed; Multiple sub-units are formed on the basic frame. Each sub-unit has a heat sink, a base island, a first pin connected to the base island, a connecting rib, and at least two second pins spaced apart from the base island. The periphery of the base island, the inner pin segment of the first pin, and the inner pin segment of the second pin are pre-encapsulated together, with the inner pin segment of the second pin exposed. Plastic stamping removes the connecting ribs between the first and second pins, as well as the end of the first pin furthest from the base island. Electroplating is performed on the inner pin section of the second pin.

2. The method for fabricating a chip packaging unit as described in claim 1, characterized in that: "Performing ball welding tests while welding" specifically includes the following steps: The lead frame with the chip is placed on the ball bonding test device, so that one test probe contacts the outer pin segment of the second pin or the connecting rib of the outer pin segment connecting multiple second pins, and another test probe contacts the heat sink located on the side of the base island away from the pin, and the test probe is turned on at the same time. Solder the two ends of the first wire to the G electrode bonding pad on the chip and the inner pin segment of the second pin corresponding to the G electrode, respectively. After soldering one end of the second wire to the S-polar bonding pad on the chip, test it. After soldering the other end of the second wire to the inner pin segment of the second pin corresponding to the S pole, test it. After soldering the two ends of the third wire to the S-type bonding pad on the chip and the inner pin segment of the second pin corresponding to the S-type, test it. The welding and testing process with the third conductor continues, as well as the welding and testing of other conductors on the S-pole bonding area and the inner pin segment of the second pin corresponding to the S-pole on the electrical connection chip. After testing, an accumulated number of test anomalies will be recorded. If the number of anomalies exceeds the preset threshold, the ball welding machine will alarm and stop.

3. The method for fabricating a chip packaging unit as described in claim 2, characterized in that: "Cumulative test anomalies" specifically refers to: reporting test anomalies to the ball welding machine and recording them on the electronic map.

4. The method for fabricating a chip packaging unit as described in claim 2, characterized in that: The preset indicator is the PPM indicator.

5. The method for fabricating a chip packaging unit as described in claim 1, characterized in that: "Electroplated tin on the exposed areas of the semi-finished product" specifically includes the following steps: The exposed areas of the heatsink and the first pin are simultaneously electroplated with tin; The exposed areas of the second pins spaced apart from the base island and the connecting ribs of the outer pin segments connecting multiple second pins are simultaneously electroplated with tin.

6. The method for fabricating a chip packaging unit as described in claim 5, characterized in that: The thickness of the second electroplated layer on the second pin and the connecting rib is between 8μm and 20μm.

7. The method for fabricating a chip packaging unit as described in claim 1, characterized in that: The front side of the first package, which pre-encapsulates the periphery of the base island, the inner pin segment of the first pin, and the inner pin segment of the second pin, is coplanar with the front side of the base island, and the back side of the first package is coplanar with the back side of the heat sink.

8. The method for fabricating a chip packaging unit as described in claim 1, characterized in that: The thickness of the electroplated layer formed after "electroplating the inner pin section of the second pin" is between 2μm and 8μm.

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