Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, the substrate having formed thereon a channel structure comprising one or more stacked channel layers, each channel layer comprising a first sacrificial layer and a channel layer on the first sacrificial layer, and a dummy gate structure across the channel structure, the dummy gate structure covering part of the sidewalls and part of the top of the channel structure, the substrate comprising a first device region and a second device region adjacent to each other; forming isolation sidewalls standing on the substrate between adjacent channel structures at the interface between the first device region and the second device region on both sides of the dummy gate structure; and forming source / drain doping layers in the channel structures on both sides of the dummy gate structure after forming the isolation sidewalls, the source / drain doping layers adjacent to each other at the interface between the first device region and the second device region being separated by the isolation sidewalls. Subsequent gate structures surround each surface of the channel layers, increasing the area of the channel layers used as channels.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor manufacturing processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as gate-all-around (GAA) transistors and forksheet transistors. Forksheet transistors, in particular, can reduce the overall cell area; however, their performance still needs improvement. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including an adjacent first device region and a second device region; a channel layer structure suspended above the substrate along the normal direction of the substrate surface, the channel layer structure including one or more spaced channel layers; a gate structure located on the substrate and spanning the channel layer structure, the gate structure including a gate dielectric layer surrounding the channel layer along the extension direction of the gate structure and a gate electrode layer located on the gate dielectric layer; source / drain doped layers located on the substrate on both sides of the gate structure, the source / drain doped layers contacting the ends of the channel layer structure; and isolation sidewalls located on both sides of the gate structure and protruding on the substrate between adjacent source / drain doped layers at the boundary between the first and second device regions.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a channel structure is formed on the substrate, the channel structure including one or more stacked channel layers along the normal direction of the substrate surface, the channel layer including a first sacrificial layer and a channel layer located on the first sacrificial layer, and a pseudo-gate structure spanning the channel structure is also formed on the substrate, the pseudo-gate structure covering part of the sidewalls and part of the top of the channel structure, and the substrate including an adjacent first device region and a second device region in a direction perpendicular to the extension direction of the channel structure; at the junction of the first device region and the second device region, on both sides of the pseudo-gate structure, an isolation sidewall protruding on the substrate is formed between adjacent channel structures; after forming the isolation sidewall, source and drain doped layers are formed in the channel structures on both sides of the pseudo-gate structure, and adjacent source and drain doped layers near the junction of the first device region and the second device region are isolated from each other by the isolation sidewall.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] The semiconductor structure provided in this embodiment of the invention includes isolation sidewalls located on both sides of the gate structure and protruding from the substrate between adjacent source / drain doped layers at the boundary between the first and second device regions. As the feature size of integrated circuits continues to decrease, adjacent devices become increasingly closer. In this embodiment, the isolation sidewalls isolate the source / drain doped layers of the first and second device regions, thereby ensuring good isolation of adjacent devices while bringing the source / drain doped layers of the adjacent first and second device regions as close as possible. This helps to reduce the distance between adjacent channel layer structures of the first and second device regions, resulting in a more compact and smaller device. Furthermore, the isolation sidewalls are located only between adjacent source / drain doped layers at the boundary between the first and second device regions, and not between adjacent channel layer structures below the gate structure. This allows the channel layer sidewalls at the boundary between the first and second device regions to be covered by the gate structure, enabling the gate structure to surround and cover all surfaces of the channel layer. This increases the area used as a channel in the channel layer while forming a smaller device, thereby increasing the operating current of the semiconductor structure and improving its performance.

[0009] In the formation method provided by this embodiment of the invention, at the junction of the first device region and the second device region, on both sides of the dummy gate structure, an isolation sidewall protruding from the substrate is formed between adjacent channel structures. After forming the isolation sidewall, source and drain doped layers are formed in the channel structures on both sides of the dummy gate structure. Adjacent source and drain doped layers near the junction of the first device region and the second device region are isolated by the isolation sidewall. As the feature size of integrated circuits continues to decrease, adjacent devices become closer and closer. In this embodiment of the invention, isolation sidewalls are used to isolate the source and drain doped layers of the first device region and the second device region, thereby ensuring a good isolation effect for adjacent devices while making the source and drain doped layers of adjacent first device regions and second device regions as close as possible, which is beneficial to reducing the impact of the isolation effect. The distance between adjacent channel structures in the first and second device regions is described to form a more compact and smaller device. Typically, the dummy gate structure and the first sacrificial layer are subsequently removed to form a gate structure covering the channel layer. In this embodiment, the isolation sidewalls are formed only between adjacent source / drain doped layers at the boundary between the first and second device regions, and not between adjacent channel structures below the dummy gate structure. This allows the channel layer sidewalls at the boundary between the first and second device regions to be covered by the gate structure, enabling the gate structure to surround and cover all surfaces of the channel layer. This increases the area used as a channel in the channel layer while forming a smaller device, thereby increasing the operating current of the semiconductor structure and improving its performance. Attached Figure Description

[0010] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figures 5 to 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 8 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0014] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] Reference Figures 1 to 3 ,in, Figure 1 It is a 3D image. Figure 2 for Figure 1 Cross-sectional view based on the AA direction, Figure 3 for Figure 1 A cross-sectional view based on the BB direction is provided, on which a channel structure 20 is formed, the channel structure 20 including one or more channel stacks 21, wherein the channel stack 21 includes a sacrificial layer 22 and a channel layer 23 located on the sacrificial layer 22, the substrate including an adjacent first device region 10N and a second device region 10P, at the junction of the first device region 10N and the second device region 10P, an isolation sidewall 41 protruding on the substrate 10 is formed between adjacent channel structures 20, the isolation sidewall 41 covers the opposite sidewall of the channel structure 20, and the isolation sidewall 41 also extends along the extension direction of the channel structure 20 to the substrate 10 on both sides of the pseudo gate structure 61.

[0016] Continue to refer to Figures 1 to 3 A pseudo-gate structure 61 is formed on the substrate 10, spanning the channel structure 20 and the isolation sidewall 41. The pseudo-gate structure 61 covers part of the sidewall of the channel structure 20 and part of the top of the channel structure 20 and the isolation sidewall 41. Source and drain doped layers 50 are formed in the channel structures 20 on both sides of the pseudo-gate structure 61.

[0017] refer to Figure 4 , Figure 4 For based on Figure 3 A cross-sectional view is shown, in which the dummy gate structure 61 is removed to expose the sacrificial layer 22; the exposed sacrificial layer 22 is removed; after removing the exposed sacrificial layer 22, a metal gate structure 60 is formed at the location of the dummy gate structure 40 and the sacrificial layer 22, covering the top, bottom and part of the sidewalls of the channel layer 23.

[0018] Currently, to reduce the spacing between adjacent channel structures 20 at the boundary between the first device region 10N and the second device region 10P, an isolation sidewall 41 is formed at the boundary between the first device region 10N and the second device region 10P, covering the sidewalls of the channel structure 20. This isolation sidewall 41 ensures effective isolation of adjacent devices while keeping the source / drain doped layers 50 of the adjacent first device region 10N and the second device region 10P as close as possible. For example, for a forksheet transistor, one region of the first device region 10N and the second device region 10P is used to form an NMOS transistor, and the other region is used to form a PMOS transistor. By setting the isolation sidewall 41 at the boundary between the first device region 10N and the second device region 10P, the spacing between adjacent NMOS transistors and PMOS transistors can be significantly reduced to accommodate the continuous shrinking of process nodes.

[0019] However, since the isolation sidewall 41 covers the sidewall of the channel layer 23 at the junction of the first device region 10N and the second device region 10P, after the metal gate structure 60 is formed, it is difficult for the metal gate structure 60 to completely cover the opposite sidewall of the channel layer 23. That is, under the shielding of the isolation sidewall 41, the metal gate structure 60 only covers the top and bottom of the channel layer 23 and the sidewall facing away from the isolation sidewall 41. The sidewall of the channel layer 23 that is in contact with the isolation sidewall 41 is difficult to be covered by the metal gate structure 60. Since the part of the channel layer 23 covered by the metal gate structure 60 is used as a channel, the area in the channel layer 23 used as a channel becomes smaller, which makes it difficult to increase the operating current of the semiconductor structure and improve the performance of the semiconductor structure.

[0020] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a channel structure is formed on the substrate, and along the normal direction of the substrate surface, the channel structure includes one or more stacked channel layers, the channel layer including a first sacrificial layer and a channel layer located on the first sacrificial layer; a dummy gate structure is also formed on the substrate spanning the channel structure, the dummy gate structure covering a portion of the sidewalls and a portion of the top of the channel structure; and in a direction perpendicular to the extension direction of the channel structure, the substrate includes adjacent first device regions and second device regions; at the boundary between the first device regions and the second device regions, on both sides of the dummy gate structure, an isolation sidewall protruding from the substrate is formed between adjacent channel structures; after forming the isolation sidewall, source / drain doped layers are formed in the channel structures on both sides of the dummy gate structure, and adjacent source / drain doped layers near the boundary between the first device regions and the second device regions are isolated from each other by the isolation sidewall.

[0021] In the formation method provided by this embodiment of the invention, isolation sidewalls are used to isolate the source and drain doped layers of the first device region and the second device region. This ensures good isolation between adjacent devices while bringing the source and drain doped layers of the adjacent first and second device regions as close as possible. This helps to reduce the distance between adjacent channel structures in the first and second device regions, resulting in a more compact and smaller device. Typically, the dummy gate structure and the first sacrificial layer are subsequently removed to form a gate structure covering the channel layer. In this embodiment, the isolation sidewalls are only formed between adjacent source and drain doped layers at the boundary between the first and second device regions, and not between adjacent channel structures below the dummy gate structure. This allows the channel layer sidewalls at the boundary between the first and second device regions to be covered by the gate structure, enabling the gate structure to surround and cover all surfaces of the channel layer. This increases the area used as a channel in the channel layer while forming a smaller device, thereby increasing the operating current of the semiconductor structure and improving its performance.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figures 5 to 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, wherein, Figure 5 It is a 3D image. Figure 6 for Figure 5 Cross-sectional view based on the AA direction, Figure 7 for Figure 5 Sectional view based on the BB direction.

[0024] The semiconductor structure includes: a substrate 101, the substrate 101 including an adjacent first device region 101N and a second device region 101P; a channel layer structure 201, suspended above the substrate 101 along the normal direction of the surface of the substrate 101, the channel layer structure 201 including one or more spaced channel layers 231; and a gate structure 601, located on the substrate 101 and spanning the channel layer structure 201, the gate structure 601 including a ring along the extending direction of the gate structure 601. The gate dielectric layer 621 surrounding the channel layer 231 and the gate electrode layer 641 located on the gate dielectric layer 621; the source / drain doped layer 501 located on the substrate 101 on both sides of the gate structure 601, the source / drain doped layer 501 being in contact with the end of the channel structure 201; the isolation sidewall 411 located on both sides of the gate structure 601 and protruding on the substrate 101 between adjacent source / drain doped layers 501 at the junction of the first device region 101N and the second device region 101P.

[0025] As the feature size of integrated circuits continues to shrink, adjacent devices are getting closer and closer. In this embodiment of the invention, the isolation sidewall 411 isolates the source and drain doped layers 501 of the first device region 101N and the second device region 101P. This ensures good isolation of adjacent devices while bringing the source and drain doped layers 501 of the adjacent first device region 101N and the second device region 101P as close as possible. This helps reduce the distance between the adjacent channel layer structures 201 of the first device region 101N and the second device region 101P, resulting in a more compact and smaller device. Furthermore, the isolation sidewall 411 is located only within... Between adjacent source / drain doped layers 501 at the junction of the first device region 101N and the second device region 101P, and between adjacent channel layer structures 201 not located below the gate structure 601, it is advantageous that the sidewalls of the channel layer 231 at the junction of the first device region 101N and the second device region 101P are also covered by the gate structure 601. This allows the gate structure 601 to surround and cover each surface of the channel layer 231, thereby increasing the area of ​​the channel layer 231 used as a channel while forming a smaller device, and thus increasing the operating current of the semiconductor structure, which is beneficial to improving the performance of the semiconductor structure.

[0026] The substrate 101 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes gate-all-around (GAA) transistors and forksheet transistors.

[0027] The substrate 101 includes a semiconductor substrate (not shown).

[0028] In this embodiment, the semiconductor substrate is made of silicon. In other embodiments, the semiconductor substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, or other materials. The semiconductor substrate may also be a silicon-on-insulator (SiI) semiconductor substrate or a germanium-on-insulator (CHI) semiconductor substrate, or other types of semiconductor substrates. The semiconductor substrate material may be suitable for process requirements or easy to integrate.

[0029] It should be noted that the substrate 101 may also include: fins (not shown) located on the semiconductor substrate.

[0030] In this embodiment, the substrate 101 further includes an isolation layer 111, which exposes the top surface of the fin. The isolation layer 111 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 111 is usually formed between NMOS transistors and PMOS transistors.

[0031] In this embodiment, the material of the isolation layer 111 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0032] In this embodiment, taking the semiconductor structure as a fork-type gate transistor as an example, the substrate 101 includes a first device region 101N and a second device region 101P that are adjacent to each other. The first device region 101N is used to form a first device, and the second device region 101P is used to form a second device.

[0033] In this embodiment, the first device region 101N includes an NMOS region, and the second device region 101P includes a PMOS region. The NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor, thereby forming a fork-gate transistor. In other embodiments, the first device region includes a PMOS region, and the second device region includes an NMOS region.

[0034] As device feature sizes continue to shrink, the use of fork-gate transistors allows for smaller spacing between adjacent NMOS transistors and PMOS crystals, resulting in better area miniaturization.

[0035] The channel layer structure 201 includes one or more longitudinally spaced channel layers 231, which serve as channels for a semiconductor structure. The longitudinal direction refers to the normal direction of the surface of the substrate 101.

[0036] In this embodiment, the material of the channel layer 231 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the channel layer 231 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0037] It should be noted that in this embodiment, the channel layer 231 and the substrate 101 are made of the same material. In other embodiments, the channel layer and the substrate may be made of different materials.

[0038] In this embodiment, the gate structure 601 is used to control the opening or closing of the transistor channel.

[0039] In this embodiment, the gate structure 601 includes a gate dielectric layer 621 that surrounds the channel layer 231 along the extending direction of the gate structure 601, and a gate electrode layer 641 located on the gate dielectric layer 621.

[0040] In this embodiment, the gate dielectric layer 621 conformally covers the sidewalls, top, and bottom of the channel layer 231, and the gate structure 601 surrounds and covers the gate dielectric layer 621, thus the gate structure 601 conformally covers the sidewalls, top, and bottom of the channel layer 231.

[0041] It should be noted that the top, bottom, and sidewalls of the channel layer 231 covered by the gate structure 601 are used as channels. In this embodiment, the gate structure 601 covers the top, opposite sidewalls, and bottom of the channel layer 231, so the top, bottom, and sidewalls of the channel layer 231 can all serve as channels, increasing the area of ​​the channel layer 231 used as channels, thereby increasing the operating current of the semiconductor structure.

[0042] The gate dielectric layer 621 is used to isolate the gate structure 601 from the channel layer 231.

[0043] The gate dielectric layer 621 is made of one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 620 is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k dielectric material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0044] In this embodiment, the gate structure 601 includes a metal gate structure.

[0045] In this embodiment, the gate electrode layer 641 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer.

[0046] The work function layer is used to adjust the threshold voltage of the transistor. For a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; for an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or two of TiAl and TiAlC.

[0047] The electrode layer is used to draw out the electrical properties of the metal gate structure.

[0048] In this embodiment, the material of the gate electrode layer 641 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0049] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0050] In this embodiment, the semiconductor structure further includes a gate sidewall 631, located on the sidewall of the gate structure 601.

[0051] The gate sidewall 631 is used to protect the sidewall of the gate structure 601.

[0052] The gate sidewall 631 can be a single-layer structure or a multilayer structure, and the material of the gate sidewall 631 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 631 is a single-layer structure, and the material of the gate sidewall 631 is silicon nitride.

[0053] The source / drain doped layer 501 is used as the source or drain region of the transistor, and the doping type of the source / drain doped layer 501 is the same as the channel conductivity type of the corresponding transistor.

[0054] Specifically, when the substrate 101 is used to form an NMOS transistor, the doping ions in the source / drain doped layer 501 are N-type ions, including P ions, As ions, or Sb ions; when the substrate 101 is used to form a PMOS transistor, the doping ions in the source / drain doped layer 501 are P-type ions, including B ions, Ga ions, or In ions.

[0055] In this embodiment, the semiconductor structure further includes: an inner sidewall (not shown), located between adjacent channel layers 231 along the normal direction of the surface of the substrate 101, and in a direction perpendicular to the extension direction of the gate structure 601, the inner sidewall is located between the sidewall of the gate structure 601 and the source / drain doped layer 501.

[0056] The inner wall serves to isolate the gate structure 601 and the source / drain doped layer 501, thereby reducing the parasitic capacitance between the device gate structure 601 and the source / drain doped layer 501.

[0057] The inner wall is made of an insulating material. In this embodiment, the material of the inner wall includes silicon oxide.

[0058] The isolation sidewall 411 is used to isolate the adjacent source / drain doped layers 501 near the junction of the first device region 101N and the second device region 101P. This ensures good isolation between adjacent devices while bringing the source / drain doped layers 501 of the adjacent first device region 101N and the second device region 101P as close as possible. This helps to reduce the distance between the adjacent channel layer structures 201 of the first device region 101N and the second device region 101P, thereby forming a more compact and smaller device.

[0059] In this embodiment, in a direction perpendicular to the extension direction of the channel layer structure 201, there is a preset distance between the sidewall of the isolation sidewall 411 and the sidewall of the adjacent channel layer 231.

[0060] The source / drain doped layer 501 is grown epitaxially to the isolation sidewall 411 in a direction perpendicular to the extension direction of the channel layer structure 201. Therefore, there is a preset distance between the sidewall of the isolation sidewall 411 and the sidewall of the adjacent channel layer 231 in a direction perpendicular to the extension direction of the channel layer structure 201, providing sufficient growth space for the formation of the source / drain doped layer 501.

[0061] In this embodiment, the preset distance is 1 nanometer to 15 nanometers.

[0062] The preset distance cannot be too large or too small. If the preset distance is too large, it increases the distance between the adjacent channel layer structures 201 of the first device region 101N and the second device region 101P, making it difficult to form a more compact and smaller device. If the preset distance is too small, the space left on both sides of the isolation sidewall 411 is too small when forming the source / drain doped layer 501, making it difficult to form a source / drain doped layer 501 of sufficient size, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the preset distance is 1 nanometer to 15 nanometers.

[0063] In this embodiment, at the junction of the first device region 101N and the second device region 101P, the source / drain doped layer 501 of the adjacent first device region 101N and the source / drain doped layer 501 of the second device region 101P are in contact with the isolation sidewall 411.

[0064] In a direction perpendicular to the extension direction of the channel layer structure 201, the source / drain doped layer 501 is epitaxially grown up to the isolation sidewall 411. Therefore, the source / drain doped layer 501 of the adjacent first device region 101N and the source / drain doped layer 501 of the second device region 101P are in contact with the isolation sidewall 411. Thus, in a direction perpendicular to the extension direction of the channel layer structure 201, the size of the source / drain doped layer 501 can be maximized as much as possible, thereby improving the performance of the semiconductor structure.

[0065] It should be noted that, in this embodiment, during the formation of the semiconductor structure, after the formation of the gate sidewall 631 and before the formation of the isolation sidewall 411, a sacrificial layer is typically formed on the sidewall of the channel layer structure 20, and the sacrificial layer is removed after the formation of the isolation sidewall 411. The sacrificial layer occupies space at the predetermined distance, and due to process variations, it also covers the sidewall of the gate sidewall 631. Therefore, in this embodiment, the sidewall of the isolation sidewall 411 is spaced apart from the gate sidewall 631 in the extension direction of the channel layer structure 201.

[0066] In this embodiment, the material of the isolation sidewall 411 includes silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide.

[0067] The silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide has good insulation properties, which enables good isolation between adjacent source / drain doped layers 501 at the junction of the first device region 101N and the second device region 101P.

[0068] Figures 8 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0069] Reference Figure 8 and Figure 9 ,in, Figure 8 It is a 3D image. Figure 9 for Figure 8 A cross-sectional view based on the AA direction is provided, on which a channel structure 200 is formed. Along the normal direction of the surface of the substrate 100, the channel structure 200 includes one or more stacked channel layers 210, each channel layer 210 including a first sacrificial layer 220 and a channel layer 230 located on the first sacrificial layer 220. A pseudo-gate structure 610 is also formed on the substrate 100, spanning the channel structure 200. The pseudo-gate structure 610 covers part of the sidewalls and part of the top of the channel structure 200. In a direction perpendicular to the extension direction of the channel structure 200, the substrate includes an adjacent first device region 100N and a second device region 100P.

[0070] The substrate 100 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes gate-all-around (GAA) transistors and forksheet transistors.

[0071] The substrate 100 includes a semiconductor substrate (not shown).

[0072] In this embodiment, the semiconductor substrate is made of silicon. In other embodiments, the semiconductor substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, or other materials. The semiconductor substrate may also be a silicon-on-insulator (SiI) semiconductor substrate or a germanium-on-insulator (CHI) semiconductor substrate, or other types of semiconductor substrates. The semiconductor substrate material may be suitable for process requirements or easy to integrate.

[0073] It should be noted that the substrate 100 may also include: fins (not shown), which are disposed on the semiconductor substrate.

[0074] In this embodiment, the substrate 100 further includes an isolation layer 110 located within the substrate 100 and surrounding the fin, with the isolation layer 110 exposed above the top surface of the fin. The isolation layer 110 is used to achieve insulation between different devices; for example, in CMOS manufacturing processes, an isolation layer 110 is typically formed between NMOS transistors and PMOS transistors.

[0075] In this embodiment, the material of the isolation layer 110 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0076] In this embodiment, taking the semiconductor structure as a fork-type gate transistor as an example, the substrate 100 includes a first device region 100N and a second device region 100P that are adjacent to each other. The first device region 100N is used to form a first device, and the second device region 100P is used to form a second device.

[0077] In this embodiment, the first device region 100N includes an NMOS region, and the second device region 100P includes a PMOS region. The NMOS region 100N is used to form an NMOS transistor, and the PMOS region 100P is used to form a PMOS transistor, thereby forming a fork-gate transistor. In other embodiments, the first device region includes a PMOS region, and the second device region includes an NMOS region.

[0078] As device feature sizes continue to shrink, the use of fork-gate transistors allows for smaller spacing between adjacent NMOS transistors and PMOS crystals, resulting in better area miniaturization.

[0079] The channel layer 230 in the channel structure 200 serves as the channel for the transistor. The first sacrificial layer 220 provides a process basis for the subsequent floating arrangement of the channel layer 230 and also occupies space for the subsequently formed gate structure. In subsequent processes, the first sacrificial layer 220 is removed, leaving the channel layer 230 floating. A gate structure is formed between the channel layer 230 and the substrate 100, and between adjacent channel layers 230, thereby causing the gate structure to surround and cover the channel layer 230.

[0080] The top and sidewalls of the channel layer 230 covered by the gate structure are used as channels. In this embodiment, the top, bottom and sidewalls of the channel layer 230 can all be used as channels, which increases the area of ​​the channel layer 230 used as channels, thereby increasing the operating current of the semiconductor structure.

[0081] In this embodiment, in the first device region 100N or the second device region 100P, there is a first interval s1 between adjacent channel structures 200, and at the junction of the first device region 100N and the second device region 100P, there is a second interval s2 between adjacent channel structures 200, the second interval s2 being smaller than the first interval s1.

[0082] When the isolation sidewall is subsequently formed on the sidewall of the channel structure 200, at the junction of the first device area 100N and the second device area 100P, the isolation sidewalls on the opposite sidewalls of the adjacent channel structures 200 need to contact each other. Therefore, the second interval s2 between the adjacent channel structures 200 needs to be smaller than the first interval s1.

[0083] In this embodiment, the material of the channel layer 230 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the channel layer 230 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0084] It should be noted that in this embodiment, the channel layer 230 and the substrate 100 are made of the same material. In other embodiments, the channel layer and the substrate may be made of different materials.

[0085] In this embodiment, the channel layer 230 is made of silicon, therefore, the first sacrificial layer 220 is made of silicon germanide.

[0086] The silicon germanide and silicon can form a large etching selectivity, which is beneficial for the subsequent removal of the first sacrificial layer 220 and reduces damage to the channel layer 230.

[0087] In other embodiments, a material with an etch selectivity that is suitable for the channel layer can be selected based on the material of the channel layer, so as to reduce damage to the channel layer when the first sacrificial layer is removed subsequently.

[0088] The pseudo-gate structure 610 occupies space for the device gate structure formed in subsequent processes.

[0089] In this embodiment, the pseudo-gate structure 610 can be a single-layer structure or a multilayer structure, and the material of the pseudo-gate structure 610 includes one or both of amorphous silicon and polycrystalline silicon. In other embodiments, the material of the pseudo-gate structure can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, or amorphous carbon.

[0090] In this embodiment, the dummy gate structure 610 is a single-layer structure, and the material of the dummy gate structure 610 is amorphous silicon. Amorphous silicon does not have a crystal orientation; therefore, the etching rate uniformity and etching effect of amorphous silicon are better, thereby improving the subsequent removal effect of the dummy gate structure 610.

[0091] It should be noted that, depending on process requirements, a gate oxide layer (not shown) may also be formed between the pseudo-gate structure 610 and the channel structure 200. The material of the gate oxide layer may be silicon oxide.

[0092] In this embodiment, the sidewall of the pseudo-gate structure 610 is further formed with a gate sidewall 630.

[0093] The gate sidewall 630 is used to protect the sidewalls of the gate structure.

[0094] The gate sidewall 630 can be a single-layer structure or a multilayer structure, and the material of the gate sidewall 630 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 630 is a single-layer structure, and the material of the gate sidewall 630 is silicon nitride.

[0095] Reference Figures 10 to 13 At the junction of the first device region 100N and the second device region 100P, on both sides of the pseudo-gate structure 610, an isolation sidewall 410 protruding from the substrate 100 is formed between adjacent channel structures 200.

[0096] As the feature size of integrated circuits continues to shrink, adjacent devices are getting closer and closer. In this embodiment of the invention, isolation sidewalls 410 are used to isolate the source and drain doped layers of the first device region 100N and the second device region 100P. This ensures good isolation between adjacent devices while bringing the source and drain doped layers of the adjacent first device region 100N and the second device region 100P as close as possible. This helps to reduce the distance between the adjacent channel structures 200 of the first device region 100N and the second device region 100P, resulting in a more compact and smaller device. Simultaneously, the dummy gate structure 610 and the first sacrificial layer 220 are typically removed subsequently, and a gate covering the channel layer 230 is formed. In this embodiment, the isolation sidewall 410 is formed only between adjacent source / drain doped layers at the junction of the first device region 100N and the second device region 100P, and not between adjacent channel structures 200 below the pseudo-gate structure 610. This facilitates the subsequent covering of the sidewalls of the channel layer 230 at the junction of the first device region 100N and the second device region 100P by the gate structure, so that the gate structure surrounds and covers each surface of the channel layer 230. This increases the area of ​​the channel layer 230 used as a channel while forming a smaller device, thereby increasing the operating current of the semiconductor structure and improving its performance.

[0097] In this embodiment, in a direction perpendicular to the extension direction of the channel structure 200, there is a preset distance between the sidewall of the isolation sidewall 410 and the sidewall of the adjacent channel layer 230.

[0098] After removing the channel structures 200 on both sides of the pseudo-gate structure 610, when forming source / drain doped layers on both sides of the pseudo-gate structure 610 that are in contact with the ends of the channel structures 200 below the pseudo-gate structure 610, sufficient growth space is left for the source / drain doped layers.

[0099] The preset distance cannot be too large or too small. If the preset distance is too large, it increases the distance between the adjacent channel structures 200 of the first device region 100N and the second device region 100P, making it difficult to form a more compact and smaller device. If the preset distance is too small, the space left on both sides of the isolation sidewall 410 is too small when the source / drain doped layer is subsequently formed, making it difficult to form a source / drain doped layer of sufficient size, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the preset distance is 1 nanometer to 15 nanometers.

[0100] In this embodiment, the material of the isolation sidewall 410 includes silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide.

[0101] The silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide have good insulation properties. After the source and drain doped layers are formed, they can provide good isolation between adjacent source and drain doped layers at the junction of the first device region 100N and the second device region 100P.

[0102] Specifically, in conjunction with reference Figure 10 and Figure 11 ,in, Figure 10 and Figure 11 For based on Figure 9 The cross-sectional view, before forming the isolation sidewall 410, also includes: forming a second sacrificial layer 310 covering the sidewall of the trench structure 200.

[0103] Subsequently, isolation sidewalls 410 are also formed on the sidewalls of the second sacrificial layer 310. After the second sacrificial layer 310 is removed, the second sacrificial layer 310 is used to ensure that there is a preset distance between the isolation sidewalls 410 and the adjacent channel structures 200. This ensures that after the channel structures 200 on both sides of the pseudo-gate structure 610 are removed, sufficient growth space is provided for the source and drain doped layers that are in contact with the ends of the channel structures 200 below the pseudo-gate structure 610 when the source and drain doped layers are formed on both sides of the pseudo-gate structure 610. At the same time, the isolation sidewalls 410 inside the first device region 100N and the second device region 1001P will also be removed. The second sacrificial layer 310 can also protect the sidewalls of the channel structures 200 during the removal of the isolation sidewalls 410.

[0104] In this embodiment, the material of the second sacrificial layer 310 includes silicon oxide or silicon nitride.

[0105] The silicon oxide or silicon nitride is easy to remove, and the silicon oxide or silicon nitride is easy to form an etching selectivity with the material of the isolation sidewall 410, which is beneficial to reduce damage to the isolation sidewall 410 during the subsequent removal of the second sacrificial layer 310.

[0106] Specifically, refer to Figure 10 The step of forming the second sacrificial layer 310 includes: forming a sacrificial material layer 300 that conformally covers the top and sidewalls of the channel structure 200.

[0107] The sacrificial material layer 300 is used to form the sacrificial layer 310.

[0108] In this embodiment, the sacrificial material layer 300 is formed using atomic layer deposition (ALD).

[0109] The sacrificial material layer 300 formed by atomic layer deposition has good thickness uniformity, and the atomic layer deposition process has good step coverage capability, which enables the sacrificial material layer 300 to cover the top and sidewalls of the channel structure 200 in good conformal way.

[0110] In this embodiment, the material of the sacrificial material layer 300 includes silicon oxide or silicon nitride, which is used to directly form the sacrificial layer 310.

[0111] refer to Figure 11 The sacrificial material layer 300 located on the top of the channel structure 200 and the top of the base 100 is removed, and the sacrificial material layer 300 located on the sidewall of the channel structure 200 is retained as the sacrificial layer 310.

[0112] The sacrificial material layer 300 located on top of the channel structure 200 and the substrate 100 is removed to provide a process basis for the subsequent formation of the isolation sidewall 410. Furthermore, the sacrificial layer 310 is exposed on top of the channel structure 200 to provide a process basis for the subsequent formation of the source / drain doped layers.

[0113] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to remove the sacrificial material layer 300 located on the top of the channel structure 200 and the top of the substrate 100.

[0114] The dry etching process has anisotropic etching characteristics. Therefore, by selecting the dry etching process, it is beneficial to reduce damage to the top of the channel structure 200 and the top of the substrate 100. At the same time, the dry etching is more directional, which is beneficial to reduce damage to the sacrificial material layer 300 located on the sidewall of the channel structure 200, and to improve the morphological quality and dimensional accuracy of the formed sacrificial layer 310.

[0115] Reference Figure 12 and Figure 13 ,in, Figure 12 and Figure 13 For based on Figure 9 In the cross-sectional view, during the step of forming the isolation sidewall 410, an isolation sidewall 410 covering the sidewall of the second sacrificial layer 310 is formed at the junction of the first device region 100N and the second device region 100P, and the isolation sidewall 410 fills the space between adjacent second sacrificial layers 310.

[0116] The isolation sidewall 410 covers the sidewall of the second sacrificial layer 310 and fills the space between adjacent second sacrificial layers 310. After the second sacrificial layer 310 is subsequently removed, there is a preset distance between the isolation sidewall 410 and the adjacent channel structure 200. This ensures that after the channel structures 200 on both sides of the pseudo gate structure 610 are subsequently removed, sufficient growth space is provided for the source / drain doped layers when the source / drain doped layers that contact the ends of the channel structures 200 below the pseudo gate structure 610 are formed on both sides of the pseudo gate structure 610.

[0117] Furthermore, at the junction of the first device region 100N and the second device region 100P, the isolation sidewall 410 fills the space between adjacent second sacrificial layers 310, making the isolation sidewall 410 at the junction of the first device region 100N and the second device region 100P an integral structure, thereby achieving better mechanical strength and electrical isolation effect.

[0118] Specifically, refer to Figure 12 The step of forming the isolation sidewall 410 includes: forming an isolation material layer 400 that conformally covers the top of the channel structure 200, the top of the substrate 100, and the sidewall of the channel structure 200, wherein the isolation material layers 400 on the opposite sidewalls of adjacent channel structures 200 are in contact at the junction of the first device region 100N and the second device region 100P.

[0119] The isolation material layer 400 is used to form an isolation sidewall 410. At the junction of the first device region 100N and the second device region 100P, the isolation material layers 400 on the opposite sidewalls of the adjacent channel structure 200 are in contact with each other, and the contacting isolation material layers 400 serve as isolation sidewalls 410.

[0120] In this embodiment, the isolation material layer 400 is formed using an atomic layer deposition process.

[0121] The isolation material layer 400 formed by atomic layer deposition has good thickness uniformity, and the atomic layer deposition process has good step coverage capability, which allows the isolation material layer 400 to cover the top of the channel structure 200, the top of the substrate 100, and the sidewalls of the channel structure 200 in a good conformal manner. Subsequently, as the deposition thickness increases, the isolation material layers 400 on the opposite sidewalls of adjacent channel structures 200 can come into contact with each other, serving as isolation sidewalls 410.

[0122] In this embodiment, at the junction of the first device region 100N and the second device region 100P, the isolation material layers 400 on the opposite sidewalls of the adjacent channel structures 200 are in contact with each other, while in the first device region 100N and the second device region 100P, the isolation material layers 400 on the opposite sidewalls of the channel structures 200 are isolated from each other, so that the isolation material layers 400 in the first device region 100N and the second device region 100P can be removed by maskless etching, and only the contacting isolation material layers 400 are retained.

[0123] In this embodiment, the material of the isolation material layer 400 includes silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide, and is used to directly form the isolation sidewall 410.

[0124] refer to Figure 13 Remove the isolation material layer 400 located on the channel structure 200 in the first device region 100N and the second device region 100P, and on the top of the substrate 100. At the junction of the first device region 100N and the second device region 100P, retain the contacting isolation material layer 400 as an isolation sidewall 410.

[0125] The isolation material layer 400 located on the channel structure 200 in the first device region 100N and the second device region 100P, and on the top of the substrate 100, is removed to form the isolation sidewall 410. At the same time, the second sacrificial layer 310 is exposed, thereby reducing the difficulty of the subsequent removal of the second sacrificial layer 310 and facilitating the subsequent removal of the second sacrificial layer 310.

[0126] In this embodiment, the process of removing the isolation material layer 400 located on the channel structure 200 in the first device region 100N and the second device region 100P, and on the top of the substrate 100, includes one or both of dry etching and wet etching processes.

[0127] The process options for removing the isolation material layer 400 located on the channel structure 200 in the first device region 100N and the second device region 100P, as well as on the top of the substrate 100, are wide-ranging. Therefore, the removal method is simple and facilitates the complete removal of the isolation material layer 400 on the channel structure 200 in the first device region 100N and the second device region 100P, as well as on the top of the substrate 100.

[0128] Reference Figure 14 and Figure 15 ,in, Figure 14 It is a 3D image. Figure 15 for Figure 14Based on the cross-sectional view along the AA direction, after forming the isolation sidewall 410 and before subsequently forming the source / drain doped layer, the process further includes: removing the second sacrificial layer 310.

[0129] Removing the second sacrificial layer 310 provides space for the subsequent formation of source and drain doped layers. Subsequently, the channel structures 200 on both sides of the pseudo gate structure 610 also need to be removed. Removing the second sacrificial layer 310 better exposes the channel structures 200 on both sides of the pseudo gate structure 610, which is beneficial for the subsequent removal of the channel structures 200 on both sides of the pseudo gate structure 610.

[0130] In this embodiment, the process for removing the second sacrificial layer 310 includes: an isotropic dry etching process or a wet etching process.

[0131] The isotropic dry etching process or wet etching process has isotropic characteristics, which is beneficial for completely removing the second sacrificial layer 310.

[0132] In this embodiment, a wet etching process is used to remove the second sacrificial layer 310. The etching solution of the wet etching process includes an alkaline etching solution or a hot phosphoric acid solution. The alkaline etching solution or hot phosphoric acid solution can obtain a high etching selectivity, which is beneficial to remove the second sacrificial layer 310 cleanly while reducing damage to the channel structure 200.

[0133] Accordingly, in this embodiment, after removing the second sacrificial layer 310, there is a preset distance d between the sidewall of the isolation sidewall 410 and the sidewall of the adjacent channel structure 200 in a direction perpendicular to the extension direction of the channel structure 200.

[0134] Reference Figures 16 to 20 After the isolation sidewall 410 is formed, source and drain doped layers 500 are formed in the channel structures 200 on both sides of the pseudo gate structure 610. Adjacent source and drain doped layers 500 near the junction of the first device region 100N and the second device region 100P are isolated from each other by the isolation sidewall 410.

[0135] The source / drain doped layer 500 is used as the source or drain region of the transistor, and the doping type of the source / drain doped layer 500 is the same as the channel conductivity type of the corresponding transistor.

[0136] Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source / drain doped layer 500 are N-type ions, including P ions, As ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the doping ions in the source / drain doped layer 500 are P-type ions, including B ions, Ga ions, or In ions.

[0137] The adjacent source / drain doped layers 500 near the junction of the first device region 100N and the second device region 100P are isolated by the isolation sidewall 410 to better ensure the isolation effect between the adjacent source / drain doped layers 500.

[0138] Reference Figure 16 and Figure 17 ,in, Figure 16 It is a 3D image. Figure 17 for Figure 16 Based on the cross-sectional view along the AA direction, the steps for forming the source / drain doped layer 500 include: after removing the second sacrificial layer 310, removing the channel structures 200 on both sides of the pseudo-gate structure 610 to form the source / drain trench 510.

[0139] The source / drain trench 510 is used to provide spatial location for forming the source / drain doped layer 500.

[0140] In this embodiment, a dry etching process is used to remove the channel structures 200 on both sides of the pseudo gate structure 610.

[0141] The dry etching process has anisotropic characteristics. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the substrate 100 at the bottom of the channel structure 200. At the same time, the dry etching is more directional, which is beneficial to improve the morphological quality and dimensional accuracy of the remaining channel layer 200.

[0142] Continue to refer to Figure 17 An inner sidewall 240 is formed in the first sacrificial layer 220 exposed on the sidewall of the source drain trench 510.

[0143] Subsequently, a gate structure is formed, and the inner wall 240 serves to isolate the gate structure and the source / drain doped layer 500 to reduce the parasitic capacitance between the gate structure and the source / drain doped layer 500.

[0144] The inner wall 240 is made of an insulating material. In this embodiment, the material of the inner wall 240 includes silicon oxide.

[0145] Specifically, the exposed first sacrificial layer 220 on the sidewall of the source / drain trench 510 is etched laterally to remove a portion of the width of the first sacrificial layer 220, forming a groove (not shown). Then, an inner sidewall 240 is formed within the groove. Here, "lateral" refers to a direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the pseudo-gate structure 610.

[0146] Reference Figures 18 to 20 ,in, Figure 18 It is a 3D image. Figure 19 for Figure 18Cross-sectional view based on the AA direction, Figure 20 for Figure 18 Based on the BB direction cross-sectional view, after the inner sidewall 240 is formed, the source / drain doped layer 500 is formed in the source / drain trench 510. At the junction of the first device region 100N and the second device region 100P, the source / drain doped layer 500 of the first device region 100N and the source / drain doped layer 500 of the second device region 100P are in contact with the isolation sidewall 410 respectively.

[0147] In a direction perpendicular to the extension direction of the channel structure 200, the source / drain doped layer 500 is formed up to the isolation sidewall 410. Therefore, the source / drain doped layer 500 of the first device region 100N and the source / drain doped layer 500 of the second device region 100P are in contact with the isolation sidewall 410, and the size of the source / drain doped layer 500 can be maximized in a direction perpendicular to the extension direction of the channel structure 200, thereby improving the performance of the semiconductor structure.

[0148] In this embodiment, a source / drain doped layer 500 is formed in the source / drain trench 510 by an epitaxial growth process.

[0149] Continue to refer to Figure 20 After forming the source / drain doped layer 500, the method further includes: forming an interlayer dielectric layer (not shown) on the substrate 100 that covers the sidewalls of the dummy gate structure 610 and the channel structure 200, wherein the interlayer dielectric layer is exposed on the top of the dummy gate structure 610.

[0150] The interlayer dielectric layer serves to isolate adjacent devices and also provides a process basis for the subsequent removal of the dummy gate structure 610 to form a gate opening.

[0151] The material of the interlayer dielectric layer is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0152] Continue to refer to Figure 20 In this embodiment, after forming the interlayer dielectric layer, the method further includes: removing the pseudo-gate structure 610 and forming a gate opening (not shown) in the interlayer dielectric layer.

[0153] The gate opening provides space for the subsequent formation of the gate structure.

[0154] In this embodiment, the forming method further includes: removing the first sacrificial layer 220 exposed by the gate opening to form a through trench (not shown) connected to the gate opening.

[0155] The through-slot is used to provide space for the subsequent formation of the gate structure. The through-slot exposes the top, bottom and sidewalls of the channel layer 230, so that the subsequently formed gate structure surrounds and covers the channel layer 230.

[0156] In this embodiment, a gate structure 600 is formed in the gate opening and the through-hole to conformally cover each surface of the channel layer 230.

[0157] The gate structure 600 is used to control the opening or closing of the transistor's channel.

[0158] The gate structure 600 covers the channel layer 230, so the top, bottom and sidewalls of the channel layer 230 can all serve as channels, increasing the area in the channel layer 230 used as channels, thereby increasing the operating current of the semiconductor structure.

[0159] In this embodiment, the gate structure 600 includes a gate dielectric layer 620 that surrounds the channel layer 230 along the extending direction of the gate structure 600, and a gate electrode layer 640 located on the gate dielectric layer 620.

[0160] The gate dielectric layer 620 is used to isolate the subsequently formed gate structure from the channel layer 230.

[0161] The gate dielectric layer 620 is made of one or more of the following materials: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 620 is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k gate dielectric layer material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0162] It should be noted that the gate dielectric layer 620 may further include a gate oxide layer located between the channel layer 230 and the high-k gate dielectric layer. As an example, the material of the gate oxide layer may be SiO2. In this embodiment, the gate structure 600 includes a metal gate structure.

[0163] In this embodiment, the gate electrode layer 640 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer.

[0164] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or two of TiAl and TiAlC.

[0165] The electrode layer is used to draw out the electrical properties of the metal gate structure.

[0166] In this embodiment, the material of the gate electrode layer 640 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0167] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0168] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first device region and a second device region that are adjacent to each other, wherein the first device region includes an NMOS region and the second device region includes a PMOS region; or, the first device region includes a PMOS region and the second device region includes an NMOS region. A channel layer structure, suspended above the substrate and along the normal direction of the substrate surface, the channel layer structure comprising one or more spaced channel layers; A gate structure is located on the substrate and spans the channel layer structure, the gate structure including a gate dielectric layer surrounding the channel layer along the extension direction of the gate structure, and a gate electrode layer located on the gate dielectric layer; Source and drain doped layers are located on the substrates on both sides of the gate structure, and the source and drain doped layers are in contact with the ends of the channel layer structure; An isolation sidewall is located on both sides of the gate structure and protrudes from the substrate between adjacent source / drain doped layers at the junction of the first device region and the second device region. The isolation sidewall is located only between adjacent source / drain doped layers at the junction of the first device region and the second device region.

2. The semiconductor structure as described in claim 1, characterized in that, In a direction perpendicular to the extension direction of the channel structure, there is a predetermined distance between the sidewall of the isolation sidewall and the sidewall of the adjacent channel layer.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, At the boundary between the first device region and the second device region, the source / drain doped layers of the adjacent first device region and the source / drain doped layers of the second device region are in contact with the isolation sidewall, respectively.

4. The semiconductor structure as described in claim 2, characterized in that, The semiconductor structure further includes: a gate sidewall, located on the sidewall of the gate structure; In the extension direction of the channel layer structure, the gate sidewall is spaced apart from the isolation sidewall, and the distance between the gate sidewall and the isolation sidewall is equal to the preset distance.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an inner sidewall located between adjacent channel layers along the normal direction of the substrate surface and in a direction perpendicular to the extension direction of the gate structure, wherein the inner sidewall is located between the sidewall of the gate structure and the source / drain doped layer.

6. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a semiconductor substrate and fins discretely disposed on the semiconductor substrate, and an isolation layer surrounding the fins, the isolation layer being exposed on the top surface of the fins.

7. The semiconductor structure as described in claim 6, characterized in that, The semiconductor substrate is made of one or more of silicon, silicon germanide, germanium, gallium nitride, and silicon carbide.

8. The semiconductor structure as described in claim 6, characterized in that, The material of the isolation layer includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

9. The semiconductor structure as described in claim 1, characterized in that, The materials of the isolation sidewalls include silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide.

10. The semiconductor structure as claimed in claim 1, characterized in that, The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC, and the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

11. The semiconductor structure as described in claim 2, characterized in that, The preset distance is 1 nanometer to 15 nanometers.

12. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a channel structure is formed. Along the normal direction of the substrate surface, the channel structure includes one or more stacked channel layers, each channel layer including a first sacrificial layer and a channel layer located on the first sacrificial layer. A pseudo-gate structure is also formed on the substrate, spanning the channel structure and covering a portion of the sidewalls and top of the channel structure. In a direction perpendicular to the extension direction of the channel structure, the substrate includes adjacent first and second device regions. The first device region includes an NMOS region, and the second device region includes a PMOS region; or, the first device region includes a PMOS region, and the second device region includes an NMOS region. At the junction of the first device region and the second device region, on both sides of the pseudo-gate structure, an isolation sidewall protruding from the substrate is formed between adjacent channel structures; After the isolation sidewall is formed, source and drain doped layers are formed in the channel structure on both sides of the pseudo-gate structure. Adjacent source and drain doped layers near the junction of the first device region and the second device region are isolated by the isolation sidewall, and the isolation sidewall is located only between adjacent source and drain doped layers at the junction of the first device region and the second device region.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, Before forming the isolation sidewall, the method further includes: forming a second sacrificial layer covering the sidewall of the trench structure; In the step of forming the isolation sidewall, an isolation sidewall covering the sidewall of the second sacrificial layer is formed at the junction of the first device area and the second device area, and the isolation sidewall fills the space between adjacent second sacrificial layers; After forming the isolation sidewalls and before forming the source / drain doped layers, the method further includes: removing the second sacrificial layer.

14. The method for forming a semiconductor structure as described in claim 12 or 13, characterized in that, The step of forming the isolation sidewall includes: forming an isolation material layer that conformally covers the top of the channel structure, the top of the substrate, and the sidewall of the channel structure, wherein the isolation material layers on the opposite sidewalls of adjacent channel structures are in contact at the junction of the first device area and the second device area; Remove the isolation material layer on the channel structure located in the first device area and the second device area, as well as on the top of the substrate. At the junction of the first device area and the second device area, retain the contacting isolation material layer as an isolation sidewall.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming the second sacrificial layer includes: forming a sacrificial material layer that conformally covers the top and sidewalls of the trench structure; Remove the sacrificial material layers located at the top of the trench structure and the top of the substrate, and retain the sacrificial material layers located on the sidewalls of the trench structure as sacrificial layers.

16. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing the substrate, there is a first interval between adjacent channel structures in the first device region or the second device region, and a second interval between adjacent channel structures at the junction of the first device region and the second device region, wherein the second interval is smaller than the first interval.

17. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming the source / drain doped layer includes: after removing the second sacrificial layer, removing the channel structures on both sides of the pseudo-gate structure to form source / drain trenches; An inner sidewall is formed in the first sacrificial layer exposed on the sidewall of the source-drain trench; After the inner sidewall is formed, the source / drain doped layer is formed in the source / drain trench. At the junction of the first device region and the second device region, the source / drain doped layer of the first device region and the source / drain doped layer of the second device region are in contact with the isolation sidewall.

18. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process for removing the second sacrificial layer includes: an isotropic dry etching process or a wet etching process.

19. The method for forming a semiconductor structure as described in claim 14, characterized in that, The isolation material layer is formed using an atomic layer deposition process.

20. The method for forming a semiconductor structure as described in claim 14, characterized in that, The process for removing the isolation material layer located on the channel structure in the first device region and the second device region, and on top of the substrate, includes one or both of dry etching and wet etching processes.

21. The method for forming a semiconductor structure as described in claim 15, characterized in that, The sacrificial material layer is formed using atomic layer deposition (ALD).

22. The method for forming a semiconductor structure as described in claim 15, characterized in that, In the step of forming the second sacrificial layer, a dry etching process is used to remove the sacrificial material layer located on top of the channel structure and on top of the substrate.

23. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming a second sacrificial layer covering the sidewalls of the trench structure, the material of the second sacrificial layer includes silicon oxide or silicon nitride.

24. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the source and drain doped layers, the method further includes: forming an interlayer dielectric layer on the substrate that covers the sidewalls of the dummy gate structure and the channel structure, wherein the interlayer dielectric layer exposes the top of the dummy gate structure; Remove the dummy gate structure and form a gate opening in the interlayer dielectric layer; Remove the first sacrificial layer exposed by the gate opening to form a through groove that communicates with the gate opening; In the gate opening and through-slot, a gate structure is formed that conformally covers each surface of the channel layer.

Images