Memory array test structure and method of forming the same

Abstract

The present disclosure relates to memory array test structures and methods of forming the same. Disclosed are test structures for 3D memory arrays and methods of forming the same. In one embodiment, a memory array includes a first word line located over a semiconductor substrate and extending in a first direction, a second word line located over the first word line and extending in the first direction, a memory film contacting the first word line and the second word line, an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being located between the OS layer and each of the first word line and the second word line, and a test structure located over the first word line and the second word line, the test structure including a first conductor electrically coupling the first word line to the second word line, the first conductor extending in the first direction.

Description

Technical Field

[0001] This disclosure generally relates to memory array test structures and methods for forming them. Background Technology

[0002] Semiconductor memories are used in integrated circuits for electronic applications (examples include radios, televisions, mobile phones, and personal computing devices). Semiconductor memories fall into two main categories: volatile memories and non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose the information they store when power is off.

[0003] On the other hand, non-volatile memory can store the data stored on it. One type of non-volatile semiconductor memory is ferroelectric random access memory (FERAM, or FRAM). The advantages of FERAM include its fast write / read speed and small size. Summary of the Invention

[0004] According to one embodiment of this disclosure, a memory array is provided, comprising: a first word line located on a semiconductor substrate, wherein the longitudinal axis of the first word line extends in a first direction; a second word line located on the first word line in a second direction perpendicular to a main surface of the semiconductor substrate, wherein the longitudinal axis of the second word line extends in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, wherein the memory film is located between each of the first word line and the second word line and the OS layer; and a test structure located on the first word line and the second word line, the test structure including a first conductor electrically coupling the first word line to the second word line, wherein the longitudinal axis of the first conductor extends in the first direction.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first word line located on a semiconductor substrate, the first word line having a first length in a first direction; a second word line located on the semiconductor substrate, the second word line having a second length in the first direction, wherein the second length is equal to the first length; a first intermetallic dielectric (IMD) located on the first word line; a first memory film contacting the first word line and the first IMD; a first oxide semiconductor (OS) layer located on the first memory film, the first OS layer contacting a source line and a bit line; a first conductive contact extending through the first IMD and electrically coupled to the first word line; a second conductive contact electrically coupled to the second word line; and a first wire extending on the first IMD and electrically coupling the first conductive contact to the second conductive contact, wherein the first wire extends in a second direction perpendicular to the first direction.

[0006] According to another embodiment of this disclosure, a method of forming a semiconductor device is provided, comprising: depositing a multilayer stack on a semiconductor substrate, the multilayer stack including alternating layers of a first material and a second material; patterning the multilayer stack such that the multilayer stack includes a stepped structure in a cross-sectional view; forming an intermetallic dielectric (IMD) on the stepped structure of the multilayer stack; forming a plurality of word lines in the multilayer stack; depositing a memory film adjacent to the plurality of word lines in the multilayer stack; depositing an oxide semiconductor (OS) layer on the memory film; etching the IMD to form a first opening exposing a first word line among the plurality of word lines and a second opening exposing a second word line among the plurality of word lines, wherein the first opening extends to a first depth, and wherein the second opening extends to a second depth different from the first depth; forming a first conductive contact electrically coupled to the first word line in the first opening, and forming a second conductive contact electrically coupled to the second word line in the second opening; and forming a first wire on the IMD, the first conductive contact, and the second conductive contact, wherein the first wire electrically couples the first conductive contact to the second conductive contact. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1A and Figure 1B Perspective views and circuit diagrams of memory arrays according to some embodiments are shown.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 24D 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 26A 、 Figure 26B 、 Figure 27A 、 Figure 27B 、 Figure 28A 、 Figure 28B 、 Figure 29A 、 Figure 29B 、 Figure 30A 、 Figure 30B 、 Figure 31A 、 Figure 31B 、 Figure 32A, Figure 32B , Figure 33A , Figure 33B , Figure 34A , Figure 34B and Figure 34C Different views of the fabrication of a semiconductor device including a memory array are shown according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] In addition, for ease of description, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0012] Various embodiments provide test structures and methods for forming the same for testing connections within a stepped structure of a 3D memory array. The 3D memory array includes stacked memory cells, including word lines extending in a direction parallel to the main surface of an underlying substrate. The word lines are arranged in a stepped structure, wherein the individual lengths of the word lines decrease in a direction away from the substrate. An inter-metal dielectric (IMD) can be formed on the stepped structure, and conductive vias can be formed through the IMD and extending to each word line in the stepped structure. Conductive vias can be formed simultaneously using a single mask, which saves time and cost, but may introduce the risk that the openings of the conductive vias do not extend to sufficient depth. Therefore, a test structure can be formed on the stepped structure to test whether each conductive via has been successfully connected to its corresponding word line. The test structure includes wires connected to each conductive via and interconnecting each word line in the stepped structure. Some wires extend in a direction parallel to the word lines, and some wires extend in a direction perpendicular to the word lines. A bias voltage can be applied to opposite ends of the test structure through all word lines to determine whether all conductive vias have been successfully connected to their respective word lines. The test structure can be used to screen memory arrays in which conductive vias have not been successfully connected to the corresponding word lines, which reduces device defects.

[0013] Figure 1A and Figure 1B An example of a memory array 200 according to some embodiments is shown. Figure 1A An example of a portion of the memory array 200 is shown in a three-dimensional view. Figure 1B A circuit diagram of a memory array 200 is shown. The memory array 200 includes a plurality of memory cells 202, which can be arranged in a grid of rows and columns. The memory cells 202 can be further vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 can be disposed in the back-end of the semiconductor die (BEOL). For example, the memory array 200 can be disposed in the interconnect layer of the semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0014] In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array. Each memory cell 202 may include a transistor 204 having a memory film 90. The memory film 90 may serve as a gate dielectric. In some embodiments, the gate of each transistor 204 is electrically coupled to a corresponding word line (e.g., wire 72), a first source / drain region of each transistor 204 is electrically coupled to a corresponding bit line (e.g., wire 106), and a second source / drain region of each transistor 204 is electrically coupled to a corresponding source line (e.g., wire 108), which electrically couples the second source / drain region to ground. Memory cells 202 in the same horizontal row of the memory array 200 may share a common word line, while memory cells 202 in the same vertical column of the memory array 200 may share a common source line and a common bit line.

[0015] The memory array 200 includes a plurality of vertically stacked conductors 72 (e.g., word lines), wherein a first material layer 52 is disposed between vertically adjacent conductors in the conductors 72. The conductors 72 are positioned relative to the underlying substrate ( Figure 1A and Figure 1B (Not shown separately) extends in a direction parallel to the main surface. The conductor 72 may have a stepped structure, such that the lower conductor 72 is longer than the endpoint of the upper conductor 72 and extends longitudinally beyond the endpoint of the upper conductor 72. For example, in Figure 1A In the diagram, multiple stacked layers of wires 72 are shown, with the topmost wire 72 being the shortest and the bottommost wire 72 being the longest. The individual lengths of the wires 72 can increase in the direction toward the substrate below. In this way, a portion of each wire 72 can be accessed from above the memory array 200, and conductive contacts can be made to the exposed portions of each wire 72.

[0016] The memory array 200 also includes multiple conductors 106 (e.g., bit lines) and multiple conductors 108 (e.g., source lines). Conductors 106 and 108 may each extend in a direction perpendicular to conductor 72. Dielectric material 102 is disposed between adjacent conductors in conductors 106 and 108 and isolates adjacent conductors in conductors 106 and 108. Each pair of conductors 106 and 108, together with intersecting conductors 72, defines the boundary of each memory cell 202, and dielectric material 98 is disposed between adjacent pairs of conductors 106 and 108 and isolates adjacent pairs of conductors 106 and 108. In some embodiments, conductor 108 is electrically coupled to ground. Although Figure 1A A specific arrangement of conductor 106 relative to conductor 108 is shown, but it should be understood that the arrangement of conductor 106 and conductor 108 can be reversed.

[0017] The memory array 200 may also include an oxide semiconductor (OS) layer 92. The OS layer 92 can provide channel regions for the transistors 204 of the memory cells 202. For example, when an appropriate voltage (e.g., higher than the corresponding threshold voltage (V) of the corresponding transistor 204) is applied through the corresponding wire 72... th When the OS layer 92 intersects with the conductor 72, the area where the conductor 72 intersects can allow current to flow from the conductor 108 to the conductor 106 (e.g., in the direction indicated by arrow 206).

[0018] A memory film 90 is disposed between the conductor 72 and the OS layer 92, and the memory film 90 can provide a gate dielectric for the transistor 204. In some embodiments, the memory film 90 comprises a ferroelectric (FE) material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc. Therefore, the memory array 200 can be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the memory film 90 can be a multilayer structure, different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), etc.

[0019] In embodiments where the memory film 90 comprises FE material, the memory film 90 can be polarized in one of two different directions. The polarization direction can be changed by applying an appropriate voltage difference across the memory film 90 and generating an appropriate electric field. The polarization can be relatively localized (e.g., typically contained within each boundary of the memory cell 202), and a continuous region of the memory film 90 can extend across multiple memory cells 202. Depending on the polarization direction of a particular region of the memory film 90, the threshold voltage of the corresponding transistor 204 varies and digital values ​​(e.g., 0 or 1) can be stored. For example, when a region of the memory film 90 has a first polarization direction, the corresponding transistor 204 can have a relatively low threshold voltage, while when a region of the memory film 90 has a second polarization direction, the corresponding transistor 204 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage offset. A larger threshold voltage offset makes reading the digital value stored in the corresponding memory cell 202 easier (e.g., less prone to error).

[0020] To perform a write operation on memory cell 202, a write voltage is applied to the portion of memory film 90 corresponding to memory cell 202. This can be achieved, for example, by applying appropriate voltages to the corresponding wire 72 (e.g., the corresponding word line) and the corresponding wires 106 and 108 (e.g., the corresponding bit line and source line). By applying the write voltage to this portion of memory film 90, the polarization direction of the region of memory film 90 can be changed. Therefore, the corresponding threshold voltage of the corresponding transistor 204 can switch from a low threshold voltage to a high threshold voltage, and vice versa, and a digital value can be stored in memory cell 202. Because wire 72 intersects with wires 106 and 108, a single memory cell 202 can be selected for the write operation.

[0021] To perform a read operation on memory cell 202, a read voltage (e.g., a voltage between a low threshold voltage and a high threshold voltage) is applied to the corresponding wire 72 (e.g., the corresponding word line). Depending on the polarization direction of the corresponding region of the memory film 90, the transistor 204 of memory cell 202 may or may not be turned on. Therefore, the corresponding wire 106 may or may not discharge through the corresponding wire 108 (e.g., the corresponding source line coupled to ground), and the digital value stored in memory cell 202 can be determined. Because wire 72 intersects with wires 106 and 108, a single memory cell 202 can be selected for the read operation.

[0022] Figure 1A A reference cross-section of the memory array 200 used in later figures is further shown. Cross-section A-A' is along the longitudinal axis of conductor 72 and in a direction parallel to, for example, the direction of current flowing through the OS layer 92 of transistor 204. Cross-section B-B' is perpendicular to cross-section A-A' and the longitudinal axis of conductor 72. Cross-section B-B' extends through dielectric material 98 and dielectric material 102. Cross-section C-C' is parallel to cross-section B-B' and extends through conductor 106. For clarity, subsequent figures refer to these reference cross-sections. Cross-section D-D' is parallel to cross-section B-B' and extends through the stepped structure portion of conductor 72.

[0023] Figures 2 to 34C This is a view of an intermediate stage in the manufacture of a memory array 200 according to some embodiments. Along Figure 1A The reference cross section A-A' shown illustrates Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11B, Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B and Figure 24B Along Figure 1A The reference cross section B-B' shown illustrates Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A , Figure 32A , Figure 33A and Figure 34A Along Figure 1A The reference cross section C-C' shown illustrates Figure 20D , Figure 21D and Figure 34C Along Figure 1A The reference cross section D-D' shown illustrates Figure 22C , Figure 23C , Figure 24C , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B , Figure 32B , Figure 33B and Figure 34B . Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A and Figure 25C A top view is shown. Figure 24D , Figure 25B A perspective view is shown.

[0024] exist Figure 2 The diagram provides a substrate 50. Substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 can be an integrated circuit die, such as a logic die, a memory die, an ASIC die, etc. Substrate 50 can be a complementary metal-oxide-semiconductor (CMOS) die and may be referred to as under-array CMOS (CUA). Substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (typically a silicon or glass substrate). Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide; or combinations thereof.

[0025] Figure 2 Further illustration shows a circuit that can be formed on the substrate 50. The circuit includes a transistor at the top surface of the substrate 50. The transistor may include a gate dielectric layer 302 on the top surface of the substrate 50 and a gate electrode 304 on the gate dielectric layer 302. A source / drain region 306 is disposed in the substrate 50, located on opposite sides of the gate dielectric layer 302 and the gate electrode 304. A gate spacer 308 is formed along the sidewall of the gate dielectric layer 302 and separates the source / drain region 306 from the gate electrode 304 by an appropriate lateral distance. The transistor may include a fin field-effect transistor (FinFET), a nanostructure (e.g., nanosheet, nanowire, gate-around, etc.) FET (nanoFET), a planar FET, or a combination thereof, and may be formed by a pre-gate process or a post-gate process.

[0026] A first ILD 310 surrounds and isolates the source / drain region 306, the gate dielectric layer 302, and the gate electrode 304, and a second ILD 312 is located above the first ILD 310. A source / drain contact 314 extends through the second ILD 312 and the first ILD 310 and is electrically coupled to the source / drain region 306. A gate contact 316 extends through the second ILD 312 and is electrically coupled to the gate electrode 304. An interconnect structure 320 (including one or more stacked dielectric layers 324 and conductive features 322 formed in one or more dielectric layers 324) is located above the second ILD 312, the source / drain contact 314, and the gate contact 316. The interconnect structure 320 may be electrically connected to the gate contact 316 and the source / drain contact 314 to form functional circuitry. In some embodiments, the functional circuitry formed by the interconnect structure 320 may include logic circuitry, memory circuitry, a sense amplifier, a controller, input / output circuitry, image sensor circuitry, or combinations thereof. although Figure 2 Transistors formed on substrate 50 have been discussed, but other active devices (e.g., diodes, etc.) and / or passive devices (e.g., capacitors, resistors, etc.) can also be formed as part of the functional circuit. For simplicity and clarity, the transistors, ILDs, and interconnect structures 320 formed on substrate 50 can be omitted from the following figures. Substrate 50, together with transistors (e.g., source / drain regions 306, gate dielectric layer 302, and gate electrode 304), gate spacers 308, first ILD 310, second ILD 312, and interconnect structures 320, can be under-array CMOS (CUA), logic dies, etc.

[0027] exist Figure 3 In this configuration, a multilayer stack 58 is formed on the substrate 50. Although the multilayer stack 58 is shown in contact with the substrate 50, any number of intermediate layers can be disposed between the substrate 50 and the multilayer stack 58. For example, one or more interconnect layers including conductive features in an insulating layer (e.g., a low-k dielectric layer) can be disposed between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features can be patterned for use with the substrate 50 and / or the memory array 200 (see [link to documentation]). Figure 1A and Figure 1B The active devices on the device provide power, ground, and / or signal lines.

[0028] The multilayer stack 58 includes alternating layers of first material layers 52A-52D (collectively referred to as first material layer 52) and second material layers 54A-54C (collectively referred to as second material layer 54). In some embodiments, the second material layer 54 may be patterned in a subsequent step to define conductors 72 (e.g., word lines). In embodiments where the second material layer 54 is patterned to define conductors 72, the second material layer 54 may include a conductive material, such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, cobalt, silver, gold, nickel, chromium, hafnium, platinum, combinations thereof, etc. The first material layer 52 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, etc. In some embodiments, the second material layer 54 may be replaced by a conductive material in a subsequent step, the conductive material defining the conductors 72. In such embodiments, the second material layer 54 may also include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, etc., and may include a material with high etch selectivity to the material of the first material layer 52. In some embodiments, the first material layer 52 may comprise an oxide, such as silicon oxide, and the second material layer 54 may comprise a nitride, such as silicon nitride. The first material layer 52 and the second material layer 54 may each be formed using, for example, CVD, ALD, physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), etc. Although Figure 3 A specific number of first material layers 52 (e.g., 4) and second material layers 54 (e.g., 3) are shown, but other embodiments may include different numbers of first material layers 52 and second material layers 54.

[0029] Figures 4 to 8 This illustrates patterning of multiple stacks 58 to form a stepped structure 68 (in...) Figure 8 (As shown in the image). Figure 4 In this process, photoresist 56 is formed on top of the multilayer stack 58. The photoresist 56 can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Patterning the photoresist 56 can expose the multilayer stack 58 in region 60 while masking the rest of the multilayer stack 58. For example, the topmost layer of the multilayer stack 58 (e.g., the first material layer 52D) can be exposed in region 60.

[0030] exist Figure 5In this process, photoresist 56 is used as a mask to etch exposed portions of the multilayer stack 58 in region 60. Etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Etching can remove portions of the first material layer 52D and the second material layer 54C in region 60 and define an opening 61 along opposite edges of the multilayer stack 58. Because the first material layer 52 and the second material layer 54 have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, the second material layer 54C acts as an etch stop layer when the first material layer 52D is etched, and the first material layer 52C acts as an etch stop layer when the second material layer 54C is etched. Therefore, portions of the first material layer 52D and the second material layer 54C can be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 can extend to a desired depth. Alternatively, after the opening 61 reaches the desired depth, a timed etching process can be used to stop etching the opening 61. In the resulting structure, the first material layer 52C is exposed in region 60.

[0031] exist Figure 6 In this process, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. An acceptable photolithography technique can be used to trim the photoresist 56. As a result of the trimming, the width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in regions 60 and 62 are exposed. For example, the top surface of the first material layer 52D in region 62 and the top surface of the first material layer 52C in region 60 can be exposed.

[0032] The exposed portions of the multilayer stack 58 can then be etched using photoresist 56 as a mask. Etching can be any suitable etching process, such as wet or dry etching, RIE, NBE, etc., or combinations thereof. The etching process can be anisotropic. Etching can extend the opening 61 further into the multilayer stack 58. Because the first material layer 52 and the second material layer 54 have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, the second material layer 54 acts as an etch stop layer when the first material layer 52 is etched, and the first material layer 52 acts as an etch stop layer when the second material layer 54 is etched. Therefore, portions of the first material layer 52 and the second material layer 54 can be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 can extend to a desired depth. Alternatively, after the opening 61 reaches the desired depth, a timed etching process can be used to stop the etching of the opening 61. Furthermore, during the etching process, the unetched portions of the first material layer 52 and the second material layer 54 act as a mask for the underlying layers, thus the previous pattern of the first material layer 52D and the second material layer 54C (see...) Figure 5The material can be transferred to the lower first material layer 52C and the lower second material layer 54B. In the resulting structure, the first material layer 52C is exposed in region 62 and the first material layer 52B is exposed in region 60.

[0033] exist Figure 7 In this process, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist 56 can be trimmed using acceptable photolithography techniques. As a result of the trimming, the width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in regions 60, 62, and 64 are exposed. For example, the top surface of the first material layer 52D in region 64, the top surface of the first material layer 52C in region 62, and the top surface of the first material layer 52B in region 60 can be exposed.

[0034] The exposed portions of the multilayer stack 58 can then be etched using photoresist 56 as a mask. Etching can be any suitable etching process, such as wet or dry etching, RIE, NBE, etc., or combinations thereof. The etching process can be anisotropic. Etching can further extend the opening 61 into the multilayer stack 58. The second material layer 54 can act as an etch stop layer during the etching of the first material layer 52. Therefore, portions of the first material layer 52 can be selectively removed without removing the portion below the second material layer 54, and the opening 61 can extend to the desired depth. Alternatively, after the opening 61 reaches the desired depth, a timed etching process can be used to stop the etching of the opening 61. Furthermore, during the etching process, the unetched portions of the first material layer 52 and the second material layer 54 act as a mask for the underlying layers, thus the previous pattern of the first material layer 52D, the second material layer 54C, the first material layer 52C, and the second material layer 54B (see [link to previous pattern]). Figure 6 The material can be transferred to the lower first material layer 52B and the lower first material layer 52C. In the resulting structure, the second material layer 54C is exposed in region 64, the second material layer 54B is exposed in region 62, and the second material layer 54A is exposed in region 60.

[0035] exist Figure 8 In the process, photoresist 56 is removed. Photoresist 56 can be removed by an acceptable ashing or wet stripping process. This forms a stepped structure 68. The stepped structure 68 comprises a stack of alternating layers of a first material layer 52 and a second material layer 54. Figure 8 As shown, the stepped structure 68 allows portions of each of the second material layers 54A-54C to be exposed from the overlying second material layer 54 and the first material layer 52. Therefore, conductive contacts can be formed from above the stepped structure 68 to each of the second material layers 54 in subsequent processing steps.

[0036] exist Figure 9In this configuration, an intermetallic dielectric (IMD) 70 is deposited on a multilayer stack 58. The IMD 70 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, PECVD, flowable CVD (FCVD), etc. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. In some embodiments, the IMD 70 may include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), combinations thereof, etc. Other dielectric materials formed by any acceptable process may be used. The IMD 70 extends along the sidewalls of the first material layers 52B-52D, the sidewalls of the second material layers 54B and 54C, the top surface of the first material layer 52D, and the top surface of the second material layers 54A-54C.

[0037] exist Figure 10 In this process, a removal process is applied to IMD 70 to remove excess dielectric material atop the multilayer stack 58. In some embodiments, the removal process may be a planarization process, such as chemical mechanical polishing (CMP), etch-back, or a combination thereof. The planarization process exposes the multilayer stack 58 such that the top surfaces of the first material layer 52D and IMD 70 are flush after the planarization process is completed.

[0038] exist Figures 11A to 13C In the middle, trenches 86 are formed in the multi-layer stack 58 (in Figures 12A to 13C (As shown in the diagram). In embodiments where the second material layer 54 comprises a conductive material, a wire 72 is defined from the second material layer 54. The wire 72 may correspond to a word line in the memory array 200 and the wire 72 may provide a gate electrode for the resulting transistor 204 of the memory array 200. Figures 11A to 19C In the diagram, those ending in "A" show a top view, and those ending in "B" show a view along... Figure 1A A cross-sectional view of line A-A', and a diagram ending with "C" showing along... Figure 1A A cross-sectional view of line B-B'.

[0039] exist Figures 11A to 11CIn this process, a hard mask 80 is deposited on a multilayer stack 58 and an IMD 70. The hard mask 80 may include, for example, silicon nitride, silicon oxynitride, etc., which can be deposited by CVD, PVD, ALD, PECVD, etc. The hard mask 80 can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. A patterned photoresist 82 is formed on the hard mask 80. The patterned photoresist 82 can be formed by depositing a photosensitive layer on the hard mask 80 using a spin coating or the like. The photosensitive layer can then be patterned by exposing the photosensitive layer to a patterned energy source (e.g., a patterned light source) and developing the photosensitive layer to remove exposed or unexposed portions of the photosensitive layer, thereby forming the patterned photoresist 82. Trench 86 exposing the hard mask 80 is formed to extend through the patterned photoresist 82. The pattern of the patterned photoresist 82 corresponds to the wires to be formed in the multilayer stack 58, as will be explained below. Figures 12A to 12C Discussed.

[0040] exist Figures 12A to 12C In this process, a patterned photoresist 82 is used as a mask to pattern a hard mask 80 to extend trenches 86 through the hard mask 80. The hard mask 80 can be patterned using an acceptable etching process (e.g., wet or dry etching, RIE, NBE, etc., or combinations thereof). The etching can be anisotropic. Thus, trenches 86 extend through the hard mask 80 and expose a multilayer stack 58. The patterned photoresist 82 can then be removed using an acceptable process (e.g., wet etching, dry etching, or combinations thereof).

[0041] exist Figures 13A to 13C In this process, a hard mask 80 is used as a mask to pattern the multilayer stack 58 to extend trenches 86 through the multilayer stack 58, thereby exposing the substrate 50. The multilayer stack 58 can be patterned using one or more acceptable etching processes (e.g., wet or dry etching, RIE, NBE, etc., or combinations thereof). The etching process can be anisotropic. Therefore, trenches 86 extend through the multilayer stack 58. Second material layers 54A-54C are etched to form conductors 72A-72C (e.g., word lines, collectively referred to as conductors 72) from each corresponding layer of the second material layers 54. Trenches 86 separate adjacent conductors 72 and portions of the first material layer 52 from each other. Furthermore, in Figures 13A to 13C In this process, the hard mask 80 can be removed by an acceptable process (e.g., wet etching process, dry etching process, planarization process, combination thereof, etc.).

[0042] Figures 14A to 17C Transistor 204 is shown to be formed and patterned in trench 86 (see [link]). Figure 1A and 1B The trench area. Figures 14A to 14CIn the trench 86, the memory film 90 and the OS layer 92 are deposited. The memory film 90 can be conformally deposited in the trench 86 along the sidewalls of the wire 72, the first material layer 52 and the IMD 70, and along the top surface of the first material layer 52D and the IMD 70. The memory film 90 can be deposited by CVD, PVD, ALD, PECVD, etc.

[0043] The memory film 90 can provide a gate dielectric for the transistor 204 formed in the memory array 200. The memory film 90 can include a material capable of switching between two different polarization directions by applying an appropriate voltage difference across the memory film 90. The memory film 90 can be a high-k dielectric material, such as a hafnium (Hf)-based dielectric material. In some embodiments, the memory film 90 includes a ferroelectric (FE) material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, etc. In some embodiments, the memory film 90 can include different ferroelectric materials or different types of memory materials. In some embodiments, the memory film 90 can be a multilayer memory structure (e.g., an ONO structure) with two SiO layers. x The layers include a SiN layer. x .

[0044] OS layer 92 is conformally deposited in trench 86 above memory film 90. OS layer 92 includes transistors 204 (see [link]). Figure 1A and 1B The OS layer 92 provides the material for the trench region. For example, the OS layer 92 may include zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium tin oxide (ITO), polycrystalline silicon (poly-Si), silicon (Si), amorphous silicon (a-Si), and combinations thereof. The OS layer 92 can be deposited by CVD, PVD, ALD, PECVD, etc. The OS layer 92 may extend along the sidewalls and bottom surface of the trench 86 above the memory film 90.

[0045] exist Figures 15A to 15C In this process, the OS layer 92 is etched using a suitable etching process (e.g., anisotropic etching), which divides the OS layer 92 into multiple OS layers 92. Horizontal portions of the OS layer 92 (e.g., portions of the OS layer 92 extending along the top surface of the memory film 90) can be removed, while vertical portions of the OS layer 92 (e.g., portions of the OS layer 92 extending along the side surfaces of the memory film 90) are retained. The suitable etching process can be any acceptable etching process, such as wet or dry etching, RIE, NBE, or combinations thereof.

[0046] exist Figures 16A to 16CIn this process, a suitable etching process (e.g., anisotropic etching) is used to etch the memory film 90, which divides the memory film 90 into multiple memory films 90. Horizontal portions of the memory film 90 (e.g., portions of the memory film 90 extending along the top surface of the substrate 50 and the first material layer 52D) can be removed, while vertical portions of the memory film 90 (e.g., portions of the memory film 90 extending along the side surfaces of the wire 72, the first material layer 52, and the IMD 70) are retained. A suitable etching process can be any acceptable etching process, such as wet or dry etching, RIE, NBE, or combinations thereof. The OS layer 92 can mask some portions of the memory film 90 during the etching process, such that the memory film 90 is L-shaped after the etching process.

[0047] exist Figures 17A to 17C In this process, a dielectric material 98 is deposited to fill the remaining portion of the trench 86. The dielectric material 98 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which can be deposited by CVD, PVD, ALD, PECVD, etc. A removal process is applied to the dielectric material 98, OS layer 92, and memory film 90 to remove excess material on the conductor 72, first material layer 52, and IMD 70. In some embodiments, a planarization process, such as CMP, etch-back process, or a combination thereof, may be used. The planarization process exposes the top surfaces of IMD 70 and first material layer 52D such that after the planarization process is completed, the top surfaces of first material layer 52D, IMD 70, memory film 90, OS layer 92, and dielectric material 98 are flush with each other.

[0048] Figures 18A to 21D Intermediate steps in manufacturing dielectric material 102, wires 106 (e.g., bit lines), and wires 108 (e.g., source lines) in memory array 200 are illustrated. Wires 106 and 108 may extend in a direction perpendicular to wire 72, allowing individual memory cells 202 of memory array 200 to be selected for read and write operations.

[0049] exist Figures 18A to 18C In the memory array 90, trenches 100 are patterned using dielectric material 98 and OS layer 92. Trenches 100 can be patterned in dielectric material 98 and OS layer 92 using a combination of photolithography and etching. Etching can be any acceptable etching process, such as wet or dry etching, RIE, NBE, etc., or combinations thereof. Etching can be anisotropic. Trenches 100 can be disposed between opposite sidewalls of memory film 90, and trenches 100 can physically separate memory array 200 (see [link to documentation]). Figure 1AThe memory cells 202 are stacked adjacently in the memory array 200. The dielectric material 98 and the OS layer 92 can be completely removed in regions 60, 62, and 64 of the step structure 68 adjacent to the IMD 70, the conductor 72, and the first material layer 52. In some embodiments (not shown separately), the trench 100 can also be patterned by the memory film 90. In this way, the trench 100 can be disposed between the opposite sidewalls of the conductor 72 and the first material layer 52, and the trench 100 can physically separate the memory array 200 (see [link to documentation]). Figure 1A The adjacent stack of memory cells 202 in ).

[0050] exist Figures 19A to 19C In this structure, dielectric material 102 is deposited in and fills trench 100. Dielectric material 102 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, PVD, ALD, PECVD, etc. Dielectric material 102 may extend along the sidewalls and bottom surface of trench 100 above OS layer 92. After deposition, planarization processes (e.g., CMP, etch-back, etc.) may be performed to remove excess portions of dielectric material 102. In the resulting structure, the top surfaces of the first material layer 52D, memory film 90, OS layer 92, IMD 70, dielectric material 98, and dielectric material 102 may be substantially flush with each other (e.g., within process variations).

[0051] In some embodiments, the materials of dielectric material 98 and dielectric material 102 may be selected such that they can be selectively etched relative to each other. For example, in some embodiments, dielectric material 98 is an oxide and dielectric material 102 is a nitride. In some embodiments, dielectric material 98 is a nitride and dielectric material 102 is an oxide. Other materials are also possible.

[0052] Figure 20A A reference cross-section of the memory array 200 used in the following figures is shown. Cross-section A-A' is along the longitudinal axis of conductor 72 and in a direction parallel to, for example, the direction of current flowing through the OS layer 92 of transistor 204. Cross-section B-B' is perpendicular to cross-section A-A' and the longitudinal axis of conductor 72. Cross-section B-B' extends through dielectric material 98 and dielectric material 102. Cross-section C-C' is parallel to cross-section B-B' and extends through subsequently formed conductors (e.g., conductor 106, hereinafter referred to). Figures 21A to 21D (As discussed). For clarity, subsequent figures reference these reference cross sections. Figures 20A to 21D In the diagram, those ending in "A" show a top view, and those ending in "B" show a view along... Figure 20A A cross-sectional view of line A-A', the diagram ending with "C" shows the view along... Figure 20AA cross-sectional view of line B-B', and a diagram ending with "D" showing along... Figure 20A A cross-sectional view of line C-C'.

[0053] exist Figures 20A to 20D In the process, trenches 104 are patterned using dielectric material 98. Corresponding wires can then be formed using trenches 104. A combination of photolithography and etching can be used to pattern trenches 104 using dielectric material 98. Etching can be any acceptable etching process, such as wet or dry etching, RIE, NBE, etc., or combinations thereof. Etching can be anisotropic. Etching can use an etchant that etches dielectric material 98 without significantly etching dielectric material 102, OS layer 92, or memory film 90. The pattern of trenches 104 can correspond to subsequently formed conductors (e.g., conductors 106 and 108, as discussed below). Figures 21A to 21D (As discussed). A portion of the dielectric material 98 may remain between each pair of trenches 104, and the dielectric material 102 may be disposed between adjacent pairs of trenches 104. Furthermore, portions of the OS layer 92 and the memory film 90 may remain adjacent to the trench 104 between each of the first material layer 52 and the conductor 72. These portions of the OS layer 92 and the memory film 90 may be used as part of a subsequently formed transistor 204. In some embodiments, in contrast to the process used for patterning the trenches 100, a different etching may be used to pattern the trenches 104 to selectively etch the material of the dielectric material 98 relative to the OS layer 92 and the memory film 90.

[0054] exist Figures 21A to 21D In the structure, trench 104 is filled with conductive material to form wires 106 and 108. Memory cells 202 and transistors 204 are formed, each including portions of wires 106, 108, 72, a memory film 90, and an OS layer 92. Wires 106 and 108 may each comprise conductive materials such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, or combinations thereof. Wires 106 and 108 can be formed using, for example, CVD, ALD, PVD, PECVD, etc. After depositing the conductive material, planarization (e.g., CMP, etch-back, etc.) can be performed to remove excess conductive material, thereby forming wires 106 and 108. In the resulting structure, the top surfaces of the first material layer 52D, IMD 70, memory film 90, OS layer 92, dielectric material 98, dielectric material 102, wires 106, and wires 108 can be substantially flush with each other (e.g., within process variations).

[0055] Wire 106 may correspond to a bit line in memory array 200, and wire 108 may correspond to a source line in memory array 200. Furthermore, wires 106 and 108 may provide source / drain electrodes for transistors 204 in memory array 200. Although Figure 21D A cross-sectional view showing only conductor 106 is shown, but a similar cross-sectional view of conductor 108 may be shown.

[0056] Although the channel region, wires 106 and 108 of transistor 204 have been discussed as being formed after the formation of the step structure 68, in some embodiments, the step structure 68 may be formed after the formation of the channel region, wires 106 and 108 of transistor 204. For example, Figures 4 to 10 The text is incomplete and contains numerous errors. A more accurate translation would require the full context. Figures 4 to 10 The manufacturing steps described for forming the stepped structure 68 can be performed in... Figures 11A to 21D The text is incomplete and contains numerous errors. A more accurate translation would require the full context. Figures 11A to 21D The described manufacturing steps are performed afterward. The same or similar processes can be used in both the pre-step and post-step embodiments.

[0057] Figure 22A A reference cross-section of the memory array 200 used in the following figures is shown. Cross-section A-A' is along the longitudinal axis of conductor 72 and in a direction parallel, for example, to the direction of current flowing through the OS layer 92 of transistor 204. Cross-section D-D' is perpendicular to cross-section A-A' and the longitudinal axis of conductor 72. Cross-section D-D' extends through region 60 of the stepped structure 68. For clarity, subsequent figures refer to these reference cross-sections. Figures 22A to 24C In the diagram, those ending in "A" show a top view, and those ending in "B" show a view along... Figure 22A A cross-sectional view of line A-A', and a diagram ending with "C" showing along... Figure 22A A cross-sectional view of line D-D'.

[0058] exist Figures 22A to 22C In this process, a trench 110 is formed in the IMD 70. The trench 110 can then be used to form conductive contacts. More specifically, the trench 110 can subsequently be used to form conductive contacts (e.g., word line contacts, gate contacts, etc.) extending to the conductor 72. Figures 22A to 22C As shown, trench 110 can extend through IMD 70 and can expose the top surface of conductor 72. The stepped shape of conductor 72 provides a surface to which trench 110 can extend on each conductor 72. Trench 110 can be formed using a combination of photolithography and etching. Etching can be any acceptable etching process, such as wet or dry etching, RIE, NBE, etc., or combinations thereof. Etching can be anisotropic.

[0059] In some embodiments, the trenches 110 in the IMD 70 can be formed using a process with high etch selectivity for the material of the IMD 70. Therefore, the trenches 110 in the IMD 70 can be formed without significantly removing material from the conductors 72. In some embodiments, openings exposing each conductor 72A-72C can be formed simultaneously. Due to the varying thickness of the IMD 70 overlying each conductor 72A-72C, conductor 72C can be exposed to etching for a longer duration than conductor 72B, conductor 72B for a longer duration than conductor 72A, and conductor 72A for the shortest duration. Exposure to etching may cause some material loss, pitting, or other damage to the conductors 72, resulting in maximum damage to conductor 72C, less damage to conductor 72B, and minimum damage to conductor 72A. Forming the trenches 110 and exposing each conductor 72A-72C using the IMD 70 saves the cost and time associated with performing multiple masking and etching steps. However, some trenches 110 may not be sufficiently etched, leaving some conductors 72 unexposed. Therefore, test structures can be formed on top of the memory array 200 (e.g., as described below). Figures 24A to 24D The test structure 120 discussed is used to detect any faulty connections in the wire 72. This reduces device defects.

[0060] exist Figures 23A to 23C In this trench 110, conductive contacts 112 are formed. The conductive contacts 112 extend through the IMD 70 to each wire 72 and can be electrically coupled to the wire 72. In some embodiments, the conductive contacts 112 may be referred to as word line contacts, gate contacts, etc. The conductive contacts 112 can be formed by forming a pad (not shown separately), such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material in the trench 110. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the IMD 70. The remaining pad and conductive material form the conductive contacts 112 in the trench 110. Figure 23B and Figure 23C As shown, the conductive contact 112 can extend to each wire 72A-72C.

[0061] exist Figures 24A to 24D In this process, a first dielectric layer 114, a conductive contact 116, a second dielectric layer 115, and a wire 118 are formed. Figures 23A to 23CThe structure is built upon the conductive contact 112, conductive contact 116, and wire 118 together form the test structure 120. The first dielectric layer 114 and the second dielectric layer 115 may include dielectric materials, such as low-k dielectric materials, ultra-low-k (ELK) dielectric materials, etc. In some embodiments, the first dielectric layer 114 and the second dielectric layer 115 may include insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, etc. The first dielectric layer 114 and the second dielectric layer 115 may be deposited using appropriate processes (e.g., CVD, ALD, PVD, PECVD, etc.).

[0062] Trenches (not shown separately) are formed through the second dielectric layer 115 and the first dielectric layer 114, which can be used to form conductive contacts 116 and wires 118. The trenches in the second dielectric layer 115 expose the top surface of the first dielectric layer 114, and the trenches in the first dielectric layer 114 expose the top surface of the conductive contacts 112. The trenches can be formed using a combination of photolithography and etching. Etching can be any acceptable etching process, such as wet or dry etching, RIE, NBE, etc., or combinations thereof. Etching can be anisotropic. The trenches in the second dielectric layer 115 and the first dielectric layer 114 can be formed using a variety of etching processes.

[0063] Conductive contacts 116 and wires 118 are then formed in trenches in the first dielectric layer 114 and the second dielectric layer 115, respectively. The conductive contacts 116 and wires 118 can be formed by forming a pad (not shown separately), such as a diffusion barrier layer or an adhesive layer, and then forming a conductive material on top of the pad. The conductive contacts 116 and wires 118 can be formed simultaneously or separately using one or more deposition processes. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the second dielectric layer 115.

[0064] Figure 24D A perspective view of the resulting structure is shown, which includes wire 72, conductive contact 112, conductive contact 116 and wire 118, while other structures are omitted in order to show the relationship between wire 72, conductive contact 112, conductive contact 116 and wire 118 more clearly. Figures 24A to 24DThe conductive path through test structure 120 is further illustrated. The conductive path can extend from the outside of memory array 200 to memory array 200 (at point 1). The conductive path extends through wire 118, conductive contact 116, and conductive contact 112 to wire 72A. The conductive path then extends through conductive contact 112, conductive contact 116, and wire 118, reaching wire 72B via points 2 and 3. The conductive path continues through memory array 200 to point 24, which extends to the outside of memory array 200. Each wire 72 is connected to a first vertically adjacent wire 72 and one of the following: a second vertically adjacent wire 72 (e.g., wire 72B connected to wires 72A and 72C), a horizontally adjacent wire 72 (e.g., wire 72C connected to wires 72B and 72C), or a connection to the outside of memory array 200 (e.g., wire 72A connected to wire 72B and an external connection). Wire 118 includes wires 118 extending in a direction parallel to the longitudinal axis of wire 72 and connecting to vertically adjacent wires 72. The wire 118 also includes a wire 118 that extends in a direction perpendicular to the longitudinal axis of the wire 72 and connects to horizontally adjacent wires 72 or provides connections to the outside of the memory array 200.

[0065] The test configuration can be used to determine if any connection between the conductive contacts 116 is faulty. For example, a bias voltage can be applied to the memory array 200 at points 1 and 24. Because the conductive path extends through all the wires 72, conductive contacts 112, conductive contacts 116, and wires 118 in the memory array 200, current measurements can be performed to determine if any faulty connections exist. Therefore, the memory array 200 with faulty connections can be shielded, and device defects can be avoided. Furthermore, as discussed above, the conductive contacts 112 and trenches 110 connected to each wire 72A-72C can be formed simultaneously, which reduces cost, shortens manufacturing time, and increases device yield.

[0066] Figures 25A to 25C The lines used to separate the various memory arrays 200 are shown. Figure 25A A top view of four memory arrays 200 is shown; Figure 25B A perspective view of two memory arrays 200 is shown; and Figure 25C A top view of a wafer 300 comprising multiple memory arrays 200 is shown. The memory arrays 200 are arranged in a grid pattern within the wafer 300, which can be centered on the wafer 300. Individual memory arrays 200 are separated by scribe lines, which are subsequently cut by sawing along the scribe lines. Figure 25A and Figure 25BAs shown, the scribe line can extend through at least some of the conductors 118 (e.g., conductors 118 extending in a direction perpendicular to the longitudinal axis of conductor 72), such that conductor 118 is subsequently bisected. Figure 25C As shown, the scribing can be set in a region 301 between adjacent memory arrays 200, which is removed by cutting. At least some portions of the test structure 120 can extend over region 301, and these portions of the test structure 120 can be removed by cutting. Figure 25C A defective memory array 200D is further illustrated, which can be detected and removed using the corresponding test structure 120. This reduces device defects.

[0067] Figures 26A to 34C An embodiment is shown in which the second material layer 54 comprises a sacrificial material replaced by a conductive material. Figures 26A to 34C In the diagram, those ending with "A" indicate the route along... Figure 1A A cross-sectional view of line B-B', the diagram ending with "B" shows along... Figure 1A A cross-sectional view of line D-D', and a diagram ending with "C" showing along... Figure 1A A cross-sectional view of line C-C'.

[0068] Figure 26A and Figure 26B It shows the execution with Figures 3 to 10 The steps shown are similar or identical to those discussed above to form the stepped structure 68 and the multilayer stack 58 following the IMD 70 on top of the stepped structure 68. The multilayer stack 58 comprises alternating layers of first material layers 52A-52D (collectively referred to as first material layers 52) and second material layers 54A-54C (collectively referred to as second material layers 54). The second material layers 54 may be replaced with a conductive material in subsequent steps to define the conductor 422 (e.g., word lines). Figures 33A to 34C (As shown in the diagram). The second material layer 54 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The first material layer 52 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The first material layer 52 may be formed of a material with high etch selectivity for etching the second material layer 54, and the substrate 50 may be formed of a material with high etch selectivity for etching both the second material layer 54 and the first material layer 52 to aid in subsequent etching steps. In some embodiments, the substrate 50 may be formed of silicon carbide, the first material layer 52 may be formed of an oxide such as silicon oxide, and the second material layer 54 may be formed of a nitride such as silicon nitride. The second material layer 54 and the first material layer 52 may each be formed using, for example, CVD, ALD, physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), etc. Although Figure 26A and Figure 26B A specific number of second material layers 54 and first material layers 52 are shown, but other embodiments may include different numbers of second material layers 54 and first material layers 52.

[0069] Further in Figure 26A and Figure 26B In this process, a first patterned photoresist 400 is formed on a multilayer stack 58, and a first trench 402 extending through the multilayer stack 58 is formed. The first patterned photoresist 400 can be formed by depositing a photosensitive layer on a first material layer 52D using spin coating or the like. The photosensitive layer can then be patterned by exposing the photosensitive layer to a patterned energy source (e.g., a patterned light source) and developing the photosensitive layer to remove exposed or unexposed portions of the photosensitive layer, thereby forming the first patterned photoresist 400.

[0070] In the illustrated embodiment, the first trench 402 extends through the multilayer stack 58 to expose the substrate 50. In some embodiments, the first trench 402 extends through some, but not all, layers of the multilayer stack 58. The first trench 402 can be formed using acceptable photolithography and etching techniques, such as an etching process selective for the multilayer stack 58 (e.g., etching the materials of the first material layer 52 and the second material layer 54 at a faster rate than the material of the substrate 50). The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. In embodiments where the substrate 50 is formed of silicon carbide, the first material layer 52 is formed of silicon oxide, and the second material layer 54 is formed of silicon nitride, the first trench 402 can be formed by dry etching using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (H2) or oxygen (O2).

[0071] exist Figure 27A and Figure 27BIn this embodiment, the first trench 402 is extended to form a first sidewall recess 404. Specifically, the portion of the sidewall of the second material layer 54 exposed by the first trench 402 is recessed to form the first sidewall recess 404. Although the sidewall of the second material layer 54 is shown as straight, the sidewall can be recessed or convex. The first sidewall recess 404 can be formed by an acceptable etching process, such as a process selective for the material of the second material layer 54 (e.g., selectively etching the material of the second material layer 54 at a faster rate compared to the materials of the first material layer 52 and the substrate 50). The etching can be isotropic. In an embodiment where the substrate 50 is formed of silicon carbide, the first material layer 52 is formed of silicon oxide, and the second material layer 54 is formed of silicon nitride, the first trench 402 can be extended by wet etching using phosphoric acid (H3PO4). However, any suitable etching process, such as dry selective etching, can also be used. Before or after the formation of the first sidewall groove 404, the first patterned photoresist 400 can be removed by an acceptable ashing or wet stripping process.

[0072] exist Figure 28A and Figure 28B In this embodiment, conductive material 406 and sacrificial material 408 are formed in the first sidewall recess 404 and fill and / or overfill the first trench 402. One or more additional layers (e.g., seed layer, adhesive layer, barrier layer, diffusion layer, filler layer, etc.) may also fill the first trench 402 and the first sidewall recess 404. In some embodiments, sacrificial material 408 may be omitted. In embodiments including a seed layer, the seed layer may comprise titanium nitride, tantalum nitride, titanium, tantalum, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations thereof, oxides thereof, etc. The conductive material 406 may be formed of a conductive material, which may be a metal, such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum nitride, alloys thereof, etc. In embodiments where the first material layer 52 is formed of an oxide such as silicon oxide, the seed layer may be formed of titanium nitride and the conductive material 406 may be formed of tungsten. The sacrificial material 408 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The sacrificial material 408 may include materials with high etch selectivity to the materials of the first material layer 52, the conductive material 406, and the substrate 50, such that the sacrificial material 408 can be subsequently removed without removing or damaging the first material layer 52, the conductive material 406, or the substrate 50. The conductive material 406 and the sacrificial material 408 may each be formed by an acceptable deposition process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.).

[0073] Once the conductive material 406 and sacrificial material 408 have been deposited to fill and / or overfill the first trench 402, the conductive material 406 and sacrificial material 408 can be planarized to remove excess material outside the first trench 402, such that after planarization, the conductive material 406 and sacrificial material 408 completely extend across the top of the first trench 402. In one embodiment, the conductive material 406 and sacrificial material 408 can be planarized using, for example, a chemical mechanical planarization (CMP) process. However, any suitable planarization process, such as a polishing process, can also be used.

[0074] exist Figure 29A and Figure 29B In this process, a second patterned photoresist 410 is formed on the multilayer stack 58, and a second trench 412 extending through the multilayer stack 58 is formed. The second patterned photoresist 410 can be formed by depositing a photosensitive layer on the first material layer 52D using spin coating or the like. The photosensitive layer can then be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing the photosensitive layer to remove exposed or unexposed portions of the photosensitive layer, thereby forming the second patterned photoresist 410.

[0075] In the illustrated embodiment, the second trench 412 extends through the multilayer stack 58 to expose the substrate 50. In some embodiments, the second trench 412 extends through some, but not all, layers of the multilayer stack 58. The second trench 412 can be formed using acceptable photolithography and etching techniques, such as an etching process selective for the multilayer stack 58 (e.g., etching the materials of the first material layer 52 and the second material layer 54 at a faster rate than the material of the substrate 50). The etching can be any acceptable etching process, such as RIE, NBE, or combinations thereof. The etching can be anisotropic. In embodiments where the substrate 50 is formed of silicon carbide, the first material layer 52 is formed of silicon oxide, and the second material layer 54 is formed of silicon nitride, the second trench 412 can be formed by dry etching using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (H2) or oxygen (O2).

[0076] exist Figure 30A and Figure 30BIn this process, the second trench 412 is extended to form a second sidewall recess 414. Specifically, the remaining portion of the second material layer 54 is removed to form the second sidewall recess 414. The second sidewall recess 414 thus exposes some portions of the conductive material 406. The second sidewall recess 414 can be formed by an acceptable etching process, such as a process that is selective to the material of the second material layer 54 (e.g., selectively etching the material of the second material layer 54 at a faster rate compared to the materials of the first material layer 52 and the substrate 50). The etching can be any acceptable etching process, and in some embodiments, it can be similar to the process described above. Figure 27A and Figure 27B The etching discussed is for forming the first sidewall recess 404. Before or after forming the second sidewall recess 414, the second patterned photoresist 410 can be removed by an acceptable ashing or wet stripping process.

[0077] exist Figure 31A and Figure 31B In this embodiment, conductive material 416 and sacrificial material 418 are formed in the second sidewall groove 414 and fill and / or overfill the second trench 412. One or more additional layers (e.g., seed layer, adhesive layer, barrier layer, diffusion layer, filler layer, etc.) may also fill the second trench 412 and the second sidewall groove 414. In some embodiments, sacrificial material 418 may be omitted. In embodiments including a seed layer, the seed layer may comprise titanium nitride, tantalum nitride, titanium, tantalum, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations thereof, oxides thereof, etc. Conductive material 416 may be formed of a conductive material, which may be a metal, such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum nitride, alloys thereof, etc. In embodiments where the first material layer 52 is formed of an oxide such as silicon oxide, the seed layer may be formed of titanium nitride and the conductive material 416 may be formed of tungsten. Sacrificial material 418 may comprise an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, etc. The sacrificial material 418 may include a material that has high etch selectivity to the materials of the first material layer 52, the conductive material 416, and the substrate 50, such that the sacrificial material 418 can be subsequently removed without removing or damaging the first material layer 52, the conductive material 416, or the substrate 50. The conductive material 416 and the sacrificial material 418 may each be formed by an acceptable deposition process (e.g., CVD, ALD, PVD, etc.).

[0078] Once the conductive material 416 and sacrificial material 418 have been deposited to fill and / or overfill the second trench 412, the conductive material 416 and sacrificial material 418 can be planarized to remove excess material outside the second trench 412, such that after planarization, the conductive material 416 and sacrificial material 418 completely extend across the top of the second trench 412. In one embodiment, the conductive material 416 and sacrificial material 418 can be planarized using, for example, a CMP process. However, any suitable planarization process, such as a polishing process, can also be used.

[0079] exist Figure 32A and Figure 32B In this process, sacrificial materials 408 and 418 can be removed using an acceptable process for forming the third trench 420. Acceptable processes can include wet etching, dry etching, or combinations thereof. In some embodiments, sacrificial materials 408 and 418 can be removed using an isotropic etching process, which is selective for the materials of sacrificial materials 408 and 418. Therefore, sacrificial materials 408 and 418 can be removed without removing or damaging the first material layer 52, conductive material 406, conductive material 416, or substrate 50.

[0080] exist Figure 33A and Figure 33B In this process, conductive materials 406 and 416 are etched to extend a third trench 420 and conductors 422A-422C (e.g., word lines, collectively referred to as conductors 422) are formed from each corresponding layer of conductive materials 406 and 416. The third trench 420 separates adjacent conductors 422 and portions of the first material layer 52 from each other. Because conductors 422 are formed from adjacent portions of conductive materials 406 and 416, each conductor 422 may include a seam, such as... Figure 33A and Figure 33B As shown. Etching conductive materials 406 and 416 to widen the third trench 420 can expose the sidewalls of the first material layer 52. In some embodiments, an anisotropic etching process, for example, can be used to etch conductive materials 406 and 416. However, any suitable etching process can be used. In some embodiments, the etching process is performed until the material of conductive materials 406 and 416 extending beyond the sidewalls of the first material layer 52 has been removed and the sidewalls of conductive materials 406 and 416 are flush with the sidewalls of the first material layer 52. Therefore, the wire 422 can have a similar or the same width as the first material layer 52. Although the sidewalls of the wire 422 are shown as straight, the sidewalls can be recessed or convex.

[0081] By forming and replacing the second material layer 54 in the multilayer stack 58 to form the wires 422, the aspect ratio of the columns of the memory array 200 is improved, and distortion or collapse of features during formation is prevented. This reduces device defects and improves device performance. Figures 26A to 33B The steps performed in the middle can be replaced Figures 11A to 13C The steps are executed in accordance with those discussed above (e.g., Figures 3 to 13C The remaining steps for forming memory array 200 are the same as those performed in the previous steps, and then the following steps are performed: Figures 26A to 33B The steps executed in the middle, and finally executed. Figures 14B to 24D The steps to be performed.

[0082] Figures 34A to 34C It shows the execution Figures 14B to 24D After the steps Figures 26A to 33B Examples of implementations. Figure 34B The structure can be similar to Figure 24C The structure shown is different except that the conductor 72 is replaced by a conductor 422 formed of conductive materials 406 and 416.

[0083] The embodiments can achieve various advantages. For example, simultaneously forming trenches 110 extending to conductors 72A-72C and simultaneously forming conductive contacts 112 in trenches 110 reduces production time, lowers costs associated with additional patterning processes, and increases yield. Test structures 120 can be formed on the memory array 200 to inspect for faulty connections. Therefore, defective memory arrays 200 can be removed and device defects can be reduced.

[0084] According to one embodiment, a memory array includes: a first word line located on a semiconductor substrate, the vertical axis of the first word line extending in a first direction; a second word line located on the first word line in a second direction perpendicular to the main surface of the semiconductor substrate, the vertical axis of the second word line extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first word line, the memory film being located between each of the first word line and the second word line and the OS layer; and a test structure located on the first word line and the second word line, the test structure including a first conductor electrically coupling the first word line to the second word line, the vertical axis of the first conductor extending in the first direction. In one embodiment, the first word line has a first length greater than a second length of the second word line. In one embodiment, the test structure further includes a second conductor electrically coupled to the first word line, the second conductor extending to a boundary of the memory array, and the vertical axis of the second conductor extending in the first direction. In one embodiment, the device further includes: a third word line adjacent to the first word line in a third direction perpendicular to the first direction; a memory film and an OS layer located between the first and third word lines in the third direction; and a test structure further includes a second conductor electrically coupling the first word line to the third word line, the second conductor having its longitudinal axis extending in the third direction. In one embodiment, the first word line includes a seam located between a first conductive material and a second conductive material. In another embodiment, the device further includes: a third word line located below the first word line in a second direction, the longitudinal axis of the third word line extending in the first direction; and a test structure further includes a second conductor electrically coupling the first word line to the third word line, the longitudinal axis of the second conductor extending in the first direction. In one embodiment, the first word line has a first length greater than the second length of the second word line, and the third word line has a third length greater than the first length.

[0085] According to another embodiment, a device includes: a first word line located on a semiconductor substrate, the first word line having a first length in a first direction; a second word line located on the semiconductor substrate, the second word line having a second length in the first direction, the second length being equal to the first length; a first intermetallic dielectric (IMD) located on the first word line; a first memory film contacting the first word line and the first IMD; a first oxide semiconductor (OS) layer located on the first memory film, the first OS layer contacting a source line and a bit line; a first conductive contact extending through the first IMD and electrically coupled to the first word line; a second conductive contact electrically coupled to the second word line; and a first wire extending on the first IMD and electrically coupling the first conductive contact to the second conductive contact, the first wire extending in a second direction perpendicular to the first direction. In one embodiment, a first distance between the first word line and the semiconductor substrate in a third direction perpendicular to the main surface of the semiconductor substrate is equal to a second distance between the second word line and the semiconductor substrate in a third direction. In one embodiment, the IMD has a stepped structure in a cross-sectional view. In one embodiment, the device further includes: a second memory film in contact with a second word line; a second OS layer located above the second memory film, the second OS layer contacting a source line and a bit line; and a first dielectric material separating the first OS layer from the second OS layer. In one embodiment, the device further includes: a second IMD located above the second word line, the second memory film in contact with the second IMD; and a second dielectric material separating the first IMD from the second IMD, the second dielectric material comprising a material different from the first dielectric material. In one embodiment, the device further includes: a third word line located above a semiconductor substrate, the third word line having a third length in a first direction, the third length being different from the first length and the second length; a third conductive contact electrically coupled to the first word line; a fourth conductive contact electrically coupled to the third word line; and a second wire electrically coupling the third conductive contact to the fourth conductive contact, the second wire extending in the first direction. In one embodiment, the first OS layer is located between the first conductive contact and the third conductive contact in the first direction.

[0086] According to another embodiment, a method includes: depositing a multilayer stack on a semiconductor substrate, the multilayer stack including alternating layers of a first material and a second material; patterning the multilayer stack such that the multilayer stack includes a stepped structure in a cross-sectional view; forming an intermetallic dielectric (IMD) on the stepped structure of the multilayer stack; forming a plurality of word lines in the multilayer stack; depositing a memory film adjacent to the plurality of word lines in the multilayer stack; depositing an oxide semiconductor (OS) layer on the memory film; etching the IMD to form a first opening exposing a first word line among the plurality of word lines and a second opening exposing a second word line among the plurality of word lines, the first opening extending to a first depth and the second opening extending to a second depth different from the first depth; forming a first conductive contact electrically coupled to the first word line in the first opening and forming a second conductive contact electrically coupled to the second word line in the second opening; and forming a first wire on the IMD, the first conductive contact and the second conductive contact, the first conductive contact electrically coupling the first conductive contact to the second conductive contact. In one embodiment, the first wire, the first word line and the second word line extend in a first direction. In one embodiment, the method further includes etching an IMD to form a third opening exposing a first word line and a fourth opening exposing a third word line among a plurality of word lines, the third and fourth openings extending to a first depth; forming a third conductive contact electrically coupled to the first word line in the third opening and a fourth conductive contact electrically coupled to the third word line in the fourth opening; and forming a second conductor over the IMD, the third conductive contact, and the fourth conductive contact, the second conductor electrically coupling the third conductive contact to the fourth conductive contact. In one embodiment, the first word line and the second word line extend in a first direction, and the second conductor extends in a second direction perpendicular to the first direction. In one embodiment, the first material comprises a dielectric material, the second material comprises a conductive material, and forming a plurality of word lines in a multilayer stack includes patterning the multilayer stack to separate adjacent word lines formed of the second material. In one embodiment, the first material comprises an oxide, the second material comprises a nitride, and forming a plurality of word lines in a multilayer stack includes patterning the multilayer stack and replacing the second material with a conductive material.

[0087] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0088] Example 1 is a memory array comprising: a first word line located on a semiconductor substrate, wherein the longitudinal axis of the first word line extends in a first direction; a second word line located on the first word line in a second direction perpendicular to a main surface of the semiconductor substrate, wherein the longitudinal axis of the second word line extends in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, wherein the memory film is located between each of the first word line and the second word line and the OS layer; and a test structure located on the first word line and the second word line, the test structure including a first conductor electrically coupling the first word line to the second word line, wherein the longitudinal axis of the first conductor extends in the first direction.

[0089] Example 2 is the memory array described in Example 1, wherein the first word line has a first length that is greater than the second length of the second word line.

[0090] Example 3 is the memory array described in Example 1, wherein the test structure further includes a second wire, wherein the second wire is electrically coupled to the first word line, wherein the second wire extends to the boundary of the memory array, and wherein the longitudinal axis of the second wire extends in the first direction.

[0091] Example 4 is the memory array described in Example 1, further comprising: a third word line adjacent to the first word line in a third direction perpendicular to the first direction, wherein the memory film and the OS layer are located between the first word line and the third word line in the third direction, wherein the test structure further comprises a second wire, wherein the second wire electrically couples the first word line to the third word line, and wherein the longitudinal axis of the second wire extends in the third direction.

[0092] Example 5 is the memory array described in Example 1, wherein the first word line includes a seam located between a first conductive material and a second conductive material.

[0093] Example 6 is the memory array described in Example 1, further comprising: a third word line located below the first word line in the second direction, wherein the longitudinal axis of the third word line extends in the first direction, wherein the test structure further comprises a second conductor electrically coupling the first word line to the third word line, wherein the longitudinal axis of the second conductor extends in the first direction.

[0094] Example 7 is the memory array described in Example 6, wherein the first word line has a first length greater than the second length of the second word line, and wherein the third word line has a third length greater than the first length.

[0095] Example 8 is a semiconductor device comprising: a first word line located on a semiconductor substrate having a first length in a first direction; a second word line located on the semiconductor substrate having a second length in the first direction, wherein the second length is equal to the first length; a first intermetallic dielectric (IMD) located on the first word line; a first memory film contacting the first word line and the first IMD; a first oxide semiconductor (OS) layer located on the first memory film, the first OS layer contacting a source line and a bit line; a first conductive contact extending through the first IMD and electrically coupled to the first word line; a second conductive contact electrically coupled to the second word line; and a first wire extending on the first IMD and electrically coupling the first conductive contact to the second conductive contact, wherein the first wire extends in a second direction perpendicular to the first direction.

[0096] Example 9 is the device described in Example 8, wherein a first distance between the first word line and the semiconductor substrate in a third direction perpendicular to the main surface of the semiconductor substrate is equal to a second distance between the second word line and the semiconductor substrate in the third direction.

[0097] Example 10 is the device described in Example 8, wherein the IMD has a stepped structure in a cross-sectional view.

[0098] Example 11 is the device described in Example 8, further comprising: a second memory film in contact with the second word line; a second OS layer located on the second memory film, the second OS layer contacting the source line and the bit line; and a first dielectric material separating the first OS layer from the second OS layer.

[0099] Example 12 is the device described in Example 11, further comprising: a second IMD located above the second word line, wherein the second memory film is in contact with the second IMD; and a second dielectric material separating the first IMD from the second IMD, the second dielectric material comprising a material different from the first dielectric material.

[0100] Example 13 is the device described in Example 8, further comprising: a third word line located on the semiconductor substrate, the third word line having a third length in the first direction, wherein the third length is different from the first length and the second length; a third conductive contact electrically coupled to the first word line; a fourth conductive contact electrically coupled to the third word line; and a second wire electrically coupling the third conductive contact to the fourth conductive contact, wherein the second wire extends in the first direction.

[0101] Example 14 is the device described in Example 13, wherein the first OS layer is located between the first conductive contact and the third conductive contact in the first direction.

[0102] Example 15 is a method of forming a semiconductor device, comprising: depositing a multilayer stack on a semiconductor substrate, the multilayer stack including alternating layers of a first material and a second material; patterning the multilayer stack such that the multilayer stack includes a stepped structure in a cross-sectional view; forming an intermetallic dielectric (IMD) on the stepped structure of the multilayer stack; forming a plurality of word lines in the multilayer stack; depositing a memory film adjacent to the plurality of word lines in the multilayer stack; depositing an oxide semiconductor (OS) layer on the memory film; etching the IMD to form a first opening exposing a first word line among the plurality of word lines and a second opening exposing a second word line among the plurality of word lines, wherein the first opening extends to a first depth, and wherein the second opening extends to a second depth different from the first depth; forming a first conductive contact electrically coupled to the first word line in the first opening, and forming a second conductive contact electrically coupled to the second word line in the second opening; and forming a first wire on the IMD, the first conductive contact, and the second conductive contact, wherein the first wire electrically couples the first conductive contact to the second conductive contact.

[0103] Example 16 is the method described in Example 15, wherein the first wire, the first word line, and the second word line extend in a first direction.

[0104] Example 17 is the method of Example 15, further comprising: etching the IMD to form a third opening exposing the first word line and a fourth opening exposing a third word line among the plurality of word lines, wherein the third opening and the fourth opening extend to the first depth; forming a third conductive contact electrically coupled to the first word line in the third opening, and forming a fourth conductive contact electrically coupled to the third word line in the fourth opening; and forming a second conductor over the IMD, the third conductive contact, and the fourth conductive contact, wherein the second conductor electrically couples the third conductive contact to the fourth conductive contact.

[0105] Example 18 is the method described in Example 17, wherein the first word line and the second word line extend in a first direction, and wherein the second wire extends in a second direction perpendicular to the first direction.

[0106] Example 19 is a method of Example 15, wherein the first material comprises a dielectric material, wherein the second material comprises a conductive material, and wherein forming the plurality of word lines in the multilayer stack comprises patterning the multilayer stack to separate adjacent word lines formed by the second material.

[0107] Example 20 is the method of Example 15, wherein the first material comprises an oxide, wherein the second material comprises a nitride, and wherein forming the plurality of word lines in the multilayer stack comprises: patterning the multilayer stack and replacing the second material with a conductive material.

Claims

1. A memory array, comprising: A first word line is located on a semiconductor substrate, wherein the vertical axis of the first word line extends in a first direction; The second word line is located above the first word line in a second direction perpendicular to the main surface of the semiconductor substrate, wherein the longitudinal axis of the second word line extends in the first direction; The memory film contacts the first word line and the second word line; An oxide semiconductor OS layer contacts a first source line and a first bit line, wherein the memory film is located between the OS layer and each of the first word line and the second word line; as well as A test structure is located above the first word line and the second word line, the test structure including a first conductor electrically coupling the first word line to the second word line, wherein the longitudinal axis of the first conductor extends in the first direction.

2. The memory array of claim 1, wherein, The first character line has a first length that is greater than the second length of the second character line.

3. The memory array as described in claim 1, wherein, The test structure further includes a second conductor, wherein the second conductor is electrically coupled to the first word line, wherein the second conductor extends to the boundary of the memory array, and wherein the longitudinal axis of the second conductor extends in the first direction.

4. The memory array of claim 1, further comprising: A third word line is adjacent to the first word line in a third direction perpendicular to the first direction, wherein the memory film and the OS layer are located between the first word line and the third word line in the third direction, wherein the test structure further includes a second wire, wherein the second wire electrically couples the first word line to the third word line, and wherein the longitudinal axis of the second wire extends in the third direction.

5. The memory array as claimed in claim 1, wherein, The first word line includes a seam located between a first conductive material and a second conductive material.

6. The memory array of claim 1, further comprising: A third word line is located below the first word line in the second direction, wherein the longitudinal axis of the third word line extends in the first direction, and wherein the test structure further includes a second conductor electrically coupling the first word line to the third word line, wherein the longitudinal axis of the second conductor extends in the first direction.

7. The memory array of claim 6, wherein, The first character line has a first length greater than the second character line's second length, and the third character line has a third length greater than the first length.

8. A semiconductor device, comprising: A first word line is located on a semiconductor substrate, and the first word line has a first length in a first direction; A second word line is located on the semiconductor substrate, and the second word line has a second length in the first direction, wherein the second length is equal to the first length. The first intermetallic dielectric IMD is located above the first word line; A first memory film is in contact with the first word line and the first intermetallic dielectric (IMD). A first oxide semiconductor OS layer is located on the first memory film, and the first oxide semiconductor OS layer contacts the source line and the bit line; A first conductive contact extends through the first intermetallic dielectric (IMD) and is electrically coupled to the first word line; The second conductive contact is electrically coupled to the second word line; as well as A first conductor extends over the first intermetallic dielectric (IMD) and electrically couples the first conductive contact to the second conductive contact, wherein the first conductor extends in a second direction perpendicular to the first direction.

9. The device as claimed in claim 8, wherein, The first distance between the first word line and the semiconductor substrate in a third direction perpendicular to the main surface of the semiconductor substrate is equal to the second distance between the second word line and the semiconductor substrate in the same third direction.

10. The device of claim 8, wherein, The first intermetallic dielectric (IMD) has a stepped structure in a cross-sectional view.

11. The device of claim 8, further comprising: The second memory film is in contact with the second word line; The second OS layer is located above the second memory film, and the second OS layer contacts the source line and the bit line; as well as A first dielectric material separates the first oxide semiconductor OS layer from the second OS layer.

12. The device of claim 11, further comprising: The second IMD is located above the second word line, wherein the second memory film is in contact with the second IMD; and A second dielectric material separates the first intermetallic dielectric (IMD) from the second IMD, and the second dielectric material includes a material different from the first dielectric material.

13. The device of claim 8, further comprising: A third word line is located on the semiconductor substrate, and the third word line has a third length in the first direction, wherein the third length is different from the first length and the second length; The third conductive contact is electrically coupled to the first word line; The fourth conductive contact is electrically coupled to the third word line; as well as A second conductor electrically couples the third conductive contact to the fourth conductive contact, wherein the second conductor extends in the first direction.

14. The device of claim 13, wherein, The first oxide semiconductor OS layer is located between the first conductive contact and the third conductive contact in the first direction.

15. A method of forming a semiconductor device, comprising: A multilayer stack is deposited on a semiconductor substrate, the multilayer stack comprising alternating layers of a first material and a second material; The multi-layer stack is patterned such that the multi-layer stack includes a stepped structure in a cross-sectional view; An intermetallic dielectric (IMD) is formed on the multilayer stacked stepped structure; Multiple word lines are formed in the multi-layer stack; A memory film adjacent to the multiple word lines is deposited in the multilayer stack; An oxide semiconductor OS layer is deposited on the memory film; The IMD is etched to form a first opening that exposes a first word line among the plurality of word lines and a second opening that exposes a second word line among the plurality of word lines, wherein the first opening extends to a first depth and wherein the second opening extends to a second depth different from the first depth; A first conductive contact electrically coupled to the first word line is formed in the first opening, and a second conductive contact electrically coupled to the second word line is formed in the second opening; as well as A first conductor is formed on the IMD, the first conductive contact, and the second conductive contact, wherein the first conductor electrically couples the first conductive contact to the second conductive contact.

16. The method of claim 15, wherein, The first conductor, the first word line, and the second word line extend in a first direction.

17. The method of claim 15, further comprising: The IMD is etched to form a third opening that exposes the first word line and a fourth opening that exposes the third word line among the plurality of word lines, wherein the third opening and the fourth opening extend to the first depth; A third conductive contact electrically coupled to the first word line is formed in the third opening, and a fourth conductive contact electrically coupled to the third word line is formed in the fourth opening; as well as A second conductor is formed on the IMD, the third conductive contact, and the fourth conductive contact, wherein the second conductor electrically couples the third conductive contact to the fourth conductive contact.

18. The method of claim 17, wherein, The first and second character lines extend in a first direction, and the second character line extends in a second direction perpendicular to the first direction.

19. The method of claim 15, wherein, The first material includes a dielectric material, wherein the second material includes a conductive material, and wherein forming the plurality of word lines in the multilayer stack includes patterning the multilayer stack to separate adjacent word lines formed by the second material.

20. The method of claim 15, wherein, The first material comprises an oxide, wherein the second material comprises a nitride, wherein forming the plurality of word lines in the multilayer stack comprises: patterning the multilayer stack and replacing the second material with a conductive material.

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