Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The structure includes: a substrate; a first dielectric layer and a gate structure, the gate structure including a metal gate layer, the gate structure being located on the substrate, and the first dielectric layer covering the sidewalls of the gate structure; a first metal layer located on the top surface of the gate structure; a second dielectric layer located on the first dielectric layer; a plurality of first openings located within the first and second dielectric layers, the first openings exposing a portion of the top surface of the first metal layer; and a first conductive plug located within the first openings. Since the metal selective growth process utilizes the property that tungsten can grow on a metal surface, the first metal layer is first formed on the top surface of the gate structure, and then the first conductive plug can be formed through the metal selective growth process. This avoids the formation of an additional high-resistance adhesion layer within the first openings, reduces the contact resistance between the first conductive plug and the gate structure, and improves the performance of the final semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous advancement of semiconductor technology, the feature size of semiconductor devices is gradually shrinking. This reduction in critical dimensions means that more transistors can be placed on a chip, while simultaneously placing higher demands on semiconductor manufacturing processes. As the size of semiconductor devices shrinks, the contact resistance of MOS transistors has an increasingly significant impact on the performance of the MOS transistors and the entire semiconductor chip. To improve the performance of semiconductor chips, it is necessary to reduce the contact resistance of MOS transistors.

[0003] However, existing MOS transistors still suffer from high contact resistance. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the final semiconductor structure.

[0005] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate; a first dielectric layer and a gate structure, the gate structure including a metal gate layer, the gate structure being located on the substrate, and the first dielectric layer covering the sidewalls of the gate structure; a first metal layer located on the top surface of the gate structure; a second dielectric layer located on the first dielectric layer; a plurality of first openings located within the second dielectric layer, the first openings exposing a portion of the top surface of the first metal layer; and a first conductive plug located within the first openings.

[0006] Optionally, it further includes: an isolation structure located on the substrate, the isolation structure being located between adjacent gate structures, and the top surface of the isolation structure being higher than the top surface of the gate structure.

[0007] Optionally, the material of the first metal layer includes tungsten, cobalt, or ruthenium.

[0008] Optionally, it further includes: a plurality of source / drain doped layers located in the substrate on both sides of the gate structure, wherein the first dielectric layer covers the source / drain doped layers.

[0009] Optionally, it further includes: a third dielectric layer located on the first dielectric layer and the first metal layer, wherein the second dielectric layer is located on the third dielectric layer; and a second metal layer located within the first dielectric layer and the third dielectric layer, wherein the second metal layer connects to the plurality of source and drain doped layers.

[0010] Optionally, the material of the second metal layer includes tungsten, cobalt, or ruthenium.

[0011] Optionally, it may also include: a plurality of second openings located within the second dielectric layer, the second openings exposing a portion of the top surface of the second metal layer.

[0012] Optionally, it also includes a second conductive plug located within the second opening.

[0013] Optionally, the material of the first conductive plug includes tungsten; the material of the second conductive plug includes tungsten.

[0014] Optionally, the substrate includes a base and a plurality of mutually discrete fins located on the base, the gate structure spanning the fins.

[0015] Optionally, it may further include: an isolation layer located on the substrate, the isolation layer covering a portion of the sidewall of the fin, and the top surface of the isolation layer being lower than the top surface of the fin.

[0016] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first dielectric layer and a gate structure, the gate structure including a metal gate layer, the gate structure being located on the substrate, and the first dielectric layer covering the sidewalls of the gate structure; forming a first metal layer on the top surface of the gate structure; forming a second dielectric layer on the first dielectric layer; forming a plurality of first openings in the second dielectric layer, the first openings exposing a portion of the top surface of the first metal layer; and forming a first conductive plug in the first openings using a metal selective growth process.

[0017] Optionally, it further includes: forming an isolation structure on the substrate, the isolation structure being located between adjacent gate structures, and the top surface of the isolation structure being higher than the top surface of the gate structure.

[0018] Optionally, the method for the gate structure and the isolation structure includes: forming a gate material film on the substrate; forming an isolation opening in the gate material film to form a plurality of initial gate structures; forming an isolation structure in the isolation opening, wherein the top surface of the isolation structure is flush with the top surface of the initial gate structure; removing a portion of the initial gate structure to form the gate structure, wherein the top surface of the gate structure is lower than the top surface of the isolation structure.

[0019] Optionally, the method of forming a first metal layer on the top surface of the gate structure includes: forming a first metal material film on the top surface of the gate structure, the top surface of the first dielectric layer, and the top surface of the isolation structure; and planarizing the first metal material film until the top surfaces of the first dielectric layer and the isolation structure are exposed, thereby forming the first metal layer.

[0020] Optionally, the material of the first metal layer includes tungsten, cobalt, or ruthenium.

[0021] Optionally, the thickness of the first metal layer is 5nm to 20nm.

[0022] Optionally, before forming the first dielectric layer and the gate structure, the method further includes: forming a plurality of source / drain doped layers in the substrate, the source / drain doped layers being located on both sides of the gate structure, and the first dielectric layer covering the source / drain doped layers.

[0023] Optionally, after forming the first metal layer and before forming the second dielectric layer, the method further includes: forming a third dielectric layer on the first dielectric layer and the first metal layer, wherein the second dielectric layer is located on the third dielectric layer; and forming a second metal layer within the first dielectric layer and the third dielectric layer, wherein the second metal layer connects to a plurality of the source / drain doped layers.

[0024] Optionally, the second metal layer method includes: forming conductive openings in the first dielectric layer and the third dielectric layer, the conductive openings exposing a portion of the source / drain doped layer; forming a second metal material film in the conductive openings and on the top surface of the third dielectric layer; and planarizing the second metal material film until the top surface of the third dielectric layer is exposed, thereby forming the second metal layer.

[0025] Optionally, the material of the second metal layer includes tungsten, cobalt, or ruthenium.

[0026] Optionally, the process of forming the first opening further includes: forming a plurality of second openings within the second dielectric layer, the second openings exposing a portion of the top surface of the second metal layer.

[0027] Optionally, the process of forming the first conductive plug may further include: forming a second conductive plug within the second opening using a metal selective growth process.

[0028] Optionally, the method for forming the first conductive plug and the second conductive plug includes: forming an initial conductive structure in the first opening and the second opening using a metal selective growth process, wherein the top surface of the initial conductive structure is higher than the top surface of the second dielectric layer; and performing a planarization process on the initial conductive structure to form the first conductive plug and the second conductive plug.

[0029] Optionally, before planarization, the method further includes: forming an adhesion layer on the surface of the initial conductive structure above the second dielectric layer and on the top surface of the second dielectric layer; forming a conductive layer on the adhesion layer, the top surface of the conductive layer being flush with the surface of the conductive layer.

[0030] Optionally, the material of the first conductive plug includes tungsten; the material of the second conductive plug includes tungsten.

[0031] Optionally, the substrate includes a base and a plurality of mutually discrete fins located on the base, the gate structure spanning the fins.

[0032] Optionally, before forming the first dielectric layer and the gate structure, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewall of the fin, and the top surface of the isolation layer being lower than the top surface of the fin.

[0033] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0034] In the structure of the technical solution of the present invention, a first metal layer is formed on the top surface of the gate structure. Since the metal selective growth process utilizes the characteristic that tungsten can grow on a metal surface, this first metal layer is first formed on the top surface of the gate structure, and then the first conductive plug can be formed through the metal selective growth process. This avoids the formation of an additional high-resistance adhesion layer within the first opening, thereby reducing the contact resistance between the first conductive plug and the gate structure, and effectively improving the performance of the final semiconductor structure.

[0035] In the method for forming the technical solution of the present invention, a first metal layer is formed on the top surface of the gate structure; and a first conductive plug is formed in the first opening using a metal selective growth process. Since the metal selective growth process utilizes the property that tungsten can grow on a metal surface, the first metal layer is first formed on the top surface of the gate structure, and then the first conductive plug can be formed using the metal selective growth process. This avoids the formation of an additional high-resistance adhesion layer in the first opening, thereby reducing the contact resistance between the first conductive plug and the gate structure, and effectively improving the performance of the final semiconductor structure.

[0036] Furthermore, the process of forming the first conductive plug also includes: forming a second conductive plug within the second opening using a metal-selective growth process. By simultaneously forming the first conductive plug on the gate structure and the second conductive plug on the source / drain doped layers in a single process step, the number of process steps is effectively reduced, and production efficiency is improved. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a semiconductor structure.

[0038] Figures 2 to 19 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0039] As described in the background section, existing MOS transistors still suffer from high contact resistance. This will be explained in detail below with reference to the accompanying drawings.

[0040] Please refer to Figure 1 A substrate 100 is provided; a first dielectric layer 101 and a gate structure 102 are formed, the gate structure 102 being located on the substrate 100, the first dielectric layer 101 covering the sidewalls of the gate structure 102; a second dielectric layer 105 is formed on the first dielectric layer 101; a plurality of first openings (not shown) are formed in the first dielectric layer 101 and the second dielectric layer 105, the first openings exposing the top surface of the gate structure 102; an adhesion layer 103 is formed on the bottom surface and sidewalls of the first openings; and a first conductive plug 104 is formed on the adhesion layer 103.

[0041] In this embodiment, the first conductive plug 104 is made of tungsten metal. Since tungsten metal can only be formed on the surface of a material with metallic properties, a titanium nitride material adhesion layer 103 needs to be formed in the first opening before the first conductive plug 104 is formed. Since the titanium nitride material adhesion layer 103 has a high resistance value, the contact resistance between the finally formed first conductive plug 103 and the gate structure 102 is relatively large.

[0042] Based on this, the present invention provides a semiconductor structure and a method for forming the same, comprising forming a first metal layer on the top surface of the gate structure and forming a first conductive plug within the first opening using a metal-selective growth process. Since the metal-selective growth process utilizes the property that tungsten can grow on a metal surface, the first metal layer is first formed on the top surface of the gate structure, and then the first conductive plug can be formed using the metal-selective growth process. This avoids the formation of an additional high-resistance adhesion layer within the first opening, thereby reducing the contact resistance between the first conductive plug and the gate structure, and effectively improving the performance of the final semiconductor structure.

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 2 to 19 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0045] Please refer to Figure 2 Provides a substrate.

[0046] In this embodiment, the substrate includes a base 200 and a plurality of mutually discrete fins 201 located on the base 200; in other embodiments, the substrate may also be a planar structure.

[0047] In this embodiment, the method for forming the substrate includes: providing an initial substrate (not shown) having a patterned layer (not shown) on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate 200 and a plurality of mutually discrete fins 201 located on the substrate 200.

[0048] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0049] In this embodiment, the fin 201 is made of silicon; in other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0050] Please refer to Figure 3 An isolation layer 202 is formed on the substrate, the isolation layer 202 covers part of the sidewall of the fin 201, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0051] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate; etching away a portion of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0052] The insulating layer 202 is made of an insulating material, including silicon oxide or silicon oxynitride; in this embodiment, the insulating layer 202 is made of silicon oxide.

[0053] After forming the isolation layer 202, the process further includes: forming a first dielectric layer and a gate structure, the gate structure including a metal gate layer, the gate structure being located on the substrate, and the first dielectric layer covering the sidewalls of the gate structure; forming a plurality of source / drain doped layers in the substrate, the source / drain doped layers being located on both sides of the gate structure, and the first dielectric layer covering the source / drain doped layers; and forming an isolation structure on the substrate, the isolation structure being located between adjacent gate structures, and the top surface of the isolation structure being higher than the top surface of the gate structure. For a detailed formation process, please refer to [reference needed]. Figures 4 to 11 .

[0054] Please refer to Figure 4 , Figure 4 The diagram is a top view of a semiconductor structure. A dummy gate material film 203 is formed on the isolation layer 202, and the dummy gate material film 203 spans the fin 201. A sidewall 204 is formed on the sidewall of the dummy gate material film 203.

[0055] In this embodiment, the dummy gate material film 203 includes: a dummy gate dielectric film and a dummy gate film (not shown) located on the dummy gate dielectric film.

[0056] In this embodiment, the method for forming the sidewall 204 includes: forming a sidewall material film (not shown) on the sidewall and top surface of the dummy gate material film 203 and the top surface of the isolation layer 202; and etching the sidewall material film back until the top surface of the dummy gate material film 203 and the isolation layer 202 is exposed, thereby forming the sidewall 204.

[0057] In this embodiment, the sidewall material film is formed using atomic layer deposition.

[0058] Please refer to Figure 5 , Figure 5 and Figure 4 With the view direction consistent, the fin 201 is etched using the pseudo-gate material film 203 and the sidewall 204 as a mask, and a source / drain opening (not shown) is formed in the fin 201; the source / drain doped layer 205 is formed in the source / drain opening.

[0059] In this embodiment, the method for forming the source / drain doped layer 205 within the source / drain opening includes: forming an epitaxial layer (not shown) within the source / drain opening using an epitaxial growth process; and performing ion implantation on the epitaxial layer after forming the epitaxial layer to form the source / drain doped layer 205.

[0060] Please refer to Figure 6 After the source / drain doped layer 205 is formed, the first dielectric layer 206 is formed, which covers the source / drain doped layer 205 and the sidewalls of the dummy gate material film 203.

[0061] In this embodiment, the method for forming the first dielectric layer 206 includes: forming an initial first dielectric layer (not shown) on the isolation layer 202, the initial first dielectric layer covering the dummy gate material film 203; and planarizing the initial first dielectric layer until the top surface of the dummy gate material film 203 is exposed, thereby forming the first dielectric layer 206.

[0062] In this embodiment, the first dielectric layer 206 is made of silicon oxide; in other embodiments, the first dielectric layer may also be made of a low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).

[0063] Please refer to Figures 7 to 9 , Figure 7 This is a top view of the semiconductor structure. Figure 8 yes Figure 7 Schematic diagram of the cross section along line AA. Figure 9 yes Figure 7 A schematic cross-sectional view along the BB line shows that after the first dielectric layer 206 is formed, the dummy gate material film 203 is removed, and a gate opening (not shown) is formed in the first dielectric layer 206; a gate material film 207 is formed in the gate opening.

[0064] In this embodiment, the gate material film 207 includes: a gate dielectric film and a gate film (not shown) located on the gate dielectric film.

[0065] Please refer to Figure 10 , Figure 10 and Figure 8 With the view orientation consistent, after forming the gate material film 207, an isolation opening (not shown) is formed in the gate material film 207 to form a plurality of initial gate structures 208; an isolation structure 209 is formed in the isolation opening, and the top surface of the isolation structure 209 is flush with the top surface of the initial gate structure 208.

[0066] In this embodiment, the method for forming the isolation structure 209 includes: forming an isolation material film (not shown) inside the isolation opening and on the top surface of the first dielectric layer 206; and planarizing the isolation material film until the top surface of the first dielectric layer 206 is exposed, thereby forming the isolation structure 209.

[0067] In this embodiment, the material of the isolation structure 209 is silicon oxide.

[0068] In other embodiments, the isolation opening and the isolation structure may also be formed after the formation of the pseudo-gate material film.

[0069] Please refer to Figure 11 After the isolation structure 209 is formed, a portion of the initial gate structure 208 is removed to form the gate structure 210, the top surface of the gate structure 210 being lower than the top surface of the isolation structure 209.

[0070] In this embodiment, the gate structure 210 includes a gate dielectric layer and a metal gate layer (not shown) located on the gate dielectric layer.

[0071] The material of the metal gate layer includes tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the material of the metal gate layer is tungsten.

[0072] In this embodiment, by placing the top surface of the gate structure 210 below the top surface of the isolation structure 209, the purpose is to provide space for the subsequent formation of a first metal layer on the top surface of the gate structure 210.

[0073] Please refer to Figure 12 After the gate structure 210 is formed, a first metal layer 211 is formed on the top surface of the gate structure 210.

[0074] In this embodiment, the method of forming a first metal layer 211 on the top surface of the gate structure 210 includes: forming a first metal material film (not shown) on the top surface of the gate structure 210, the top surface of the first dielectric layer 206, and the top surface of the isolation structure 209; and performing planarization on the first metal material film until the top surfaces of the first dielectric layer 206 and the isolation structure 209 are exposed, thereby forming the first metal layer 211.

[0075] In this embodiment, the first metal layer 211 is made of tungsten; in other embodiments, the first metal layer may also be made of cobalt or ruthenium.

[0076] In this embodiment, the thickness of the first metal layer 211 is 5nm to 20nm.

[0077] Please refer to Figure 13 , Figure 13 and Figure 9 With the view orientation consistent, a third dielectric layer 212 is formed on the first dielectric layer 206 and the first metal layer 211; a second metal layer 213 is formed within the first dielectric layer 206 and the third dielectric layer 212, and the second metal layer 213 connects to a plurality of the source and drain doped layers 205.

[0078] In this embodiment, the method for forming the second metal layer 211 includes: forming conductive openings (not shown) in the first dielectric layer 206 and the third dielectric layer 212, the conductive openings exposing a portion of the source / drain doped layer 205; forming a second metal material film (not shown) in the conductive openings and on the top surface of the third dielectric layer 212; and planarizing the second metal material film until the top surface of the third dielectric layer 212 is exposed, thereby forming the second metal layer 213.

[0079] In this embodiment, the material of the third dielectric layer 212 is silicon oxide; in other embodiments, the material of the third dielectric layer may also be a low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).

[0080] In this embodiment, the material of the second metal layer 213 is cobalt; in other embodiments, the material of the second metal layer may also be tungsten or ruthenium.

[0081] Please refer to Figure 14 and Figure 15 After the second metal layer 213 is formed, a second dielectric layer 214 is formed on the first dielectric layer 206.

[0082] In this embodiment, the second dielectric layer 214 is specifically located on the third dielectric layer 212, and the material of the second dielectric layer 214 is silicon oxide; in other embodiments, the material of the second dielectric layer may also be a low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).

[0083] Please refer to Figure 16 and Figure 17 A plurality of first openings 215 are formed in the second dielectric layer 214, the first openings 215 exposing a portion of the top surface of the first metal layer 211.

[0084] In this embodiment, the process of forming the first opening 215 further includes: forming a plurality of second openings 216 in the second dielectric layer 214, wherein the second openings 216 expose a portion of the top surface of the second metal layer 213.

[0085] Please refer to Figure 18 and Figure 19 A first conductive plug 217 is formed in the first opening 215 using a metal selective growth process.

[0086] In this embodiment, a first metal layer 211 is formed on the top surface of the gate structure 210; and a first conductive plug 217 is formed within the first opening 215 using a metal selective growth process. Since the metal selective growth process utilizes the property that tungsten can grow on a metal surface, the first metal layer 211 is first formed on the top surface of the gate structure 210, and then the first conductive plug 217 can be formed using the metal selective growth process. This avoids the formation of an additional high-resistance adhesion layer within the first opening 215, thereby reducing the contact resistance between the first conductive plug 217 and the gate structure 210, and effectively improving the performance of the final semiconductor structure.

[0087] In this embodiment, the process of forming the first conductive plug 217 further includes: forming a second conductive plug 218 in the second opening 216 using a metal selective growth process.

[0088] In this embodiment, the method for forming the first conductive plug 217 and the second conductive plug 218 includes: forming an initial conductive structure (not shown) in the first opening 215 and the second opening 216 using a metal selective growth process, wherein the top surface of the initial conductive structure is higher than the top surface of the second dielectric layer 214; and performing planarization processing on the initial conductive structure to form the first conductive plug 217 and the second conductive plug 218.

[0089] In this embodiment, by forming a first conductive plug 217 on the gate structure 210 and a second conductive plug 218 on the source / drain doped layer 205 in a single process, the number of process steps is effectively reduced and production efficiency is improved.

[0090] In this embodiment, the first conductive plug 217 is made of tungsten; the second conductive plug 218 is also made of tungsten.

[0091] In this embodiment, before planarization, the process further includes: forming an adhesion layer on the surface of the initial conductive structure above the second dielectric layer 214 and on the top surface of the second dielectric layer; and forming a conductive layer on the adhesion layer, the top surface of which is flush with the surface (not shown). Since the top surface of the initial conductive structure is higher than the top surface of the second dielectric layer 214 and is relatively small, this presents a challenge for planarization. By forming the conductive layer, the grinding contact area for subsequent planarization increases, thereby improving the planarization effect.

[0092] Accordingly, an embodiment of the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 18 and Figure 19 The device includes: a substrate; a first dielectric layer 206 and a gate structure 210, the gate structure 210 including a metal gate layer, the gate structure 210 being located on the substrate, and the first dielectric layer 206 covering the sidewalls of the gate structure 210; a first metal layer 211 located on the top surface of the gate structure 210; a second dielectric layer 214 located on the first dielectric layer 206; a plurality of first openings 215 located within the second dielectric layer 214, the first openings 215 exposing a portion of the top surface of the first metal layer 211; and a first conductive plug 217 located within the first openings 215.

[0093] In this embodiment, a first metal layer 211 is formed on the top surface of the gate structure 210. Since the metal selective growth process utilizes the characteristic that tungsten can grow on a metal surface, the first metal layer 211 is first formed on the top surface of the gate structure 210, and then the first conductive plug 217 can be formed through the metal selective growth process. This avoids the formation of an additional high-resistance adhesion layer within the first opening 215, thereby reducing the contact resistance between the first conductive plug 217 and the gate structure 210, and effectively improving the performance of the final semiconductor structure.

[0094] In this embodiment, the system further includes an isolation structure 209 located on the substrate, the isolation structure 209 being located between adjacent gate structures 210, and the top surface of the isolation structure 209 being higher than the top surface of the gate structure 210.

[0095] In this embodiment, the first metal layer 211 is made of tungsten; in other embodiments, the first metal layer may also be made of cobalt or ruthenium.

[0096] In this embodiment, it further includes: a plurality of source / drain doped layers 205 located in the substrate on both sides of the gate structure 210, wherein the first dielectric layer 206 covers the source / drain doped layers 205.

[0097] In this embodiment, it further includes: a third dielectric layer 212 located on the first dielectric layer 206 and the first metal layer 211, and a second dielectric layer 214 located on the third dielectric layer 212; and a second metal layer 213 located within the first dielectric layer 206 and the third dielectric layer 212, wherein the second metal layer 213 is connected to a plurality of the source and drain doped layers 206.

[0098] In this embodiment, the material of the second metal layer 213 is cobalt; in other embodiments, the material of the second metal layer may also be tungsten or ruthenium.

[0099] In this embodiment, it further includes a plurality of second openings 216 located within the second dielectric layer 214, the second openings 216 exposing a portion of the top surface of the second metal layer 213.

[0100] In this embodiment, a second conductive plug 218 located within the second opening 216 is also included.

[0101] In this embodiment, the first conductive plug 217 is made of tungsten; the second conductive plug 218 is also made of tungsten.

[0102] In this embodiment, the substrate includes a base 200 and a plurality of mutually discrete fins 201 located on the base 200, and the gate structure 210 spans the fins 201.

[0103] In this embodiment, it further includes: an isolation layer 202 located on the substrate, the isolation layer 202 covering a portion of the sidewall of the fin 201, and the top surface of the isolation layer 202 being lower than the top surface of the fin 201.

[0104] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first dielectric layer and a gate structure, the gate structure including a metal gate layer, the gate structure being located on the substrate, and the first dielectric layer covering the sidewalls of the gate structure; The first metal layer located on the top surface of the gate structure; A second dielectric layer located on top of the first dielectric layer; A plurality of first openings are located within the second dielectric layer, the first openings exposing a portion of the top surface of the first metal layer; A first conductive plug located within the first opening; wherein... The first conductive plug is formed based on the first metal layer using a metal selective growth process; The method for forming the first conductive plug includes: forming an initial conductive structure in the first opening using a metal selective growth process, wherein the top surface of the initial conductive structure is higher than the top surface of the second dielectric layer; forming an adhesion layer on the surface of the initial conductive structure higher than the second dielectric layer and on the top surface of the second dielectric layer; forming a conductive layer on the adhesion layer, wherein the top surface of the conductive layer is flush with the top surface of the conductive layer; and performing a planarization process on the initial conductive structure and the conductive layer until the surface of the second dielectric layer is exposed, thereby forming the first conductive plug.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: An isolation structure is located on the substrate, the isolation structure is also located between adjacent gate structures, and the top surface of the isolation structure is higher than the top surface of the gate structure.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the first metal layer includes tungsten, cobalt, or ruthenium.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: A plurality of source / drain doped layers are located in the substrate on both sides of the gate structure, and the first dielectric layer covers the source / drain doped layers.

5. The semiconductor structure as described in claim 4, characterized in that, Also includes: A third dielectric layer is located on the first dielectric layer and the first metal layer, and the second dielectric layer is located on the third dielectric layer; A second metal layer is located within the first dielectric layer and the third dielectric layer, and the second metal layer is connected to a plurality of source and drain doped layers.

6. The semiconductor structure as described in claim 5, characterized in that, The material of the second metal layer includes tungsten, cobalt, or ruthenium.

7. The semiconductor structure as described in claim 5, characterized in that, Also includes: A plurality of second openings are located within the second dielectric layer, the second openings exposing a portion of the top surface of the second metal layer.

8. The semiconductor structure as described in claim 7, characterized in that, Also includes: The second conductive plug is located within the second opening.

9. The semiconductor structure as described in claim 8, characterized in that, The material of the first conductive plug includes tungsten; the material of the second conductive plug includes tungsten.

10. The semiconductor structure as claimed in claim 1, characterized in that, The substrate includes a base and a plurality of mutually discrete fins located on the base, the gate structure spanning the fins.

11. The semiconductor structure as described in claim 10, characterized in that, Also includes: An isolation layer is located on the substrate, the isolation layer covers a portion of the sidewall of the fin, and the top surface of the isolation layer is lower than the top surface of the fin.

12. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first dielectric layer and a gate structure are formed, the gate structure including a metal gate layer, the gate structure being located on the substrate, and the first dielectric layer covering the sidewalls of the gate structure; A first metal layer is formed on the top surface of the gate structure; A second dielectric layer is formed on the first dielectric layer; A plurality of first openings are formed within the second dielectric layer, the first openings exposing a portion of the top surface of the first metal layer; A first conductive plug is formed within the first opening using a metal-selective growth process; wherein... The first conductive plug is formed based on the first metal layer using a metal selective growth process; The method for forming the first conductive plug includes: forming an initial conductive structure in the first opening using a metal selective growth process, wherein the top surface of the initial conductive structure is higher than the top surface of the second dielectric layer; forming an adhesion layer on the surface of the initial conductive structure higher than the second dielectric layer and on the top surface of the second dielectric layer; forming a conductive layer on the adhesion layer, wherein the top surface of the conductive layer is flush with the top surface of the conductive layer; and performing a planarization process on the initial conductive structure and the conductive layer until the surface of the second dielectric layer is exposed, thereby forming the first conductive plug.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, Also includes: An isolation structure is formed on the substrate, the isolation structure being located between adjacent gate structures, and the top surface of the isolation structure being higher than the top surface of the gate structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for the gate structure and the isolation structure includes: forming a gate material film on the substrate; forming an isolation opening in the gate material film to form a plurality of initial gate structures; forming an isolation structure in the isolation opening, wherein the top surface of the isolation structure is flush with the top surface of the initial gate structure; removing a portion of the initial gate structure to form the gate structure, wherein the top surface of the gate structure is lower than the top surface of the isolation structure.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, A method for forming a first metal layer on the top surface of the gate structure includes: forming a first metal material film on the top surface of the gate structure, the top surface of the first dielectric layer, and the top surface of the isolation structure; and planarizing the first metal material film until the top surfaces of the first dielectric layer and the isolation structure are exposed, thereby forming the first metal layer.

16. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the first metal layer includes tungsten, cobalt, or ruthenium.

17. The method for forming a semiconductor structure as described in claim 12, characterized in that, The thickness of the first metal layer is 5nm-20nm.

18. The method for forming a semiconductor structure as described in claim 12, characterized in that, Before forming the first dielectric layer and the gate structure, the method further includes: forming a plurality of source / drain doped layers in the substrate, the source / drain doped layers being located on both sides of the gate structure, and the first dielectric layer covering the source / drain doped layers.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, After forming the first metal layer and before forming the second dielectric layer, the method further includes: forming a third dielectric layer on the first dielectric layer and the first metal layer, wherein the second dielectric layer is located on the third dielectric layer; and forming a second metal layer within the first dielectric layer and the third dielectric layer, wherein the second metal layer connects to a plurality of the source and drain doped layers.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The second metal layer method includes: forming conductive openings in the first dielectric layer and the third dielectric layer, the conductive openings exposing a portion of the source / drain doped layer; forming a second metal material film in the conductive openings and on the top surface of the third dielectric layer; and planarizing the second metal material film until the top surface of the third dielectric layer is exposed, thereby forming the second metal layer.

21. The method for forming a semiconductor structure as described in claim 19, characterized in that, The material of the second metal layer includes tungsten, cobalt, or ruthenium.

22. The method for forming a semiconductor structure as described in claim 19, characterized in that, The process of forming the first opening also includes: forming a plurality of second openings within the second dielectric layer, the second openings exposing a portion of the top surface of the second metal layer.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, The process of forming the first conductive plug also includes: forming a second conductive plug in the second opening using a metal selective growth process.

24. The method for forming a semiconductor structure as described in claim 23, characterized in that, The method for forming the first conductive plug and the second conductive plug includes: forming an initial conductive structure in the first opening and the second opening using a metal selective growth process, wherein the top surface of the initial conductive structure is higher than the top surface of the second dielectric layer; and performing a planarization process on the initial conductive structure to form the first conductive plug and the second conductive plug.

25. The method for forming a semiconductor structure as described in claim 24, characterized in that, Prior to planarization, the process further includes: forming an adhesion layer on the surface of the initial conductive structure above the second dielectric layer and on the top surface of the second dielectric layer; and forming a conductive layer on the adhesion layer, the top surface of which is flush with the top surface of the conductive layer.

26. The method for forming a semiconductor structure as described in claim 23, characterized in that, The material of the first conductive plug includes tungsten; the material of the second conductive plug includes tungsten.

27. The method for forming a semiconductor structure as described in claim 12, characterized in that, The substrate includes a base and a plurality of mutually discrete fins located on the base, the gate structure spanning the fins.

28. The method for forming a semiconductor structure as described in claim 27, characterized in that, Before forming the first dielectric layer and the gate structure, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewall of the fin, and the top surface of the isolation layer being lower than the top surface of the fin.

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