Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, the method comprising: a substrate; a first fin located on the substrate; a second fin located on the substrate, the second fin including a first barrier layer on the substrate, a second barrier layer on the first barrier layer, and a channel layer on the second barrier layer; a first well region located within the first fin and a portion of the substrate; a second well region located within the second fin and a portion of the substrate; and an isolation structure layer located on the surface of the substrate, the isolation structure layer being located on the sidewalls of the first fin and the second fin, and the isolation structure layer exposing the channel layer. The first barrier layer can block the lateral diffusion of doped ions in the initial first well region to the channel material layer, thereby stabilizing the doped ion concentration in the subsequently formed first and second fins, improving the stability of the doped ion concentration in the channel region of the formed device, and thus improving the device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the existing semiconductor field, the FinFET is an emerging multi-gate device. Compared with the planar metal-oxide-semiconductor field-effect transistor (MOSFET), the FinFET has stronger short-channel rejection capability and higher operating current, and is now widely used in various semiconductor devices.

[0003] With the continuous development of semiconductor technology, the gate size of fin field-effect transistors is also constantly decreasing. At this time, the distribution width of boron and phosphorus doped ions has become an important factor affecting the short channel effect (SCE) of fin field-effect transistors.

[0004] The performance of semiconductor structures formed using existing fin field-effect transistors urgently needs improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; a first fin located on the substrate; a second fin located on the substrate, the second fin including a first barrier layer located on the substrate, a second barrier layer located on the first barrier layer, and a channel layer located on the second barrier layer; a first well region located within the first fin and a portion of the substrate; a second well region located within the second fin and a portion of the substrate; and an isolation structure layer located on the surface of the substrate, the isolation structure layer being located on the sidewalls of the first fin and the second fin, and the isolation structure layer exposing the channel layer.

[0007] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing an initial substrate, the initial substrate including a first region and a second region adjacent to the first region; forming an initial first well region in the first region; forming an initial second well region in the second region, the initial second well region having a different conductivity type than the initial first well region; etching the second region to form a trench in the initial substrate, the trench sidewalls exposing the sidewalls of the initial first well region; modifying the initial first well region exposed by the trench sidewalls to form a first barrier material layer; forming the first... After the blocking material layer is formed, a channel material layer is formed in the groove; the initial substrate and the channel material layer are etched to form a substrate, a first fin and a second fin located on the substrate, a first well region located within the first fin and a portion of the substrate, and a second well region located within the second fin and a portion of the substrate. The first fin is formed by a first region of the initial substrate, the second fin is formed by a second region of the initial substrate and the channel material layer, the second fin includes a channel layer formed by the channel material layer, the first well region is formed by the initial first well region, and the second well region is formed by the initial second well region.

[0008] Optionally, the modification process includes performing an ion implantation process on the initial first well region exposed on the sidewall of the groove.

[0009] Optionally, the process parameters of the ion implantation process include: the implanted ions include N-type ions or P-type ions, and the dose range of the implanted ions is 2E12 atom / cm². 3 Up to 2E13 atom / cm 3 The energy range is from 0.5 keV to 3 keV.

[0010] Optionally, the conductivity type of the implanted ions is different from the conductivity type of the initial first well region.

[0011] Optionally, the implanted ions may also include carbon ions.

[0012] Optionally, the first barrier material layer is also located at the bottom of the trench, and the method for forming the first barrier material layer further includes: the ion implantation further doping the bottom of the trench; and the first barrier material layer is etched to form a first barrier layer when the initial substrate and the channel material layer are etched.

[0013] Optionally, the modification process further includes performing a heat treatment process after the ion implantation process.

[0014] Optionally, the second fin may further include a second barrier layer located between the substrate and the channel layer.

[0015] Optionally, the method for forming the second barrier layer includes: forming a second barrier material layer on the sidewall and bottom surface of the groove after forming the first barrier material layer and before forming the channel material layer; and etching the second barrier material layer to form the second barrier layer during etching of the initial substrate and the channel material layer.

[0016] Optionally, the formation process of the second barrier material layer includes an epitaxial growth process; the material of the second barrier material layer includes germanium silicon.

[0017] Optionally, it further includes: forming an isolation structure layer on the surface of the substrate, the isolation structure layer being located on the sidewalls of the first fin and the second fin, and exposing the channel layer.

[0018] Optionally, the formation process of the initial first well region and the initial second well region includes an ion implantation process, wherein the process parameters of the ion implantation process include: the dopant ions are N-type ions or P-type ions; the dopant ions include phosphorus ions, and the concentration range of the phosphorus ions is 6E12 atom / cm³. 3 Up to 6E13 atom / cm 3 The energy range is from 50 keV to 300 keV; the doped ions include boron ions, and the concentration of the boron ions ranges from 6E12 atom / cm³. 3 Up to 6E13 atom / cm 3 The energy range is from 10 keV to 120 keV.

[0019] Optionally, the method for forming the initial first well region includes: forming a first mask layer on the initial substrate, the first mask layer exposing the surface of the first region; and implanting a first dopant ion into the first region.

[0020] Optionally, the method for forming the initial second well region includes: forming a second mask layer on the initial substrate, the second mask layer exposing the surface of the second region; and implanting a second dopant ion into the second region.

[0021] Optionally, the process for forming the groove includes a dry etching process.

[0022] Optionally, the material of the channel material layer includes silicon.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0024] In the semiconductor structure formation method provided by the present invention, the first well region exposed on the sidewall of the groove is modified to form a first barrier material layer. After the first barrier material layer is formed, a channel material layer is formed in the groove. In the subsequent heat treatment process, the first barrier material layer can block the lateral diffusion of doped ions in the initial first well region to the channel material layer, so as to stabilize the doped ion concentration in the subsequently formed first fin and second fin, thereby improving the stability of the doped ion concentration in the channel region of the subsequently formed device and thus improving the performance of the device.

[0025] Furthermore, the conductivity type of the implanted ions is different from that of the initial first well region. When the doped ions in the initial first well region are N-type ions, the implanted ions are P-type ions, and vice versa. This serves to prevent the diffusion of doped ions in the initial first well region into the channel material layer.

[0026] Furthermore, the implanted ions also include carbon ions. Due to the blocking effect of carbon ions on dopant ions, the lateral diffusion of dopant ions on both sides of the first blocking material layer can be further blocked, improving the stability of the dopant ion concentration in the channel region of the subsequently formed device, thereby improving the device performance. Attached Figure Description

[0027] Figures 1 to 3 This is a schematic cross-sectional view of the semiconductor structure formation process;

[0028] Figures 4 to 8 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0029] As described in the background section, the performance of semiconductor structures formed using existing FinFET technology urgently needs improvement. This paper will now illustrate and analyze one such semiconductor structure.

[0030] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0031] Figures 1 to 3 This is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0032] Please refer to Figure 1 An initial substrate 100 is provided, the initial substrate including an adjacent first region I and a second region II; N-type dopant ions are implanted into the first region I to form an initial first well region 101; and P-type dopant ions are implanted into the second region II to form an initial second well region 102.

[0033] Please refer to Figure 2 The initial substrate 100 is etched to form a substrate 103, a first fin 104 located in the first region I, and a second fin 105 located in the second region II. A first well region 106 is formed with the initial first well region 101, and the first well region 106 is located within a portion of the substrate 103 and a portion of the first fin 104. A second well region 107 is formed with the initial second well region 102, and the second well region 107 is located within a portion of the substrate 103 and a portion of the second fin 105.

[0034] Please refer to Figure 3 An isolation medium layer 108 is formed on the substrate 105. The isolation medium layer 108 is also located on the sidewalls of the first fin 106 and the second fin 107, and exposes the top surface and part of the sidewall surface of the first fin 106 and the second fin 107.

[0035] The above method is used in FinFET devices. The first region I and the second region II are used to form devices with different conductivity types. A PN interface is formed between the initial first well region 101 and the initial second well region 104. The first fin 106 is used to form the first channel layer, and the second fin 107 is used to form the second channel layer. Due to the different types of doped ions on both sides of the PN interface, the doped ion concentration varies significantly on both sides of the PN interface. In subsequent thermal processing, such as the thermal annealing required to form shallow trench isolation (STI), N-type doped ions will diffuse from the initial first well region 101 to the initial second well region 102, or P-type doped ions will diffuse from the initial second well region 102 to the initial first well region 101. Therefore, this diffusion will affect the doped ion concentration in the subsequently formed first and second channel layers, thereby affecting the device's threshold voltage and other performance characteristics, leading to anomalies such as short-channel effects and reducing the reliability of the device performance.

[0036] To address the aforementioned issues, this invention provides a method for forming a semiconductor structure. The first well region exposed on the sidewall of the groove is modified to form a first barrier material layer. After forming the first barrier material layer, a channel material layer is formed within the groove. During subsequent heat treatment, the first barrier material layer can prevent the lateral diffusion of doped ions from the initial first well region into the channel material layer, thereby stabilizing the doped ion concentration in the subsequently formed first and second fins. This improves the stability of the doped ion concentration in the channel region of the subsequently formed device, thereby enhancing the device's performance.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 4 to 8 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 4 An initial substrate 200 is provided, the initial substrate 200 including a first region I and a second region II adjacent to the first region I; an initial first well region 201 is formed in the first region I; an initial second well region 202 is formed in the second region II, the initial second well region 202 having a different conductivity type than the initial first well region 201.

[0040] The formation process of the initial first well region 201 and the initial second well region 202 includes an ion implantation process. The process parameters of the ion implantation process include: the dopant ions are N-type ions or P-type ions; the dopant ions include phosphorus ions, and the concentration range of the phosphorus ions is 6E12 atom / cm³. 3 Up to 6E13 atom / cm 3 The energy range is from 50 keV to 300 keV; the doped ions include boron ions, and the concentration of the boron ions ranges from 6E12 atom / cm³. 3 Up to 6E13 atom / cm 3 The energy range is 10 keV to 120 keV. In this embodiment, the doped ions in the initial first well region 201 are N-type ions; the doped ions in the initial second well region 202 are P-type ions. Subsequently, the initial first well region 201 is used to form a first well region, and the first region I is used to form a PMOS device; the initial first well region 201 is used to form a first well region, and the second region II is used to form an NMOS device.

[0041] The method for forming the initial first well region 201 and the initial second well region 202 includes: forming a first mask layer (not shown in the figure) on the initial substrate 200, the first mask layer exposing the surface of the first region I; implanting a first dopant ion into the first region I; forming a second mask layer (not shown in the figure) on the initial substrate 200, the second mask layer exposing the surface of the second region II; implanting a second dopant ion into the second region II, the second dopant ion having a different conductivity type than the first dopant ion.

[0042] The implantation surface of the initial first well region 201 (the initial second well region 202) is a planar substrate. Compared with the process of implanting ions into a substrate after the fins have been formed to form a well region, the ion implantation has better uniformity, which is conducive to the formation of a uniform first well region (second well region) and thus improves the stability of the device.

[0043] Please refer to Figure 5 The second region II is etched to form a groove 203 in the initial substrate 200, and the sidewall of the groove 203 exposes the sidewall of the initial first well region 201; the initial first well region 201 exposed by the sidewall of the groove 203 is modified to form a first barrier material layer 206.

[0044] In this embodiment, the method for forming the groove 203 includes: forming a third mask layer 205 on the surface of the initial substrate 200, the third mask layer 205 exposing the surface of the second region II; etching the second region II to form the groove 203 in the initial substrate 200.

[0045] In this embodiment, before forming the third mask layer 205, an oxide material layer (not shown in the figure) is formed on the surface of the initial substrate 200; a third mask material layer (not shown in the figure) is formed on the surface of the oxide material layer; the third mask material layer and the oxide material layer are patterned to form the third mask layer 205 and the oxide layer 204. The oxide layer 204 is used to protect the initial first well region 201 from etching damage during the etching process of forming the groove 203.

[0046] The formation process of the groove 203 includes a dry etching process. The dry etching process is beneficial for forming a better morphology of the groove 203.

[0047] The modification process includes performing an ion implantation process on the initial first well region 201 exposed on the sidewall of the groove 203.

[0048] The process parameters for the ion implantation process include: implanted ions include N-type ions or P-type ions, and the dose range of the implanted ions is 2E12 atom / cm². 3 Up to 2E13 atom / cm 3 The energy range is from 0.5 keV to 3 keV.

[0049] The conductivity type of the implanted ions differs from that of the initial first well region 201. In this embodiment, the dopant ions in the initial first well region 201 are N-type ions, and the implanted ions are P-type ions. In another embodiment, the dopant ions in the initial first well region are P-type ions, and the implanted ions are both P-type ions. By implanting ions into the initial first well region 201 exposed on the sidewall of the groove 203, the implanted ions can prevent the diffusion of dopant ions in the initial first well region into the channel material layer. In this embodiment, the dopant ions in the initial first well region are N-type ions, and the implanted ions are P-type ions.

[0050] The implanted ions also include carbon ions. Because carbon ions block the dopant ions, they further prevent the lateral diffusion of dopant ions on both sides of the first barrier material layer, improving the stability of the dopant ion concentration in the channel region of the subsequently formed device, thereby improving the device performance.

[0051] The modification process further includes performing a heat treatment process after the ion implantation process. The heat treatment process is used to reduce the damage caused by the ion implantation process to the initial first well region 201 and the initial second well region 202.

[0052] In this embodiment, the first barrier material layer 206 is also located at the bottom of the groove 203, and the method for forming the first barrier material layer 206 further includes: the ion implantation further doping the bottom of the groove 203.

[0053] Subsequently, after the first barrier material layer 206 is formed, a channel material layer is formed in the groove 203.

[0054] On one hand, the first barrier material layer 206 is used to form the first barrier layer. On the other hand, a portion of the first barrier material layer 206 is located between the initial first well region 201 and the channel material layer. During subsequent heat treatment, the first barrier material layer 206 can prevent the lateral diffusion of doped ions in the initial first well region 201 into the channel material layer, thereby stabilizing the doped ion concentration in the subsequently formed first and second fins, improving the stability of the doped ion concentration in the channel region of the subsequently formed device, and thus improving the device performance.

[0055] Please refer to Figure 6 After the first barrier material layer 206 is formed, a channel material layer 207 is formed in the groove 203.

[0056] The channel material layer 207 is made of silicon. In this embodiment, the channel material layer 207 is made of silicon.

[0057] In this embodiment, after forming the first barrier material layer 206 and before forming the channel material layer 207, a second barrier material layer 208 is formed on the sidewall and bottom surface of the groove 203. Subsequently, the second barrier material layer 208 is used to form a second barrier layer.

[0058] In this embodiment, after forming the second barrier material layer 208, the third mask layer 205 and the oxide layer 204 are also removed.

[0059] The formation process of the second barrier material layer 208 includes an epitaxial growth process; the material of the second barrier material layer 208 includes germanium silicon.

[0060] Please refer to Figure 7 The initial substrate 200 and the channel material layer 207 are etched to form a substrate 301, a first fin 302 and a second fin located on the substrate 301, a first well region 303 located within the first fin 302 and a portion of the substrate 301, and a second well region 304 located within the second fin and a portion of the substrate 301. The first fin 302 is formed by a first region I of the initial substrate 200, the second fin is formed by a second region II of the initial substrate 200 and the channel material layer 207, and the second fin includes a channel layer 305 formed by the channel material layer 207. The first well region 303 is formed by the initial first well region 201, and the second well region 304 is formed by the initial second well region 202.

[0061] The channel layer 305 is used to form the channel for the device on the second region II.

[0062] In this embodiment, when etching the initial substrate 200 and the channel material layer 207, the first barrier material layer 206 is etched to form a first barrier layer 306.

[0063] In this embodiment, the second fin further includes a second barrier layer 307 located between the substrate 301 and the channel layer 305.

[0064] The method for forming the second barrier layer 307 includes: during the etching of the initial substrate 200 and the channel material layer 207, the second barrier material layer 207 is etched to form the second barrier layer 307. The second barrier layer 307 is used to block the diffusion of doped ions in the second well region 304 to the channel layer 305, which helps to improve the stability of the doped ion concentration in the channel layer 305, thereby improving the stability of the threshold voltage and other performance characteristics of the device in the second region II, and improving the performance of the device.

[0065] Please refer to Figure 8 An isolation structure layer 308 is formed on the surface of the substrate 301. The isolation structure layer 308 is located on the sidewalls of the first fin 302 and the second fin, and exposes the channel layer 305.

[0066] The material of the isolation structure layer 308 includes a dielectric material, which includes one or more of silicon borohydride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the isolation structure layer 308 is silicon oxide.

[0067] The isolation structure layer 308 is formed using a chemical vapor deposition process. In this embodiment, the isolation structure layer 308 is formed using a fluid chemical vapor deposition process.

[0068] The method for forming the isolation structure layer 308 includes: forming a dielectric material layer (not shown in the figure) on the surface of the substrate 300, the top surface and sidewall of the first fin 302, and the top surface and sidewall of the second fin; planarizing the dielectric material layer until the top surfaces of the first fin 302 and the second fin are exposed; and etching back the dielectric material layer until the sidewall of the channel layer 305 is exposed.

[0069] In this embodiment, the dielectric material layer is etched back, exposing the sidewalls of the first barrier layer 306 and the second barrier layer 307. In other embodiments, only the sidewall of the channel layer 305 may be exposed; or the sidewall of the channel layer 305 and part or all of the sidewall of the second barrier layer 307 may be exposed; or the sidewall of the channel layer 305, the sidewall of the second barrier layer 307, and part or all of the sidewall of the first barrier layer 306 may be exposed.

[0070] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 8 The fin includes: a substrate 301; a first fin 302 located on the substrate 301; a second fin located on the substrate 301, the second fin including a first barrier layer 306 located on the substrate 301, a second barrier layer 307 located on the first barrier layer 306, and a channel layer 305 located on the second barrier layer 307; a first well region 303 located within the first fin 302 and a portion of the substrate 301; a second well region 304 located within the second fin and a portion of the substrate 301; and an isolation structure layer 308 located on the surface of the substrate 301, the isolation structure layer 308 being located on the sidewalls of the first fin 302 and the second fin, and the isolation structure layer 308 exposing the channel layer 305.

[0071] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: An initial substrate is provided, the initial substrate comprising a first region and a second region adjacent to the first region; An initial first well region is formed within the first region; An initial second well region is formed within the second region, and the conductivity type of the initial second well region is different from that of the initial first well region. The second region is etched to form a groove in the initial substrate, the sidewalls of the groove exposing the sidewalls of the initial first well region; The initial first well region exposed on the sidewall of the groove is modified to form a first barrier material layer; After the first barrier material layer is formed, a channel material layer is formed in the groove. The first barrier material layer is used to block the lateral diffusion of doped ions in the initial first well region into the channel material layer. The initial substrate and the channel material layer are etched to form a substrate, a first fin and a second fin located on the substrate, a first well region located within the first fin and a portion of the substrate, and a second well region located within the second fin and a portion of the substrate. The first fin is formed by a first region of the initial substrate, the second fin is formed by a second region of the initial substrate and the channel material layer, the second fin includes a channel layer formed by the channel material layer, the first well region is formed by the initial first well region, and the second well region is formed by the initial second well region.

2. The semiconductor structure formation method according to claim 1, characterized in that, The modification process includes performing an ion implantation process on the initial first well region exposed on the sidewall of the groove.

3. The semiconductor structure formation method as described in claim 2, characterized in that, The process parameters for the ion implantation process include: implanted ions include N-type ions or P-type ions, and the dose range of the implanted ions is 2E12 atom / cm². 2 Up to 2E13 atom / cm 2 The energy range is from 0.5 keV to 3 keV.

4. The semiconductor structure formation method as described in claim 3, characterized in that, The conductivity type of the implanted ions is different from the conductivity type of the initial first well region.

5. The semiconductor structure formation method as described in claim 4, characterized in that, The implanted ions also include carbon ions.

6. The semiconductor structure formation method according to claim 2, characterized in that, The first barrier material layer is also located at the bottom of the trench, and the method for forming the first barrier material layer further includes: the ion implantation further doping the bottom of the trench; and the first barrier material layer being etched to form a first barrier layer when the initial substrate and the channel material layer are etched.

7. The semiconductor structure formation method according to claim 2, characterized in that, The modification process further includes performing a heat treatment process after the ion implantation process.

8. The semiconductor structure formation method according to claim 1, characterized in that, The second fin also includes a second barrier layer located between the substrate and the channel layer.

9. The semiconductor structure formation method as described in claim 8, characterized in that, The method for forming the second barrier layer includes: forming a second barrier material layer on the sidewall and bottom surface of the groove after forming a first barrier material layer and before forming the channel material layer; and etching the initial substrate and the channel material layer to form the second barrier layer.

10. The semiconductor structure formation method as described in claim 9, characterized in that, The formation process of the second barrier material layer includes an epitaxial growth process; the material of the second barrier material layer includes germanium silicon.

11. The semiconductor structure formation method according to claim 1, characterized in that, Also includes: An isolation structure layer is formed on the surface of the substrate, the isolation structure layer being located on the sidewalls of the first fin and the second fin, and exposing the channel layer.

12. The semiconductor structure formation method according to claim 1, characterized in that, The formation process of the initial first well region and the initial second well region includes an ion implantation process. The process parameters of the ion implantation process include: the dopant ions are N-type ions or P-type ions; the dopant ions include phosphorus ions, and the dose range of the phosphorus ions is 6E12 atom / cm. 2 Up to 6E13 atom / cm 2 The energy range is 50 keV to 300 keV; the doping ions include boron ions, and the dose range of the boron ions is 6E12 atom / cm. 2 Up to 6E13 atom / cm 2 The energy range is from 10 keV to 120 keV.

13. The semiconductor structure formation method according to claim 1, characterized in that, The method for forming the initial first well region includes: forming a first mask layer on the initial substrate, the first mask layer exposing the surface of the first region; and implanting a first dopant ion into the first region.

14. The semiconductor structure formation method according to claim 1, characterized in that, The method for forming the initial second well region includes: forming a second mask layer on the initial substrate, the second mask layer exposing the surface of the second region; and implanting a second dopant ion into the second region.

15. The semiconductor structure formation method according to claim 1, characterized in that, The process for forming the groove includes a dry etching process.

16. The semiconductor structure formation method according to claim 1, characterized in that, The material of the channel material layer includes silicon.

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