A small molecule floating gate type organic field effect transistor memory based on fluorenone derivatives and a preparation method thereof

Abstract

The present invention discloses a small molecule floating gate type organic field effect transistor memory based on fluorenone derivatives and a preparation method thereof. The memory includes a substrate, a gate electrode, a gate electrode insulating layer, a charge trapping layer, a semiconductor layer, and source-drain electrodes which are sequentially arranged from bottom to top. The electron trapping layer is composed of a floating gate layer made of a small molecule of fluorenone derivative and a tunneling layer and a charge blocking layer made of a high dielectric constant polymer. The field effect transistor memory of the present invention uses a small molecule material with a simple structure as the floating gate layer, realizes bipolar storage performance, has stable device performance, high tolerance, large storage density, adopts a simple processing technology, can be prepared in a large area, is suitable for the preparation of flexible devices, reduces the production cost of the device, and is conducive to the popularization and application of organic field effect transistor memories.

Description

Technical Field

[0001] The present invention relates to the field of organic field effect transistor memory devices, and specifically to a small molecule floating gate type bipolar organic field effect transistor memory based on fluorenone derivatives and a preparation method thereof. Background Art

[0002] Due to its many advantages such as low cost, easy processing, large area, high-density information storage, single transistor drive, non-destructive reading, and easy integration with circuits, organic field effect transistor non-volatile memories (OFET NVMs) are regarded as the next-generation memories and have broad application prospects. For OFET NVMs, the ability of the charge trapping layer material to capture and release charges is a key factor in generating storage phenomena, increasing the number of read / write / erase cycles, and maintaining time. According to the different charge trapping layer materials, OFET NVMs can be divided into three categories: floating gate type, ferroelectric type, and polymer dielectric type. Among these memories, floating gate type memories can regulate the operating voltage and storage characteristics by regulating the charge trapping sites and tunneling layers, and have become a type of widely studied memories.

[0003] In floating gate type OFET NVMs, using small molecules as the floating gate layer has obvious advantages compared with traditional polymers, inorganic carbon materials, and metal nanoparticles as the floating gate layer. Small molecules have a clear structure, stable properties, and the energy band structure of small molecules can be adjusted according to requirements. Compared with traditional continuous floating gate type OFET NVMs, the small molecule floating gate type OFET NVMs use a molecular-level discontinuous floating gate layer as the charge storage layer, increasing the storage density and suppressing the leakage current, improving the storage characteristics, maintaining time, and stability of the memory, while reducing the thickness of the insulating layer and lowering device operating voltage and other parameters. Therefore, small molecule floating gate type OFET NVMs have significant storage advantages, attracting high attention from scientists and the industrial community, and having good industrial development value. However, currently, there are few small molecule materials applied to small molecule floating gate type field effect transistor memories, and they are concentrated in unipolar memories. It is difficult to achieve bipolar high-performance storage with a single small molecule material. Summary of the Invention

[0004] In view of the above problems existing in the existing small molecule floating gate type organic field effect transistors, the present invention proposes a small molecule floating gate type bipolar organic field effect transistor memory based on a small molecule material with excellent hole and electron capture capabilities, effectively solving the problems of achieving bipolar storage with a single molecule and simplifying the device preparation process, preparing a bipolar, high-density, high-speed, and high-stability and tolerance storage device, showing great potential value in the storage field.

[0005] In order to solve the above technical problems, the technical solutions adopted by the present invention are as follows:

[0006] The present invention provides a small molecule floating gate organic field effect transistor memory based on fluorenone derivatives. The memory includes a substrate, a gate electrode, a gate electrode insulating layer (i.e., gate insulating layer), a charge trapping layer, a semiconductor layer, and source-drain electrodes, which are arranged in sequence from bottom to top. The electron trapping layer is a composite film composed of small molecule fluorenone derivatives and a high dielectric constant polymer. The two source-drain electrodes are respectively arranged on both sides of the upper surface of the semiconductor layer.

[0007] The small molecule fluorenone derivative serves as a floating gate material and has the function of storing charges; the high dielectric constant polymer serves as a tunneling material and a charge blocking material and has the functions of tunneling and charge blocking.

[0008] Furthermore, a small molecule fluorenone derivative (TFO) has the following structural general formula:

[0009]

[0010] R1 and R2 are respectively hydrogen or a straight-chain, branched-chain or cyclic alkyl chain having 1 to 15 carbon atoms;

[0011] The high dielectric constant polymer is one or two of polystyrene and polyvinylpyrrolidone.

[0012] Furthermore, the small molecule fluorenone derivative TFO and the high dielectric constant polymer are respectively prepared into solutions with a concentration of 5 - 10 mg / mL, and are doped by a volume ratio of 1:(1 - 10) or 2:1, and a composite film is obtained by spin coating in air.

[0013] Furthermore, the source-drain electrode material is one of a metal or an organic semiconductor material, and its thickness is 50 - 100 nm;

[0014] The semiconductor layer is made of a P-type organic semiconductor layer material or an n-type semiconductor material; the P-type organic semiconductor layer material is one of pentacene, tetracene, rubrene, 3-hexylthiophene, titanium bronze or titanium fluoride bronze, and the n-type semiconductor material is C60, and its thickness is 35 - 50 nm;

[0015] The gate electrode insulating layer material is one of silicon dioxide, aluminum oxide, zirconium oxide, polystyrene or polyvinylpyrrolidone, and its thickness is 50 - 300 nm;

[0016] The gate electrode material is one of highly doped silicon, aluminum, copper, silver, gold, titanium or tantalum;

[0017] The substrate material is one of a highly doped silicon wafer, glass or plastic PET.

[0018] The present invention also provides a method for preparing the above-mentioned organic field-effect transistor memory, which includes the following steps:

[0019] (1) Select a fluorenone derivative (TFO) and a high-k polymer, and use heating or ultrasonic treatment to fully dissolve them in toluene. After 24 hours, dope TFO with the high-k polymer solution by volume ratio to obtain a mixed solution;

[0020] (2) Use a heavily doped silicon wafer as the substrate and gate electrode, and thermally grow a gate insulating layer on the heavily doped silicon wafer. The substrate, gate electrode, and gate insulating layer form a substrate, which is cleaned and dried after cleaning;

[0021] (3) Expose the clean substrate in step (2) to ultraviolet light for 10 minutes, then place it on the platform of a spin coater, adjust the rotation speed to 2500 - 3000 rpm, drop 140 μl of the mixed solution in step (1), and spin coat in air for 25 - 30 s. The spin-coated sample is annealed in a vacuum drying oven at 80°C for 30 minutes to obtain a charge trapping layer with a thickness of 10 - 30 nm;

[0022] (4) Vacuum deposit a semiconductor layer and source / drain electrodes on the dried charge trapping layer to obtain a small molecule floating gate type organic field-effect transistor memory.

[0023] Furthermore, the evaporation rate during the vacuum deposition of the semiconductor layer is The vacuum degree is 5×10 -4 -4×10 -5 ; When depositing the source / drain electrodes, select an electrode mask with a channel length L = 150 μm and a width W = 1500 μm, and the evaporation rate is The vacuum degree is 5×10 -4 -4×10 -5 .

[0024] The present invention has the following beneficial effects: The present invention applies a small molecule fluorenone derivative as a floating gate layer to organic field-effect transistor storage, providing a storage device with bipolarity, high density, high speed, high stability, and high tolerance. Compared with the prior art, it has the following advantages:

[0025] 1. The present invention provides a simple organic small molecule, which is blended with a high-k polymer and spin-coated to obtain a flat composite film as the charge trapping layer. This method has a simple process and low cost.

[0026] 2. The organic field-effect transistor memory provided by the present invention not only realizes bipolar storage (87.1 V), but also has a relatively high mobility (0.24 cm 2 V -1 S -1) and on / off ratio (10 4 ).

[0027] 3. The organic field-effect transistor memory provided by the present invention realizes a large storage window, has good storage stability and tolerance, and there is no obvious charge leakage after 10,000 s of testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of the organic field-effect transistor memory based on fluorenone terfluorene according to an embodiment of the present invention;

[0029] Figure 2 is an AFM photograph of the composite film of fluorenone terfluorene and high-dielectric-constant PS (TFO / PS) according to Embodiment 1 of the present invention;

[0030] Figure 3 is a transfer characteristic curve of the organic field-effect transistor memory test according to Embodiment 1 of the present invention;

[0031] Figure 4 is a transfer characteristic curve of the organic field-effect transistor memory test according to Embodiment 2 of the present invention;

[0032] Figure 5 is a forward storage window characteristic curve of the organic field-effect transistor memory test according to Embodiment 2 of the present invention;

[0033] Figure 6 is a negative storage window characteristic curve of the organic field-effect transistor memory test according to Embodiment 2 of the present invention;

[0034] Figure 7 is a retention time characteristic curve of the organic field-effect transistor memory test according to Embodiment 2 of the present invention;

[0035] Figure 8 is a read / write / erase cycle characteristic curve of the organic field-effect transistor memory test according to Embodiment 2 of the present invention;

[0036] Figure 9 is a forward storage window characteristic curve of the organic field-effect transistor memory test according to Embodiment 3 of the present invention;

[0037] Figure 10 is a negative storage window characteristic curve of the organic field-effect transistor memory test according to Embodiment 3 of the present invention;

[0038] Figure 11 is a general structure diagram of the organic field-effect transistor memory based on fluorenone terfluorene of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0039] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the accompanying drawings. The present invention can be implemented in different forms and is not limited to the embodiments described in the text. On the contrary, the embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0040] Embodiment 1

[0041] Figure 1 Shown is the organic field-effect transistor memory structure provided in this embodiment. The memory includes a substrate, a gate electrode, a gate electrode insulating layer, a charge trapping layer, a semiconductor layer, and source-drain electrodes which are arranged in sequence from bottom to top. Among them, the electron trapping layer is a composite film composed of fluorene ketone derivative small molecules and a high dielectric constant polymer. The fluorene ketone derivative small molecules serve as the floating gate layer (floating gate material), and the high dielectric constant polymer serves as the tunneling layer and the charge blocking layer (tunneling material and charge blocking material).

[0042] Among them, heavily doped silicon is used as the substrate and the gate electrode; silicon dioxide with a thickness of 300 nm is used as the gate insulating layer; the small molecule fluorene ketone trimer and polystyrene are blended in a mass ratio of 1:10, and the charge trapping layer is obtained by spin coating on the gate insulating layer, and its thickness is 25 nm; a pentacene layer with a thickness of 50 nm is used as the semiconductor layer; copper is the material of the source-drain electrodes, and the thickness is 100 nm.

[0043] The molecular structural formula of the fluorene ketone trimer - 2,7-(9,9-din-propylfluorene-2-yl)-fluorene ketone is as follows:

[0044]

[0045] The solvent for preparing the mixed solution is toluene and has not undergone any treatment. At the same time, the preparation process is carried out at room temperature.

[0046] The specific preparation steps of the memory described in Embodiment 1 are as follows:

[0047] Step (1): The fluorene ketone trimer and polystyrene are respectively dissolved in toluene (used as the solvent) to obtain a fluorene ketone trimer solution and a polystyrene solution; the solution concentration is 10 mg / mL for both (it means the concentration of the fluorene ketone trimer in the fluorene ketone trimer solution is 10 mg / mL; the concentration of polystyrene in the polystyrene solution is 10 mg / mL, the same hereinafter). After one day, the fluorene ketone trimer solution and the polystyrene PS solution are prepared into a mixed solution for use according to a volume ratio of 1:10.

[0048] Step (2): Use SiO2 with a thickness of 300 nm thermally grown on a heavily doped silicon wafer as the gate insulating layer. The heavily doped silicon wafer (including the substrate and the gate electrode) and the gate insulating layer form a substrate (which is still a silicon wafer). Use a diamond pen to cut the silicon wafer (i.e., the substrate) into a size of 1.5 * 1.5 cm to make it consistent with the specifications of the electrode mask template for fabricating the device. Ultrasonically clean the cut substrate successively with acetone - ethanol - ultrapure water for 10 minutes, then blow it dry with nitrogen, put it into an oven at 120 °C, dry it for 30 minutes, and then perform ultraviolet ozone treatment in an ultraviolet ozone treatment instrument with a power of 100 W for 10 minutes;

[0049] Step (3): Place the silicon wafer (i.e., the substrate) processed in the above step (2) on the spinning platform of a spin coater, adjust the rotation speed to 3000 rpm, drop 140 μL of the mixed solution in step (1), and spin coat for 30 s. Obtain a uniform thin film with a thickness of about 25 nm, and anneal this thin film in a vacuum drying oven at 80 °C for 30 minutes to obtain the charge trapping layer of the device.

[0050] Step (4): Put the device obtained in the above step (3) into a vacuum evaporation chamber and evaporate the semiconductor layer. Close the chamber door, evacuate to below 5 * 10 -4 Pa, then turn on the heater, and control the evaporation rate to be stable at or so by adjusting the heating temperature, start evaporating the semiconductor layer with a thickness of about 50 nm. After the organic semiconductor layer evaporation is completed, close the baffle, turn off the heating source, and cool it in vacuum for 30 minutes to prevent the organic semiconductor from being oxidized, and then take out the sample.

[0051] Step (5): Evaporate the source and drain electrodes. Select a mask with a channel length L = 150 μm and a width W = 1500 μm, place the device in step (4) on the mask template, and put it into the evaporation chamber. When the vacuum degree of the evaporation chamber reaches below 5 × 10 -4 Pa, slowly heat the metal source, and control the evaporation rate to be stable at or so by adjusting the heating current, start evaporating the electrodes with a thickness of about 100 nm. After evaporating the electrodes, cool the entire evaporation system for one hour, take out the device, and the device fabrication is completed.

[0052] The light source used in the experiment is a light - emitting diode. The electrical properties of the device are tested on a Keithley 2636B dual - channel digital source meter. All electrical property tests are completed in an air environment. The transfer curve plotted from the data processing is as Figure 3 shown, and the mobility reaches 0.24 cm 2 V -1 S -1 .

[0053] Figure 2 It is the AFM photograph of the composite thin film of the fluorene trimer molecular floating gate layer. As can be seen from the figure, the spin-coated blend film is flat, which is beneficial to improving the carrier mobility and charge trapping density.

[0054] Example 2

[0055] Example 2 is generally the same as Example 1 in terms of device structure and preparation process, except for the following differences:

[0056] The fluorene trimer and polystyrene are respectively dissolved in toluene, and the solution concentration is 10 mg / mL for both. After one day, the fluorene trimer solution and the PS solution are prepared into a blend solution in a volume ratio of 2:1 for standby.

[0057] Figure 4 It is the transfer curve of the device, and the on / off ratio reaches 10 4 .

[0058] Figure 5 It is the forward storage window characteristic curve of the device test. As can be seen from the figure, when the writing voltage is 80 V and light is applied for 1 s, the forward storage window can reach 48 V. When a voltage of -40 V is applied for 1 s, it can return to the original position.

[0059] Figure 6 It is the negative storage window characteristic curve of the device test. As can be seen from the figure, when the writing voltage is -80 V for 1 s, the negative storage window can reach 39.1 V. When a positive voltage of 10 V is applied and light is applied for 1 s, it can return to the original position.

[0060] Figure 7 It is the retention time characteristic curve of the device test. As can be seen from the figure, within 10 4 s, the device shows stable programming and erasing states.

[0061] Figure 8 It is the read / write / erase cycle characteristic curve of the device test. As can be seen from the figure, after 100 read / write / erase cycles, the device shows stable programming and erasing states.

[0062] Example 3

[0063] Example 3 is generally the same as Example 1 in terms of device structure and preparation process, except for the following differences:

[0064] Polystyrene is dissolved in toluene to obtain a polystyrene solution, and the concentration of polystyrene in the polystyrene solution is 10 mg / mL. This solution is directly used as the charge trapping layer by spin coating.

[0065] Figure 9It is the forward storage window characteristic curve of device testing. It can be seen from the figure that when the writing voltage is 80V for 1s, the forward storage window is only 10.2V. Applying a voltage of -80V for 1s can return to the original position. This shows that the forward storage is mainly generated by the capture of electrons by the fluorenone trimer.

[0066] Figure 10 It is the negative storage window characteristic curve of device testing. It can be seen from the figure that when the writing voltage is -80V for 1s, the forward storage window is only 4.9V. Applying a voltage of 10V for 1s can return to the original position. This shows that the negative storage is mainly generated by the capture of holes by the fluorenone trimer.

[0067] The present invention adopts a small molecule floating gate type organic field effect transistor memory based on a fluorenone derivative. Among them, a small molecule material with a simple structure is used as the floating gate layer, realizing bipolar storage performance. The device has stable performance, high tolerance, large storage density, and the adopted processing technology is simple, can be prepared on a large scale, is suitable for the preparation of flexible devices, and at the same time reduces the production cost of the device, which is beneficial to the popularization and application of the organic field effect transistor memory.

[0068] Although the embodiments of the present invention have been disclosed as above, it is not limited to the applications listed in the specification and embodiments. It can be fully applied to various fields suitable for the present invention. For those familiar with the field, additional modifications can be easily made. Therefore, without departing from the general concept defined by the claims and the equivalent scope, the present invention is not limited to specific details.

Claims

1. A small molecule floating gate type organic field effect transistor memory based on fluorenone derivatives, the memory comprising a substrate, a gate electrode, a gate electrode insulating layer, a charge trapping layer, a semiconductor layer, and source-drain electrodes sequentially arranged from bottom to top, characterized in that: The electron capture layer is a composite film composed of a fluorene ketone derivative small molecule and a high dielectric constant polymer; the fluorene ketone derivative small molecule is 2,7-(9,9-dipropylfluorene-2-yl)-fluorene ketone; the high dielectric constant polymer is one or two of polystyrene and polyvinylpyrrolidone.

2. The organic field effect transistor memory according to claim 1, wherein: The fluorene ketone derivative small molecule serves as a floating gate material, and the high dielectric constant polymer serves as a tunneling material and a charge blocking material.

3. The organic field effect transistor memory according to claim 2, wherein: Prepare 5-10 mg / mL solutions of the fluorene ketone derivative small molecule and the high dielectric constant polymer respectively. The fluorene ketone derivative small molecule solution and the high dielectric constant polymer solution are doped according to a volume ratio of 1:(1-10) or 2:1, and a composite film is obtained by spin coating in air.

4. The organic field effect transistor memory according to claim 1, wherein: The material of the source-drain electrode is one of a metal or an organic semiconductor material, and its thickness is 50-100 nm; The semiconductor layer is made of a P-type organic semiconductor layer material or an n-type semiconductor material; the P-type organic semiconductor layer material is one of pentacene, tetracene, rubrene, 3-hexylthiophene, copper phthalocyanine, or copper phthalocyanine fluoride, and the n-type semiconductor material is C 60 ; the thickness of the semiconductor layer is 35 - 50 nm; The material of the gate electrode insulating layer is one of silicon dioxide, aluminum oxide, zirconium oxide, polystyrene or polyvinylpyrrolidone, and its thickness is 50-300 nm; The material of the gate electrode is one of heavily doped silicon, aluminum, copper, silver, gold, titanium or tantalum; The material of the substrate is one of a heavily doped silicon wafer, glass or plastic PET.

5. A method for preparing an organic field effect transistor memory according to any one of claims 1-4, characterized in that: It includes the following steps: (1) Use heating or ultrasonic treatment to fully dissolve the fluorene ketone derivative small molecule and the high dielectric constant polymer in toluene respectively; after 24 hours, mix the fluorene ketone derivative small molecule solution and the high dielectric constant polymer solution according to the volume ratio to obtain a mixed solution; (2) Use a heavily doped silicon wafer as the substrate and the gate electrode, and prepare the gate insulating layer by thermal growth on the heavily doped silicon wafer. The substrate, the gate electrode and the gate insulating layer form a substrate. After cleaning the substrate, dry it; (3) Expose the clean substrate in step (2) to ultraviolet light, then place it on the platform of a spin coater, adjust the rotation speed to 2500-3000 rpm, drop the mixed solution obtained in step (1), and spin coat in air for 25-30 s; place the spin-coated sample in a vacuum drying oven for annealing treatment to obtain a charge capture layer with a thickness of 10-30 nm; (4) Vacuum deposit a semiconductor layer and source-drain electrodes on the dried charge capture layer to obtain a small molecule floating gate type organic field effect transistor memory.

6. The preparation method according to claim 5, characterized in that: In step (4), the evaporation rate during the vacuum evaporation of the semiconductor layer is 0.2 Å / s, and the vacuum degree is 5× 10 -4 -4× 10 -5 Pa; when evaporating the source and drain electrodes, an electrode mask with a channel length L = 150 μm and a width W = 1500 μm is used, the evaporation rate is 0.5 Å / s, and the vacuum degree is 5×10 -4 -4×10 -5 Pa.

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