Amplifier bias compensation circuit

Abstract

A bias compensation circuit includes a detection circuit comprising a diode-connected transistor circuit having a first terminal for receiving a first current and a second terminal; and a first diode circuit having a first terminal for receiving a second current and a second terminal; wherein the detection circuit provides a first voltage level based on the diode-connected transistor circuit and provides a second voltage level based on the first diode circuit; a voltage-to-current conversion circuit coupled to the detection circuit for generating a first reference current based on the first voltage level and the second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit for receiving the first reference current to provide a bias level based on the first reference current.

Description

Technical Field

[0001] This invention relates to a circuit, and more particularly to a bias compensation circuit for an amplifier. Background Technology

[0002] In existing technologies, power amplifiers are widely used in various circuits to improve signal quality. In this context, bias circuits can be used to enhance the performance of the power amplifier. However, depending on its process corners, the current through the power amplifier can deviate, resulting in varying (unstable) performance. Furthermore, the power amplifier's temperature varies with its input power, which also affects the current flowing through it. Therefore, compensating for the effects of these factors on the current to maintain stability of the current flowing through the power amplifier is a pressing problem that needs to be solved. Summary of the Invention

[0003] This invention provides a bias compensation circuit to solve the above-mentioned problems.

[0004] This invention discloses a bias compensation circuit, comprising a detection circuit, a diode-connected transistor circuit having a first terminal for receiving a first current and a second terminal coupled to a first reference voltage terminal; and a first diode circuit having a first terminal for receiving a second current and a second terminal coupled to the first reference voltage terminal; wherein the detection circuit provides a first voltage level based on the diode-connected transistor circuit and a second voltage level based on the first diode circuit; a voltage-to-current conversion circuit coupled to the detection circuit for generating a first reference current based on the first voltage level and the second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit for receiving the first reference current to provide a bias level based on the first reference current.

[0005] The present invention further discloses a bias compensation circuit for providing a bias level to a first amplifying transistor, comprising a detection circuit including a diode-connected transistor circuit having a first terminal for receiving a first current and a second terminal coupled to a first reference voltage terminal; wherein the detection circuit provides a first voltage level based on the diode-connected transistor circuit, the diode-connected transistor circuit including a diode-connected transistor, and the first amplifying transistor and the diode-connected transistor having the same or similar process corners; a voltage-to-current conversion circuit coupled to the diode-connected transistor circuit for generating a first reference current based on the first voltage level and a second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit for receiving the first reference current to provide the bias level to the first amplifying transistor based on the first reference current. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the bias compensation circuit in Embodiment 1 of the present invention.

[0007] Figure 2 This is a schematic diagram of the bias compensation circuit in Embodiment 1 of the present invention.

[0008] Figure 3 This is a schematic diagram of the bias compensation circuit in Embodiment 1 of the present invention.

[0009] Figure 4 This is a schematic diagram of the bias compensation circuit in Embodiment 1 of the present invention.

[0010] Figure 5 This is a schematic diagram of the bias circuit in Embodiment 1 of the present invention.

[0011] Figure 6A , Figure 6B This is a schematic diagram of the bias circuit in Embodiment 1 of the present invention.

[0012] Figure 7 This is a schematic diagram of the bias compensation circuit in Embodiment 1 of the present invention.

[0013] Symbol Explanation

[0014] 10, 20, 30, 40, 70: Bias compensation circuit

[0015] 100, 200, 300, 400, 700: Detection circuit

[0016] 102, 202, 402, 702: Transistor circuits connected in diode form.

[0017] 104, 204, 306: Diode circuits

[0018] 110, 210: Voltage-to-current conversion circuit

[0019] 120, 50, 60A, 60B: Bias circuit

[0020] C1: Capacitor

[0021] CS1, CS2, CS3, CS4: Current Sources

[0022] D1, D2: Diodes

[0023] E_CPA1, E_C53, E_C65: Transistor control terminals

[0024] E1~E20, E_P1, E_P2: Endpoints

[0025] FC1, FC2: Filter circuits

[0026] I1, I2, I3, Icc: Current

[0027] Iadp: Adaptable Current

[0028] Ibias: Bias current

[0029] Iref, Iref1, Iref2: Reference currents

[0030] K1, K2, K3: Parameters

[0031] M_PA1, M_PA2: Amplifying transistors

[0032] M1, M2, M3, M51, M52, M64: Transistors connected in diode form.

[0033] M53, M65: Transistors

[0034] R1, R2, R3, R5: Resistors

[0035] R4: Resistor circuit

[0036] RFin: Input signal

[0037] RFout: Output signal

[0038] S_in: Signal input terminal

[0039] S_out: Signal output terminal

[0040] V_REF1, V_REF2: Reference voltage terminals

[0041] VDD: System voltage terminal

[0042] VGS, V_D1, V_D2: On-state voltage

[0043] VBG1,VF,VBE,VBG: Voltage levels

[0044] VGG: Bias Level

[0045] VOUT: Output voltage level Detailed Implementation

[0046] Figure 1 This is a schematic diagram of a bias compensation circuit 10 according to an embodiment of the present invention. The bias compensation circuit 10 can be used in an amplifier (e.g., a power amplifier). The bias compensation circuit 10 includes a detection circuit 100, a voltage-to-current conversion circuit 110, and a bias circuit 120. The detection circuit 100 includes a transistor circuit 102 and a diode circuit 104 connected in a diode configuration. The diode-connected transistor circuit 102 has a first terminal E1 and a second terminal E2. The first terminal E1 of the diode-connected transistor circuit 102 can be used to receive current I1, and the second terminal E2 of the diode-connected transistor circuit 102 can be coupled to a reference voltage terminal V_REF1. The diode circuit 104 has a first terminal E3 and a second terminal E4. The first terminal E3 of the diode circuit 104 can be used to receive current I2, and the second terminal E4 of the diode circuit 104 can be coupled to the reference voltage terminal V_REF1. The voltage-to-current conversion circuit 110 is coupled to the diode-connected transistor circuit 102 and diode circuit 104. The bias circuit 120 is coupled to the voltage-to-current conversion circuit 110. Specifically, the detection circuit 100 provides a voltage level VBG1 according to the diode-connected transistor circuit 102, and a voltage level VF according to the diode circuit 104. Based on the voltage levels VBG1 and VF, the voltage-to-current conversion circuit 110 generates a reference current Iref. The bias circuit 120 receives the reference current Iref to provide a bias level VGG based on the reference current Iref.

[0047] It is important to note that transistors can exhibit different behaviors depending on factors such as voltage or temperature. Therefore, transistors will have different characteristics due to different process parameters. Transistor process parameters can be categorized into TT, FF, and SS. When two transistors have the same or similar process parameters, the process variation between them is small. Conversely, when two transistors have significantly different process parameters, the process variation between them is large.

[0048] In one embodiment, current source CS1 may be coupled to the first terminal E1 of transistor circuit 102 connected in diode form, and current source CS1 may be used to provide current I1. In one embodiment, current source CS2 may be coupled to the first terminal E3 of diode circuit 104, and current source CS2 may be used to provide current I2. In one embodiment, reference voltage terminal V_REF1 may be a ground voltage or a common voltage, but is not limited thereto.

[0049] In one embodiment, a bias level VGG may be provided to an amplifier (e.g., an amplifying transistor). In one embodiment, a diode-connected transistor circuit 102 may include at least one diode-connected transistor, and the at least one diode-connected transistor has the same or similar process parameters as the amplifying transistor. In one embodiment, a voltage level VF may be one of a voltage level that is not easily affected by process variations (e.g., a voltage level independent of process variations) VBE or a voltage level that is not easily affected by temperature variations (e.g., a voltage level independent of temperature variations) VBG. In one embodiment, if the voltage level VF is a voltage level VBE, the diode-connected transistor circuit 102 may be used to detect process parameters. In one embodiment, the distance between the diode circuit 104 and the amplifying transistor is greater than the distance between the diode-connected transistor circuit 102 and the amplifying transistor. In this case, if the voltage level VF is a voltage level VBG, the diode-connected transistor circuit 102 may be used to detect the temperature of the amplifying transistor.

[0050] Based on the foregoing description, the present invention provides a bias compensation circuit that can be used to adjust the magnitude of a reference current. According to the reference current, the bias circuit can provide a bias level to adjust the current passing through the amplifier. Therefore, the current passing through the amplifier can be adjusted, and the effects of amplifier process variations and temperature on this current can be reduced.

[0051] Figure 2This is a schematic diagram of a bias compensation circuit 20 according to an embodiment of the present invention. The bias compensation circuit 20 includes a detection circuit 200, a voltage-to-current conversion circuit 210, and a bias circuit 120. The detection circuit 200 can be used to implement the detection circuit 100, and the voltage-to-current conversion circuit 210 can be used to implement the voltage-to-current conversion circuit 110. The detection circuit 200 includes a transistor circuit 202 and a diode circuit 204 connected in a diode configuration. The diode-connected transistor circuit 202 may include a transistor M1 and a transistor M2 connected in a diode configuration. The diode-connected transistor circuit 202 has a first terminal E1 and a second terminal E2. The diode-connected transistor M1 is coupled to the first terminal E1 of the diode-connected transistor circuit 202, and the diode-connected transistor M2 is coupled between the diode-connected transistor M1 and the second terminal E2 of the diode-connected transistor circuit 202. The diode circuit 204 has a first terminal E3 and a second terminal E4. The diode circuit 204 may include a diode D1. In detail, according to the diode-connected transistor circuit 202, the detection circuit 200 can provide a voltage level VBG1, and according to the diode circuit 204, the detection circuit 200 can provide a voltage level VBE. Based on the voltage levels VBG1 and VBE, the voltage-to-current conversion circuit 210 can generate a reference current Iref. After receiving the reference current Iref, the bias circuit 120 can provide a bias level VGG to the amplifier, which can have an amplifying transistor M_PA1.

[0052] In one embodiment, the voltage-to-current conversion circuit 210 may include an adder 212 and a voltage-to-current converter 214. The adder 212 may be coupled to the detection circuit 200, and the voltage-to-current converter 214 may be coupled to the adder 212. In one embodiment, the adder 212 may generate an output voltage level VOUT based on voltage levels VBG1 and VBE. In one embodiment, the voltage-to-current converter 214 may generate a reference current Iref based on the output voltage level VOUT.

[0053] In one embodiment, the detection circuit 200 may include at least one of resistors R1 and R2. That is, when the process parameter is TT, the voltage level VBG1 and the voltage level VBE are equal, then resistors R1 and R2 may be present simultaneously or only one of them may be present. In one embodiment, resistor R1 may be coupled to the first terminal E1 of the diode-connected transistor circuit 202. In one embodiment, resistor R2 may be coupled to the first terminal E3 of the diode circuit 204. In one embodiment, current source CS1 may be coupled to resistor R1. In one embodiment, current source CS2 may be coupled to resistor R2. In one embodiment, based on the diode-connected transistor circuit 202 and resistor R1, the detection circuit 200 can provide the voltage level VBG1. In one embodiment, based on the diode circuit 204 and resistor R2, the detection circuit 200 can provide the voltage level VBE. That is, resistor R1 can be used to adjust the voltage level VBG1, and resistor R2 can be used to adjust the voltage level VBE. In one embodiment, voltage level VBG1 and voltage level VBE can be generated according to the following procedures:

[0054] VBG1=I1*R1+N*VGS (Equation 1)

[0055] VBE=I2*R2+V_D1 (Equation 2)

[0056] Where N is the number of diode-connected transistors in series in the diode-connected transistor circuit 202, VGS is the forward voltage of the diode-connected transistor, and V_D1 is the forward voltage of diode D1.

[0057] In one embodiment, the diode-connected transistor circuit 202 may include at least one of a diode-connected transistor M1 and a diode-connected transistor M2. In one embodiment, at least one diode-connected transistor M1 or M2 in the diode-connected transistor circuit 202 has the same or similar process parameters as the amplifying transistor M_PA1.

[0058] In one embodiment, the bias circuit 120 provides a bias level VGG to the amplifying transistor M_PA1. In one embodiment, the input signal RFI can be input through the signal input terminal S_in, and the input signal RFI can be input to the control terminal E_CPA1 of the amplifying transistor M_PA1. The adaptability current Iadp can be generated according to the power of the input signal RFI based on the bias level VGG. It should be noted that the adaptability current Iadp may have different magnitudes due to offset depending on the process parameters of the amplifying transistor M_PA1. Furthermore, in the absence of an input signal RFI, the magnitude of the adaptability current Iadp is 0. In one embodiment, the output signal RFout can be output through the signal output terminal S_out, where the current Icc is the operating current flowing through the amplifying transistor M_PA1, and the signal output terminal S_out can be located at the first terminal E_P1 of the amplifying transistor M_PA1. In one embodiment, the second terminal E_P2 of the amplifying transistor M_PA1 can be coupled to the reference voltage terminal V_REF1.

[0059] Since diode-connected transistors M1 and M2 have the same or similar process parameters as amplifying transistor M_PA1, the voltage level VBG1 will change with variations in the process of amplifying transistor M_PA1, while the voltage level VBE is less affected by these variations. Therefore, the detection circuit 200 can detect variations in the process of amplifying transistor M_PA1 based on the voltage level VBG1 and generate a corresponding reference current Iref to compensate for these variations. In other words, the diode-connected transistor circuit 202 can be used to detect process parameters, ensuring that amplifying transistors M_PA1 manufactured with different process parameters can still have the same or similar adaptability current Iadp under different power input signals RFI. This, in turn, ensures that the operating current Icc flowing through amplifying transistor M_PA1 is the same or similar, so that amplifying transistor M_PA1 maintains the same or similar linearity under different process parameters. For example, the detection circuit 200 can make the amplifying transistor M_PA1 manufactured with different process parameters have the same or similar power-adaptive current Iadp relationship curves of the input signal RFin.

[0060] Figure 3This is a schematic diagram of a bias compensation circuit 30 according to an embodiment of the present invention. The bias compensation circuit 30 includes a detection circuit 300, a voltage-to-current conversion circuit 210, and a bias circuit 120. Compared to the bias compensation circuit 20, the detection circuit 300 further includes a diode circuit 306. The diode circuit 306 has a first terminal E5 and a second terminal E6. The first terminal E5 of the diode circuit 306 can be used to receive current I3, and the second terminal E6 of the diode circuit 306 can be coupled to a reference voltage terminal V_REF1. The diode circuit 306 may include a diode D2. According to the diode circuit 306, the detection circuit 200 can provide a voltage level VBG.

[0061] In one embodiment, the detection circuit 300 may include a resistor R3, which is coupled to a first terminal E5 of the diode circuit 306. In one embodiment, a current source CS3 may be coupled to the resistor R3, and the current source CS3 may be used to provide a current I3. In one embodiment, based on the diode circuit 306 and the resistor R3, the detection circuit 300 can provide a voltage level VBG. That is, the resistor R3 may be used to adjust the voltage level VBG. In one embodiment, the voltage level VBG may be generated according to the following procedure:

[0062] VBG = I3*R3 + V_D2 (Equation 3)

[0063] Where V_D2 is the forward voltage of diode D2. In one embodiment, adder 212 can generate output voltage level VOUT based on voltage levels VBG1, VBE, and VBG. Based on output voltage level VOUT, voltage-to-current converter 214 can generate reference current Iref. Based on reference current Iref, bias circuit 120 can provide bias level VGG.

[0064] The operation and function of other circuit components can be found in the preceding paragraphs and will not be repeated here.

[0065] In one embodiment, the diode-connected transistor circuit 202 may include at least one of diode-connected transistor M1 and diode-connected transistor M2. In one embodiment, at least one diode-connected transistor M1 or M2 in the diode-connected transistor circuit 202 has the same or similar process parameters as the amplifying transistor M_PA1. In this case, when voltage levels VBE and VBG are present, since the diode-connected transistor circuit 202 and the amplifying transistor M_PA1 have the same or similar process parameters, the diode-connected transistor circuit 202 can be used to detect the process parameters. Its principle and function can be referred to the preceding paragraphs and will not be repeated here.

[0066] In one embodiment, the distance between diode circuit 204 and amplifying transistor M_PA1 is greater than the distance between diode circuit 306 and amplifying transistor M_PA1. For example, diode circuit 306 and amplifying transistor M_PA1 may be disposed on the same die, while diode circuit 204 may be disposed on another die. In this case, diode circuit 306 can be used to detect the temperature of amplifying transistor M_PA1, so that amplifying transistor M_PA1 at different temperatures, under different power input signals RFI, can still have the same or similar adaptability current Iadp, thereby making the operating current Icc flowing through amplifying transistor M_PA1 the same or similar, so that amplifying transistor M_PA1 still has the same or similar linearity at different temperatures. For example, detection circuit 200 can make amplifying transistor M_PA1 at different temperatures have the same or similar power-adaptability current Iadp relationship curves for input signal RFI.

[0067] In one embodiment, the output voltage level VOUT can be generated according to the following procedure:

[0068] VOUT=K1*VBG+K2*(VBG–VBE)+K3*(VBG1–VBE) (Equation 4)

[0069] Where K1 is the basic parameter, K2 is the temperature compensation parameter, and K3 is the process compensation parameter. Specifically, the voltage level VBE changes with the temperature of the amplifying transistor M_PA1, while the voltage level VBG does not change significantly with the temperature of the amplifying transistor M_PA1. Therefore, the detection circuit 300 can detect the temperature change of the amplifying transistor M_PA1 based on the voltage levels VBE and VBG, and use this information to compensate for the effects of the temperature change. On the other hand, the voltage level VBG1 changes with variations in the process technology of the amplifying transistor M_PA1, while the voltage level VBE does not change significantly with variations in the process technology of the amplifying transistor M_PA1. Therefore, the detection circuit 300 can detect variations in the process technology of the amplifying transistor M_PA1 based on the voltage levels VBG1 and VBE, and use this information to compensate for the effects of the variations in the process technology of the amplifying transistor M_PA1. It should be noted that (Equation 4) can be appropriately adjusted according to the number of voltage levels supplied to the adder 212. In one embodiment, K1, K2, and K3 can be set to appropriate values ​​of 0 or non-zero according to design requirements, and K1, K2, and K3 will not all be 0 at the same time.

[0070] Figure 4This is a schematic diagram of a bias compensation circuit 40 according to an embodiment of the present invention. The bias compensation circuit 40 includes a detection circuit 400, a voltage-to-current conversion circuit 210, and a bias circuit 120. The detection circuit 400 includes a transistor circuit 402, a diode circuit 204, and a diode circuit 306 connected in a diode configuration. Compared to the bias compensation circuit 20, the resistors may be omitted entirely or partially, or the diode-connected transistor circuit 402 may only include a diode-connected transistor M3. The diode-connected transistor M3 may be a diode-connected transistor M1 or a diode-connected transistor M2, and is not limited thereto. The operation of the bias compensation circuit 20 or the bias compensation circuit 30 can be applied to the bias compensation circuit 40, and will not be described in detail here.

[0071] Figure 5 This is a schematic diagram of a bias circuit 50 according to an embodiment of the present invention. The bias circuit 50 can be used to implement the bias circuit 120. The bias circuit 50 may include a diode-connected transistor M51, a diode-connected transistor M52, a transistor M53, and a capacitor C1. The diode-connected transistor M51 has a first terminal E7 and a second terminal E8, and the diode-connected transistor M52 has a first terminal E9 and a second terminal E10. The transistor M53 has a first terminal E11, a second terminal E12, and a control terminal E_C53. The capacitor C1 has a first terminal E13 and a second terminal E14. The first terminal E7 of the diode-connected transistor M51 can be used to receive a reference current Iref. The reference current Iref can be provided by the aforementioned voltage-to-current conversion circuit 210. The first terminal E9 of the diode-connected transistor M52 can be coupled to the second terminal E8 of the diode-connected transistor M51, and the second terminal E10 of the diode-connected transistor M52 can be coupled to the reference voltage terminal V_REF1. The first terminal E11 of transistor M53 can be coupled to the system voltage terminal VDD, and the control terminal E_C53 of transistor M53 can be coupled to the first terminal E7 of transistor M51, which is connected in a diode configuration. The first terminal E13 of capacitor C1 can be coupled to the first terminal E7 of transistor M51 (connected in a diode configuration) and the control terminal E_C53 of transistor M53, and the second terminal E14 of capacitor C1 can be coupled to the reference voltage terminal V_REF1.

[0072] In one embodiment, the bias circuit 50 provides a bias level VGG at the second terminal E12 of transistor M53 to amplifying transistor M_PA1. Based on the bias level VGG, the input signal RFin has an adaptability current Iadp. In one embodiment, the bias circuit 50 further includes a filter circuit FC1, which can be coupled between the system voltage terminal VDD and transistor M53. In one embodiment, the filter circuit FC1 can be a low-pass filter circuit, but is not limited thereto.

[0073] It should be noted that capacitor C1 can be used to adjust the current curve of the adaptive current Iadp. In other words, by adjusting capacitor C1, the current curve of the adaptive current Iadp can be adjusted, thereby further adjusting the current curve of the current Icc.

[0074] The operation and function of other circuit components can be found in the foregoing content and will not be repeated here.

[0075] Figure 6A This is a schematic diagram of a bias circuit 60A according to an embodiment of the present invention. The bias circuit 60A can be used to implement the bias circuit 120. The bias circuit 60A includes a diode-connected transistor M51, diode-connected transistors M52 and M53, a capacitor C1, a diode-connected transistor M64, and a resistor circuit R4. The coupling method of the diode-connected transistors M51, M52, and M53 and the capacitor C1 can be referred to the foregoing description and will not be repeated here. Compared to the bias circuit 50, the first terminal E7 of the diode-connected transistor M51 can be used to receive a reference current Iref1. The reference current Iref1 can be the reference current Iref provided by the aforementioned voltage-to-current conversion circuit 210. Furthermore, in the bias circuit 60A, the diode-connected transistor M64 has a first terminal E15 and a second terminal E16. The first terminal E15 of the diode-connected transistor M64 can receive the bias current Ibias. The second terminal E16 of the diode-connected transistor M64 can be coupled to the reference voltage terminal V_REF1, and the control terminal of the diode-connected transistor M64 can be coupled to the first terminal E15. The resistor circuit R4 can be coupled between the control terminal of the diode-connected transistor M64 and the second terminal E12 of the transistor M53.

[0076] Figure 6BThis is a schematic diagram of a bias circuit 60B according to an embodiment of the present invention. The bias circuit 60B can be used to implement the bias circuit 120. Compared to the bias circuit 60A, the control terminal of the diode-connected transistor M64 may not be coupled to the first terminal E15 of the diode-connected transistor M64. In one embodiment, the bias circuit 60B may further include a transistor M65. The transistor M65 has a first terminal E17, a second terminal E18, and a control terminal E_C65. In one embodiment, the first terminal E17 of the transistor M65 can be used to receive a reference current Iref2, the second terminal E18 of the transistor M65 can be coupled to a current source CS4, and the control terminal E_C65 of the transistor M65 can be coupled to a reference voltage terminal V_REF2. In one embodiment, the bias circuit 60B may further include an operational amplifier OP. The operational amplifier OP has a first terminal (i.e., the non-inverting input terminal of the operational amplifier OP, represented by "+"), a second terminal (i.e., the inverting input terminal of the operational amplifier OP, represented by "-"), and an output terminal. In one embodiment, the first terminal of operational amplifier OP can be coupled to the second terminal E18 of transistor M65, and the output terminal of operational amplifier OP can be coupled to the control terminal of transistor M64 connected in a diode configuration. In one embodiment, bias circuit 60 may further include resistor R5. Resistor R5 can be coupled between the second terminal of operational amplifier OP and the first terminal E15 of transistor M64 connected in a diode configuration. In one embodiment, bias circuit 60 may further include filter circuit FC2, and filter circuit FC2 can be coupled between reference voltage terminal V_REF2 and control terminal E_C65 of transistor M65. In one embodiment, filter circuit FC2 may be a low-pass filter circuit, but is not limited thereto.

[0077] In one embodiment, the resistor circuit R4 may include a plurality of resistors connected in series. Similar to capacitor C1, resistor circuit R4 can be used to adjust the current curve of adaptive current Iadp, thereby further adjusting the current curve of current Icc. Therefore, by adjusting the current curve of current Iadp, current Icc can be stably maintained, allowing amplifying transistor M_PA1 to maintain good linearity.

[0078] In one embodiment, the first terminal E_P1 of the amplifying transistor M_PA1 may have a voltage level VDS1, the first terminal E15 of the diode-connected transistor M64 may have a voltage level VDS2, and the second terminal E18 of the transistor M65 may have a voltage level VDS3. An operational amplifier OP can be used to maintain voltage levels VDS2 and VDS3 equal to each other. That is, the operational amplifier OP can be used to maintain the voltage level VDS3 at the second terminal E18 of transistor M65 equal to the voltage level VDS2 at the first terminal E15 of the diode-connected transistor M64. By maintaining the voltage levels VDS3 and VDS2 equal, voltage level VDS1 can have a magnitude close to or the same as voltage level VDS3, and the reference current Iref2 can be stably mirrored and amplified into the operating current Icc flowing through the amplifying transistor M_PA1. Therefore, even if the amplifying transistor M_PA1 is manufactured with different process parameters, the reference current Iref2 can still be stably mirrored and amplified into the current Icc to maintain the linear performance of the power amplifier.

[0079] In one embodiment, bias circuit 60 provides a bias level VGG to amplifying transistor M_PA1. Amplifying transistors M_PA1 and M_PA2 are cascode-coupled relative to bias circuit 50. In one embodiment, transistor M65 is matched to amplifying transistor M_PA2. That is, transistors M65 and M_PA2 can be oriented in the same direction, and can be positioned close to each other to allow for better mirroring of the reference current Iref2 and the current Icc.

[0080] Figure 7This is a schematic diagram of a bias compensation circuit 70 according to an embodiment of the present invention. The bias compensation circuit 70 can be used in an amplifier (e.g., a power amplifier). The bias compensation circuit 70 includes a detection circuit 700, a voltage-to-current conversion circuit 110, and a bias circuit 120. The detection circuit 700 includes a diode-connected transistor circuit 702. The diode-connected transistor circuit 702 has a first terminal E19 and a second terminal E20. The first terminal E19 of the diode-connected transistor circuit 702 can be used to receive current I1, and the second terminal E20 of the diode-connected transistor circuit 702 can be coupled to a reference voltage terminal V_REF1. Current I1 can be provided by a current source CS1. The diode-connected transistor circuit 702 may include at least one diode-connected transistor, and the at least one diode-connected transistor has the same or similar process parameters as the amplifying transistor M_PA1. Compared to the bias compensation circuit 20, resistor R1 can be selectively omitted according to design requirements, and diode circuit 204, resistor R2, and current source CS2 can be omitted. A voltage level VBE that is not easily affected by process variations (e.g., a fixed voltage level that does not easily change with process variations) can be provided to the voltage-to-current conversion circuit 110 by an external circuit. Based on the voltage level VBG1 and the voltage level VBE, the voltage-to-current conversion circuit 110 can generate a reference current Iref. The bias circuit 120 receives the reference current Iref and provides a bias level VGG to the amplifying transistor M_PA1 based on the reference current Iref. The operation and function of this embodiment of the invention are as described above and will not be repeated here.

[0081] Based on the above description, the present invention provides a bias compensation circuit that can be used to adjust the magnitude of a reference current. According to the reference current, the bias circuit can generate a bias level to adjust the operating current through the amplifier. Therefore, the impact of amplifier process variations on this operating current can be reduced.

[0082] The operation of the bias compensation circuit 20 can be applied to the bias compensation circuit 70, which will not be described in detail here.

[0083] In summary, this invention provides a bias compensation circuit for adjusting the magnitude of a reference current. Based on the reference current, the bias circuit generates a bias level to adjust the operating current through the amplifier. Therefore, the operating current through the amplifier can be adjusted, ensuring that even if the amplifier is manufactured with different process parameters or operates at different temperatures, the amplifier maintains the same or near-linearity, thus keeping the operating current stable. Furthermore, even with varying input signal power, the amplifier with the bias compensation circuit maintains stable linearity.

[0084] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included within the scope of the present invention.

Claims

1. A bias compensation circuit, characterized by, Comprising: a detection circuit, the detection circuit comprising: a diode-connected transistor circuit having a first end for receiving a first current and a second end coupled to a first reference voltage terminal; and a first diode circuit having a first end for receiving a second current and a second end coupled to the first reference voltage terminal, the first diode circuit further comprising a diode; wherein the detection circuit provides a first voltage level according to the diode-connected transistor circuit and a second voltage level according to the first diode circuit; a voltage-to-current conversion circuit coupled to the detection circuit for generating a first reference current according to the first voltage level and the second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit for receiving the first reference current to provide a bias voltage level according to the first reference current. wherein the diode-connected transistor circuit comprises:

2. The bias compensation circuit of claim 1, wherein, a first diode-connected transistor coupled to the first end of the diode-connected transistor circuit; and a second diode-connected transistor coupled between the first diode-connected transistor and the second end of the diode-connected transistor circuit. wherein the voltage-to-current conversion circuit comprises:

3. The bias compensation circuit of claim 1, wherein, an adder coupled to the detection circuit for generating an output voltage level according to the first voltage level and the second voltage level; and a voltage-to-current converter coupled to the adder for generating the first reference current according to the output voltage level. wherein the detection circuit further comprises:

4. The bias compensation circuit of claim 1, wherein, a first resistor coupled to the first end of the diode-connected transistor circuit; and a second resistor coupled to the first end of the first diode circuit; wherein the detection circuit provides the first voltage level according to the diode-connected transistor circuit and the first resistor and the second voltage level according to the first diode circuit and the second resistor. wherein the detection circuit further comprises:

5. The bias compensation circuit of claim 1, wherein, a second diode circuit having a first end for receiving a third current and a second end coupled to the first reference voltage terminal; wherein the detection circuit provides a third voltage level according to the second diode circuit and the voltage-to-current conversion circuit generates the first reference current according to the first voltage level, the second voltage level and the third voltage level. wherein the bias circuit provides the bias voltage level to a first amplification transistor, the diode-connected transistor circuit comprises at least one diode-connected transistor, and the first amplification transistor and the at least one diode-connected transistor have a same or similar process parameter.

6. The bias compensation circuit of claim 5, wherein, wherein a distance between the first diode circuit and the first amplification transistor is greater than a distance between the second diode circuit and the first amplification transistor.

7. The bias compensation circuit of claim 6, wherein, wherein the bias circuit comprises:

8. The bias compensation circuit of claim 1, wherein, a third diode-connected transistor having a first end for receiving the first reference current and a second end; ​ a fourth diode-connected transistor having a first end coupled to the second end of the third diode-connected transistor and a second end coupled to the first reference voltage terminal; a first transistor having a first end coupled to a system voltage terminal, a second end, and a control end coupled to the first end of the third diode-connected transistor; and a capacitor having a first end coupled to the first end of the third diode-connected transistor and the control end of the first transistor, and a second end coupled to the first reference voltage terminal.

9. The bias compensation circuit of claim 8, wherein, wherein the bias circuit provides the bias level at the second end of the first transistor.

10. The bias compensation circuit of claim 8, wherein, wherein the bias circuit further comprises: a first filter circuit coupled between the system voltage terminal and the first transistor.

11. The bias compensation circuit of claim 8, wherein, wherein the bias circuit further comprises: a fifth diode-connected transistor having a first end for receiving a bias current, a second end coupled to the first reference voltage terminal, and a control end coupled to the first end; and a resistance circuit coupled between the control end of the fifth diode-connected transistor and the second end of the first transistor.

12. The bias compensation circuit of claim 8, wherein, wherein the bias circuit further comprises: a fifth diode-connected transistor having a first end for receiving a bias current, and a second end coupled to the first reference voltage terminal; a resistance circuit coupled between a control end of the fifth diode-connected transistor and the second end of the first transistor; a second transistor having a first end for receiving a second reference current, a second end coupled to a current source, and a control end; an operational amplifier having a first end coupled to the second end of the second transistor, a second end, and an output end coupled to the control end of the fifth diode-connected transistor; and a third resistance coupled between the second end of the operational amplifier and the first end of the fifth diode-connected transistor.

13. The bias compensation circuit of claim 12, wherein, wherein the bias circuit further comprises: a second filter circuit coupled between a second reference voltage terminal and the control end of the second transistor.

14. The bias compensation circuit of claim 12, wherein, wherein the bias circuit provides the bias level to a first amplification transistor, the first amplification transistor is connected to a second amplification transistor, and the second transistor is matched to the second amplification transistor.

15. The bias compensation circuit of claim 1, wherein, wherein the bias circuit provides the bias level to a first amplification transistor, the diode-connected transistor circuit comprises at least one diode-connected transistor, and the first amplification transistor and the at least one diode-connected transistor have a same or similar process parameter.

16. The bias compensation circuit of claim 1, wherein, wherein the bias circuit provides the bias level to a first amplification transistor, a distance between the first diode circuit and the first amplification transistor is greater than a distance between the diode-connected transistor circuit and the first amplification transistor.

17. A bias compensation circuit, comprising: for providing a bias level to a first amplification transistor, comprising: a detection circuit, the detection circuit comprising: a diode-connected transistor circuit having a first end for receiving a first current, and a second end coupled to a first reference voltage terminal; a second diode-connected transistor circuit having a first end for receiving a second current, and a second end coupled to a second reference voltage terminal; and a third diode-connected transistor circuit having a first end for receiving a third current, and a second end coupled to a third reference voltage terminal. The detection circuit provides a first voltage level according to a diode-connected transistor circuit, the diode-connected transistor circuit includes a diode-connected transistor, and the first amplification transistor and the diode-connected transistor have a same or similar process parameter; a voltage-to-current conversion circuit coupled to the diode-connected transistor circuit, for generating a first reference current according to the first voltage level and a second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit, for receiving the first reference current to provide the bias voltage level to the first amplification transistor according to the first reference current.

18. The bias compensation circuit of claim 17, wherein, The voltage-to-current conversion circuit includes: an adder coupled to the detection circuit, for generating an output voltage level according to the first voltage level and the second voltage level; and a voltage-to-current converter coupled to the adder, for generating the first reference current according to the output voltage level.

19. The bias compensation circuit of claim 17, wherein, The detection circuit further includes: a first resistor coupled to the first end of the diode-connected transistor circuit; The detection circuit provides the first voltage level according to the diode-connected transistor circuit and the resistor.

20. The bias compensation circuit of claim 17, wherein, The bias circuit includes: a first diode-connected transistor having a first end for receiving the first reference current and a second end; a second diode-connected transistor having a first end coupled to the second end of the first diode-connected transistor and a second end coupled to the first reference voltage terminal; a first transistor having a first end coupled to a system voltage terminal, a second end, and a control end coupled to the first end of the first diode-connected transistor; and a capacitor having a first end coupled to the first end of the first diode-connected transistor and the control end of the first transistor, and a second end coupled to the first reference voltage terminal.

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