Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate comprises a substrate, and a first data line, a second data line, a plurality of sub-pixels and a first voltage signal line arranged on the substrate. The first data line and the second data line are arranged alternately along a first direction. Each column of sub-pixels comprises a first sub-pixel and a second sub-pixel arranged alternately along a second direction. Along the first direction, a first sub-pixel in a column of sub-pixels is electrically connected to a first data line located on one side and adjacent to the first sub-pixel, and a second sub-pixel is electrically connected to a second data line located on the other side and adjacent to the first sub-pixel. The orthographic projection of each first voltage signal line is located between the orthographic projections of the first data line and the second data line between two adjacent columns of sub-pixels. The first voltage signal line comprises a first sub-voltage signal line and a second sub-voltage signal line, the second sub-voltage signal line being arranged on a side of the first sub-voltage signal line close to the substrate and electrically connected to the first sub-voltage signal line, and the first sub-voltage signal line is arranged on the same layer as the first data line and the second data line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] The refresh rate of a display device (also called vertical refresh rate or vertical scanning rate) refers to the number of times a display screen can display a new image per second. For example, a display screen can display a new image 60 times per second at a refresh rate of 60Hz. When the refresh rate of a display device is high, such as 75Hz, 90Hz, 120Hz or higher, it can avoid blurring and smearing when displaying high-speed moving images, thereby improving image quality and user visual experience. Summary of the invention

[0003] On the one hand, a display panel is provided. The display panel includes a substrate, and a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, and a plurality of first voltage data lines arranged on the substrate. The plurality of sub-pixels are arranged in an array. A first data line and a second data line are arranged between each two adjacent columns of sub-pixels. Each column of sub-pixels includes a plurality of first sub-pixels and second sub-pixels, and the first sub-pixels and the second sub-pixels are alternately arranged along the second direction; along the first direction, a column of sub-pixels is adjacent to a first data line and a second data line, and the first data line and the second data line are respectively located on both sides of the column of sub-pixels, each first sub-pixel in the column of sub-pixels is electrically connected to the first data line adjacent to it, and each second sub-pixel in the column of sub-pixels is electrically connected to the second data line adjacent to it. The orthographic projection of each first voltage signal line on the substrate is located between the orthographic projections of the first data line and the second data line between two adjacent columns of sub-pixels on the substrate; the first voltage signal line is electrically connected to at least one column of sub-pixels; the first voltage signal line includes: a first sub-voltage signal line and a second sub-voltage signal line, the second sub-voltage signal line is arranged on a side of the first sub-voltage signal line close to the substrate and is electrically connected to the first sub-voltage signal line, and the first sub-voltage signal line is arranged on the same layer as the first data line and the second data line.

[0004] In some embodiments, along the first direction, the first sub-pixels and the second sub-pixels are arranged alternately.

[0005] In some embodiments, the display substrate further includes a first insulating layer disposed between the first sub-voltage signal line and the second sub-voltage signal line, the first insulating layer including a plurality of first vias. The first sub-voltage signal line and the second sub-voltage signal line are electrically connected through at least one first via among the plurality of first vias. Among the first data line, the second data line and the first sub-voltage signal line located between two adjacent columns of sub-pixels, a portion of the first data line adjacent to the first via is bent in a direction away from the first via to form a first bent portion. A portion of the second data line adjacent to the first via is bent in a direction away from the first via to form a second bent portion. The first bent portion and the second bent portion are opposite to each other to form a receiving area. The first sub-voltage signal line includes a conductive portion passing through the first via, and the conductive portion is located in the receiving area.

[0006] In some embodiments, along the first direction, the size of the conductive portion is larger than the width of the first sub-voltage signal line; and the size of the accommodating space is larger than the spacing between the portion of the non-first bending portion of the first data line and the portion of the non-second bending portion of the second data line between two adjacent columns of sub-pixels.

[0007] In some embodiments, along the first direction, a distance between the conductive portion and the first bent portion is equal to or substantially equal to a distance between the conductive portion and the second bent portion.

[0008] In some embodiments, along the first direction, the spacing between the conductive portion and the first bent portion is equal to or approximately equal to the spacing between the portion of the first data line that is not the first bent portion and the portion of the non-conductive portion of the first sub-voltage signal line; and / or, along the first direction, the spacing between the conductive portion and the second bent portion is equal to or approximately equal to the spacing between the portion of the second data line that is not the second bent portion and the portion of the non-conductive portion of the first sub-voltage signal line.

[0009] In some embodiments, in the first data line and the second data line adjacent to a column of sub-pixels and located on both sides of the column of sub-pixels along the first direction, a first connecting portion is arranged between the first bent portion and the second bent portion, and the first connecting portion is arranged on the same layer as the first sub-voltage signal line.

[0010] In some embodiments, the display substrate further comprises an anode layer and a first light emission control transistor disposed on the substrate, the anode layer being disposed on a side of the first connection portion away from the substrate. The first light emission control transistor comprises an active layer, the active layer comprises a first conductor portion, and the first connection portion is electrically connected to the first conductor portion and the anode layer.

[0011] In some embodiments, the display substrate further includes a second connection portion. The second connection portion is disposed between the active layer of the first light emission control transistor and the first connection portion, and is disposed in the same layer as the second sub-voltage signal line. The second connection portion is electrically connected to the first conductor portion and the first connection portion.

[0012] In some embodiments, along the second direction, a size of the first connecting portion is greater than or equal to a length of the first curved portion and the second curved portion.

[0013] In some embodiments, an orthographic projection of the first connection portion on the substrate and an orthographic projection of the second connection portion on the substrate have an overlapping area.

[0014] In some embodiments, the first via hole is located between two adjacent rows of sub-pixels and between two adjacent columns of sub-pixels.

[0015] In some embodiments, when the display substrate further includes the first connection portion, along the second direction, maximum sizes of two portions of the first connection portion located on both sides of a line connecting centers of two adjacent first via holes of the first connection portion are substantially equal.

[0016] In some embodiments, each sub-pixel includes a second light emission control transistor and a capacitor. The second sub-voltage signal line is electrically connected to the active layer of the second light emission control transistor. The capacitor includes a first electrode plate located on a side of the film layer where the second sub-voltage signal line is located close to the substrate, and a second electrode plate located on a side of the first electrode plate close to the substrate. The second sub-voltage signal line is also electrically connected to the first electrode plate.

[0017] In some embodiments, the first plates of the capacitors of multiple sub-pixels in each row of sub-pixels are electrically connected to each other to form a plurality of auxiliary conductive strips extending along the first direction, and the plurality of auxiliary conductive strips are interlaced with the orthographic projections of the plurality of first sub-voltage signal lines on the substrate to form a grid structure.

[0018] On the other hand, a display device is provided, comprising the display substrate as described above.

[0019] On the other hand, a method for preparing a display substrate is provided. The preparation method includes: providing a substrate; forming a pixel driving circuit of a plurality of sub-pixels arranged in an array on the substrate, wherein each column of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels, and the first sub-pixels and the second sub-pixels are arranged alternately along a second direction; forming a plurality of second sub-voltage signal lines on a side of the pixel driving circuit of the plurality of sub-pixels away from the substrate, wherein the orthographic projection of each second sub-voltage signal line on the substrate is located between two adjacent columns of sub-pixels; forming a plurality of first data lines, a plurality of second data lines, and a plurality of first sub-voltage signal lines on a side of the plurality of second sub-voltage signal lines away from the substrate, wherein a first sub-voltage signal line and a second sub-voltage signal line are arranged alternately. A first voltage signal line is formed, each first voltage signal line is electrically connected to a pixel driving circuit of at least one column of sub-pixels, an orthographic projection of each first voltage signal line on the substrate is located between the orthographic projections of two adjacent columns of sub-pixels on the substrate, first data lines and second data lines are alternately arranged along a first direction, along the first direction, a column of sub-pixels is adjacent to a first data line and a second data line, and the first data line and the second data line are respectively located on both sides of the column of sub-pixels, a pixel driving circuit of each first sub-pixel in the column of sub-pixels is electrically connected to the first data line adjacent thereto, and a pixel driving circuit of each second sub-pixel in the column of sub-pixels is electrically connected to the second data line adjacent thereto. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 is an equivalent circuit diagram of a 7T1C pixel driving circuit according to some embodiments;

[0022] Figure 2 for Figure 1 The signal timing diagram of the pixel driving circuit shown;

[0023] Figure 3 is a schematic diagram of a driving architecture according to some embodiments;

[0024] Figure 4 for Figure 3 The signal timing diagram of the drive architecture shown;

[0025] Figure 5A schematic structural diagram of another drive system according to some embodiments;

[0026] Figure 6 for Figure 5 The signal timing diagram of the drive system shown;

[0027] Figure 7 is a schematic top view of a display substrate according to some embodiments;

[0028] Figures 8A to 8H for Figure 7 A schematic top view of each film layer of the display substrate shown;

[0029] Fig. 9A for Figure 7 A partial enlarged schematic diagram of the middle area S1;

[0030] Fig. 9B For along Figure 7 and Fig. 9A A schematic cross-sectional view of the display substrate taken along the dotted line XX';

[0031] Fig. 10A is a schematic diagram of a sub-pixel structure according to some embodiments;

[0032] Fig. 10B is a schematic diagram of the structure of another sub-pixel according to some embodiments;

[0033] Fig.11 for Figure 7 An equivalent circuit diagram of a portion of the display substrate in region S2 is shown;

[0034] Fig.12 for Figure 7 A partial enlarged schematic diagram of a region S3 of a display substrate is shown;

[0035] Fig.13 is a schematic diagram of another display substrate according to some embodiments;

[0036] Fig.14 for Fig.13 A partial enlarged schematic diagram of a region S4 of a display substrate is shown;

[0037] Figures 15A to 15F It is a schematic diagram of various steps of a method for preparing a display substrate according to some embodiments. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0041] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other, or to indicate that two or more components are indirectly physically or electrically connected to each other.

[0042] It should be understood that in the description of the present disclosure, the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0043] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0044] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0045] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0046] In addition, in the present disclosure, the term “plurality” in terms such as “plurality”, “plurality of strips”, “plurality of columns” and “plurality of rows” refers to two or more in quantity.

[0047] When the display device operates at a higher refresh rate (e.g., 75Hz, 90Hz, 120Hz or higher), the displayed image quality and the user's visual experience can be improved. However, a higher refresh rate will bring about the problem of shortening the data writing and compensation time of each sub-pixel in the display device, which may lead to insufficient charging rate of each sub-pixel and reduced threshold voltage compensation effect, thereby reducing the display effect of the display device.

[0048] like Figure 1 As shown, taking a display device including a pixel driving circuit of a 7T1C structure as an example, the display device includes a plurality of sub-pixels, each of which has a pixel driving circuit of the 7T1C structure, and the pixel driving circuit includes seven transistors (a first transistor T1 to a seventh transistor T7) and a capacitor Cst. The seven transistors may be P-type transistors, that is, they are turned on when the gate receives a low-level signal and are turned off when a high-level signal is received; the seven transistors may also be N-type transistors, that is, they are turned on when the gate receives a high-level signal and are turned off when a low-level signal is received.

[0049] In order to conveniently introduce the pixel driving circuit of 7T1C, the electrical connection point between the second electrode of the first transistor T1, the second plate B1 of the capacitor Cst and the gate of the third transistor T3 is called the first node N1, and the voltages of the first node N1, the second plate B1 of the capacitor Cst and the gate of the third transistor T3 are equal; the electrical connection point between the second electrode of the fifth transistor T5, the second electrode of the fourth transistor T4 and the first electrode of the third transistor T3 is called the second node N2; the electrical connection node between the third transistor T3, the second transistor T2 and the sixth transistor T6 is called the third node N3.

[0050] It should be noted that the channel width-to-length ratio of the driving transistor is usually greater than the channel width-to-length ratio of other switching transistors, that is, the channel width-to-length ratio of the third transistor T3 is usually greater than the channel width-to-length ratio of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In addition, taking the electroluminescent device as an example, the luminous brightness of the light-emitting device E corresponding to each sub-pixel is related to the magnitude of the driving current I flowing through it. According to the formula I = K (Vgs-Vth) 2 It can be seen that the driving current I is related to the source and gate voltage difference Vgs of the driving transistor and the threshold voltage Vth of the driving transistor, that is, when the voltage difference Vgs is constant, the luminous brightness of each light-emitting device E will be mainly affected by the threshold voltage Vth of the corresponding driving transistor. In this way, when the threshold voltages Vth of the driving transistors in the sub-pixels of the display device are not equal, for example, when the threshold voltage Vth of the driving transistor drifts as the working time increases, the display device may have uneven display brightness.

[0051] The components of the above-mentioned 7T1C pixel driving circuit and the connection relationship between the components are introduced below. Here, the transistors included in the pixel driving circuit are taken as an example as P-type transistors, that is, the first transistor T1 to the seventh transistor T7 are turned on when the signal received by the gate is a low level, and are turned off when the signal received by the gate is a high level.

[0052] The gate of the first transistor T1 is electrically connected to the reset signal terminal RESET, the first electrode is electrically connected to the initialization voltage signal terminal INIT, and the second electrode is electrically connected to the first node N1. The gate of the second transistor T2 is electrically connected to the scan signal terminal GATE, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the first node N1. The gate of the third transistor T3 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the scan signal terminal GATE, the first electrode is electrically connected to the data signal terminal DATA, and the second electrode is electrically connected to the second node N2. The gate of the fifth transistor T5 is electrically connected to the light emitting signal terminal EM, the first electrode is electrically connected to the first voltage signal terminal VDD, and the second electrode is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the light emitting signal terminal EM, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the anode of the light emitting device E of the sub-pixel. The gate of the seventh transistor T7 is electrically connected to the reset signal terminal RESET, the first electrode is electrically connected to the initialization voltage signal terminal INIT, and the second electrode is electrically connected to the anode of the sub-pixel light emitting device E. The first plate A1 of the capacitor Cst is electrically connected to the first voltage signal terminal VDD, and the second plate B1 is electrically connected to the first node N1.

[0053] In addition, the anode of the light emitting device E of the sub-pixel is electrically connected to the above-mentioned pixel driving circuit, and the cathode is electrically connected to the second voltage signal terminal VSS.

[0054] Combine the following Figure 2 The signal timing diagram shown introduces the working process of the above-mentioned 7T1C pixel driving circuit. In one frame time, the working process of the pixel driving circuit includes a reset phase P1, a writing and compensation phase P2 and a light emitting phase P3.

[0055] In the reset phase P1, the reset signal Vre transmitted from the reset signal terminal RESET to the gate of the first transistor T1 and the gate of the seventh transistor T7 is at a low level, and the first transistor T1 and the seventh transistor T7 are turned on. The first transistor T1 transmits the initialization voltage signal Vinit from the initialization voltage signal terminal INIT to the first node N1 to reset the voltage of the second plate B1 of the capacitor Cst and the gate of the third transistor T3 (also referred to as the driving transistor T3), and the voltage of the second plate B1 is equal to the voltage Vi of the initialization voltage signal Vinit. The seventh transistor T7 transmits the initialization voltage signal Vinit from the initialization voltage signal terminal INIT to the anode of the light emitting device E to reset the anode voltage of the light emitting device E.

[0056] Here, the initialization voltage signal Vinit is at a low level in the reset phase P1, and the voltage of the first node N1 is a low voltage, so the third transistor T3 whose gate is electrically connected to the first node N1 is turned on. Exemplarily, the initialization voltage signal Vinit may be a constant low voltage signal.

[0057] In the writing and compensation phase P2, the reset signal Vre is high, the first transistor T1 and the seventh transistor T7 are turned off, the voltage of the first node N1 is equal to the voltage of the second plate B1 of the capacitor Cst, that is, the voltage of the first node N1 is still low, and the third transistor T3 remains turned on.

[0058] The scanning signal Vgate transmitted from the scanning signal terminal GATE to the gate of the fourth transistor T4 (which can be called the writing transistor T4) and the gate of the second transistor T2 (which can be called the compensation transistor T2) is at a low level, and the fourth transistor T4 and the second transistor T2 are turned on. The fourth transistor T4 transmits the data signal Vdata from the data signal terminal DATA to the third transistor T3. The data signal Vdata is transmitted to the second transistor T2 through the turned-on third transistor T3, and then transmitted to the first node N1 through the turned-on second transistor T2, so as to be written to the capacitor Cst. The process of the data signal Vdata being written to the capacitor Cst is actually the charging process of the second plate B1 of the capacitor Cst (i.e., the process of the voltage of the second plate B1 gradually increasing). The voltage of the first node N1 gradually increases from Vi in the previous stage (i.e., the reset stage P1) until the voltage of the first node N1 rises to Vdata+Vth, and the third transistor T3 is turned off, where Vth is the threshold voltage value of the third transistor T3. At this time, the voltage of the second plate B1 of the capacitor Cst is equal to Vdata+Vth, so that the threshold voltage value Vth of the third transistor T3 is compensated to the data signal written into the capacitor Cst.

[0059] It should be noted that the duration 1H of the effective level of the scanning signal Vgate (ie, the level that turns on the corresponding transistor) is the time required for a row of sub-pixels to complete the writing of the data signal Vdata.

[0060] In the light-emitting stage P3, the light-emitting signal Vem transmitted to the gate of the fifth transistor T5 and the gate of the sixth transistor T6 of the light-emitting signal terminal EM is at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on. The source voltage Vs of the third transistor T3 is equal to the first voltage Vdd of the first voltage signal terminal VDD, and the gate voltage Vg of the third transistor T3 is equal to Vdata+Vth, where the first voltage Vdd is greater than Vdata+Vth, so the third transistor T3 is turned on. In this way, a current path is formed between the first voltage signal terminal VDD and the second voltage signal terminal VSS, so that the light-emitting device E can emit light.

[0061] It should be noted that the driving current I flowing through the light emitting device E in the light emitting stage P3 is I=K(Vgs-Vth) 2 =K(Vdata+Vth-Vdd-Vth) 2 =K(Vdata-Vdd) 2 In this way, the magnitude of the driving current I is independent of the threshold voltage value Vth of the third transistor T3, thereby avoiding the influence of the threshold voltage drift of the third transistor T3 on the driving current I, and making the light luminance of each sub-pixel in the display device more uniform.

[0062] When the display device needs to be refreshed at a faster frequency, the time of each frame is shortened due to the large number of new images displayed per second, resulting in a corresponding shortening of the writing and compensation phase P2 within a frame, that is, the duration of the effective level of the scanning signal is shortened. This may cause the data writing time (i.e., the charging time of the sub-pixel) and the threshold voltage compensation time of the display device to be shorter, resulting in insufficient charging rate of the sub-pixel and poor threshold voltage compensation effect, affecting the image quality of the display device and the visual experience of the user.

[0063] To solve the above problem, two data lines DL can be set to provide a data signal Vdata to a column of sub-pixels. Figures 3 to 6 , the display device with the 7T1C pixel driving circuit mentioned above adopts the driving method scheme to exemplarily introduce.

[0064] like Figure 3 and 5 As shown, the display device includes a plurality of sub-pixels PX, a plurality of data lines DL and a plurality of gate lines GL (for example, GL1 to GL4), and these sub-pixels PX can be arranged in an array. Each column of sub-pixels corresponds to two data lines DL (for example, DL1 to DL8), and the two data lines DL are respectively arranged on the left and right sides of the column of sub-pixels. In the sub-pixels located in the same column, each two adjacent sub-pixels PX are respectively electrically connected to different data lines DL in the above-mentioned left and right data lines DL, that is, along the extension direction of the column of sub-pixels, the sub-pixels PX located in the same column are alternately electrically connected to the left and right data lines DL. The sub-pixels located in the same row can be electrically connected to the same gate line GL, where the gate line GL can provide a scanning signal Vgate to a row of sub-pixels electrically connected thereto, so that the data signal Vdata from the data line DL is transmitted to the corresponding sub-pixel PX, and the data signal Vdata is written. The data writing process of each sub-pixel PX can refer to the description of the writing and compensation stage P2 above, which will not be repeated here.

[0065] It should be noted that, along the extension direction of each row of sub-pixels, the sub-pixels PX located in the same row can be alternately electrically connected to the data lines DL on the left and right sides thereof (eg Figure 3 and Figure 5 As shown), they may also be electrically connected to the data line DL located on the left or the right thereof.

[0066] The display device may further include a plurality of source drive signal lines S (e.g., S1 to S4) and a source driver 100, and the plurality of source drive signal lines S are electrically connected to the source driver 100. The source driver 100 is used to provide data signals Vdata of images to be displayed by the display device, and these data signals Vdata may be provided to each sub-pixel PX through the source drive signal lines S and the data lines DL.

[0067] Each adjacent plurality of data lines DL is electrically connected to the same source drive signal line S. In this way, the source driver 100 can transmit the data signal Vdata to the plurality of data lines DL electrically connected to the source drive signal line S through the source drive signal line S, thereby reducing the number of interfaces for outputting the data signal Vdata provided on the source driver 100. A switch SW is provided between each data line DL and its corresponding source drive signal line S. In this way, by controlling the opening and closing of the corresponding switch SW, the source drive signal line S can be time-division multiplexed. Here, the control electrodes of the switches SW corresponding to the same source drive signal line S and located on the left side of a column of sub-pixels are all connected to the same control signal line MUX (for example, Figure 3 The control signal line MUX is electrically connected to the MUX1 or MUX2 in the source drive signal line S, and the switch SW corresponding to the data line DL can be controlled to be turned on and off through the control signal line MUX, thereby controlling the data signal Vdata from the source drive signal line S in a certain frame to be transmitted to a specific data line DL, so that the data signal Vdata can be controlled to be written into the corresponding sub-pixel PX.

[0068] Here, the switch SW may include an N-type or P-type transistor. In the case where the switch SW includes an N-type transistor, the switch SW is turned on when the signal from the control signal line MUX is at a high level, and is turned off when the signal is at a low level. In the case where the switch SW includes a P-type transistor, the switch SW is turned on when the signal from the control signal line MUX is at a low level, and is turned off when the signal is at a high level.

[0069] The following will be Figure 2 and Figure 4 As an example, the structure of the display device shown in FIG. 1 is used to introduce the driving process of the display device. The pixel driving circuit in the sub-pixel of the display device can refer to Figure 1Here, the second transistor T2 and the fourth transistor T4 in the pixel driving circuit and the switch SW are P-type transistors as an example, and along the extension direction of a row of sub-pixels, the sub-pixels PX in the same row are alternately electrically connected to the data lines DL on the left and right sides thereof.

[0070] For some examples, see Figure 3 , every two adjacent data lines DL are electrically connected to the same source drive signal line S. For example, the source drive signal line S1 is electrically connected to the data line DL1 and the data line DL2, that is, the source driver 100 can provide the data signal Vdata to the first column sub-pixel PC1 through the source drive signal line S1, the data line DL1 and the data line DL2. Similarly, the source drive signal line S2 is electrically connected to the data line DL3 and the data line DL4, and the source driver 100 can provide the data signal Vdata to the second column sub-pixel PC2 through the source drive signal line S2, the data line DL3 and the data line DL4; the source drive signal line S3 is electrically connected to the data line DL5 and the data line DL6, and the source drive signal line S4 is electrically connected to the data line DL7 and the data line DL8, and the source driver 100 can provide the data signal Vdata to the fourth column sub-pixel PC4 through the source drive signal line S4, the data line DL7 and the data line DL8.

[0071] In the two data lines DL corresponding to the same source driving signal line S, in each switch SW electrically connected to each data line DL located on the left side of the corresponding column sub-pixel, the gate of the thin film transistor is electrically connected to the control signal line MUX1; in the switch SW corresponding to each data line DL located on the right side of the corresponding column sub-pixel, the gate of the thin film transistor is electrically connected to the control signal line MUX2. For example, the gate of the thin film transistor in each switch SW electrically connected to the data lines DL1, DL3, DL5 and DL7 is electrically connected to the control signal line MUX1, and the gate of the thin film transistor in the switch SW corresponding to the data lines DL2, DL4, DL6 and DL8 is electrically connected to the control signal line MUX2.

[0072] Thus, by transmitting signals of different levels to the thin film transistors in different switches SW, different data lines DL can be selected to transmit the data signal Vdata to the corresponding sub-pixels PX. In this way, the source driver 100 can transmit the data signal Vdata to two data lines DL electrically connected to the source drive signal line S through one source drive signal line S.

[0073] In this case, see Figure 4In the first stage T11, the control signal Vumx1 transmitted via the control signal line MUX1 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX1 is turned on; the control signal Vumx2 transmitted via the control signal line MUX2 is at a high level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX2 is turned off. The scanning signal Vgate1 transmitted via the scanning signal line GL1 is at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 are turned on; the scanning signal Vgate2 transmitted via the scanning signal line GL2 is at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the second sub-pixel row PR2 are turned off. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located in the first row sub-pixel PR1 and the first column sub-pixel PC1, and the data signal Vdata transmitted via the source drive signal line S3 is written into the sub-pixel located in the first row sub-pixel PR1 and the third column sub-pixel PC3.

[0074] In the second stage T12, the control signal Vumx1 transmitted through the control signal line MUX1 is at a high level, and each switch SW electrically connected to the control signal line MUX1 is closed; the control signal Vumx2 transmitted through the control signal line MUX2 is at a low level, and each switch SW electrically connected to the control signal line MUX2 is opened. The scanning signal Vgate1 transmitted through the scanning signal line GL1 and the scanning signal Vgate2 transmitted through the scanning signal line GL2 are both at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first row of sub-pixels PR1 and the second row of sub-pixels PR2 are both turned on. In this way, although the fourth transistor T4 of each sub-pixel in the first row of sub-pixels PR1 and the second row of sub-pixels PR2 are all turned on, since the switches SW corresponding to the data lines DL1, DL3, DL5 and DL7 are all closed, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixels located in the second row of sub-pixels PR2 and the first column of sub-pixels PC1 by the data line DL2, the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixels located in the first row of sub-pixels PR1 and the second column of sub-pixels PC2 by the data line DL4, the data signal Vdata transmitted via the source drive signal line S3 is written into the sub-pixels located in the second row of sub-pixels PR2 and the third column of sub-pixels PC3 by the data line DL6, and the data signal Vdata transmitted via the source drive signal line S4 is written into the sub-pixels located in the first row of sub-pixels PR1 and the fourth column of sub-pixels PC4 by the data line DL8.

[0075] It should be noted that in the above driving mode, the duration of the effective level of the scanning signal Vgate of the sub-pixel PX is 2H, that is, the duration of the effective level of the scanning signal Vgate of the sub-pixel PX is equal to the time required for two rows of sub-pixels to complete the writing of the data signal Vdata. In this way, the time of the writing and compensation phase P2 can be increased, so that the charging time of the sub-pixel PX is sufficient and the threshold voltage compensation effect is improved, thereby improving the display effect of the display device at a high refresh rate.

[0076] In some embodiments, see Figure 5 Every four adjacent data lines DL are electrically connected to the same source driving signal line S. For example, the source driving signal line S1 is electrically connected to the data lines DL1 to DL4, and the source data line S2 is electrically connected to the data lines DL5 to DL8.

[0077] From left to right along the extension direction of a row of sub-pixels, in every 4 data lines DL corresponding to the same source drive signal line S, the gates of the thin film transistors in each switch SW electrically connected to each data line DL numbered 1 are electrically connected to the control signal line MUX1, the gates of the thin film transistors in each switch SW electrically connected to each data line DL numbered 2 are electrically connected to the control signal line MUX2, the gates of the thin film transistors in each switch SW electrically connected to each data line DL numbered 3 are electrically connected to the control signal line MUX3, and the gates of the thin film transistors in each switch SW electrically connected to each data line DL numbered 4 are electrically connected to the control signal line MUX4.

[0078] Similarly, by transmitting signals of different levels to the thin film transistors in different switches SW, different data lines DL can be selected to transmit the data signal Vdata to the corresponding sub-pixels PX. In this way, by time-division multiplexing the source drive signal line S, the source driver 100 can transmit the data signal Vdata to the four data lines DL electrically connected to the source drive signal line S through the same source drive signal line S, so that the corresponding four columns of sub-pixels can realize the writing of the data signal Vdata.

[0079] In this case, see Figure 6In the first stage T21, the control signal Vumx1 transmitted via the control signal line MUX1 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX1 is turned on; the control signals Vumx2 to Vumx4 transmitted via the control signal lines MUX2 to MUX4 are all at a high level, and the thin film transistors in the switch SW electrically connected to the control signal lines MUX2 to MUX4 are all turned off. The scanning signal Vgate1 transmitted via the scanning signal line GL1 is at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 are turned on; the scanning signals Vgate2 to Vgate4 transmitted via the scanning signal lines GL2 to GL4 are all at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the second pixel row PR2 to the fourth pixel row PR4 are all turned off. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located in the first row of sub-pixel PR1 and the first column of sub-pixel PC1, and the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixel located in the first row of sub-pixel PR1 and the third column of sub-pixel PC3.

[0080] In the second stage T22, the control signal Vumx2 transmitted via the control signal line MUX2 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX2 is turned on; the control signals Vumx1, Vumx3 and Vumx4 transmitted via the control signal lines MUX1, MUX3 and MUX4 are all at a high level, and the thin film transistors in the switch SW electrically connected to the control signal lines MUX1, MUX3 and MUX4 are all turned off. The scanning signals Vgate1 and Vgate2 transmitted via the scanning signal lines GL1 and GL2 are at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 and the second sub-pixel row PR2 are turned on; the scanning signals Vgate3 and Vgate4 transmitted via the scanning signal lines GL3 and GL4 are both at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the third pixel row PR3 and the fourth pixel row PR4 are all turned off. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located in the second row sub-image PR2 and the first column sub-pixel PC1, and the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixel located in the second row sub-image PR2 and the third column sub-pixel PC3.

[0081] In the third stage T3, the control signal Vumx3 transmitted via the control signal line MUX3 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX3 is turned on; the control signals Vumx1, Vumx2 and Vumx4 transmitted via the control signal lines MUX1, MUX2 and MUX4 are all at a high level, and the thin film transistors in the switch SW electrically connected to the control signal lines MUX1, MUX2 and MUX4 are all turned off. The scanning signals Vgate1 to Vgate3 transmitted via the scanning signal lines GL1 to GL3 are at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 to the third sub-pixel row PR3 are turned on; the scanning signal Vgate4 transmitted via the scanning signal line GL4 is at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the fourth pixel row PR4 are all turned off. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located in the second row sub-pixel PR2 and the second column sub-pixel PC2, and the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixel located in the second row sub-pixel PR2 and the fourth column sub-pixel PC4.

[0082] In the fourth stage T4, the control signal Vumx4 transmitted via the control signal line MUX4 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX4 is turned on; the control signals Vumx1 to Vumx3 transmitted via the control signal lines MUX1 to MUX3 are all at a high level, and the thin film transistors in the switch SW electrically connected to the control signal lines MUX1 to MUX3 are all turned off. The scanning signals Vgate1 to Vgate4 transmitted via the scanning signal lines GL1 to GL4 are all at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 to the fourth sub-pixel row PR4 are all turned on. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located at the first row sub-image PR2 and the second column sub-pixel PC2 and the sub-pixel located at the third row sub-image PR3 and the second column sub-pixel PC2, and the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixel located at the first row sub-image PR1 and the fourth column sub-pixel PC4 and the sub-pixel located at the third row sub-image PR3 and the fourth column sub-pixel PC4.

[0083] Here, the duration of the effective level of the scanning signal Vgate of the sub-pixel PX is 2H, and the time of the writing and compensation stage P2 can also be increased to make the charging time of the sub-pixel PX sufficient and the threshold voltage compensation effect improved, thereby improving the display effect of the display device at a high refresh rate.

[0084] It should be noted that in the fourth stage T4, the data signal Vdata written into the sub-pixel located in the third row sub-image PR3 and the second column sub-pixel PC2, and the data signal Vdata written into the sub-pixel located in the third row sub-image PR3 and the fourth column sub-pixel PC4 are not the data signals actually required in the light-emitting stage. When the duration of the effective level of the scanning signal is 2H, before the effective level of the scanning signal Vgate3 corresponding to the above two sub-pixels ends, the two sub-pixels will be written with new data signals Vdata again, and the newly written data signals Vdata are the data signals required in the light-emitting stage.

[0085] However, when the display device adopts the above-mentioned driving method of providing a data signal Vdata to a column of sub-pixels through two data lines DL, the number of data lines DL provided in the display device will be doubled, so that the spacing between the data lines DL becomes smaller, which may cause a large parasitic capacitance between adjacent data lines DL. The large parasitic capacitance may cause crosstalk between the data signals Vdata transmitted by the adjacent data lines DL, affect the data writing and threshold voltage compensation of the sub-pixels, and thus may reduce the display effect of the display device.

[0086] See also Figures 7 to 14 Some embodiments of the present disclosure provide a display substrate 200. Figure 7 , 9A As shown in FIGS. 9B and 9B , the display substrate 200 includes a substrate 10, a plurality of first data lines 21 and a plurality of second data lines 22 disposed on the substrate 10, and a plurality of sub-pixels arranged in an array on the substrate 10. A first data line 21 and a second data line 22 are disposed between each two adjacent columns of sub-pixels.

[0087] like Figure 7 , 10A As shown in FIG. 10B , each column of sub-pixels includes a plurality of first sub-pixels 31 and a plurality of second sub-pixels 32. Here, for the convenience of description, a direction perpendicular or substantially perpendicular to the extension direction of a column of sub-pixels is defined as a first direction OU, that is, the first direction OU is the row direction of the plurality of sub-pixels arranged in an array, and a direction parallel or substantially parallel to the extension direction of a column of sub-pixels is defined as a second direction OV, that is, the second direction OV is the column direction of the plurality of sub-pixels arranged in an array. Along the second direction OV, the first sub-pixels 31 and the second sub-pixels 32 are arranged alternately. Along the first direction OU, a column of sub-pixels is adjacent to a first data line 21 and a second data line 22, and the first data line 21 and the second data line 22 are respectively located on both sides of the column of sub-pixels. Each first sub-pixel 31 of the column of sub-pixels is electrically connected to the first data line 21 adjacent thereto, and each second sub-pixel 32 of the column of sub-pixels is electrically connected to the second data line 22 adjacent thereto.

[0088] The display substrate 200 further includes a first voltage signal line 40 disposed on the substrate 10, and an orthographic projection of each first voltage signal line 40 on the substrate 10 is between the orthographic projections of the first data line 21 and the second data line 22 between two adjacent columns of sub-pixels on the substrate 10, and each first voltage signal line 40 is electrically connected to at least one column of sub-pixels. Exemplarily, between the orthographic projections of the first data line 21 and the second data line 22 between two adjacent columns of sub-pixels on the substrate 10, there is an orthographic projection of the first voltage signal line 40 on the substrate 10.

[0089] It should be noted that a film layer such as an inorganic buffer layer 11 may be disposed between the substrate 10 and the plurality of sub-pixels. The inorganic buffer layer 11 may be a single-layer structure or a multi-layer stacked structure, such as a stacked structure of alternating inorganic and organic film layers.

[0090] Fig.11 for Figure 7 The equivalent circuit diagram of the portion of the display substrate 200 located in the area S2 is shown. Here, the display substrate 200 includes two first sub-pixels 31 and two second sub-pixels 32 arranged in a matrix in the area S2 as an example for explanation. Each first sub-pixel 31 and each second sub-pixel 32 has a pixel driving circuit with a 7T1C structure, and the pixel driving circuit includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst. The electrical connection relationship between the components inside the pixel driving circuit and the working process of the driving circuit can refer to the above description, and will not be repeated here.

[0091] The following will refer to Figures 7 to 9B , the structure of each component in the pixel driving circuit of the sub-pixel in the display panel 200 is exemplarily introduced. Along the thickness direction of the substrate 10, the display panel 200 includes an active layer L sequentially arranged on the substrate 10 A , the first gate metal layer L G1 , the second gate metal layer L G2 and the first source-drain metal layer L SD1 It should be noted that Fig.8D Middle area S P is the area corresponding to a sub-pixel, that is Fig.8D Middle area S P The structure in the display substrate 200 is a minimum repeating unit. Here and below, the area S corresponding to a sub-pixel is used. P The structure in is used as an example to introduce it.

[0092] like Fig. 8A and 9B As shown, the active layer L AThe active layer 71 includes an active layer 71 of a first transistor T1, an active layer 72 of a second transistor T2, an active layer 73 of a third transistor T3, an active layer 74 of a fourth transistor T4, an active layer 75 of a fifth transistor T5, an active layer 76 of a sixth transistor T6 and an active layer 77 of a seventh transistor T7.

[0093] like Figure 8B and 9B As shown, the first gate metal layer L G1 The first gate metal layer L includes a gate G1 of the first transistor T1, a gate G2 of the second transistor T2, a gate G3 of the third transistor T3, a gate G4 of the fourth transistor T4, a gate G5 of the fifth transistor T5, a gate G6 of the sixth transistor T6, and a gate G7 of the seventh transistor T7. G1 The present invention also includes a second electrode plate B1 of the capacitor Cst, a reset signal line RL, a gate line GL, and a light-emitting signal line EML. Here, the reset signal line RL is configured to transmit a reset signal Vre from a reset signal terminal RESET to a corresponding sub-pixel, the gate line GL is configured to transmit a scan signal Vgate from a scan signal terminal GATE to a corresponding sub-pixel, and the light-emitting signal line EML is configured to transmit a light-emitting signal Vem from a light-emitting signal terminal EM to a corresponding sub-pixel.

[0094] It should be noted that the first gate metal layer L G1 The overlapped portion with the positive projection of the active layer 71 of the first transistor T1 on the substrate 10 can be used as the gate G1 of the first transistor T1. G1 The overlapped portion with the positive projection of the active layer 72 of the second transistor T2 on the substrate 10 can be used as the gate G2 of the second transistor T2. G1 The overlapped portion with the positive projection of the active layer 73 of the third transistor T3 on the substrate 10 can be used as the gate G3 of the third transistor T3. G1 The overlapping portion with the positive projection of the active layer 74 of the fourth transistor T4 on the substrate 10 can be used as the gate G4 of the fourth transistor T4. G1 The overlapping portion with the positive projection of the active layer 75 of the fifth transistor T5 on the substrate 10 can be used as the gate G5 of the fifth transistor T5. G1 The overlapping portion with the positive projection of the active layer 76 of the sixth transistor T6 on the substrate 10 can be used as the gate G6 of the sixth transistor T6. G1 The overlapping portion with the orthographic projection of the active layer 77 of the seventh transistor T7 on the substrate 10 may serve as the gate G7 of the seventh transistor T7.

[0095] like Figure 8C and 9BAs shown, the second gate metal layer L G2 The first electrode A1 of the capacitor Cst, the initialization voltage signal line IL and the shielding part 102 are included. The initialization voltage signal line IL is configured to transmit the initialization voltage signal Vin from the initialization voltage signal terminal INIT to the corresponding sub-pixel.

[0096] like Figure 8G and 9B As shown, the first source and drain metal layer L SD1 The first signal lines 21 and the second signal lines 22 are included, and along the first direction OU, the first signal lines 21 and the second signal lines 22 are alternately arranged.

[0097] Refer to the following Fig.11 , the connection relationship between the pixel driving circuit of each sub-pixel and the signal line in the display substrate is explained.

[0098] In the same column of sub-pixels, the fourth transistor T4 of the first sub-pixel 31 is electrically connected to the same first data line 21, and the fourth transistor T4 of the second sub-pixel 32 is electrically connected to the same second data line 22. That is, the first sub-pixel 31 receives the data signal Vdata through the first data line 21, and the second sub-pixel 32 receives the data signal Vdata through the second data line 22.

[0099] The first electrodes of the fifth transistors T5 of the sub-pixels in the same column are electrically connected to the first voltage signal terminal VDD through the same first voltage signal line 40. Here, the first voltage signal line 40 can be used to transmit the first voltage signal Vdd from the first voltage signal terminal VDD to the sub-pixels electrically connected thereto, and the first voltage signal Vdd is a constant voltage signal, for example Fig.11 The middle is a constant low voltage signal.

[0100] The gates of the second transistor T2 and the fourth transistor T4 of the sub-pixels in the same row are electrically connected to the same level scanning signal terminal GATE (for example, the Nth level scanning signal terminal GATE) through the same gate line GL. N Or the (N+1)th level scanning signal terminal GATA N+1 ).

[0101] The gates of the fifth transistor T5 and the sixth transistor T6 of the sub-pixels in the same row are electrically connected to the same-level light emitting signal terminal EM (for example, the Nth-level light emitting signal terminal EM) through the same light emitting signal line EML. N Or the (N+1)th luminous signal terminal EM N+1 ).

[0102] The gates of the first transistor T1 and the seventh transistor T7 of the sub-pixel in the same row are electrically connected to the previous scanning signal terminal GATE through the same reset signal line RL. It should be noted that the scanning signal Vgate output by the previous scanning signal terminal GATE is used as the reset signal Vre, that is, the previous scanning signal terminal GATE is used as the reset signal terminal RESET of the current sub-pixel. For example, Fig.11 In the Nth level, the scan signal terminal GATE N The output scanning signal Vgate is used as the second transistor T2 and the fourth transistor T4 to connect to the (N+1)th stage scanning signal terminal GATA. N+1 Reset signal Vre of the electrically connected sub-pixel.

[0103] The first electrodes of the first transistor T1 and the seventh transistor T7 of the sub-pixel in the same row are electrically connected to the initialization voltage signal terminal INIT through the same initialization voltage signal line IL. Here, the initialization voltage signal Vin output by the initialization voltage signal terminal INIT may be a constant voltage signal, for example, Fig.11 The initialization voltage signal Vin in can be a constant low voltage signal.

[0104] In some embodiments, see Figure 8G and 9B The display substrate 200 also includes a first source-drain metal layer L SD1 and the second gate metal layer L G2 The second source-drain metal layer L SD2 .

[0105] like Fig. 8E , 8G As shown in FIG. 9B , each first voltage signal line 40 includes a first sub-voltage signal line 41 and a second sub-voltage signal line 42, and the first sub-voltage signal line 41 is electrically connected to the first sub-voltage signal line 41. Here, the first sub-voltage signal line 41 is disposed on the first source-drain metal layer L SD1 In the embodiment, the second sub-voltage signal line 42 is disposed on the second source-drain metal layer L SD2 That is, the second sub-voltage signal line 42 is disposed on a side of the first sub-voltage signal line 41 close to the substrate 10, and the first sub-voltage signal line 41, the first data line 21 and the second data line 22 are disposed in the same layer.

[0106] The first voltage signal line 40 can transmit a first voltage signal Vdd which is a constant voltage signal to the sub-pixel electrically connected thereto, that is, the voltages on the first sub-voltage signal line 41 and the second sub-voltage signal line 42 can both be stable voltages. When the display device including the above-mentioned display substrate 200 displays a picture, the first sub-voltage signal line 41 which is arranged in the same layer as the first data line 21 and the second data line 22 and is located between the two can shield the data signal Vdata transmitted on the first data line 21 and the second data line 22 because of its stable voltage. In this way, during the display process of the display device, the parasitic capacitance between the adjacent first data line 21 and the second data line 22 can be reduced by the first self-voltage signal line 41 arranged between the two, thereby reducing the crosstalk between the data signals Vdata and improving the display effect of the display device.

[0107] It should be noted that the first sub-voltage signal line 41 , the first data line 21 and the second data line 22 may be formed by the same patterning process so that they are disposed in the same layer.

[0108] In addition, along the first direction OU, the first sub-pixels 31 and the second sub-pixels 32 may be arranged alternately, for example Figure 7 In the display substrate 200 shown, the first sub-pixels 31 and the second sub-pixels 32 are arranged alternately along the first direction OU. Along the first direction OU, the first sub-pixels 31 and the second sub-pixels 32 may also be arranged non-alternatingly, for example, a row of sub-pixels is composed entirely of first sub-pixels 31 or entirely of second sub-pixels 32; for another example, a row of sub-pixels includes both a plurality of first sub-pixels 31 and a plurality of second sub-pixels 32, and at least some of the first sub-pixels 31 and / or the second sub-pixels 32 are arranged continuously.

[0109] For example, see Fig.8F , 9B 12, the display substrate 200 further includes a first insulating layer IS1 disposed between the first sub-voltage signal line 41 and the second sub-voltage signal line 42, and the first insulating layer IS1 includes a plurality of first via holes 501. The first sub-voltage signal line 41 and the second sub-voltage signal line 42 are electrically connected through at least one first via hole 501 among the plurality of first via holes 501.

[0110] Exemplarily, the orthographic projections of the first sub-voltage signal line 41 and the second sub-voltage signal line 42 on the substrate 10 overlap or partially overlap. Thus, the first via 501 can be disposed in the overlapped or overlapping region of the orthographic projections of the two, so that the two can be connected through the first via 501.

[0111] Here, the first insulating layer IS1 may be a single-layer structure or a stacked structure including multiple film layers. Fig. 9BAs shown, the first insulating layer IS1 includes a stacked first planar layer 502 and a passivation layer 503. In this case, the first via hole 501 is a through hole penetrating the first planar layer 502 and the passivation layer 503.

[0112] For example, see Fig.8F , a line connecting the centers of two adjacent first via holes 501 may be parallel or substantially parallel to the first direction OU.

[0113] In some embodiments, see Figure 7 , 8G and Fig.12 , the first data line 21 located between two adjacent columns of sub-pixels (refer to Fig.12 The middle data line DL3), the second data line 22 (refer to Fig.12 In the embodiment of the present invention, in the first data line DL2) and the first sub voltage signal line 41, the portion of the first data line 21 adjacent to the first via hole 501 is bent in a direction away from the first via hole 501 to form a first bent portion 211; the portion of the second data line 22 adjacent to the first via hole 501 is bent in a direction away from the first via hole 501 to form a second bent portion 221. The first bent portion 211 and the second bent portion 221 are opposite to each other to form an accommodation area A. The first sub voltage signal line 41 includes a conductive portion 411 passing through the first via hole 501, and the conductive portion 411 is located in the accommodation area A.

[0114] It should be noted that the first sub-voltage signal line 41 is electrically connected to the second sub-voltage signal line 42 through its conductive portion 411 located at the first via hole 501. In this case, for example, see Fig.12 Along the first direction OU, the size D1 of the conductive portion 411 is greater than the width D0 of the first sub-voltage signal line 41 , so that the first via 501 has a larger size along the first direction OU, thereby ensuring good electrical contact between the first sub-voltage signal line 41 and the second sub-voltage signal line 41 .

[0115] The size D3 of the accommodation space A may be greater than the spacing D2 between the portion of the first data line 21 (refer to the data line DL3) that is not the first curved portion and the portion of the second data line 22 (refer to the data line DL2) that is not the second curved portion between two adjacent columns of sub-pixels. Here, the first curved portion 211 is beneficial for the first data line 21 to avoid the conductive portion 43 at the first via hole 501. Similarly, the second curved portion 211 is beneficial for the second data line 22 to avoid the conductive portion 43 at the first via hole 501. Thus, the first data line 21 and the second data line 22 can be kept away from the first voltage signal line 40, that is, the first data line 21 and the second data line 22 can be prevented from short-circuiting with the first voltage signal line 40, thereby improving the yield of the display substrate 200.

[0116] For example, see Figure 7 and 12 , the first via 501 is arranged between two adjacent rows of sub-pixels, and is located between two adjacent columns of sub-pixels. In this case, it can be avoided that the first bent portion 211 and the second bent portion 221 occupy the installation space of components in the sub-pixels adjacent thereto, so that the bending degree of the first bent portion 211 and the second bent portion 221 along the first direction OU can be set to be larger without hindering the installation of components in adjacent sub-pixels. Therefore, the size D3 of the accommodating area A formed by the first bent portion 211 and the second connecting portion 221 can be set to be larger, so that along the first direction OU, the size D1 of the conductive portion 411 and the size of the first via 501 can also be set to be larger, which is beneficial to the electrical contact between the first sub-voltage signal line 41 and the second sub-voltage signal line. Based on this, for example, see Fig.12 , among the first data line 21, the second data line 22 and the first sub-voltage signal line 41 located between two adjacent columns of sub-pixels, along the first direction OU, the spacing D4 between the conductive portion 411 and the first curved portion 211 is equal to or approximately equal to the spacing D5 between the conductive portion 411 and the second curved portion 221.

[0117] For example, see Fig.12 , among the first data line 21, the second data line 22 and the first sub-voltage signal line 41 located between two adjacent columns of sub-pixels, along the first direction OU, the spacing D4 between the conductive portion 411 and the first curved portion 211 is equal to or approximately equal to the spacing D4' between the non-first curved portion of the first data line 21 and the non-conductive portion of the first sub-voltage signal line 41.

[0118] For example, see Fig.12 , among the first data line 21, the second data line 22 and the first sub-voltage signal line 41 located between two adjacent columns of sub-pixels, along the first direction OU, the spacing D5 between the conductive portion 411 and the second curved portion 221 is equal to or approximately equal to the spacing D5' between the portion of the second data line 22 other than the second curved portion and the portion of the non-conductive portion of the first sub-voltage signal line 41.

[0119] In some embodiments, see Figure 7 , 8G , 9B and 12 are adjacent to a column of sub-pixels and are located on both sides of the column of sub-pixels along the first direction OU (i.e. Fig.12 The first data line 21 (refer to the left and right sides of the sub-pixel) Fig.12 The middle data line DL1) and the second data line 22 (refer to Fig.12In the data line DL2), the first curved portion 211 is bent toward the first data line 21, and the second curved portion 221 is bent toward the second data line 22, that is, the bending directions of the two are opposite. In this case, for example, see Figure 8G and 9B The display substrate 20 also includes a first source and drain metal layer L SD2 That is, the first sub voltage signal line 41 is provided at the same layer as the first connection part 60. The first connection part 60 is provided between the first bending part 211 and the second bending part 221. Here, the first connection part 60 can be configured to shield the data signal Vdata of the first data line 21 and the second data line 22.

[0120] It should be noted that, in the first signal line 21 (refer to the data line DL3) and the second signal line 22 (refer to the data line DL2) located between two columns of pixels, the bending directions of the first curved portion 211 and the second curved portion 221 are opposite, that is, the first curved portion 221 is bent in a direction away from the second curved portion 221, and the second curved portion 221 is bent in a direction away from the first curved portion 211, so as to avoid the first via 501 located therebetween. Therefore, in the first signal line 21 (refer to the data line DL1) and the second signal line 22 (refer to the data line DL2) electrically connected to the same column of sub-pixels, the first curved portion 211 and the second curved portion 221 are arranged opposite to each other, that is, the first curved portion 211 is bent in a direction close to the second curved portion 221, and the second curved portion 221 is bent in a direction close to the first curved portion 211.

[0121] In the case where the first connection portion 60 is not provided, the above situation may result in that in the first signal line 21 and the second signal line 22 electrically connected to the same column of sub-pixels, the distance between the first curved portion 211 and the second curved portion 221 is small, causing a large parasitic capacitance between the first curved portion 211 and the second curved portion 221, affecting the data writing and threshold voltage compensation of the sub-pixels. In the case where the first connection portion 60 is provided, the first connection portion 60 can shield the data signal Vdata of the first signal line 21 and the second signal line 22, thereby reducing the crosstalk between the data signals Vdata and improving the display effect of the display device.

[0122] For example, see Fig.12 Along the second direction OV, the size L1 of the first connecting portion 60 is greater than or equal to the length L2 of the first bending portion 211 and the length L3 of the second bending portion 221. This can reduce the relative area between the first bending portion 211 and the second bending portion 221, that is, the parasitic capacitance can be further reduced, which is beneficial for the first connecting portion 60 to further reduce the crosstalk between the data signals Vdata.

[0123] In some embodiments, see Fig.12 In the case where the display substrate 200 further includes the first connection portion 60, along the second direction OV, the maximum sizes of two portions of the first connection portion 60 located on both sides of a line connecting the centers of two adjacent first via holes 501 are substantially equal.

[0124] It should be noted that the orthographic projection of the first connecting portion 60 on the substrate 10 may be a regular shape or an irregular shape. Figure 7 and 12 , when the orthographic projection of the first connection portion on the substrate 10 is a regular shape, the orthographic projection of the geometric center O1 of the first connection portion 60 on the substrate 10 and the orthographic projection of the center O2 of the two first via holes 501 adjacent to the first connection portion 60 on the substrate 10 are approximately located on the same straight line. Here, when the orthographic projection of the first connection portion 60 on the substrate 10 is a regular shape, that is, when the orthographic projection of the first connection portion 60 has a geometric center, the geometric center of the orthographic projection of the first connection portion 60 can be approximately located on the same straight line as the geometric center of the orthographic projection of the two first via holes 501 adjacent to the first connection portion 60. In this way, the relative area of ​​the first curved portion 211 and the second curved portion 221 is reduced to 0, thereby further improving the shielding effect of the first connection portion 60 on the data signal Vdata of the first data line 21 and the second data line 22, and reducing the crosstalk between the data signals Vdata.

[0125] In some embodiments, see Fig. 8A , 9B , 10A, 10B and 11, the display substrate 200 further includes an anode layer 90 disposed in the light emitting device E of each sub-pixel and a sixth transistor T6 disposed in the pixel driving circuit of each sub-pixel. The active layer 76 of the sixth transistor T6 includes a first conductor portion, and the first connecting portion 60 is electrically connected to the first conductor portion of the active layer 76 and the anode layer 90. That is, the first conductor portion of the active layer 76 is electrically connected to the anode layer 90 through the first connecting portion 60.

[0126] Here, the active layer 76 of the sixth transistor T6 may include a first conductor portion, a channel portion, and a second conductor portion, and the first conductor portion and the second conductor portion are connected through the channel portion. The first conductor portion and the second conductor portion may serve as one of the source and the drain of the sixth transistor T6, and the second conductor portion may serve as the other of the source and the drain. For example, see Fig.11 In the case where the sixth transistor T6 is a P-type transistor, the first conductive portion connected to the anode layer 90 serves as the drain of the sixth transistor T6, and the second conductive portion serves as the source of the sixth transistor T6.

[0127] In addition, refer to Fig.11 As described above, the sixth transistor T6 and the fifth transistor T5 are configured to conduct the line between the first voltage signal terminal VDD and the second voltage signal terminal VSS in response to the light emission signal Vem from the light emission signal segment EM. Here, the sixth transistor T6 can be called the first light emission control transistor, and the fifth transistor T5 can be called the second light emission control transistor.

[0128] In this way, the first connection portion 60 is electrically connected to the light-emitting device E, and the light-emitting device E is electrically connected to the second voltage signal terminal VSS. Therefore, in the process of displaying an image by a display device including the display substrate 200, the first connection portion 60 can shield the data signal Vdata on the first signal line 21 and the second signal line 22 located between two columns of pixels due to its stable voltage, thereby reducing crosstalk between the data signals Vdata and improving the display effect of the display device.

[0129] It should also be noted that since the first connecting portion 60 in the above-mentioned display substrate 200 is arranged on the same layer as the first sub-voltage signal line 41, the first data line 21 and the second data line 22, the first connecting portion 60 can be formed to reduce the crosstalk between the data signal Vdata of the first data line 21 and the second data line 22 without adding an additional composition process.

[0130] It should be noted that, since the display substrate 200 includes many film layers, Fig.13 The light emitting device E of each sub-pixel is not shown. Exemplarily, the light emitting device E is disposed on a side of the first connecting portion 60 away from the substrate 10, and the light emitting device E includes an anode layer 90, a light emitting functional layer and a cathode layer disposed in a direction away from the substrate. Fig. 9B At least a portion of the anode layer 90 electrically connected to the first connection portion 60 is shown in the form of a dashed outline.

[0131] For example, see 8D and Fig. 9B The display substrate 200 further includes a A and the second source and drain metal layer L SD2 The third insulating layer IS3, the fourth insulating layer IS4 and the fifth insulating layer IS5 are arranged in sequence in a direction away from the substrate 10. It should be noted that: Fig.8D What is shown is a top view of a stacked structure 12 composed of a third insulating layer IS3 , a fourth insulating layer IS4 and a fifth insulating layer IS5 . Here, in order to clearly show the positions of the via holes provided in the stacked structure 12 , the stacked structure 12 is shown in a transparent form.

[0132] Based on this, in some embodiments, the display substrate 200 further includes second connection portions 80. Each second connection portion 80 is disposed between the active layer 76 of the sixth transistor T6 and the corresponding first connection portion 60, and the second connection portion 80 and the second sub-voltage signal line 42 are disposed in the same layer.

[0133] The second connection portion 80 is electrically connected to the active layer 76 of the sixth transistor T6 and the corresponding first connection portion 60. That is, the first connection portion 60 and the anode layer 90 are electrically connected through the second connection portion 80. The second connection portion 80 facilitates the electrical connection between the first connection portion 60 and the anode layer 90.

[0134] For example, see Fig.8D , 9B 14 , a sixth via hole 508 is further provided in the stacked structure 12 , and the second connecting portion 80 is electrically connected to the active layer 76 of the sixth transistor T6 through the sixth via hole 508 .

[0135] The light-emitting functional layer includes a light-emitting material layer, and further, may include at least one of an election transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), or a hole injection layer (HIL). The light-emitting material layer may be an organic light-emitting material layer, in which case the display device including the display substrate 200 is an OLED (Organic Light-Emitting Diode) display device. The light-emitting material layer may also be a quantum dot light-emitting material layer, in which case the display device including the display substrate 200 is a QLED (Quantum Dot Light-Emitting Diode) display device.

[0136] For example, see Figure 8H , 9A 9B, the display substrate 200 further includes a second insulating layer IS2 disposed between the anode layer 90 and the first connecting portion 60. The second insulating layer IS2 may be, for example, a second flat layer. A second via hole 504 is disposed in the second insulating layer IS2. The orthographic projection of the second via hole 504 on the substrate 10 is located within the orthographic projection of the first connecting portion 60 on the substrate 10. The anode layer 90 of the light-emitting device E is electrically connected to the first connecting portion 60 through the second via hole 504.

[0137] In some embodiments, see Fig.12The orthographic projection of the first connection portion 60 on the substrate 10 and the orthographic projection of the second connection portion 80 on the substrate 10 have an overlapping area. In this way, a via hole can be provided in the overlapping area to facilitate the connection of the two through the via hole.

[0138] For example, see Fig.8F , 9A , 9B and 14, a third via 505 is further provided in the first insulating layer IS1, each of the third vias 505 is located in the overlapping portion of the positive projection of the first connecting portion 60 and the second connecting portion 80 on the substrate 10, and the first connecting portion 60 and the second connecting portion 80 are electrically connected through the third via 505.

[0139] In some embodiments, see Figures 10A to 11 In the case where both the first sub-pixel 31 and the second sub-pixel 32 include a fifth transistor T5 (which may be referred to as a second light emission control transistor) and a capacitor Cst, as shown in FIG. Fig. 9B As shown, the second sub voltage signal line 42 is electrically connected to the active layer 75 of the fifth transistor T5.

[0140] For example, Fig.8D , 9B As shown in FIG. 14 , a fourth via hole 506 is provided in the third insulating layer IS3 , the fourth insulating layer IS4 and the fifth insulating layer IS5 , and the active layer 75 of the fifth transistor T5 is electrically connected to the second sub-voltage signal line 42 through the fourth via hole 506 .

[0141] Based on this, in some embodiments, Fig.8D , 9B As shown in Figures 14 and 15, the first plate A1 of the capacitor Cst is disposed between the fourth insulating layer IS4 and the fifth insulating layer IS5, and the second plate B1 is disposed between the third insulating layer ISO3 and the fourth insulating layer IS4. That is, the first plate A1 is located on the side of the second sub-voltage signal line 42 close to the substrate 10, and the second plate B1 is located on the side of the first plate A1 close to the substrate 10. The first plate A1 and the second plate B1 are disposed opposite to each other, that is, the plate surfaces of the two are at least partially opposite to each other. The second sub-voltage signal line 42 is also electrically connected to the first plate A1 of the capacitor Cst. For example, see Fig. 9B , a plurality of fifth via holes 507 are provided in the fifth insulating layer IS5, and the second sub-voltage signal line 42 passes through the fifth via hole 507 and the first electrode plate A1 of the capacitor Cst. Here, the second sub-voltage signal line 42 passes through one fifth via hole 507 and the first electrode plate A1 of the capacitor Cst; it can also be as follows Fig.14 As shown, the second sub-voltage signal line 42 passes through two or more fifth via holes 507 and the first electrode plate A1 of the capacitor Cst to ensure good electrical contact between the two.

[0142] In some embodiments, see Figure 7 and 8C , in each sub-pixel located in the same row, the first plates A1 of the capacitors Cst of at least two adjacent sub-pixels are electrically connected. Here, at least part of the first sub-voltage signal lines 41 can be connected in parallel through the first plates A1 of the capacitors Cst electrically connected to each other, that is, at least part of the first voltage signal lines 40 are connected in parallel, so that the resistance of the first voltage signal lines 40 connected in parallel can be reduced, and then the divided voltage on the first voltage signal lines 40 can be reduced.

[0143] Based on this, for example, Figure 7 and 8C As shown, the first electrodes A1 of the capacitors Cst of the plurality of sub-pixels in each row of sub-pixels, for example, all the sub-pixels in each row of sub-pixels, are electrically connected to each other, forming a plurality of auxiliary conductive strips 101 extending along the first direction OU, and the orthographic projections of the plurality of auxiliary conductive strips 101 on the substrate 10 are interlaced with the orthographic projections of the plurality of first sub-voltage signal lines 41 on the substrate 10, forming a grid structure. In this way, the first voltage signal lines 40 can be connected in parallel, thereby further reducing the resistance of the first voltage signal lines 40, and further reducing the voltage division thereon.

[0144] The following will provide an exemplary introduction to other connection relationships in the pixel driving circuit in the display substrate 200 that have not been introduced before.

[0145] See also Fig. 8E , the second source and drain metal layer L SD2 The third connecting portion 110, the fourth connecting portion 120 and the fifth connecting portion 130 are also included. Fig.8D and 15D The stacked structure 12 further includes a plurality of seventh via holes 510 extending therethrough, the fifth insulating layer IS5 further includes a plurality of tenth via holes 513 extending therethrough, and the fourth insulating layer IS4 and the fifth insulating layer IS5 include a plurality of eleventh via holes 514 extending therethrough.

[0146] See also Fig. 8A , 15D15E, the first end of the third connection portion 110 is electrically connected to the initialization voltage signal line IL through the tenth via 513, and the second end of the third connection portion 110 is electrically connected to the first end of the active layer 71 of the first transistor T1 through the seventh via 510B, so that the active layer 71 of the first transistor T1 can be electrically connected to the initialization voltage signal line IL. The first end of the fourth connection portion 120 is electrically connected to the second end of the active layer 71 of the first transistor T1 through the seventh via 510C, and the second end of the fourth connection portion 120 is electrically connected to the second plate B1 of the capacitor Cst through the eleventh via 514, so that the active layer 71 of the first transistor T1 can be electrically connected to the second plate B1 of the capacitor Cst. It should be noted that the second plate B1 of the capacitor Cst and the gate G3 of the third transistor T3 are integrally formed, and the overlapped portion of the orthographic projection of the second plate B1 of the capacitor Cst and the active layer 73 of the third transistor T3 serves as the gate G3 of the third transistor T3. That is, the second end of the active layer 71 of the first transistor T1 is also electrically connected to the gate G3 of the third transistor T3. The gate G1 of the first transistor T1 is electrically connected to the reset signal line RL. Here, the portion where the reset signal line RL overlaps with the orthographic projection of the active layer 71 of the first transistor T1 can be used as the gate G1 of the first transistor T1.

[0147] The second end of the active layer 72 of the second transistor T2 is electrically connected to the first end of the fourth connection portion 120 through the seventh via 510C, thereby achieving electrical connection with the second electrode plate B1 of the capacitor Cst. The first end of the active layer 72 of the second transistor T2 is electrically connected to the second end of the active layer 73 of the third transistor T3. The gate G2 of the second transistor T2 is electrically connected to the gate line GL.

[0148] The first end of the active layer 73 of the third transistor T3 is electrically connected to the second end of the active layer 74 of the fourth transistor T4 and the second end of the active layer 75 of the fifth transistor T5. The second end of the active layer 73 of the third transistor T3 is also electrically connected to the first end of the active layer 76 of the sixth transistor T6.

[0149] See also Fig. 8A , 8E 15D to 15F, the first end of the fifth connection portion 130 is electrically connected to the first end of the active layer 74 of the fourth transistor T4 through the seventh via hole 510E. Fig.8F and 13, an eighth via hole 511 is further provided in the first insulating layer IS1. Continuing to refer to 15D to 15F, the second end of the fifth connection portion 130 is electrically connected to the first data line 21 or the second data line 22 through the eighth via hole 511. In this way, the first end of the active layer 74 of the fourth transistor T4 can be electrically connected to the first data line 21 or the second data line 22 through the fifth connection portion 130. The gate G4 of the fourth transistor T4 is electrically connected to the gate line GL. Here, the portion where the gate line GL overlaps with the positive projection of the active layer 74 of the fourth transistor T4 can be used as the gate G4 of the fourth transistor T4.

[0150] It should be noted that see Fig. 8E and 8F , region S P1 is the area where the first sub-pixel 31 is located, and area S P2 is the area where the second sub-pixel 32 is located. The plane MN is perpendicular to the plane where the substrate 10 is located. P1 and S P2 The first sub-pixel 31 is connected to the first signal line 21 on its left side, and the second sub-pixel 32 is connected to the second signal line 22 on its right side, so the connection position between the first sub-pixel 31 and the first signal line 21 and the connection position between the second sub-pixel 32 and the second signal line 22 can be set to be different, that is, the eighth via hole 511 in the first sub-pixel 31 is located in the area S P1 The distribution position in the area S is the same as that of the eighth via hole 511 in the second sub-pixel 32. P2 The distribution positions are different.

[0151] On this basis, for example, Figure 7 , 8E , 10A and 10B, the eighth via hole 511 in the first sub-pixel 31 and the eighth via hole 511 in the second sub-pixel 32 are not mirror-symmetrical with respect to the plane MN. In addition, the fifth connecting portion 130 of the first sub-pixel 31 and the second sub-pixel 32 can be set to a non-identical structure to facilitate the electrical connection of the fourth transistor T4 with the corresponding data line. In this way, when there is a process deviation during preparation, for example, when each eighth via hole 511 and / or the fifth connecting portion 130 is offset to one side, the offset of the above structure relative to the other side can be avoided from doubling. This can reduce the dimensional error caused by process fluctuations.

[0152] The gate G5 of the fifth transistor T5 is electrically connected to the light emitting signal line EML. Here, the portion where the light emitting signal line EML overlaps with the active layer 75 of the fifth transistor T5 in orthographic projection may be used as the gate G5 of the fifth transistor T5.

[0153] The gate G6 of the sixth transistor T6 is electrically connected to the light emitting signal line EML. Here, the portion where the light emitting signal line EML and the active layer 76 of the sixth transistor T6 overlap in orthographic projection may be used as the gate G6 of the sixth transistor T6.

[0154] See also Fig. 8A , 15D and 15E, the first end of the active layer 77 of the seventh transistor T7 is electrically connected to the first end of the third connection portion 110 through the tenth via hole 513, and is thereby electrically connected to the initialization voltage signal line IL through the third connection portion 110. The second end of the active layer 77 of the seventh transistor T7 is electrically connected to the anode layer 90 of the light emitting device E. It should be noted that due to Figure 7 The display panel 200 shown does not show the anode layer 90, so the connection relationship between the two is not shown in the figure. It should be understood that the connection structure between the second end of the active layer 77 of the seventh transistor T7 and the anode layer 90 of the light emitting device E can be set according to actual needs.

[0155] In some embodiments, see Figure 8C , the second metal layer L G2 It also includes a shielding portion 102, see Fig.8D , 9B 15D, the fifth insulating layer IS5 further includes a plurality of ninth via holes 512. Fig.15D and 15E , each sub-pixel is located in the area S P The shielding portion 102 is electrically connected to the second sub-voltage signal line 42 through the ninth via hole 512, and the orthographic projection of the shielding portion 102 on the substrate 20 partially overlaps with the orthographic projections of the active layer 71 of the first transistor T1, the active layer 72 of the second transistor T2, the active layer 75 of the fourth transistor T4, and the active layer 77 of the seventh transistor T7 on the substrate 10. In this way, when the display device including the display substrate 200 displays an image, the shielding portion 102 can play a light shielding role, thereby reducing the leakage current of the above transistors.

[0156] Some embodiments of the present disclosure provide a display device, including the display substrate 200 described above. The beneficial effects of the display device are the same as those of the display substrate 200 described above, and will not be described in detail herein.

[0157] See also Figure 7 , 13 15A to 15F, some embodiments of the present disclosure provide a method for preparing a display substrate, which can be used to prepare the above-mentioned display substrate 200. The preparation method includes the following S110 to S140.

[0158] In S110, see Figure 7 , providing a substrate 10.

[0159] In S120, see Figure 7 , a pixel driving circuit of a plurality of sub-pixels arranged in an array is formed on the substrate 10. Here, see Figure 7 Each column of sub-pixels includes a plurality of first sub-pixels 31 and second sub-pixels 32, and the first sub-pixels 31 and the second sub-pixels 32 are alternately arranged along the second direction OV.

[0160] In S130, see Fig.15E , a plurality of second sub-voltage signal lines 42 are formed on the side of the pixel driving circuit of the plurality of sub-pixels away from the substrate 10, and the positive projection of each second sub-voltage signal line 42 on the substrate 10 is located between two adjacent columns of sub-pixels. It should be noted that the equivalent circuit diagram of the pixel driving circuit of the sub-pixel can be found in Fig.11 The structures of the first transistor T1 to the seventh transistor T7 and the storage capacitor Cst included therein can refer to the relevant description above.

[0161] In S140, see Figure 7 and 15F , a plurality of first data lines 21 , a plurality of second data lines 22 , and a plurality of first sub-voltage signal lines 41 are formed on a side of the plurality of second sub-voltage signal lines 42 away from the substrate 10 .

[0162] Here, a first sub-voltage signal line 41 and a second sub-voltage signal line 42 constitute a first voltage signal line 40, each first voltage signal line 40 is electrically connected to the pixel driving circuit of at least one column of sub-pixels, and the positive projection of each first voltage signal line 40 on the substrate 10 is located between the positive projections of two adjacent columns of sub-pixels on the substrate 10. In addition, the first data lines 21 and the second data lines 22 are arranged alternately along the first direction. Along the first direction OU, a column of sub-pixels is adjacent to a first data line 21 and a second data line 22, and the first data line 21 and the second data line 22 are respectively located on both sides of the column of sub-pixels, and the pixel driving circuit of each first sub-pixel 31 of the column of sub-pixels is electrically connected to the first data line 21 adjacent to it, and the pixel driving circuit of each second sub-pixel 32 of the column of sub-pixels is electrically connected to the second data line 22 adjacent to it.

[0163] The beneficial effects of the preparation method are the same as those of the display substrate 200 described above, and will not be described in detail herein.

[0164] The following is an overall and exemplary introduction to the method for preparing the display substrate 200. In some embodiments, the method includes the following steps S210 to S310.

[0165] In S210, if Fig. 9B and 15A As shown, an active layer L is formed on the substrate 10. AIn the area S corresponding to a sub-pixel P Inside, the active layer L A The active layer 71 includes an active layer 71 of a first transistor T1, an active layer 72 of a second transistor T2, an active layer 73 of a third transistor T3, an active layer 74 of a fourth transistor T4, an active layer 75 of a fifth transistor T5, an active layer 76 of a sixth transistor T6 and an active layer 77 of a seventh transistor T7.

[0166] For example, see Fig. 9B Before S10, an inorganic buffer layer 11 is formed on the substrate 10. The inorganic buffer layer 11 may be a single-layer structure or a multi-layer stacked structure, such as a stacked structure of alternately arranged inorganic film layers and organic film layers.

[0167] In S220, if Fig. 9B As shown, in the active layer L A A third insulating layer IS3 is formed on a side of the substrate away from the substrate 10 .

[0168] In S230, if Fig. 9B and 15B As shown, a first gate metal layer L is formed on a side of the third insulating layer IS3 away from the substrate 10. G1 In the area S P Inside, the first gate metal layer L G1 It includes a gate G1 of a first transistor T1, a gate G2 of a second transistor T2, a gate G3 of a third transistor T3, a gate G4 of a fourth transistor T4, a gate G5 of a fifth transistor T5, a gate G6 of a sixth transistor T6 and a gate G7 of a seventh transistor T7, as well as a second plate B1 of a capacitor Cst, a reset signal line RL, a gate line GL and a light emitting signal line EML.

[0169] In S240, Fig. 9B As shown, in the first gate metal layer L G1 A fourth insulating layer IS4 is formed on a side of the substrate away from the substrate 10 .

[0170] For example, see Fig.15D After S240, the manufacturing method further includes S241. In S241, a plurality of tenth via holes 513 are formed in the fourth insulating layer IS4.

[0171] In S250, Fig. 9B and 15C As shown, a second gate metal layer L is formed on a side of the fourth insulating layer IS4 away from the substrate 10. G2 , the second gate metal layer L G2 The device includes a first electrode plate A1 of a capacitor Cst, an initialization voltage signal line IL and a shielding portion 102 .

[0172] In S260, Fig. 9B As shown, in the second gate metal layer L G2 A fifth insulating layer IS5 is formed on a side of the substrate 10 away from the substrate 10 .

[0173] For example, Fig.15D As shown, after S260, the above-mentioned preparation method further includes S261 to S263. In S261, a plurality of fifth vias 507 and a plurality of ninth vias 512 are formed in the fifth insulating layer IS5. In S262, a plurality of penetrating eleventh vias 514 are formed in the fourth insulating layer IS4 and the fifth insulating layer IS5. In S263, a plurality of penetrating fourth vias 506, sixth vias 508 and seventh vias 510 (including 510B, 510C and 510E) are formed in the third insulating layer IS3, the fourth insulating layer IS4 and the fifth insulating layer IS5. That is, a plurality of penetrating fourth vias 506, sixth vias 508 and seventh vias 510 are formed in the stacked structure 12.

[0174] It should be noted that the order of S261 to S263 is not limited here, and S261 to S263 can be performed in a certain order, or the three steps can be performed simultaneously.

[0175] In S270, see Fig. 8E , 9B and 15E, forming a second source-drain metal layer L on a side of the fifth insulating layer IS5 away from the substrate 10. SD2 The second source and drain metal layer L SD2 A second sub voltage signal line 42 , a second connection portion 80 , a third connection portion 110 , a fourth connection portion 120 , and a fifth connection portion 130 may be included.

[0176] In S280, Fig.8F and 9B As shown, in the second gate metal layer L G2 A first insulating layer IS1 is formed on a side of the substrate away from the substrate 10 .

[0177] Exemplarily, when the first insulating layer IS1 includes the first planar layer 502 and the passivation layer 503, S280 includes: G2 A first planar layer 502 is formed on a side of the first planar layer 502 away from the substrate 10 , and a passivation layer 503 is formed on a side of the first planar layer 502 away from the substrate 10 , thereby forming a first insulating layer IS1 .

[0178] For example, see Fig.8F and 13After S280, the manufacturing method further includes S281. In S281, a plurality of first via holes 501, third via holes 505 and eighth via holes 511 are formed in the first insulating layer IS1.

[0179] In S290, see Figure 8G and 9B 15F, forming a first source-drain metal layer L on a side of the first insulating layer IS1 away from the substrate 10 SD1 . The first source and drain metal layer L SD1 The system includes a plurality of first connection parts 60 , a first data line 21 , a second data line 22 and a first sub-voltage signal line 41 .

[0180] In S300, see Figure 8H and 9B , in the first source and drain metal layer L SD1 A second insulating layer IS2 is formed on a side of the substrate away from the substrate 10 .

[0181] Exemplarily, after S300, the manufacturing method further includes S301. In S301, a plurality of second via holes 504 are formed in the second insulating layer IS2.

[0182] In some embodiments, after S300, the preparation method further includes S310.

[0183] In S310, see Figure 7 , 8H and 9B, an anode layer 90 of each light emitting device E is formed on a side of the second insulating layer IS2 away from the substrate 10 .

[0184] It should be noted that the structure and function of the vias and the film layer can refer to the above description, which has been described in detail above and will not be repeated here. The preparation of the pixel driving circuit of the sub-pixel in S120 of the above preparation method can refer to S210 to S250 above.

[0185] In addition, the above-mentioned film layer and vias can be formed by a composition process, and the composition process can include a photolithography process. The photolithography process refers to a process including film formation (such as chemical vapor deposition, Chemical Vapor Deposition, CVD for short), exposure, development and other process and using photoresist, mask template, exposure machine and the like to form a pattern.

[0186] It is worth noting that throughout the specification, reference to "some embodiments" means that the specific features, structures or characteristics described in connection with the embodiment are included in at least one embodiment. Therefore, throughout the specification, the phrase "in some embodiments" appearing in various places does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0187] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: substrate; A plurality of first data lines and a plurality of second data lines are disposed on the substrate, wherein the first data lines and the second data lines are alternately arranged along a first direction; A plurality of sub-pixels arranged in an array are disposed on the substrate, a first data line and a second data line are disposed between each two adjacent columns of sub-pixels; each column of sub-pixels includes a plurality of first sub-pixels and second sub-pixels, and the first sub-pixels and the second sub-pixels are alternately arranged along the second direction; along the first direction, a column of sub-pixels is adjacent to a first data line and a second data line, and the first data line and the second data line are respectively located on both sides of the column of sub-pixels, each first sub-pixel in the column of sub-pixels is electrically connected to the first data line adjacent thereto, and each second sub-pixel in the column of sub-pixels is electrically connected to the second data line adjacent thereto; and, A plurality of first voltage signal lines are arranged on the substrate, wherein an orthographic projection of each first voltage signal line on the substrate is located between an orthographic projection of a first data line and a second data line between two adjacent columns of sub-pixels on the substrate; The first voltage signal line is electrically connected to at least one column of sub-pixels; The first voltage signal line includes: a first sub-voltage signal line and a second sub-voltage signal line, the second sub-voltage signal line is arranged on a side of the first sub-voltage signal line close to the substrate and is electrically connected to the first sub-voltage signal line, and the first sub-voltage signal line is arranged on the same layer as the first data line and the second data line.

2. The display substrate according to claim 1, wherein: Along the first direction, the first sub-pixels and the second sub-pixels are arranged alternately.

3. The display substrate according to claim 1, further comprising a first insulating layer disposed between the first sub-voltage signal line and the second sub-voltage signal line, the first insulating layer comprising a plurality of first via holes; the first sub-voltage signal line and the second sub-voltage signal line are electrically connected through at least one first via hole among the plurality of first via holes; wherein, Among the first data line, the second data line and the first sub voltage signal line located between two adjacent columns of sub-pixels, A portion of the first data line adjacent to the first via hole is bent in a direction away from the first via hole to form a first bent portion; A portion of the second data line adjacent to the first via hole is bent in a direction away from the first via hole to form a second bent portion; The first curved portion and the second curved portion are opposite to each other to form a receiving area; The first sub-voltage signal line includes a conductive portion passing through the first via hole, and the conductive portion is located in the accommodating area.

4. The display substrate according to claim 3, wherein: Along the first direction, the size of the conductive portion is larger than the width of the first sub-voltage signal line; and the size of the accommodating space is larger than the spacing between the non-first bending portion of the first data line and the non-second bending portion of the second data line between two adjacent columns of sub-pixels.

5. The display substrate according to claim 3 or 4, wherein: Along the first direction, a distance between the conductive portion and the first bent portion is equal to a distance between the conductive portion and the second bent portion.

6. The display substrate according to claim 3 or 4, wherein: Along the first direction, the distance between the conductive portion and the first bent portion is equal to the distance between the portion of the first data line other than the first bent portion and the portion of the first sub-voltage signal line other than the conductive portion; and / or, Along the first direction, a distance between the conductive portion and the second bent portion is equal to a distance between a portion of the second data line other than the second bent portion and a portion of the first sub-voltage signal line other than the conductive portion.

7. The display substrate according to claim 3 or 4, wherein: In the first data line and the second data line adjacent to a column of sub-pixels and located on both sides of the column of sub-pixels along the first direction, a first connecting portion is arranged between the first bending portion and the second bending portion, and the first connecting portion is arranged in the same layer as the first sub-voltage signal line.

8. The display substrate according to claim 7, further comprising: an anode layer, disposed on a side of the first connecting portion away from the substrate; A first light emission control transistor is disposed on the substrate, wherein the first light emission control transistor includes an active layer, and the active layer includes a first conductor portion; the first connecting portion is electrically connected to the first conductor portion and the anode layer.

9. The display substrate according to claim 8, further comprising: A second connection portion, wherein the second connection portion is arranged between the active layer of the first light emitting control transistor and the first connection portion, and is arranged in the same layer as the second sub-voltage signal line; the second connection portion is electrically connected to the first conductor portion and the first connection portion.

10. The display substrate according to claim 8 or 9, wherein: Along the second direction, a size of the first connecting portion is greater than or equal to a length of the first curved portion and the second curved portion.

11. The display substrate according to claim 9, wherein: An orthographic projection of the first connection portion on the substrate and an orthographic projection of the second connection portion on the substrate have an overlapping area.

12. The display substrate according to claim 4, wherein: The first via hole is located between two adjacent rows of sub-pixels and between two adjacent columns of sub-pixels.

13. The display substrate according to claim 8, wherein: When the display substrate further includes the first connection portion, along the second direction, maximum sizes of two portions of the first connection portion located on both sides of a line connecting centers of two adjacent first via holes of the first connection portion are equal.

14. The display substrate according to claim 3, wherein: Each sub-pixel consists of: a second light emission control transistor, wherein the second sub-voltage signal line is electrically connected to an active layer of the second light emission control transistor; The capacitor comprises a first plate located on the side of the film layer where the second sub-voltage signal line is located close to the substrate, and a second plate located on the side of the first plate close to the substrate; the second sub-voltage signal line is also electrically connected to the first plate.

15. The display substrate according to claim 14, wherein: The first plates of the capacitors of the multiple sub-pixels in each row of sub-pixels are electrically connected to each other to form a plurality of auxiliary conductive strips extending along the first direction, and the plurality of auxiliary conductive strips are staggered with the orthographic projections of the plurality of first sub-voltage signal lines on the substrate to form a grid structure.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A method for preparing a display substrate, comprising: providing a substrate; A pixel driving circuit for forming a plurality of sub-pixels arranged in an array on the substrate; Each column of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels, and the first sub-pixels and the second sub-pixels are alternately arranged along the second direction; forming a plurality of second sub-voltage signal lines on a side of the pixel driving circuit of the plurality of sub-pixels away from the substrate, wherein the positive projection of each second sub-voltage signal line on the substrate is located between two adjacent columns of sub-pixels; A plurality of first data lines, a plurality of second data lines and a plurality of first sub-voltage signal lines are formed on a side of the plurality of second sub-voltage signal lines away from the substrate; one first sub-voltage signal line and one second sub-voltage signal line constitute a first voltage signal line, and each first voltage signal line is electrically connected to a pixel driving circuit of at least one column of sub-pixels; The positive projection of each first voltage signal line on the substrate is located between the positive projections of the two adjacent columns of sub-pixels on the substrate; the first data lines and the second data lines are alternately arranged along the first direction; along the first direction, a column of sub-pixels is adjacent to a first data line and a second data line, and the first data line and the second data line are respectively located on both sides of the column of sub-pixels, the pixel driving circuit of each first sub-pixel in the column of sub-pixels is electrically connected to the first data line adjacent to it, and the pixel driving circuit of each second sub-pixel in the column of sub-pixels is electrically connected to the second data line adjacent to it.

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