A power distribution network fault testing device and a multi-point synchronous output correction method

Abstract

The application provides a power distribution network fault testing device and a correction method of multi-point synchronous output. The power distribution network fault testing device comprises a control unit, a synchronous input / output unit and a fault testing unit. The control unit and the fault testing unit are respectively connected in communication, the control unit provides input data to the fault testing unit, and one fault testing unit is specified as a main system. Each synchronous input / output unit is connected to each other, each synchronous input / output unit is connected to one fault testing unit, the fault testing unit synchronously outputs the processed input data, the main system sends the synchronous output signal to all synchronous input / output units, and each synchronous input / output unit sends the synchronous output signal to the fault testing unit. The output precision is high, the cost is low, the operation is convenient, the openness is good, and the application is beneficial to popularization and application.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power detection, in particular to a power distribution network fault testing device and a multi-point synchronous output correction method. BACKGROUND

[0002] At present, in response to the integration and development trend of energy revolution and digital revolution, State Grid Corporation of China adopts a "one body and four wings" development layout, and realizes the goals of "four digitizations" of equipment, operation, management and collaboration, so as to comprehensively promote the digital transformation of equipment management. With the development of distributed power and the increasing requirements for power supply quality and economic efficiency of power grid operation under the new situation, the distribution technology is facing new opportunities and challenges, so that "smart distribution network" and "active distribution network" emerge as the times require and become the focus of power technology research and the focus of popularization and application. Since the distribution network equipment is extensive, covers a wide range, is closely related to people's production and life, and develops rapidly with a short upgrading and reconstruction cycle, therefore, the reliability, safety and stability of the distribution network are very important. The distribution network lines are various, with the characteristics of many points, long lines and wide range, and the principles and collaborative chain actions of fault discovery, positioning, removal and recovery of power supply under different types of lines are different. In order to ensure the correctness and reliability of feeder automation of each type of distribution network system, an effective detection means is needed to truly simulate the entire process from normal operation to fault occurrence to fault removal of the actual line.

[0003] At present, the common means for detecting the feeder automation function of the entire distribution network system is generally two kinds: the first kind is to build a true distribution network test field, but this means is too high in cost and cannot be flexibly adapted to different scenarios; the second kind is to model a simulation system, and to synchronize the outputs of each test instrument through multi-point communication or GPS, but this means has the shortcomings of large communication delay error, test site limited by satellite signal, and although the starting point is synchronized, the error will increase with the increase of output time when multi-point synchronous output. SUMMARY

[0004] The purpose of the present application is to provide a low-cost high-precision distribution network fault testing device and a multi-point synchronous output correction method.

[0005] In order to solve the above problems, the application provides a power distribution network fault testing device, which comprises a control unit, at least two synchronous input and output units and at least two fault testing units, the control unit is in communication connection with all the fault testing units respectively and is used for providing input data to all the fault testing units, and a fault testing unit is specified as a main system, each of the synchronous input and output units is connected with each other, and each of the synchronous input and output units is connected with a fault testing unit, so that the synchronous input and output units and the fault testing units are connected one by one, the fault testing unit is used for synchronously outputting the processed input data according to the synchronous output signal, the main system is used for sending a synchronous output signal to the synchronous input and output unit connected with the main system, the synchronous input and output unit connected with the main system sends the synchronous output signal to all the synchronous input and output units, and each of the synchronous input and output units is used for sending the synchronous output signal to all the fault testing units.

[0006] Optionally, the input data comprises steady-state data or transient-state data.

[0007] Optionally, the power distribution network fault testing device comprises a first synchronous input and output unit, a second synchronous input and output unit, a third synchronous input and output unit, a first fault testing unit, a second fault testing unit and a third fault testing unit,

[0008] The control unit is connected with the first fault testing unit, the second fault testing unit and the third fault testing unit respectively, provides the input data to the first fault testing unit, the second fault testing unit and the third fault testing unit respectively, and specifies the first fault testing unit as the main system, the first synchronous input and output unit, the second synchronous input and output unit and the third synchronous input and output unit are connected with each other, the first synchronous input and output unit is connected with the first fault testing unit, the second synchronous input and output unit is connected with the second fault testing unit, and the third synchronous input and output unit is connected with the third fault testing unit;

[0009] The first fault test unit as the main system sends a synchronous output signal to the first synchronous input and output unit, the first synchronous input and output unit sends the synchronous output signal to the second synchronous input and output unit and the third synchronous input and output unit respectively, the first synchronous input and output unit sends the synchronous output signal to the first fault test unit, the second synchronous input and output unit sends the synchronous output signal to the second fault test unit, the third synchronous input and output unit sends the synchronous output signal to the third fault test unit, the first fault test unit, the second fault test unit and the third fault test unit are used to convert the input data into analog quantity, and an external interrupt request is generated according to the synchronous output signal, and the analog quantity is output synchronously according to the external interrupt request.

[0010] Optionally, each of the synchronous input and output units comprises a synchronous input part and a synchronous output part connected with each other, each of the synchronous output parts is connected with all the synchronous input parts, and each of the synchronous input parts and the synchronous output part is connected with one of the fault test units.

[0011] Optionally, each of the fault test units comprises a control processing part, each of the synchronous input parts and the synchronous output part is connected with one of the control processing parts, and the control processing part is further connected with the control unit, each of the control processing parts receives the synchronous output signal at the same time, generates an external interrupt request according to the synchronous output signal, and determines the output of analog quantity data according to the external interrupt request.

[0012] Further, the control processing part comprises a central processing module, a crystal oscillator, a storage module and a timer, the crystal oscillator is used to generate a clock signal frequency necessary for the central processing module to execute instructions, the central processing module is used to read instructions, decode instructions and execute instructions, and is used to process data in software in the fault test unit, the storage module is used to save the analog quantity before synchronous output, and the central processing module of the main system is further used to send the synchronous output signal.

[0013] In another aspect, the application further provides a correction method for multi-point synchronous output of a power distribution network fault test device, and the method comprises the following steps of:

[0014] S1: the control unit provides input data to all the fault test units, and simultaneously specifies one of the fault test units as a main system, the main system sends a synchronous output signal to each of the fault test units through all the synchronous input and output units;

[0015] S2: All the fault test units simultaneously receive the synchronization output signal and simultaneously output the processed input data synchronously according to the synchronization output signal. Each fault test unit has a crystal oscillator frequency error when synchronously outputting the processed input data; and

[0016] S3: Perform dynamic error correction on the crystal oscillator frequency error.

[0017] Optionally, step S1 includes:

[0018] The control unit provides input data to all the fault test units, the central processing module of each fault test unit processes the input data to obtain analog quantities, and the storage module of the control processing unit of each fault test unit stores the analog quantities.

[0019] After the control unit detects that each of the fault test units has completed the preparatory work such as processing and storing the input data, it designates one of the fault test units as the main system.

[0020] The fault test unit sends the synchronous output signal to the synchronous output section of the synchronous input / output unit connected to it;

[0021] The synchronous output section of the synchronous input / output unit connected to the main system sends the synchronous output signal to the synchronous input section of all the synchronous input / output units, and all the synchronous input sections send the synchronous output signal to the central processing module of the fault test unit connected to them.

[0022] Furthermore, step S2 includes:

[0023] Each of the central processing modules simultaneously receives the synchronization output signal and generates an external interrupt request based on the synchronization output signal. After each central processing module finds the external interrupt request, it directly switches to the interrupt handling entry address of the analog output, retrieves the analog quantity from the storage module, and outputs it synchronously.

[0024] Furthermore, step S3 includes:

[0025] Establish a correction model for crystal oscillator frequency error; and

[0026] The crystal oscillator frequency error is corrected according to the correction model.

[0027] Furthermore, the correction model for crystal oscillator frequency error includes:

[0028] Determine the number of output points per cycle and the number of timer cycles for the steady-state data converted to analog signals; and

[0029] Calculate the correction period of the timer.

[0030] Furthermore, when the control unit provides steady-state data to all the fault test units,

[0031] The number of output points per wave cycle satisfies the formula: A1=G*P1 / f;

[0032] The timer correction period A2 is: A2=G*P1 / f-1+(Δp*(G*P1 / f-1)+Δt) / P1;

[0033] Where G is the peripheral clock frequency of the timer, f is the AC frequency of the analog quantity, A1 is the number of timer cycles, n is a positive integer, Δp is the error value of the cycle output counting point, Δt is the timer error value, t is the timer timing, and A1, P1 and f are all integers, and P1 is an integer.

[0034] Furthermore, the number of output points per cycle is an integer between 512 and 2028.

[0035] Furthermore, when the control unit provides steady-state data to all the fault test units, correcting the crystal oscillator frequency error according to the correction model includes:

[0036] When the number of output points per cycle is greater than or equal to the first preset value, the number of cycles of the timer is corrected according to the correction period of the timer. At the same time, when the central processing module receives the synchronization output signal and processes the external interrupt request each time, it resets the cycle output count point error value and the timer error value to 0, so that each cycle is compensated and corrected.

[0037] When the number of output points per cycle is less than the first preset value, only the central processing module resets the cycle output count point error value and the timer error value to 0 each time it receives the synchronization output signal and processes the external interrupt request, so as to compensate and correct each cycle.

[0038] Furthermore, when the control unit provides transient data to all the fault test units,

[0039] The number of output points per cycle, P1', is: P1' = round(S / H);

[0040] The correction period A2' of the timer per second is: A2'=G / S-1+(Δs*(G / S-1)+Δt) / S;

[0041] Where S is the sampling frequency of the inversion output file, n is a positive integer, Δt is the timer error value, t is the timer timing, Δs is the sampling frequency error, and P1' is an integer.

[0042] Furthermore, when the control unit provides transient data to all the fault test units, correcting the crystal oscillator frequency error according to the correction model includes:

[0043] When the sampling frequency of the transient data inversion output file is greater than or equal to the second preset value, the number of timer cycles is compensated and corrected according to the correction period. Simultaneously, when the central processing module receives the synchronization output signal and processes an external interrupt request each time, it resets the sampling frequency error and the timer error value to 0, thus compensating and correcting for each second of data output.

[0044] When the sampling frequency of the inversion output file is less than the second preset value, the central processing module resets the sampling frequency error and the timer error value to 0 only when it receives the synchronization output signal and processes the external interrupt request, so that compensation and correction are performed every second of data output.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] This invention provides a power distribution network fault testing device and a method for correcting multi-point synchronous output. The power distribution network fault testing device includes a control unit, at least two synchronous input / output units, and at least two fault testing units. The control unit is communicatively connected to all the fault testing units and is used to provide input data to all the fault testing units. One of the fault testing units is designated as the master system. Each synchronous input / output unit is interconnected, and each synchronous input / output unit is connected to one fault testing unit, such that the synchronous input / output units and the fault testing units are connected in a one-to-one correspondence. The fault testing units are used to perform synchronous output correction on the processed input data according to the synchronous output signal. The main system sends a synchronous output signal to the synchronous input / output unit connected to it. The synchronous input / output unit connected to the main system sends the synchronous output signal to all synchronous input / output units. Each synchronous input / output unit sends the synchronous output signal to all fault test units. It can synchronously simulate the 10kV high voltage and primary current signals of each node in different power distribution networks. It has high output accuracy, large adjustable range, high stability, low cost, convenient operation, and strong load-carrying capacity. It can reproduce the real situation of the entire power distribution system to a greater extent. It has good openness and can support the relevant technical standards and specifications of the power industry and State Grid Corporation, which is conducive to its promotion and application. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the structure of a power distribution network fault testing device according to an embodiment of the present invention;

[0048] Figure 2 This is a flowchart illustrating a correction method for multi-point synchronous output of a power distribution network fault testing device according to an embodiment of the present invention.

[0049] Explanation of reference numerals in the attached figures:

[0050] 10-Control unit; 21-First synchronization input unit; 22-First synchronization output unit; 23-Second synchronization input unit; 24-Second synchronization output unit; 25-Third synchronization input unit; 26-Third synchronization output unit; 31-First fault test unit; 311-First control processing unit; 32-Second fault test unit; 321-Second control processing unit; 33-Third fault test unit; 331-Third control processing unit. Detailed Implementation

[0051] The following will provide a more detailed description of a power distribution network fault testing device and a multi-point synchronous output correction method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0052] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0053] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0054] Figure 1 This is a schematic diagram of the structure of a power distribution network fault testing device provided in this embodiment. Figure 1 As shown, this embodiment provides a power distribution network fault testing device, including a control unit 10, at least two synchronous input / output units, and at least two fault testing units.

[0055] The control unit 10 is communicatively connected to all the fault test units respectively. Furthermore, the control unit 10 communicates with all the fault test units via Ethernet and is used to provide input data to all the fault test units, while also designating one of the fault test units as the master system. The input data includes steady-state data or transient data.

[0056] Each of the synchronous input / output units is interconnected, and each synchronous input / output unit is connected to one of the fault test units, so that the synchronous input / output units and the fault test units are connected in a one-to-one correspondence. The fault test unit is used to independently simulate the electrical characteristics of a 10kV primary side bay according to the input data and output it. The main system is used to send synchronous output signals to the synchronous input / output units connected to it. The synchronous input / output units connected to the main system send the synchronous output signals to all the synchronous input / output units. Each synchronous input / output unit is used to send the synchronous output signals to all the fault test units.

[0057] In this embodiment, the fault testing unit is used to synchronously output the processed input data according to the synchronous output signal. The power distribution network fault testing device includes three synchronous input / output units and three fault testing units. The three synchronous input / output units are a first synchronous input / output unit, a second synchronous input / output unit, and a third synchronous input / output unit. The three fault testing units are a first fault testing unit 31, a second fault testing unit 32, and a third fault testing unit 33. The control unit 10 is connected to the first fault testing unit 31, the second fault testing unit 32, and the third fault testing unit 33 respectively, and provides the input data to the first fault testing unit 31, the second fault testing unit 32, and the third fault testing unit 33 respectively, and designates the first fault testing unit 31 as the master system.

[0058] The first, second, and third synchronous input / output units are interconnected. The first synchronous input / output unit is connected to the first fault test unit 31, the second synchronous input / output unit is connected to the second fault test unit 32, and the third synchronous input / output unit is connected to the third fault test unit 33. The first fault test unit 31, acting as the main system, sends a synchronous output signal to the first synchronous input / output unit. The first synchronous input / output unit sends the synchronous output signal to the second and third synchronous input / output units respectively. The first synchronous input / output unit sends the synchronous output signal to the first fault test unit 31, the second synchronous input / output unit sends the synchronous output signal to the second fault test unit 32, and the third synchronous input / output unit sends the synchronous output signal to the third fault test unit 33. The first, second, and third fault test units 31, 32, and 33 are all used to convert the input data into analog quantities, generate external interrupt requests based on the synchronous output signals, and synchronously output the analog quantities based on the external interrupt requests.

[0059] Each of the synchronous input / output units includes a synchronous input section and a synchronous output section that are interconnected. Each of the synchronous output sections is interconnected with all of the synchronous input sections. Each of the synchronous input sections and synchronous output sections can be simultaneously connected to one of the fault test units.

[0060] In this embodiment, the first synchronous input / output unit includes a first synchronous input section 21 and a first synchronous output section 22 interconnected with each other; the second synchronous input / output unit includes a second synchronous input section 23 and a second synchronous output section 24 interconnected with each other; and the third synchronous input / output unit includes a third synchronous input section 25 and a third synchronous output section 26 interconnected with each other. The first synchronous output section 22 is interconnected with the first synchronous input section 21, the second synchronous input section 23, and the third synchronous input section 25, respectively. The first synchronous input section 21 and the first synchronous output section 22 are simultaneously connected to the first fault test unit 31; the second synchronous input section 23 and the second synchronous output section 24 are simultaneously connected to the second fault test unit 32; and the third synchronous input section 25 and the third synchronous output section 26 are simultaneously connected to the third fault test unit 33.

[0061] The first fault test unit 31, acting as the main system, sends a synchronization output signal to the first synchronization output unit 22. The first synchronization output unit 22 sends the synchronization output signal to the first synchronization input unit 21, the second synchronization input unit 23, and the third synchronization input unit 25, respectively. The first synchronization input unit 21 sends the synchronization output signal to the first fault test unit 31, the second synchronization input unit 23 sends the synchronization output signal to the second fault test unit 32, and the third synchronization input unit 25 sends the synchronization output signal to the third fault test unit 33.

[0062] The control processing unit, as the central hub of the fault testing unit, receives the input data and converts it into an analog quantity, receives and sends the synchronization output signal, and determines the output of the analog quantity based on the synchronization output signal. In this embodiment, control processing unit 311 serves as the central hub of the first fault testing unit 31, control processing unit 321 serves as the central hub of the second fault testing unit 32, and control processing unit 331 serves as the central hub of the third fault testing unit 33.

[0063] Each fault test unit includes a control processing unit. Each synchronization input and synchronization output unit is simultaneously connected to one of these control processing units. The control processing unit is also connected to the control unit. Each control processing unit simultaneously receives the synchronization output signal and generates an external interrupt request based on the synchronization output signal. It then determines the output of analog data based on the external interrupt request. Each control processing unit configures its interrupt priority level and sets the synchronization output signal to the highest interrupt priority. This ensures that when the control processing unit receives the synchronization output signal, it generates an external interrupt request for synchronization output, directly jumps to the interrupt handling entry address for analog output based on the external interrupt request, and performs synchronous analog output. Because the synchronization output signal is set to the highest interrupt priority, the output of each fault test unit only experiences an interrupt response time of 2 to 3 machine clock cycles. Since the system clock frequency of the fault test unit is above 100 MHz, the synchronization startup time error is on the order of nanoseconds.

[0064] The control processing unit includes a central processing module (CPU), a crystal oscillator, a storage module, and a timer. The crystal oscillator generates the clock signal frequency necessary for the CPU to execute instructions. The CPU, for example, is responsible for reading instructions, decoding and executing instructions, and processing data in the software of the fault test unit. In this embodiment, the CPU converts the input data into analog signals, receives the synchronization output signal, generates an external interrupt request based on the synchronization output signal, and then, upon detecting the external interrupt request, directly jumps to the interrupt handling entry address for analog data output and performs synchronous output. The storage module is used to save the analog signals before synchronous output. The timer ensures the synchronous output and correctness of the analog signals. The CPU of the main system is also used to issue the synchronization output signal.

[0065] Figure 2 This is a flowchart illustrating the correction method for the multi-point synchronous output of the distribution network fault testing device provided in this embodiment. Figure 2 As shown, this embodiment also provides a method for correcting the multi-point synchronous output of a power distribution network fault testing device, including the following steps:

[0066] S1: The control unit provides input data to all fault test units and designates one of the fault test units as the master system. The master system sends synchronous output signals to each of the fault test units through all synchronous input / output units.

[0067] S2: All the fault test units simultaneously receive the synchronization output signal and simultaneously output the processed input data synchronously according to the synchronization output signal. Each fault test unit has a crystal oscillator frequency error when synchronously outputting the processed input data; and

[0068] S3: Perform dynamic error correction on the crystal oscillator frequency error.

[0069] First, step S1 is executed. The control unit 10 provides input data to all fault test units and designates one of the fault test units as the master system. The master system sends a synchronization output signal to each of the fault test units through all the synchronization input / output units.

[0070] This step specifically includes:

[0071] First, the control unit 10 provides input data to all fault test units. The central processing module of each fault test unit processes the input data to obtain analog quantities, and the storage module of the control processing unit stores the analog quantities. The input data includes steady-state data or transient data.

[0072] Next, after the control unit 10 detects that each fault test unit has completed the preparatory work such as processing and storing the input data, it designates one of the fault test units as the master system. In this embodiment, the first fault test unit 31 is designated as the master system.

[0073] Next, the first fault test unit 31, which is the main system, sends the synchronous output signal to the synchronous output section of the synchronous input / output unit connected to it (for example, the first synchronous output section 22 of the first synchronous input / output unit).

[0074] Next, the synchronization output unit of the synchronization input / output unit connected to the main system sends the synchronization output signal to the synchronization input units of all the synchronization input / output units, and all the synchronization input units send the synchronization output signal to the central processing module of the fault test unit connected to them. In this embodiment, the first synchronization output unit 22 sends the synchronization output signal to the first synchronization input unit 21, the second synchronization input unit 23, and the third synchronization input unit 25, respectively. The first synchronization input unit 21 sends the synchronization output signal to the central processing module of the first fault test unit 31, the second synchronization input unit 23 sends the synchronization output signal to the central processing module of the second fault test unit 32, and the third synchronization input unit 25 sends the synchronization output signal to the central processing module of the third fault test unit 33.

[0075] Next, step S2 is executed, where all the fault test units simultaneously receive the synchronization output signal and simultaneously output the processed input data synchronously according to the synchronization output signal. Each fault test unit has a crystal oscillator frequency error when synchronously outputting the processed input data.

[0076] This step specifically includes:

[0077] The central processing module of each fault test unit simultaneously receives the synchronization output signal and generates an external interrupt request based on the synchronization output signal. After querying the external interrupt request, each central processing module directly jumps to the interrupt handling entry address of the analog output, retrieves the analog signal from the storage module, and outputs it synchronously. Since each crystal oscillator has a frequency error, without dynamic correction, after the synchronous output of each fault test unit is started, the output frequency and phase will gradually differ as the output time increases, resulting in a crystal oscillator frequency error.

[0078] Next, step S3 is executed to dynamically correct the crystal oscillator frequency error.

[0079] When the control unit 10 provides steady-state data to all fault test units, this step specifically includes: step S31, establishing a correction model for crystal oscillator frequency error.

[0080] First, determine the number of output points P1 per cycle of the steady-state data converted to analog signals and the number of timer cycles A1. The formula for calculating the number of timer cycles is as follows:

[0081] A1 = G*P1 / f;

[0082] Where G is the peripheral clock frequency of the timer, f is the AC frequency of the analog signal, and A1 is the number of timer cycles, which is an integer.

[0083] When outputting the analog quantity, it is necessary to select an appropriate number of output points P1 per cycle. The larger the number of output points P1 per cycle, the higher the output resolution, but the heavier the load on the central processing module. When A1 is an integer, the output error caused by each cycle can be avoided. Therefore, the number of output points P1 per cycle is an integer between 512 and 2028.

[0084] Next, the correction period of the timer is calculated. Specifically, in addition to the timer counting, when the cycle output count point P2 is an integer multiple of the number of cycle output points P1, one cycle of the analog quantity is completed. After the main system completes one cycle output, the main system again sends a synchronization output signal to each of the fault test units through all synchronization input / output units, and each of the fault test units simultaneously receives the synchronization output signal. At this time, there is an error between the system clock of the main system and the system clock of each of the fault test units, causing the cycle output count point M1 of each of the fault test units to be:

[0085] M1 = nP1 + Δp;

[0086] t = Δt;

[0087] Where P1 is the number of output points per cycle, n is a positive integer, Δp is the error value of the cycle output counting points, Δt is the timer error value, and t is the timer count.

[0088] The overall clock error K1 for each wave is:

[0089] K1 = Δp*(G*P1 / f-1) + Δt;

[0090] Where P1 is the number of output points per cycle, n is a positive integer, f is the AC frequency of the analog quantity, Δp is the error value of the cycle output counting points, and Δt is the timer error value.

[0091] The calculated timer correction period A2 is:

[0092] A2=G*P1 / f-1+(Δp*(G*P1 / f-1)+Δt) / P1.

[0093] Step S32: Correct the crystal oscillator frequency error according to the correction model.

[0094] First, when P1≥(Δp*(G*P 1 / f-1)+Δt), the number of cycles of the timer is compensated and corrected according to the formula of the timer correction period A2. At the same time, when the central processing module of the control processing unit receives the synchronization output signal and processes the external interrupt request each time, it resets the cycle output count point error value Δp and the timer error value Δt to 0, so that each cycle is compensated and corrected.

[0095] When P1 < (Δp*(G*P 1 / f-1)+Δt), the number of cycles of the timer does not need to be corrected. Only when the central processing module of the control processing unit receives the synchronous output signal and processes the external interrupt request, the cycle output count point error value Δp and the timer error value Δt are reassigned to 0, so as to maximize the synchronous output between each fault test unit and the main system.

[0096] When the control unit 10 provides transient data to all fault test units, this step specifically includes: step S31', establishing a correction model for crystal oscillator frequency error.

[0097] First, determine the number of output points P1' per cycle of the steady-state data converted to analog quantities and the number of timer cycles A1'. The transient data includes the inversion output file.

[0098] The number of output points P1' per wave is:

[0099] P1' = round(S / H);

[0100] A1' = round(G / S);

[0101] Where H is the waveform frequency of the inversion output file, S is the sampling frequency of the inversion output file, and G is the peripheral clock frequency of the timer.

[0102] Next, the correction period of the timer is calculated. Specifically, since P1' must be an integer, but S / H is not necessarily an integer, the correction period is modified to occur once per second to increase the number of compensation cycles of the timer. Therefore, after the main system completes one second of data output, the main system again sends a synchronization output signal to each of the fault test units through all the synchronization input / output units, and each fault test unit simultaneously receives the synchronization output signal. At this time, there is an error between the system clock of the main system and the system clock of each fault test unit, resulting in the following output data per second for each fault test unit:

[0103] M2 = nS + Δs;

[0104] t = Δt;

[0105] Where S is the sampling frequency of the inversion output file, n is a positive integer, Δt is the timer error value, t is the timer timing, and Δs is the sampling frequency error.

[0106] The correction period A2' of the timer per second is calculated as follows:

[0107] A2'=G / S-1+(Δs*(G / S-1)+Δt) / S.

[0108] Step S32': Correct the crystal oscillator frequency error according to the correction model.

[0109] First, when S≥(Δs*(G / S-1)+Δt), the number of cycles of the timer is compensated and corrected according to the formula of the correction period A2'. At the same time, when the central processing module of the control processing unit receives the synchronous output signal and processes the external interrupt request each time, the sampling frequency error Δs and the timer error value Δt are reset to 0, so that compensation and correction are performed every second of data output.

[0110] When S < (Δs*(G / S-1)+Δt), the central processing module of the control processing unit resets the sampling frequency error Δs and the timer error value Δt to 0 each time it receives the synchronous output signal and processes the external interrupt request, thereby maximizing the guarantee that each fault test unit can output synchronously with the main system.

[0111] When Δs is set to 0, since the data for each cycle of the transient data is different, setting Δs to 0 requires considering whether it is positive or negative, i.e., whether the actual output points shift forward or backward. Furthermore, the output of transient data often utilizes repeated output from the first cycle to perform steady-state output before the transient state. Therefore, setting Δs to 0 also requires determining whether it is a repeated output; if so, it simply requires returning to the starting position of the first cycle.

[0112] In summary, the present invention provides a power distribution network fault testing device and a multi-point synchronous output method. The power distribution network fault testing device can synchronously simulate the 10kV high voltage and primary current signals of each node in different power distribution networks. It has high output accuracy, large adjustable range, high stability, low cost, convenient operation, and strong load-carrying capacity. It can reproduce the real situation of the entire power distribution system to a greater extent. It has good openness and can support the relevant technical standards and specifications of the power industry and the State Grid Corporation, which is conducive to its widespread application.

[0113] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first," "second," etc., in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0114] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A power distribution network fault testing device, characterized in that, The system includes a control unit, at least two synchronous input / output units, and at least two fault test units. The control unit is communicatively connected to all the fault test units and is used to provide input data to all the fault test units. One of the fault test units is designated as the master system. Each synchronous input / output unit is interconnected, and each synchronous input / output unit is connected to one fault test unit, creating a one-to-one correspondence between the synchronous input / output units and the fault test units. The master system sends synchronous output signals to the synchronous input / output units connected to it. The synchronous input / output units connected to the master system send the synchronous output signals to all the synchronous input / output units. Each synchronous input / output unit sends the synchronous output signal to all the fault test units. The fault test units synchronously output the processed input data according to the synchronous output signals. The input data includes steady-state data or transient data, and when the control unit provides steady-state data to all the fault test units, it determines the number of output points per cycle of the steady-state data converted into analog quantities and the number of timer cycles, and calculates the correction period of the timer; Wherein, the number of output points per wave P1 and the number of timer cycles A1 satisfy the formula: A1=G*P1 / f; The correction period A2 of the timer is: A2=G*P1 / f -1+(Δp*(G* P1 / f -1)+Δt) / P1; Where G is the peripheral clock frequency of the timer, f is the AC frequency of the analog quantity, n is a positive integer, Δp is the error value of the cycle output counting point, Δt is the timer error value, t is the timer timing, and A1, P1 and f are all integers.

2. The power distribution network fault testing device as described in claim 1, characterized in that, The power distribution network fault testing device includes a first synchronous input / output unit, a second synchronous input / output unit, a third synchronous input / output unit, a first fault testing unit, a second fault testing unit, and a third fault testing unit. The control unit is connected to the first fault test unit, the second fault test unit, and the third fault test unit respectively, and provides the input data to the first fault test unit, the second fault test unit, and the third fault test unit respectively, and designates the first fault test unit as the master system. The first synchronous input / output unit, the second synchronous input / output unit, and the third synchronous input / output unit are interconnected, and the first synchronous input / output unit is connected to the first fault test unit, the second synchronous input / output unit is connected to the second fault test unit, and the third synchronous input / output unit is connected to the third fault test unit. In this system, the first fault test unit, acting as the main system, sends a synchronization output signal to the first synchronization input / output unit. The first synchronization input / output unit then sends the synchronization output signal to the second and third synchronization input / output units respectively. The first synchronization input / output unit sends the synchronization output signal to the first fault test unit, the second synchronization input / output unit sends the synchronization output signal to the second fault test unit, and the third synchronization input / output unit sends the synchronization output signal to the third fault test unit. The first, second, and third fault test units are all used to convert the input data into analog quantities, generate external interrupt requests based on the synchronization output signals, and synchronously output the analog quantities based on the external interrupt requests.

3. The power distribution network fault testing device as described in claim 1, characterized in that, Each of the synchronous input / output units includes a synchronous input section and a synchronous output section that are interconnected. Each of the synchronous output sections is interconnected with all of the synchronous input sections. Each of the synchronous input sections and synchronous output sections is simultaneously connected to one of the fault test units.

4. The power distribution network fault testing device as described in claim 1, characterized in that, Each of the fault test units includes a control processing unit. Each of the synchronous input units and synchronous output units is simultaneously connected to one of the control processing units. At the same time, the control processing unit is also connected to the control unit. Each of the control processing units simultaneously receives the synchronous output signal and generates an external interrupt request based on the synchronous output signal. Based on the external interrupt request, it determines the output of analog data.

5. The power distribution network fault testing device as described in claim 4, characterized in that, The control processing unit includes a central processing module, a crystal oscillator, a storage module, and a timer. The crystal oscillator is used to generate the clock signal frequency required for the central processing module to execute instructions. The central processing module is responsible for reading instructions, decoding and executing instructions, and processing data in the software of the fault test unit. The storage module is used to save the analog quantity before synchronous output. The central processing module of the main system is also used to issue the synchronous output signal.

6. A method for correcting the multi-point synchronous output of a distribution network fault testing device, employing the distribution network fault testing device as described in any one of claims 1 to 5, characterized in that, Includes the following steps: S1: The control unit provides input data to all fault test units and designates one of the fault test units as the master system. The master system sends a synchronous output signal to each of the fault test units through all synchronous input / output units. The input data includes steady-state data or transient data. S2: All the fault test units simultaneously receive the synchronization output signal and simultaneously output the processed input data synchronously according to the synchronization output signal. Each fault test unit has a crystal oscillator frequency error when synchronously outputting the processed input data; and S3: Determine the number of output points per cycle and the number of timer cycles for the steady-state data converted to analog quantities; Calculate the correction period of the timer; correct the crystal oscillator frequency error according to the correction model; Specifically, when the control unit provides steady-state data to all the fault test units, The number of output points P1 per cycle and the number of timer cycles A1 satisfy the formula: A1=G*P1 / f; The correction period A2 of the timer is: A2=G*P1 / f -1+(Δp*(G* P1 / f -1)+Δt) / P1; Where G is the peripheral clock frequency of the timer, f is the AC frequency of the analog quantity, n is a positive integer, Δp is the error value of the cycle output counting point, Δt is the timer error value, t is the timer timing, and A1, P1 and f are all integers.

7. The correction method for multi-point synchronous output of the power distribution network fault testing device as described in claim 6, characterized in that, Step S1 includes: The control unit provides input data to all the fault test units, the central processing module of each fault test unit processes the input data to obtain analog quantities, and the storage module of the control processing unit of each fault test unit stores the analog quantities. After the control unit detects that each of the fault test units has completed the processing and storage preparation of the input data, it designates one of the fault test units as the master system. The fault test unit sends the synchronous output signal to the synchronous output section of the synchronous input / output unit connected to it; The synchronous output section of the synchronous input / output unit connected to the main system sends the synchronous output signal to the synchronous input section of all the synchronous input / output units, and all the synchronous input sections send the synchronous output signal to the central processing module of the fault test unit connected to them.

8. The correction method for multi-point synchronous output of the power distribution network fault testing device as described in claim 7, characterized in that, Step S2 includes: Each of the central processing modules simultaneously receives the synchronization output signal and generates an external interrupt request based on the synchronization output signal. After each central processing module finds the external interrupt request, it directly switches to the interrupt handling entry address of the analog output, retrieves the analog quantity from the storage module, and outputs it synchronously.

9. The correction method for multi-point synchronous output of the power distribution network fault testing device as described in claim 7, characterized in that, The number of output points per cycle is an integer between 512 and 2028.

10. The correction method for multi-point synchronous output of the power distribution network fault testing device as described in claim 7, characterized in that, When the control unit provides steady-state data to all the fault test units, correcting the crystal oscillator frequency error according to the correction model includes: When the number of output points per cycle is greater than or equal to the first preset value, the number of cycles of the timer is corrected according to the correction period of the timer. At the same time, when the central processing module receives the synchronization output signal and processes the external interrupt request each time, it resets the cycle output count point error value and the timer error value to 0, so that each cycle is compensated and corrected. When the number of output points per cycle is less than the first preset value, only the central processing module resets the cycle output count point error value and the timer error value to 0 each time it receives the synchronization output signal and processes the external interrupt request, so as to compensate and correct each cycle.

11. The correction method for multi-point synchronous output of the power distribution network fault testing device as described in claim 7, characterized in that, When the control unit provides transient data to all the fault test units The number of output points per cycle, P1', is: P1' = round(S / H); The correction period A2' of the timer per second is: A2'=G / S-1+(Δs*(G / S-1)+Δt) / S; Where S is the sampling frequency of the inversion output file, n is a positive integer, Δt is the timer error value, t is the timer timing, Δs is the sampling frequency error, P1' is an integer, and H is the waveform frequency of the inversion output file.

12. The correction method for multi-point synchronous output of the power distribution network fault testing device as described in claim 11, characterized in that, When the control unit provides transient data to all the fault test units, correcting the crystal oscillator frequency error according to the correction model includes: When the sampling frequency of the transient data inversion output file is greater than or equal to the second preset value, the number of timer cycles is compensated and corrected according to the correction period. Simultaneously, when the central processing module receives the synchronization output signal and processes an external interrupt request each time, it resets the sampling frequency error and the timer error value to 0, thus compensating and correcting for each second of data output. When the sampling frequency of the inversion output file is less than the second preset value, the central processing module resets the sampling frequency error and the timer error value to 0 only when it receives the synchronization output signal and processes the external interrupt request, so that compensation and correction are performed every second of data output.

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