A locking control circuit

Abstract

The present invention relates to the field of MCU chip technology, and in particular to a latching control circuit. The present invention discloses a latching control circuit, which comprises a bleeder diode, a first delay resistor, a delay capacitor, a second delay resistor, and a MOS transistor to form a controllable delay circuit. During the MCU loading of a program, the output of a third AND gate is latched to prevent the MCU from erroneously sending a signal due to an unstable IO pin state during the loading of the program. The present invention also comprises an MCU, a first photoelectric switch, and a second photoelectric switch to form a control circuit. After the MCU completes program loading, the first photoelectric switch and the second photoelectric switch control the MOS transistor to conduct, unlocking the third AND gate F3, so that the MCU can promptly send a control signal after completing program loading. This solves the problem in the prior art that the MCU chip cannot promptly send a control signal after completing program loading, thereby improving the reliability and timeliness of the latching circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of MCU chips, and in particular to a locking control circuit. Background Art

[0002] A microcontroller unit (MCU), also known as a single-chip microcomputer or single-chip microcomputer, integrates a central processing unit (CPU), memory, counters, USB, A / D converters, and other interfaces, as well as driver circuits, onto a single chip. MCU chips are widely used in measurement and control systems, intelligent instruments, smart interfaces, distributed control systems, and other industrial fields.

[0003] After powering on, an MCU chip takes a while to load its program, which can range from a few milliseconds to several seconds. During this period, the MCU's IO pins are unstable and prone to erroneous signal transmission. To prevent critical output ports from erroneously transmitting signals during the MCU's program loading period, control circuits containing the MCU chip employ hardware lockout circuits to block the MCU's output ports.

[0004] Existing hardware latch circuits are constructed using RC circuits and AND gate circuits. Their latching principle is to block the output signal from the MCU's output port before the output voltage of the RC circuit reaches the AND gate circuit's input high threshold. Because errors exist in the RC parameters of the RC circuit and the AND gate circuit's high threshold in existing hardware latch circuits, a larger margin is generally set for the RC parameters to reduce these errors. However, during the time period corresponding to the RC parameter margin, the MCU cannot normally issue control instructions. Consequently, there is a problem where the MCU chip has completed the program loading task but still needs to wait for the RC circuit's output to reach the AND gate circuit's input high threshold before it can normally issue instructions, affecting the timeliness of the MCU. Summary of the Invention

[0005] The present invention provides a locking control circuit for solving the problem in the prior art that an MCU chip cannot send a control signal in time after a program is loaded.

[0006] The present invention provides a locking control circuit, comprising: a positive power supply, a negative power supply, a first filter capacitor, a second filter capacitor, a bleeder diode, a first delay resistor, a delay capacitor, a second delay resistor, a MOS transistor, a gate drive resistor, a bleeder resistor, a first photoelectric switch, a second photoelectric switch, a first AND gate, a second AND gate, a third AND gate, and an MCU chip;

[0007] The first end of the first filter capacitor, the first end of the discharge diode, and the first end of the first delay resistor are respectively connected to the positive power supply; the second end of the first filter capacitor is grounded;

[0008] The first end of the first delay resistor is connected to the first input end of the first AND gate;

[0009] The second end of the first delay resistor is respectively connected to the second input end of the first AND gate, the second end of the discharge diode, and the first end of the delay capacitor;

[0010] The second end of the delay capacitor is connected to the first end of the second delay resistor and the second end of the MOS transistor respectively;

[0011] The second end of the second delay resistor is connected to the third end of the MOS tube and the first end of the second filter capacitor respectively; the second end of the second delay resistor is grounded;

[0012] The first end of the MOS transistor is connected to the first end of the bleeder resistor and the first end of the gate drive resistor respectively; the third end of the MOS transistor is connected to the second end of the bleeder resistor respectively;

[0013] The second end of the gate driving resistor is connected to the first end of the first photoelectric switch; the second end of the first photoelectric switch is connected to the first end of the second photoelectric switch;

[0014] The second end of the second photoelectric switch and the second end of the second filter capacitor are respectively connected to the negative power supply;

[0015] The output end of the first AND gate is connected to the first input end of the second AND gate, the second input end of the second AND gate, and the first input end of the third AND gate respectively;

[0016] The third end and the fourth end of the first photoelectric switch, the third end and the fourth end of the second photoelectric switch, the output end of the second AND gate, and the second input end of the third AND gate are respectively connected to the MCU chip.

[0017] Optionally, the MOS transistor is a depletion-type MOS transistor; the first end of the MOS transistor is a gate, the second end of the MOS transistor is a drain, and the third end of the MOS transistor is a source.

[0018] Optionally, the first end of the discharge diode is a cathode, and the second end of the discharge diode is an anode.

[0019] Optionally, the first photoelectric switch includes a first photosensitive transistor group and a first light emitting diode;

[0020] The two ends of the first photosensitive transistor group are respectively a first end and a second end of the first photoelectric switch;

[0021] The first end and the second end of the first light emitting diode are the third end and the fourth end of the first photoelectric switch respectively.

[0022] Optionally, the second photoelectric switch includes a second photosensitive transistor group and a second light emitting diode;

[0023] Two ends of the second photosensitive transistor group are respectively a first end and a second end of the second photoelectric switch;

[0024] The first end and the second end of the second light emitting diode are the third end and the fourth end of the second photoelectric switch respectively.

[0025] Optionally, the first photosensitive transistor group consists of two MOS transistors connected in series.

[0026] Optionally, the second photosensitive transistor group consists of two MOS transistors connected in series.

[0027] Optionally, the resistance of the second delay resistor is three times or more than three times that of the first delay resistor.

[0028] Optionally, the resistance of the first delay resistor is 10 kΩ.

[0029] Optionally, a value range of the first delay resistor R1 is 1 kΩ to 50 kΩ.

[0030] It can be seen from the above technical solutions that the present invention has the following advantages:

[0031] This embodiment provides a latching control circuit. A controllable delay circuit is formed by a bleeder diode, a first delay resistor, a delay capacitor, a second delay resistor, and a MOS transistor. During the program loading period of the MCU, the output of the third AND gate is latched to prevent the IO pin from erroneously sending a signal due to an unstable state during the program loading period. Furthermore, a control circuit is formed by the MCU, a first photoelectric switch, and a second photoelectric switch. After the MCU completes program loading, the first and second photoelectric switches control the MOS transistor to conduct, thereby unlocking the third AND gate F3. This allows the MCU to promptly send a control signal after program loading is completed. This solves the problem in the prior art where the MCU chip cannot promptly send a control signal after program loading is completed, thereby improving the reliability and timeliness of the latching circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1A schematic structural diagram of a locking control circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The embodiment of the present invention provides a locking control circuit for solving the technical problem in the prior art that an MCU chip cannot send a control signal in time after loading a program.

[0035] In order to make the purpose, features, and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0036] See also Figure 1 , Figure 1 A schematic structural diagram of a locking control circuit provided by an embodiment of the present invention.

[0037] This embodiment provides a latching control circuit including: a positive power supply Vcc and a negative power supply Vdd; a first filter capacitor C1, a second filter capacitor C2, a bleeder diode D1, a first delay resistor R1, a delay capacitor C3, a second delay resistor R2, a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) tube Q1, a gate drive resistor R3, a bleeder resistor R4, a first photoelectric switch S1, a second photoelectric switch S2, a first AND gate F1, a second AND gate F2, a third AND gate F3, and an MCU chip.

[0038] The first end of the first filter capacitor C1, the first end of the discharge diode D1, and the first end of the first delay resistor R1 are respectively connected to the positive power supply Vcc; the second end of the first filter capacitor C1 is grounded;

[0039] A first end of the first delay resistor R1 is connected to a first input end of the first AND gate F1;

[0040] The second end of the first delay resistor R1 is respectively connected to the second input end of the first AND gate F1, the second end of the discharge diode D1, and the first end of the delay capacitor C3;

[0041] The second end of the delay capacitor C3 is connected to the first end of the second delay resistor R2 and the second end of the MOS tube respectively;

[0042] The second end of the second delay resistor R2 is connected to the third end of the MOS transistor Q1 and the first end of the second filter capacitor C2 respectively; the second end of the second delay resistor R2 is grounded;

[0043] The first end of the MOS transistor Q1 is connected to the first end of the bleeder resistor R4 and the first end of the gate drive resistor R3 respectively; the third end of the MOS transistor Q1 is connected to the second end of the bleeder resistor R4 respectively;

[0044] The second end of the gate drive resistor R3 is connected to the first end of the first photoelectric switch S1; the second end of the first photoelectric switch S1 is connected to the first end of the second photoelectric switch S2;

[0045] The second end of the second photoelectric switch S2 and the second end of the second filter capacitor C2 are respectively connected to the negative power supply Vdd;

[0046] The output end of the first AND gate F1 is connected to the first input end of the second AND gate F2, the second input end of the second AND gate F2, and the first input end of the third AND gate F3 respectively;

[0047] The third and fourth terminals of the first photoelectric switch S1 , the third and fourth terminals of the second photoelectric switch S2 , the output terminal of the second AND gate F2 , and the second input terminal of the third AND gate F3 are respectively connected to the MCU chip.

[0048] In a specific embodiment, the MOS transistor Q1 is a depletion-type MOS transistor Q1 , wherein the first terminal of the MOS transistor Q1 is a gate G, the second terminal is a drain D, and the third terminal is a source S.

[0049] It should be noted that due to manufacturing process reasons, the MOS tube Q1 has a parasitic diode inside. Figure 1 shown.

[0050] The working principle of the locking control circuit provided in this embodiment is:

[0051] Before the circuit is powered on, the positive power supply Vcc and the negative power supply Vdd are voltage-free, and the first filter capacitor C1, the second filter capacitor C2, and the delay capacitor C3 are voltage-free. Therefore, the first and second input terminals of the first AND gate F1 are at a low level, and the output terminal of the first AND gate F1 is at a low level. Since the output terminal of the first AND gate F1 is connected to the first and second input terminals of the second AND gate F2, and the first input terminal of the third AND gate F3, respectively, when the output terminal of the first AND gate F1 is at a low level, the output terminal of the second AND gate F2 and the first input terminal of the third AND gate F3 are both at a low level.

[0052] After the positive power supply Vcc and the negative power supply Vdd are powered on, the positive power supply Vcc supplies power to the first AND gate F1, the second AND gate F2, the third AND gate F3, and the MCU chip, causing the first input terminal of the first AND gate F1 to be high. Since the first and second photoelectric switches S1 and S2 are in the off state, and the gate of the MOS transistor Q1 is not subjected to control voltage, its drain and source terminals are in a conductive state. Therefore, the positive power supply Vcc can charge the delay capacitor C3 through the first delay resistor R1 and the drain and source terminals of the MOS transistor Q1. Since the initial voltage of the delay capacitor C3 during charging is 0V, the second input terminal of the first AND gate F1, which is connected to the first terminal of the delay capacitor C3, is low, causing the output of the first AND gate F1 to be low. The output end of the first AND gate F1 is respectively connected to the first input end and the second input end of the second AND gate F2, and the first input end of the third AND gate F3. When the output of the first AND gate F1 is low, the second AND gate F2 and the third AND gate F3 both output low levels, so that the MCU chip connected to the second input end of the third AND gate F3 cannot output a signal, thereby achieving the purpose of locking the MCU chip, thereby preventing the MCU chip from outputting uncontrollable control signals during program loading after the positive power supply Vcc and the negative power supply Vdd are powered on.

[0053] It should be noted that when the first end of the third AND gate F3 is at a low level, no matter what signal the MCU chip inputs to the third AND gate F3, the output of the third AND gate F3 is a low level. Based on this, the MCU chip cannot output a control signal during program loading, thereby avoiding the MCU chip outputting uncontrollable control signals during program loading.

[0054] After the MCU determines that program loading is complete, it outputs control signals to the first and second photoelectric switches S1 and S2, turning them on. When the first and second photoelectric switches S1 and S2 are turned on, the gate G of the MOS transistor Q1 is connected to the negative power supply Vdd through the gate drive resistor R3. At this point, the drain and source of the MOS transistor Q1 enter a cutoff state. The initial circuit state, where the voltage is divided by the first delay resistor R1 and the delay capacitor C3, changes to a voltage divided by the first delay resistor R1, the delay capacitor C3, and the second delay resistor R2. The resistance of the second delay resistor R2 is more than three times that of the first delay resistor R1. Therefore, when the drain and source of the MOS transistor Q1 enter a cutoff state, the second delay resistor shares more voltage, causing the voltage at the second input of the first AND gate F1 to reach the high threshold of the first AND gate, thereby causing both inputs of the first AND gate F1 to be high and, consequently, the output of the first AND gate F1 to be high. Since the output end of the first AND gate F1 is respectively connected to the first input end and the second input end of the second AND gate F2, and the first input end of the third AND gate F3, when the output end of the first AND gate F1 is at a high level, the output end of the second AND gate F2 and the first input end of the third AND gate F3 are both at a high level.

[0055] The output of the second AND gate F2 is connected to the MCU chip. Based on this connection, the second AND gate F2 feeds back a high-level signal to the MCU chip. When the MCU chip receives the high-level signal fed back by the second AND gate F2, it indicates that the first input of the third AND gate F3 is at a high level, that is, the third AND gate F3 has been unlocked. At this time, the MCU chip can normally output the control signal through the second input of the third AND gate F3. Therefore, with the control circuit provided in this embodiment, the MCU chip no longer needs to wait for the capacitor to charge to meet the high threshold of the AND gate before issuing a command, as in the prior art.

[0056] In another preferred embodiment, when the MCU chip receives the high level signal sent by the second AND gate F2, it outputs a control signal to the second input terminal of the third AND gate F3, and outputs a signal through the third AND gate F3.

[0057] This embodiment provides a latching control circuit. A controllable delay circuit is formed by a bleeder diode D1, a first delay resistor R1, a delay capacitor C3, a second delay resistor R2, and a MOS transistor Q1. During program loading of the MCU, the output of the third AND gate F3 is latched to prevent erroneous signal transmission due to unstable IO pin status during program loading. Furthermore, a control circuit is formed by the MCU, a first photoelectric switch S1, and a second photoelectric switch S2. After the MCU completes program loading, the first photoelectric switch S1 and the second photoelectric switch S2 control the MOS transistor Q1 to conduct, thereby unlocking the third AND gate F3. This allows the MCU to promptly issue a control signal after program loading is completed. This solves the problem in the prior art where the MCU chip cannot promptly issue a control signal after program loading is completed.

[0058] Moreover, in this embodiment, a delay capacitor C3 is provided. Even if the MOS transistor Q1, the gate drive resistor R3, the bleeder resistor R4, the first photoelectric switch S1, and the second photoelectric switch S2 fail and cannot control the depletion-mode MOS transistor Q1 to be turned off, the first delay resistor R1 and the delay capacitor C3 can still be used for voltage division to achieve unlocking of the third AND gate F3, further improving the fault tolerance of the latching control circuit.

[0059] In a specific embodiment, the first end of the discharge diode D1 is a cathode, and the second end is an anode. The discharge diode D1 is used to provide a fast discharge channel for the delay capacitor C3 after the circuit loses power, so as to prepare for the next power-on of the MCU.

[0060] In a specific embodiment, the first photoelectric switch S1 includes a first photosensitive transistor group and a first light-emitting diode; the two ends of the first photosensitive transistor group are respectively the first end and the second end of the first photoelectric switch S1; the first end and the second end of the first light-emitting diode are respectively the third end and the fourth end of the first photoelectric switch S1.

[0061] In a specific embodiment, the first photosensitive transistor group consists of two MOS transistors connected in series.

[0062] It should be noted that, please refer to Figure 1 In the first photoelectric switch S1, the gates of the two MOS tubes are connected to each other, and the sources are connected to each other.

[0063] In a specific embodiment, the second photoelectric switch S2 includes a second photosensitive transistor group and a second light-emitting diode; the two ends of the second photosensitive transistor group are respectively the first end and the second end of the second photoelectric switch S2; the first end and the second end of the second light-emitting diode are respectively the third end and the fourth end of the second photoelectric switch S2.

[0064] In a specific embodiment, the second photosensitive transistor group consists of two MOS transistors connected in series.

[0065] It should be noted that, please refer to Figure 1 In the second photoelectric switch S2, the gates of the two MOS tubes are connected to each other, and the sources are connected to each other.

[0066] It should be noted that, in this embodiment, the first end of the first light-emitting diode is the anode and the second end is the cathode, the first end of the second light-emitting diode is the anode and the second end is the cathode. After the MCU chip completes loading the program, it controls the four ports connected to the first light-emitting diode and the second light-emitting diode to output corresponding electrical signals, turning on the first light-emitting diode and the second light-emitting diode.

[0067] It is understandable that only when the MCU chip outputs the correct electrical signal can the first light-emitting diode and the second light-emitting diode be turned on, and then the first phototransistor group and the second phototransistor group are turned on through the first light-emitting diode and the second light-emitting diode.

[0068] As an example, after the MCU chip determines that the program loading is complete, it controls the port connected to the anode end of the light-emitting diode to output a positive electrical signal, and controls the port connected to the cathode end of the light-emitting diode to output a negative electrical signal, so that the light-emitting diode is forward-conducted (that is, a forward conduction current is provided to the light-emitting diode), and then the phototransistor group is turned on through the light-emitting diode.

[0069] Therefore, this embodiment sets up two groups of photoelectric switches and sets the four output ports of the MCU to be connected to the two groups of photoelectric switches respectively, so as to avoid the MCU chip outputting uncontrollable signals to turn on the photoelectric switches in an unstable situation, unlocking the third AND gate circuit, and thus outputting erroneous signals, thereby further improving the reliability of the locking control circuit.

[0070] It should be noted that the number of photoelectric switches can be set to more than two groups, thereby further improving the reliability of the locking control circuit.

[0071] In a specific embodiment, the resistance of the second delay resistor is three times or more than three times that of the first delay resistor.

[0072] In a specific embodiment, the value of the first delay resistor R1 may be 10 kΩ.

[0073] In another specific embodiment, the value range of the first delay resistor R1 may be 1 kΩ to 50 kΩ.

[0074] In a specific embodiment, the value of the second delay resistor R2 may be 30 kΩ.

[0075] In another specific embodiment, the value of the second delay resistor R2 may range from 3 kΩ to 150 kΩ.

[0076] In a specific embodiment, the value of the delay capacitor C3 may be 47 uF.

[0077] In another specific embodiment, the value range of the delay capacitor C3 may be 1 uF-1000 uF.

[0078] In a specific embodiment, the delay capacitor C3 can be a ceramic capacitor or a tantalum capacitor with a relatively small leakage current.

[0079] In a specific embodiment, the second filter capacitor C2 is used to filter the negative power supply Vdd to provide a stable electrical signal for the MOS transistor Q1, thereby preventing the MOS transistor Q1 from being randomly turned on and off, thereby further improving the reliability and stability of the latching control circuit.

[0080] In a specific embodiment, the bleeder resistor R4 is used to stabilize the gate voltage of the MOS transistor Q1 to prevent the MOS transistor Q1 from switching on and off randomly, thereby further improving the reliability and stability of the latching control circuit.

[0081] In a specific embodiment, the first filter capacitor C1 is used to filter the positive power supply Vcc.

[0082] In summary, the locking control circuit provided by this embodiment has at least the following advantages:

[0083] (1) A controllable delay circuit is formed by the bleeder diode D1, the first delay resistor R1, the delay capacitor C3, the second delay resistor R2, and the MOS tube Q1. During the MCU loading program, the output of the third AND gate F3 is locked to avoid the situation where the IO pin state is unstable and the IO pin sends a signal incorrectly during the MCU loading program, thereby improving the reliability of the lock control circuit.

[0084] (2) The control circuit is composed of the MCU, the first photoelectric switch S1, and the second photoelectric switch S2. After the MCU chip completes program loading, the first photoelectric switch S1 and the second photoelectric switch S2 control the MOS tube Q1 to be turned on, unlocking the third AND gate F3, so that the MCU chip can send a control signal in time after completing program loading, thereby improving the timeliness of the MCU chip and enhancing the software coordination between the hardware locking circuit and the MCU chip.

[0085] (3) In this embodiment, a delay capacitor C3 is provided. Even if the MOS transistor Q1, the gate drive resistor R3, the bleeder resistor R4, the first photoelectric switch S1, and the second photoelectric switch S2 fail and cannot control the depletion-type MOS transistor Q1 to be turned off, the first delay resistor R1 and the delay capacitor C3 can still be used to divide the voltage to achieve unlocking of the third AND gate F3, further improving the fault tolerance of the latching control circuit.

[0086] (4) By setting the discharge diode D1, a fast discharge channel is provided for the delay capacitor C3 after the circuit is powered off, so as to prepare for the next power-on of the MCU chip.

[0087] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0088] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0089] Unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application.

[0090] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A locking control circuit, characterized in that: include: Positive power supply, negative power supply, first filter capacitor, second filter capacitor, bleeder diode, first delay resistor, delay capacitor, second delay resistor, MOS tube, gate drive resistor, bleeder resistor, first photoelectric switch, second photoelectric switch, first AND gate, second AND gate, third AND gate, MCU chip; The first end of the first filter capacitor, the first end of the discharge diode, and the first end of the first delay resistor are respectively connected to the positive power supply; the second end of the first filter capacitor is grounded; The first end of the first delay resistor is connected to the first input end of the first AND gate; The second end of the first delay resistor is respectively connected to the second input end of the first AND gate, the second end of the discharge diode, and the first end of the delay capacitor; The second end of the delay capacitor is connected to the first end of the second delay resistor and the second end of the MOS transistor; The second end of the second delay resistor is connected to the third end of the MOS tube and the first end of the second filter capacitor respectively; the second end of the second delay resistor is grounded; The first end of the MOS transistor is connected to the first end of the bleeder resistor and the first end of the gate drive resistor respectively; the third end of the MOS transistor is connected to the second end of the bleeder resistor respectively; The second end of the gate driving resistor is connected to the first end of the first photoelectric switch; the second end of the first photoelectric switch is connected to the first end of the second photoelectric switch; The second end of the second photoelectric switch and the second end of the second filter capacitor are respectively connected to the negative power supply; The output end of the first AND gate is connected to the first input end of the second AND gate, the second input end of the second AND gate, and the first input end of the third AND gate respectively; The third end and the fourth end of the first photoelectric switch, the third end and the fourth end of the second photoelectric switch, the output end of the second AND gate, and the second input end of the third AND gate are respectively connected to the MCU chip.

2. The circuit according to claim 1, wherein: The MOS tube is a depletion-type MOS tube; the first end of the MOS tube is a gate, the second end of the MOS tube is a drain, and the third end of the MOS tube is a source.

3. The circuit according to claim 1, wherein: The first end of the discharge diode is a cathode, and the second end of the discharge diode is an anode.

4. The circuit according to claim 1, wherein: The first photoelectric switch includes a first photosensitive transistor group and a first light emitting diode; The two ends of the first photosensitive transistor group are respectively a first end and a second end of the first photoelectric switch; The first end and the second end of the first light emitting diode are the third end and the fourth end of the first photoelectric switch respectively.

5. The circuit according to claim 1, wherein: The second photoelectric switch includes a second photosensitive transistor group and a second light emitting diode; Two ends of the second photosensitive transistor group are respectively a first end and a second end of the second photoelectric switch; The first end and the second end of the second light emitting diode are the third end and the fourth end of the second photoelectric switch respectively.

6. The circuit according to claim 4, characterized in that The first photosensitive transistor group consists of two MOS transistors connected in series.

7. The circuit according to claim 5, characterized in that The second photosensitive transistor group consists of two MOS transistors connected in series.

8. The circuit according to claim 1, wherein: The resistance of the second delay resistor is more than three times that of the first delay resistor.

9. The circuit according to claim 1, wherein: The resistance of the first delay resistor is 10 kΩ.

10. The circuit according to claim 1, wherein: The value range of the first delay resistor is 1 kΩ to 50 kΩ.

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