Manufacturing method of touch display device and touch display panel

Abstract

This invention proposes a method for manufacturing a touch display device and a touch display panel. The method for manufacturing the touch display panel includes: forming a first metal layer on a substrate, the first metal layer including a gate line and a gate; forming a first insulating layer on the first metal layer; forming a channel layer on the first insulating layer; forming a second metal layer including a data line, a source electrode, a drain electrode, and a touch signal line; forming a second insulating layer; forming two connection holes in the second insulating layer to expose the drain electrode and the touch signal line on the second metal layer, respectively; and forming a transparent conductive layer on the second insulating layer, the transparent conductive layer including a pixel electrode and a sub-touch electrode, which are electrically connected to the drain electrode and the touch signal line through the two connection holes, respectively. This allows for the formation of an embedded touch display device through a five-mask process.

Description

TECHNICAL FIELD

[0001] The present application relates to a touch display panel and a manufacturing method thereof. BACKGROUND

[0002] In-cell touch display device is to set touch electrodes which provide touch function in pixel structure, the touch electrodes will be connected to a circuit through the wire, the circuit can detect the change of the capacitance on the touch electrodes to determine whether the corresponding position on the touch display device is touched. Generally, when in touch detection, the touch electrodes are used to detect touch, and during display, the touch electrodes are applied with a common voltage as a common electrode. However, how to manufacture the display panel to make the pixel structure have the above-mentioned function and at the same time reduce the cost is the topic concerned by the technical personnel in this field. SUMMARY

[0003] The present application relates to a touch display panel and a manufacturing method thereof.

[0004] Embodiments of the present application provide a manufacturing method of a touch display panel, which can form an in-cell touch display device through a five-mask process. The method comprises: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer comprises a gate line and a gate electrode of a thin film transistor; forming a first insulating layer on the first metal layer, wherein the first insulating layer comprises a gate insulating layer of the thin film transistor; forming a second metal layer on the first insulating layer, wherein the second metal layer comprises a data line, a source electrode and a drain electrode of the thin film transistor, and a touch signal line; forming a second insulating layer on the second metal layer; forming a first connection hole and a second connection hole in the second insulating layer, the first connection hole exposes the drain electrode, and the second connection hole exposes the touch signal line; and forming a transparent conductive layer on the second insulating layer, wherein the transparent conductive layer comprises a pixel electrode and a touch electrode, the pixel electrode is electrically connected to the drain electrode through the first connection hole, and the touch electrode is electrically connected to the touch signal line through the second connection hole.

[0005] In some embodiments, the first metal layer comprises an electrode line, and at least a portion of the drain electrode overlaps a portion of the electrode line.

[0006] In another aspect, embodiments of the present disclosure provide a touch display device, which includes a touch display panel having a display region and a peripheral region. The touch display panel includes a substrate, a plurality of gate lines, a plurality of data lines, a plurality of touch signal lines, and a plurality of sub-pixels. The gate lines, the data lines, the touch signal lines, and the sub-pixels are disposed on the substrate. The sub-pixels are located in the display region, and each of the sub-pixels includes a thin film transistor, a pixel electrode, and a common electrode. The thin film transistor is disposed on the substrate, and includes a gate, a drain, and a source, wherein the gate is electrically connected to a gate line, and the source is electrically connected to a data line. The pixel electrode is electrically connected to the drain, and the common electrode is electrically connected to a touch signal line. The pixel electrode and the common electrode are formed by a same transparent conductive layer.

[0007] In some embodiments, during a display period of the touch display panel, the sub touch electrode of the sub-pixel receives a common voltage.

[0008] In some embodiments, the plurality of sub-pixels includes a first sub-pixel and a second sub-pixel, the plurality of touch signal lines includes a first touch signal line, and the first touch signal line is located between the first sub-pixel and the second sub-pixel.

[0009] In some embodiments, the common electrode of at least one of the first sub-pixel and the second sub-pixel has an opening, and the opening overlaps a portion of the first touch signal line.

[0010] In some embodiments, the plurality of gate lines includes a first gate line, the plurality of data lines includes a first data line and a second data line, the first sub-pixel and the second sub-pixel are electrically connected to the first gate line, the first sub-pixel and the second sub-pixel are electrically connected to the first data line and the second data line, respectively, and the first sub-pixel and the second sub-pixel are configured to display different colors.

[0011] In some embodiments, the plurality of gate lines includes a first gate line, the plurality of data lines includes a first data line and a second data line, the first sub-pixel and the second sub-pixel are electrically connected to the first gate line, the first sub-pixel and the second sub-pixel are electrically connected to the first data line and the second data line, respectively, and the first sub-pixel and the second sub-pixel are configured to display the same color.

[0012] In some embodiments, the plurality of gate lines includes a first gate line and a second gate line, the plurality of data lines includes a first data line and a second data line, the first sub-pixel and the second sub-pixel are electrically connected to the first gate line and the second gate line, respectively, and the first sub-pixel and the second sub-pixel are electrically connected to the first data line and the second data line, respectively.

[0013] In some embodiments, the touch display panel further includes an electrode line, and the electrode line overlaps at least a portion of the drain of the first sub-pixel and at least a portion of the drain of the second sub-pixel.

[0014] Compared with the prior art, the touch display device and the manufacturing method of the touch display panel have the following beneficial effects: the in-cell touch display device can be formed through the five-mask process, thereby reducing the manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to make the above features and advantages of the present application more apparent, the following embodiments are specifically described, and the detailed description is given below with reference to the accompanying drawings.

[0016] Figure 1A , Figure 2A , Figure 3A , Figure 4A With Figure 5A are side views of stages in the formation method of the touch panel according to the first embodiment.

[0017] Figure 1B , Figure 2B , Figure 3B , Figure 4B With Figure 5B are top views of stages in the formation method of the touch panel according to the first embodiment.

[0018] Figure 5C is a top view of a transparent conductive layer according to the first embodiment.

[0019] Figure 6 is a top view of an arrangement of a plurality of sub-pixels according to the first embodiment.

[0020] Figure 7 is a circuit schematic diagram of the touch display panel according to the first embodiment.

[0021] Figure 8 is a top view of a touch display panel according to the second embodiment.

[0022] Figure 9 is Figure 8 is a side view of a cross-sectional line.

[0023] Figure 10A , Figure 10B , Figure 10C , Figure 10D With Figure 10E are top views of layers of the touch panel according to the second embodiment.

[0024] Figure 11 is a top view of a transparent conductive layer according to a variation of the second embodiment.

[0025] Figure 12 is a top view of an arrangement of a plurality of sub-pixels according to the second embodiment.

[0026] Figure 13is a circuit diagram of a touch display panel according to the second embodiment.

[0027] Figure 14 is a top view of a touch display panel according to the third embodiment.

[0028] Figure 15 is Figure 14 side view of a cross-sectional line.

[0029] Figure 16A , Figure 16B , Figure 16C , Figure 16D and Figure 16E is a top view of layers of a touch panel according to the third embodiment.

[0030] Figure 17 is a top view of a transparent conductive layer according to a variation of the third embodiment.

[0031] Figure 18 is a top view of arrangement of a plurality of sub-pixels according to the third embodiment.

[0032] Figure 19 is a circuit diagram of a touch display panel according to the third embodiment.

[0033] Figure 20 is a schematic view of a display region and a peripheral region in a touch display device according to an embodiment.

[0034] Main figure mark explanation:

[0035] AA', BB'- cross-sectional line; INS-2 - second insulating layer; 102-D - drain; 104-1 - first connection hole; 104-2 - second connection hole; 108-2 - second connection hole; COM - common electrode; 106 - transparent conductive layer; PE - pixel electrode; Sx - touch signal line; M2 - second metal layer. DETAILED DESCRIPTION

[0036] As to "first", "second" and so on used herein, it is not particularly meant to mean order or sequence, and it is merely for distinguishing elements or operations described with the same technical terms.

[0037] First embodiment

[0038] Figure 1A , Figure 2A , Figure 3A , Figure 4A and Figure 5A is a side view of each stage in a method of forming a touch display panel according to the first embodiment of the present application, Figure 1B , Figure 2B , Figure 3B ,Figure 4B With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application. Figure 5B With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application.

[0039] With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application. Figure 1A With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application. Figure 1B , Figure 1A A side view along the cross-sectional line AA' is shown. First, a substrate SUB is provided, and then a first metal layer Ml is formed on the substrate SUB using a first mask process, the first metal layer Ml including a gate line G1, a gate 102-G of a thin film transistor, and an electrode line 104, wherein the gate line G1 is connected to the gate 102-G. The electrode line 104 and the gate line G1 both extend along a first direction X, but are electrically insulated from each other. Figure 1B With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application.

[0040] With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application. Figure 2A With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application. Figure 2B , Figure 2A A side view along the cross-sectional line AA' is shown. Next, a first insulating layer INS-1 (not shown in FIG. 1B) is formed, covering the first metal layer Ml and including a gate insulating layer 102-GI of the thin film transistor. Subsequently, a channel layer 102-C and a contact layer CL of the thin film transistor are formed on the gate insulating layer 102-GI. The contact layer CL can be, for example, an N-type semiconductor layer, but is not limited thereto. For example, the first insulating layer 102-GI, a semiconductor layer, and an N-type semiconductor layer can be sequentially formed on the first metal layer Ml, and then a second mask process is used to form the stacked semiconductor layer and N-type semiconductor layer into the channel layer 102-C and the contact layer CL which are block-shaped and stacked on each other, but is not limited thereto. Figure 2B The reference "102-C, CL" in FIG. 1B indicates that the channel layer 102-C and the contact layer CL are stacked, and the contact layer CL is disposed on the channel layer 102-C. Figure 2B Figure 2B With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application. With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application.

[0041] With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application. Figure 3A With reference to FIG. 1A, a top view of a touch display panel is shown according to a first embodiment of the present application. Figure 3B , Figure 3A A side view along the cross-sectional line AA' is shown. Next, a first insulating layer INS-1 (not shown in FIG. 1B) is formed, covering the first metal layer Ml and including a gate insulating layer 102-GI of the thin film transistor. Subsequently, a channel layer 102-C and a contact layer CL of the thin film transistor are formed on the gate insulating layer 102-GI. The contact layer CL can be, for example, an N-type semiconductor layer, but is not limited thereto. For example, the first insulating layer 102-GI, a semiconductor layer, and an N-type semiconductor layer can be sequentially formed on the first metal layer Ml, and then a second mask process is used to form the stacked semiconductor layer and N-type semiconductor layer into the channel layer 102-C and the contact layer CL which are block-shaped and stacked on each other, but is not limited thereto. Figure 3BSide views of section lines AA' and BB'. Next, a second metal layer M2 is formed using a third masking process. This second metal layer M2 includes data lines D1-D3, the source 102-S and drain 102-D of the thin-film transistor, and a touch signal line Sx. Data line D1 is connected to the source 102-S, and data line D1 and touch signal line Sx extend along the second direction Y. Furthermore, a portion of the drain 102-D covers a portion of the electrode line 104; that is, in the top view, a portion of the drain 102-D overlaps a portion of the electrode line 104. The method for forming the second metal layer M2 can be, for example, first forming a metal layer and then using a third mask process to form data lines D1 to D3, source 102-S and drain 102-D, and touch signal line Sx. In the above etching process, the contact layer CL not covered by source 102-S and drain 102-D will be removed, and the contact layer CL located below source 102-S and drain 102-D that has not been removed will form ohmic contact layer 102-OC.

[0042] Please refer to Figure 4A and Figure 4B , Figure 4A It is drawn along Figure 4B Side views of section lines AA' and BB'. Next, the second insulating layer INS-2 is formed (not shown in the diagram). Figure 4B The second insulating layer INS-2 covers the second metal layer M2, and a first connection hole 104-1 and a second connection hole 104-2 are formed in the second insulating layer INS-2 using a fourth mask process. The first connection hole 104-1 exposes a portion of the drain electrode 102-D, and the second connection hole 104-2 exposes a portion of the touch signal line Sx.

[0043] Please refer to Figure 5A and Figure 5B , Figure 5A It is drawn along Figure 5B Side views of the mid-section lines AA' and BB'. Next, a transparent conductive layer 106 is formed on the second insulating layer INS-2 using a fifth masking process. This transparent conductive layer 106 includes a pixel electrode PE and a common electrode COM. The pixel electrode PE is electrically connected to the drain electrode 102-D through a first connection hole 104-1, and the common electrode COM is electrically connected to the touch signal line Sx through a second connection hole 104-2. Please also refer to... Figure 5B and Figure 5C , Figure 5CThis is a top view of the transparent conductive layer 106. In some embodiments, the common electrode COM of the transparent conductive layer 106 further includes a first opening 108-1 and a second opening 108-2. The first opening 108-1 at least partially overlaps the touch signal line Sx, thereby reducing the loading of the touch signal line Sx and avoiding affecting the transmission of signals on the touch signal line Sx. The second opening 108-2 at least partially overlaps the gate line G1, thereby reducing the loading of the gate line G1 and avoiding affecting the transmission of signals on the gate line G1. Furthermore, the common electrode COM of the transparent conductive layer 106 does not overlap the channel layer 102-C located between the source 102-S and the drain 102-D, that is, the common electrode COM may also include a third opening 108-3, which at least partially overlaps the channel layer 102-C to avoid leakage current in the thin-film transistor.

[0044] In this embodiment, the pixel electrode PE includes a first strip electrode 110-1, and the common electrode COM includes a second strip electrode 110-2. The first strip electrode 110-1 and the second strip electrode 110-2 are arranged alternately, and there is a gap SL between adjacent first strip electrodes 110-1 and second strip electrodes 110-2. Since the pixel electrode PE and the common electrode COM are formed in the same transparent conductive layer 106, the touch display panel of the present invention can be fabricated using only five masking processes, thereby saving costs.

[0045] In the above description, forming a metal layer or transparent conductive layer using a mask process means first forming a metal film or transparent conductive film, then using a mask for exposure, followed by development and etching processes to pattern the metal film or transparent conductive film to form a metal layer or transparent conductive layer; forming a channel layer and contact layer using a mask process means first forming a semiconductor film and conductor film (e.g., an N-type semiconductor film), then using a mask for exposure, followed by development and etching processes to pattern the semiconductor film and conductor film to form a channel layer and contact layer; and forming a connection hole in an insulating layer using a mask process means using a mask for exposure, followed by development and etching processes to form a connection hole in the insulating layer.

[0046] exist Figure 5BIn this embodiment, three sub-pixels SP1, SP2, and SP3 are drawn along the first direction X. These three sub-pixels correspond to different colors (e.g., red, blue, and green) to form a pixel P. Each sub-pixel SP1, SP2, and SP3 includes a thin-film transistor 102, which includes the aforementioned gate 102-G, channel layer 102-C, ohmic contact layer 102-OC, drain 102-D, and source 102-S. The common electrode COM in each sub-pixel SP1, SP2, and SP3 serves as a sub-touch electrode, and these sub-touch electrodes are electrically connected to each other to form at least a portion of the touch electrode 112. In this embodiment, the common electrodes of multiple sub-pixels are electrically connected to each other to form the touch electrode 112. For example, the touch display panel has a resolution of 720x1440 and includes 18x32 = 576 touch electrodes 112, which are arranged in 18 columns and 32 rows. In this embodiment, each pixel P includes three sub-pixels SP1, SP2, and SP3 sequentially arranged in the first direction X. Therefore, each touch electrode 112 is formed by electrically connecting the common electrode COM of ((720x3) / 18)x(1440 / 32) = 120x45 = 5400 sub-pixels. During the display of the touch display panel, a common voltage is applied to the common electrode COM, and the voltage difference between the common electrode COM and the pixel electrode PE is used to control the rotation direction of the liquid crystal molecules. During touch sensing on the touch display panel, when a pen or finger touches the corresponding location, the capacitance on the touch electrode 112 changes. The change in capacitance can be calculated by sensing the touch signal on the touch signal line Sx, thereby determining whether the device has been touched and the location of the touch. Furthermore, the electrode line 104 extends along the first direction X and partially overlaps the drain 102-D of each sub-pixel SP1, SP2, SP3 in pixel P to form a storage capacitor. In this embodiment, the electrode line 104 overlaps at least a portion of the drain 102-D, such that a portion of the electrode line 104, at least a portion of the drain 102-D, and the first insulating layer INS-1 located between the electrode line 104 and the drain 102-D can form a storage capacitor. During the display period of the touch display panel, the electrode line 104 receives a common voltage. However, during touch sensing on the touch display panel, although the electrode line 104 receives touch signals, it is not used to determine whether the device has been touched and the location of the touch. For example, a touch display device includes a touch display panel and a touch sensing circuit. The touch display panel includes M touch signal lines Sx, and the touch sensing circuit includes N touch pads, where N is greater than M, that is, the number of touch pads is greater than the number of touch signal lines Sx.During the display period of the touch display panel, the touch sensing circuit outputs a common voltage from the touch pads. During the touch sensing period of the touch display panel, the touch sensing circuit outputs touch signals from the touch pads, and the touch pads sense changes in capacitance. M of the N touch pads of the touch sensing circuit are electrically connected to the M touch signal lines Sx of the touch sensing panel, while the remaining (NM) of the N touch pads of the touch sensing circuit are electrically connected to electrode lines 104. During the display period of the touch display panel, all N touch signal pads of the touch sensing circuit output a common voltage, meaning that the potentials of electrode line 104 and touch electrode 112 are the same. During the touch sensing period of the touch display panel, all N touch signal pads of the touch sensing circuit output touch signals, but the touch sensing circuit only determines whether the device is touched and the touch location based on the signals received by the M touch pads electrically connected to the M touch signal lines Sx, and not based on the signals received by the (NM) touch pads electrically connected to the electrode line 104. Further details can be found later. Figure 20 Explanation.

[0047] Figure 6 This is a top view illustrating the arrangement of multiple sub-pixels according to an embodiment. Figure 7 This is a circuit diagram of the touch display panel according to the first embodiment. Figure 6 for Figure 7 A top view of the touch display panel 600 with pixels 610 and 620. Please refer to... Figure 6 and Figure 7 The touch display panel 600 includes gate lines G1-G3, data lines D1-D6, multiple sub-pixels SP1, SP2, SP3, and multiple touch signal lines Sx. The multiple sub-pixels are arranged in multiple sub-pixel rows and multiple sub-pixel columns. Each sub-pixel row is electrically connected to a different gate line. All sub-pixels in each sub-pixel row are electrically connected to the same gate line and to different data lines. Similarly, each sub-pixel column is electrically connected to different data lines, and all sub-pixels within the same sub-pixel column are electrically connected to the same data line and to different gate lines. Figure 6Six sub-pixels are drawn along the first direction X. The three sub-pixels SP1, SP2, and SP3 on the left form pixel 610, and the three sub-pixels SP1, SP2, and SP3 on the right form pixel 620. A touch signal line Sx is set between pixel 610 and pixel 620. Pixels 610 and 620 are arranged sequentially along the first direction X. Sub-pixels SP1, SP2, and SP3 in each pixel 610 and pixel 620 are also arranged sequentially along the first direction X. Gate line G1 also extends along the first direction X (that is, the length direction of gate line G1 is parallel to the first direction X). Each data line D1 to D6 and each touch signal line Sx extend along the second direction Y (that is, the length direction of each data line D1 to D6 and each touch signal line Sx is parallel to the second direction Y). Electrode line 104 extends along the first direction X (that is, the length direction of electrode line 104 is parallel to the first direction X) and overlaps at least a portion of the drain 102-D of sub-pixels SP1, SP2, and SP3 in each pixel 610 and pixel 620. In this embodiment, sub-pixels SP1, SP2, and SP3 in each pixel P are used to display different colors. For example, sub-pixels SP1, SP2, and SP3 are red, green, and red sub-pixels, respectively, but this is not a limitation. Therefore, the sub-pixels in each pixel column are used to display the same color, and any two adjacent pixel columns are used to display different colors. In summary, the multiple sub-pixels of the touch display panel include a first sub-pixel (e.g., sub-pixel SP3 of pixel 610) and a second sub-pixel (e.g., sub-pixel SP1 of pixel 620). The multiple touch signal lines of the touch display panel include a first touch signal line (e.g., touch signal line Sx located between sub-pixel SP3 of pixel 610 and sub-pixel SP1 of pixel 620), and the first touch signal line is located between the first sub-pixel and the second sub-pixel. The touch display panel includes multiple gate lines, including a first gate line (e.g., gate line G1), and multiple data lines, including a first data line (e.g., data line D3) and a second data line (e.g., data line D4). A first sub-pixel and a second sub-pixel are both electrically connected to the first gate line. The first sub-pixel and the second sub-pixel are also electrically connected to the first data line and the second data line, respectively, and are used to display different colors. Furthermore, at least one of the first sub-pixel and the second sub-pixel has a common electrode with a first opening 108-1, which overlaps with a portion of the first touch signal line.

[0048] Second Embodiment

[0049] Please refer to Figure 8 , Figure 9 as well as Figure 10A-10E , Figure 8 This is a partial top view of a touch display panel according to a second embodiment of the present invention. Figure 9 forFigure 8 Side view of the center section AA' and section BB'. Figure 10A-10E These are partial patterns of each layer of the touch display panel in this embodiment. Figure 8 Sub-pixels 801 and 802 are illustrated, and these two sub-pixels 801 and 802 are arranged sequentially along the first direction X. The pattern of the first metal layer M1 has diagonal lines, while the pattern of the second metal layer M2 has "+" signs to facilitate differentiation between the first metal layer M1 and the second metal layer M2. The first metal layer M1 includes gate line G1, gate line G2, gates 811-G, gates 812-G, and electrode line 820. Please also refer to... Figure 8 and Figure 10A From a top view, gate line G1 is positioned above sub-pixels 801 and 802 and connected to the gate 812-G of the thin-film transistor in sub-pixel 802. Gate line G2 is positioned below sub-pixels 801 and 802 and connected to the gate 811-G of the thin-film transistor in sub-pixel 801. Therefore, the two sub-pixels 801 and 802 in the same pixel row are electrically connected to the two gate lines G1 and G2, respectively. Electrode line 820 is positioned between gate line G1 and gate line G2, and electrode line 820 is electrically insulated from gate lines G1 and G2. The manufacturing method of the touch display panel in this embodiment is similar to that in the first embodiment. Please also refer to... Figure 8 , Figure 9 and Figure 10A A first metal layer M1 is formed on the substrate SUB using a first masking process. This first metal layer M1 includes gates 811-G and 812-G, gate lines G1 and G2, and electrode lines 820. Gate lines G1 and G2 extend along a first direction X (that is, the length direction of gate lines G1 and G2 is parallel to the first direction X). Electrode lines 820 include a first portion 820a, a second portion 820b, a third portion 820c, and a fourth portion 820d. The opposite ends of the first portion 820a are respectively coupled to the second portion 820b and the third portion 820c, and the opposite ends of the second portion 820b are respectively coupled to the first portion 820a and the fourth portion 820d. The first part 820a and the fourth part 820d extend along the second direction Y (that is, the length direction of the first part 820a and the fourth part 820d is parallel to the second direction Y), the second part 820b and the third part 820c extend along the first direction X (that is, the length direction of the second part 820b and the third part 820c is parallel to the first direction X), and the first part 820a is located between sub-pixels 801 and 802. Because Figure 8Only a partial top view of the touch display panel is shown. When another sub-pixel (not shown) is disposed to the left of sub-pixel 801, the fourth part 820d is disposed between sub-pixel 801 and the aforementioned other sub-pixel. Next, a first insulating layer INS-1 is formed. This first insulating layer INS-1 covers the first metal layer M1 and includes the gate insulating layers 811-GI and 812-GI of the thin-film transistors. Please also refer to... Figure 8 , Figure 9 and Figure 10B The channel layers 811-C and 812-C of the thin film transistor and the contact layer CL are formed on the gate insulating layer using a second masking process. Figure 10B The label “811-C,CL” indicates that the channel layer 811-C and the contact layer CL are stacked, and the contact layer CL is disposed on the channel layer 811-C. Figure 10B The marking "812-C,CL" is similar and will not be repeated here. Please refer to [the website / company name] as well. Figure 8 , Figure 9 and Figure 10C A second metal layer M2 is formed using a third masking process. The second metal layer M2 includes data line D1 and touch signal line Sx, the drain 811-D and source 811-S of the thin-film transistor in sub-pixel 801, and the drain 812-D and source 812-S of the thin-film transistor in sub-pixel 802. Data line D1 is connected to source 812-S and source 811-S. The contact layers CL located below source 811-S and drain 811-D and not removed, and the contact layers CL located below source 812-S and drain 812-D and not removed, respectively form ohmic contact layers 811-OC and 812-OC. Data line D1 and touch signal line Sx extend along the second direction Y (i.e., the length direction of data line D1 and touch signal line Sx is parallel to the second direction Y). Next, a second insulating layer INS-2 is formed, covering the second metal layer M2. Please refer to [further details omitted]. Figure 8 , Figure 9 and Figure 10D A first connection hole 814-1 and a second connection hole 814-2 are formed in the second insulating layer INS-2 using a fourth mask process. The first connection hole 814-1 exposes a portion of the drain electrode 811-D or 812-D, and the second connection hole 814-2 exposes a portion of the touch signal line Sx.

[0050] Please participate simultaneously Figure 8 , Figure 9 and Figure 10ENext, a fifth masking process is used to form a transparent conductive layer 106 on the second insulating layer INS-2. The transparent conductive layer 106 includes the pixel electrode PE-1 and common electrode COM-1 of sub-pixel 801, and the pixel electrode PE-2 and common electrode COM-2 of sub-pixel 802. Pixel electrodes PE-1 and PE-2 respectively include first strip electrodes PE-1F and PE-2F, and common electrodes COM-1 and COM-2 respectively include second strip electrodes COM-1F and COM-2F. The first strip electrode PE-1F of pixel electrode PE-1 of sub-pixel 801 and the second strip electrode COM-1F of common electrode COM-1 are arranged alternately, and the first strip electrode PE-2F of pixel electrode PE-2 of sub-pixel 802 and the second strip electrode COM-2F of common electrode COM-2 are arranged alternately, with gaps SL between the first strip electrode PE-1F and the second strip electrode COM-1F, and between the first strip electrode PE-2F and the second strip electrode COM-2F. Pixel electrode PE-1 is electrically connected to drain electrode 811-D through first connection hole 814-1, and pixel electrode PE-2 is electrically connected to drain electrode 812-D through another first connection hole 814-1. Common electrode COM-1 is electrically connected to touch signal line Sx located on the left side through second connection hole 814-2. In this embodiment, common electrodes COM-1 and COM-2 belong to different touch electrodes, but this is not a limitation. Therefore, common electrode COM-2 is electrically connected to another touch signal line Sx (not shown) through another second connection hole 814-2 (not shown). In embodiments where common electrodes COM-1 and COM-2 belong to the same touch electrode 112, common electrodes COM-1 and COM-2 can be electrically connected to each other, but this is not a limitation. The common electrodes COM-1 and COM-2 include openings 818-1 (also referred to as second openings), which at least partially overlap gate lines G1 and G2, respectively, thereby reducing the load on gate lines G1 and G2 and avoiding interference with signal transmission on gate lines G1 and G2. Furthermore, the common electrodes COM-1 and COM-2 also include openings 818-2 (also referred to as third openings), which at least partially overlap channel layers 811-C located between source 811-S and drain 811-D and channel layers 812-C located between source 812-S and drain 812-D, respectively, to prevent leakage current in the thin-film transistor. Please refer to... Figure 11 , Figure 11This is a partial pattern of the transparent conductive layer in a variation of the second embodiment. In addition to openings 818-1 and 818-2, the common electrodes COM-1 and COM-2 may also include another opening 818-3 (also referred to as the first opening). The opening 818-3 at least partially overlaps the touch signal line Sx, thereby reducing the load on the touch signal line Sx and avoiding any impact on signal transmission on the touch signal line Sx.

[0051] like Figure 8 and Figure 10A , 10C As shown in Figure 10E, in this embodiment, the fourth portion 820d of the electrode line 820 extends along the second direction Y to the left of the sub-pixel 801 and at least partially overlaps with the touch signal line Sx. The electrode line 820 turns to the first direction X below the sub-pixel 801 (that is, the second portion 820b of the electrode line 820 extends along the first direction X) and at least partially overlaps with the drain 811-D. The electrode line 820 extends upward along the second direction Y to the right of the sub-pixel 801 (that is, the first portion 820a of the electrode line 820 extends along the second direction Y) and at least partially overlaps with the data line D1. The electrode line 820 turns to the first direction X above the sub-pixel 802 (that is, the third portion 820c of the electrode line 820 extends along the first direction X) and at least partially overlaps with the drain 812-D. Therefore, electrode lines 820 can overlap at least a portion of the drain 811-D of sub-pixel 811 and at least a portion of the drain 812-D of sub-pixel 812 to form a storage capacitor. Similar to the first embodiment, during the display period of the touch display panel, electrode lines 820 receive a common voltage, while during the touch sensing period of the touch display panel, although electrode lines 820 receive touch signals, they are not used to determine whether the device is touched or the location of the touch. Furthermore, similar to the first embodiment, the second embodiment only requires five masking processes to fabricate the touch display panel of the present invention, thereby saving costs.

[0052] Figure 12 This is a top view illustrating the arrangement of multiple sub-pixels according to an embodiment. Figure 13 This is a circuit diagram of a touch display panel according to an embodiment. Figure 12 What is drawn is Figure 13 A top view of the sub-pixels in region 1010. (See image.) Figure 13As shown, the touch display panel includes gate lines G1-G7, multiple data lines D1-D4, multiple sub-pixels, and multiple touch signal lines Sx. The sub-pixels are arranged in multiple sub-pixel rows and multiple sub-pixel columns. Two gate lines are positioned between two adjacent sub-pixel rows, and one data line or one touch signal line is positioned between two adjacent sub-pixel columns. The data lines and touch signal lines are interleaved, with one touch signal line positioned between two adjacent data lines and another between two adjacent data lines. Each sub-pixel row is electrically connected to two gate lines, and two sub-pixels within the same sub-pixel row are electrically connected to the same data line. Figure 12 The diagram illustrates four sub-pixels 901-904 arranged along a first direction X. Sub-pixels 901 and 902 are electrically connected to data line D2, and sub-pixels 903 and 904 are electrically connected to data line D3. Sub-pixels 902 and 904 are electrically connected to gate line G1, and sub-pixels 901 and 903 are electrically connected to gate line G2. Furthermore, electrode line 920 overlaps at least a portion of the drain of sub-pixels 901-904 (see reference). Figure 8 The electrode line 920 and the drains 811-D and 812-D of sub-pixels 801 and 802 are described in detail here. In this embodiment, the electrode line 920 continuously spans four sub-pixels 901 to 904, extending along the second direction Y between adjacent sub-pixels and at least partially overlapping the touch signal line Sx or data line (e.g., data lines D2 and D3). In this embodiment, the sub-pixels in each pixel column are used to display the same color, and any two adjacent pixel columns are used to display different colors, but this is not a limitation. For example, in an embodiment where each pixel consists of three sub-pixels of different colors, the three sub-pixels 901 to 903 are used to display different colors, and sub-pixels 901 and 904 are used to display the same color, but this is not a limitation. In summary, the multiple sub-pixels of the touch display panel include a first sub-pixel (e.g., sub-pixel 902) and a second sub-pixel (e.g., sub-pixel 903). The multiple touch signal lines of the touch display panel include a first touch signal line (e.g., touch signal line Sx located between sub-pixels 902 and 903), and the first touch signal line is located between the first sub-pixel and the second sub-pixel. The multiple gate lines of the touch display panel include a first gate line (e.g., gate line G1) and a second gate line (e.g., gate line G2). The multiple data lines of the touch display panel include a first data line (e.g., data line D2) and a second data line (e.g., data line D3). The first sub-pixel and the second sub-pixel are electrically connected to the first gate line and the second gate line, respectively, and the first sub-pixel and the second sub-pixel are electrically connected to the first data line and the second data line, respectively. Furthermore, the common electrode of at least one of the first sub-pixel and the second sub-pixel may have an opening, similar to... Figure 11The opening 818-3 overlaps with a portion of the first touch signal line.

[0053] Third Embodiment

[0054] Please refer to Figure 14 , Figure 15 as well as Figure 16A-16E , Figure 14 This is a partial top view of a touch display panel according to a third embodiment of the present invention. Figure 15 for Figure 14 Side view of the center section AA' and section BB'. Figure 16A-16E These are partial patterns of each layer of the touch display panel in this embodiment. Figure 14 In this embodiment, three sub-pixels 1101-1103 in a pixel are sequentially arranged along the second direction Y, and sub-pixels 1101-1103 are used to display different colors, for example, sub-pixels 1101-1103 are red sub-pixels, green sub-pixels, and red sub-pixels respectively, but are not limited thereto. Each gate line G1-G4 extends along the first direction X (that is, the length direction of each gate line G1-G4 is parallel to the first direction X), wherein gate line G1 is electrically connected to sub-pixel 1101, gate line G2 is electrically connected to sub-pixel 1102, gate line G3 is electrically connected to sub-pixel 1103, and gate line G4 is electrically connected to another sub-pixel (not shown). Touch signal line Sx and data line D1 extend along the second direction Y (that is, the length direction of touch signal line Sx and data line D1 is parallel to the second direction Y), wherein data line D1 is electrically connected to sub-pixels 1101-1103. Electrode lines 1111 to 1113 are sequentially arranged along the second direction Y, and each electrode line 1111 to 1113 extends along the first direction X (that is, the length direction of each electrode line 1111 to 1113 is parallel to the first direction X). Electrode line 1111 is disposed between gate line G1 and gate line G2, electrode line 1112 is disposed between gate line G2 and gate line G3, and electrode line 1113 is disposed between gate line G3 and gate line G4. Electrode lines 1111, 1112, and 1113 overlap at least a portion of the drain 1122-D in sub-pixels 1101, 1102, and 1103 to form a storage capacitor. Similar to the first and second embodiments, during the display period of the touch display panel, the electrode lines 1111, 1112, and 1113 receive a common voltage. However, during the touch sensing period of the touch display panel, although the electrode lines 1111, 1112, and 1113 receive touch signals, they are not used to determine whether the device is touched or the location of the touch.

[0055] The manufacturing method of the touch display panel in this embodiment is similar to that in the first and second embodiments. Please refer to the following: Figure 14 , Figure 15 andFigure 16A A first metal layer M1 is formed on the substrate SUB using a first masking process. This first metal layer M1 includes a gate electrode 1122-G, gate lines G1 to G4, and electrode lines 1111 to 1113. Next, a first insulating layer INS-1 is formed. This first insulating layer INS-1 covers the first metal layer M1 and includes the gate insulating layer 1122-GI of the thin-film transistor. Please refer to [further details omitted]. Figure 14 , Figure 15 and Figure 16B The channel layer 1122-C and the contact layer CL of the thin film transistor are formed on the gate insulating layer 1122-GI using a second masking process. Figure 16B The designation "1122-C,CL" indicates that the channel layer 1122-C and contact layer CL are stacked, with the contact layer CL positioned on top of the channel layer 1122-C. Please also refer to... Figure 14 , Figure 15 and Figure 16C A second metal layer M2 is formed using a third masking process. The second metal layer M2 includes data line D1 and touch signal line Sx, as well as the drain 1122-D and source 1122-S of the thin-film transistor in the sub-pixel. Data line D1 is connected to source 1122-S. The contact layer CL, located below source 1122-S and drain 1122-D and not removed, forms an ohmic contact layer 1122-OC. Next, a second insulating layer INS-2 is formed, covering the second metal layer M2. Please refer to [further details omitted]. Figure 14 , Figure 15 and Figure 16D A fourth masking process is used to form a first connection hole 1124-1 and a second connection hole 1124-2 in the second insulating layer INS-2. The first connection hole 1124-1 exposes a portion of the drain electrode 1122-D, and the second connection hole 1124-2 exposes a portion of the touch signal line Sx. Please also refer to... Figure 14 , Figure 15 and Figure 16ENext, a fifth masking process is used to form a transparent conductive layer 106 on the second insulating layer INS-2. The transparent conductive layer 106 includes a pixel electrode PE and a common electrode COM. The pixel electrode PE includes a first strip electrode PE-F, and the common electrode COM includes a second strip electrode COM-F. The first strip electrode PE-F and the second strip electrode COM-F of the pixel electrode PE of each sub-pixel 1101, 1102, and 1103 are arranged alternately, and there is a gap SL between the first strip electrode PE-F and the second strip electrode COM-F. The pixel electrode PE is electrically connected to the drain electrode 1122-D through the first connection hole 1124-1, and the common electrode COM is electrically connected to the touch signal line Sx through the second connection hole 1124-2. In this embodiment, the common electrode COM of the sub-pixels 1101, 1102, and 1103 belongs to the same touch electrode and is therefore electrically connected to each other, but this is not a limitation. The common electrode COM includes an opening 1128-1 (also referred to as a third opening), which at least partially overlaps the channel layer 1122-C located between the source 1122-S and the drain 1122-D to prevent leakage current in the thin-film transistor. The common electrode COM may also include an opening 1128-2 (also referred to as a first opening), which at least partially overlaps the touch signal line Sx, thereby reducing the load on the touch signal line Sx and avoiding interference with signal transmission on the touch signal line Sx. Please refer to... Figure 17 , Figure 17 This is a partial pattern of the transparent conductive layer 106 in a variation of the third embodiment. In addition to openings 1128-1 and 1128-2, the common electrode COM may also include another opening 1128-2, which at least partially overlaps with another touch signal line Sx, thereby reducing the load on this touch signal line Sx. Furthermore, the common electrode COM may also include another opening 1128-3 (also referred to as a second opening), which at least partially overlaps with gate lines G1 to G4, thereby reducing the load on gate lines G1 to G4 and avoiding interference with signal transmission on gate lines G1 to G4. Similar to the first and second embodiments, the third embodiment only requires five masking processes to fabricate the touch display panel of the present invention, thereby saving costs.

[0056] Figure 18 This is a top view illustrating the arrangement of multiple sub-pixels according to an embodiment. Figure 19 This is a circuit diagram of a touch display panel based on the third embodiment. Figure 18 for Figure 19 A top view of the touch display panel with pixels 1210 and 1220. Figure 18The diagram illustrates two pixels 1210 and 1220 arranged sequentially along a first direction X. Each pixel 1210 and 1220 includes sub-pixels SP1, SP2, and SP3 arranged sequentially along a second direction Y, and sub-pixels SP1, SP2, and SP3 are used to display different colors. An electrode line 1111 extends along the first direction X and overlaps at least a portion of the drain electrode in sub-pixel SP1 of pixel 1210 and at least a portion of the drain electrode in sub-pixel SP1 of pixel 1220. Further details can be found in [reference needed]. Figure 14 This will not be elaborated further here. Similarly, electrode line 1112 overlaps at least a portion of the drain of sub-pixel SP2 in pixel 1210 and at least a portion of the drain of sub-pixel SP2 in pixel 1220. Electrode line 1113 overlaps at least a portion of the drain of sub-pixel SP3 in pixel 1210 and at least a portion of the drain of sub-pixel SP3 in pixel 1220. Each gate line G1 to G6 extends along the first direction X, and pixels 1210 and 1220 are sequentially arranged along the first direction X. Sub-pixels SP1, SP2, and SP3 in each pixel 1210 and pixel 1220 are sequentially arranged along the second direction Y. In summary, the multiple sub-pixels of the touch display panel include a first sub-pixel (e.g., sub-pixel SP1 of pixel 1210) and a second sub-pixel (e.g., sub-pixel SP1 of pixel 1220). The multiple touch signal lines of the touch display panel include a first touch signal line (e.g., touch signal line Sx located between sub-pixels SP1 of pixel 1220), and the first touch signal line is located between the first sub-pixel and the second sub-pixel. The multiple gate lines of the touch display panel include a first gate line (e.g., gate line G1), and the multiple data lines of the touch display panel include a first data line (e.g., data line D1) and a second data line (e.g., data line D2). The first sub-pixel and the second sub-pixel are electrically connected to the first gate line, and the first sub-pixel and the second sub-pixel are respectively electrically connected to the first data line and the second data line. The first sub-pixel and the second sub-pixel are respectively used to display the same color. Furthermore, at least one of the first sub-pixel and the second sub-pixel has an opening in its common electrode, similar to... Figure 16E The opening 1128-2 overlaps with a portion of the first touch signal line.

[0057] Figure 20 This is a schematic diagram illustrating the display area and surrounding area of ​​a touch display device according to one embodiment. Please refer to... Figure 20The touch display device 1400 has a display area 1410 and a peripheral area 1420. The touch display device 1400 includes a touch display panel 1490 and a touch sensing circuit 1480, with the touch sensing circuit 1480 electrically connected to the touch display panel 1490. The touch display panel 1490 includes a substrate SUB and a plurality of touch electrodes TE, a plurality of electrode lines EL, a potential line 1430, a plurality of touch signal lines Sx, and a plurality of connection pads disposed on the substrate SUB. The touch electrodes TE can be formed by electrically connecting the sub-touch electrodes (common electrodes) of a plurality of sub-pixels in the first to third embodiments described above. The plurality of connection pads includes a plurality of first connection pads 1460 and at least one second connection pad 1470. Figure 20 The diagram illustrates nine first connecting pads 1460 disposed between two second connecting pads 1470, but is not limited thereto. Potential lines 1430 and connecting pads are disposed in the peripheral area 1420, surrounding the display area 1410. Potential lines 1430 can be formed from a first metal layer M1, a second metal layer M2, or a combination thereof. For example, potential lines 1430 can be formed entirely from the first metal layer M1 or entirely from the second metal layer M2, or a portion of potential lines 1430 can be formed from the first metal layer M1 and another portion from the second metal layer M2, with said portion and said other portion electrically connected to each other. Electrode lines EL are electrically connected to potential lines 1430. Electrode lines EL can be electrode lines from the first to third embodiments described above, for example, electrode lines EL can be electrode lines 104 of the first embodiment, electrode lines 820 and 920 of the second embodiment, or electrode lines 1111, 1112, and 1113 of the third embodiment. Figure 20 The example shown is based on the electrode line EL extending along the second direction Y, but is not limited to this.

[0058] Each touch electrode TE is electrically connected to a corresponding first contact pad 1460 via a corresponding touch signal line Sx. Furthermore, a potential line 1430 is electrically connected to a second contact pad 1470 via a wire 1450. A touch sensing circuit 1480 is disposed in the peripheral area 1420. The touch sensing circuit 1480 includes a plurality of first touch pads 1482 and at least one second touch pad 1484. The first touch pads 1482 are electrically connected to the first contact pads 1460, and the second touch pads 1484 are electrically connected to the second contact pads 1470. Figure 20 In the top view, the first touch pad 1482 overlaps with and is electrically connected to the corresponding first connection pad 1460, and the second touch pad 1484 overlaps with and is electrically connected to the corresponding second connection pad 1470. Figure 20The markings "1460, 1482" indicate overlapping and electrically connected first touch pad 1482 and first connecting pad 1460, with the first touch pad 1482 disposed on the first connecting pad 1460; the markings "1470, 1484" indicate overlapping and electrically connected second touch pad 1484 and second connecting pad 1470, with the second touch pad 1484 disposed on the second connecting pad 1470. During the display of the touch display panel 1400, the touch sensing circuit 1480 outputs a common voltage to the first touch pad 1482 and the second touch pad 1484. Therefore, the common voltage can be transmitted to the common electrode (touch electrode TE) via the first connecting pad 1460 and the touch signal line Sx, and the common voltage can be transmitted to the electrode line EL via the second connecting pad 1470, the wire 1450, and the potential line 1430. The grayscale voltage is transmitted to the pixel electrode via the data line. The electrode line EL overlaps at least a portion of the drain electrode. The electrode line EL, the drain electrode, and the first insulating layer located between the electrode line and the drain electrode form a capacitor to store grayscale voltage. During touch sensing of the touch display panel 1400, the touch sensing circuit 1480 outputs touch signals to the first touch pad 1482 and the second touch pad 1484. Therefore, the touch signal can be transmitted to the touch electrode TE via the first connecting pad 1460 and the touch signal line Sx, and the touch signal can be transmitted to the electrode line EL via the second connecting pad 1470, the wire 1450, and the potential line 1430. However, the touch sensing circuit 1480 only determines whether the device is touched and the touch location based on the signal received by the first touch pad 1482 electrically connected to the touch signal line Sx, and does not determine whether the device is touched and the touch location based on the signal received by the second touch pad 1484 electrically connected to the electrode line EL. In summary, the touch display device includes a touch display panel and a touch sensing circuit, with the touch sensing circuit electrically connected to the touch display panel. The touch display panel includes M touch electrodes (e.g., Figure 20 The nine touch electrodes (TE) and M touch signal lines (e.g.) Figure 20 The touch sensing circuit contains 9 touch signal lines (Sx), and each touch electrode is electrically connected to its corresponding touch signal line. The touch sensing circuit includes N touch pads (e.g., ...). Figure 20 The circuit contains 11 touch pads, including 9 first touch pads 1482 and 2 second touch pads 1484, where N and M are both positive integers greater than 0, and N is greater than M, meaning the number of touch pads is greater than the number of touch signal lines. M of the N touch pads in the touch sensing circuit (e.g., ...) Figure 20 The nine first touch pads 1482 in the circuit are electrically connected to the M touch signal lines of the touch sensing panel, while the remaining (NM) of the N touch signal pads in the touch sensing circuit (e.g., Figure 20 The two second touch pads 1484 in the middle are electrically connected to the electrode wires (e.g. Figure 20The electrode line EL is electrically connected via potential line 1430. During the display period of the touch display panel, all N touch pads of the touch sensing circuit output a common voltage, that is, the potentials of the electrode line and the touch electrode are the same voltage. During the touch sensing period of the touch display panel, all N touch signal pads of the touch sensing circuit output touch signals. However, the touch sensing circuit only determines whether the device is touched and the touch position based on the signals received by the M touch signal pads electrically connected to the M touch signal lines, and does not determine whether the device is touched and the touch position based on the signals received by the (NM) touch signal pads electrically connected to the electrode lines.

[0059] The materials of the aforementioned substrate SUB include, for example, glass, polymers, polyethylene terephthalate (PET), polycarbonate (PC), polyethersulfone (PES), triacetyl cellulose (TAC), polymethyl methacrylate (PMMA), polyethylene, cyclic olefin polymers (COP), polyimide (PI), and composite materials composed of polycarbonate (PC) and polymethyl methacrylate (PMMA), etc., and this invention is not limited thereto. The material of the transparent conductive layer 106 may include indium tin oxide (ITO), indium zinc oxide (IZO), antimony tin oxide (ATO), fluorine tin oxide (FTO), or other conductive and transparent materials, such as nanowires (silver nanowires, copper nanowires). The metal layer mentioned in this specification may be a single metal layer such as aluminum, copper, titanium, or tungsten, or a composite metal layer such as molybdenum / aluminum / molybdenum, titanium / aluminum-titanium, titanium / copper / titanium, titanium / copper, etc., and this invention is not limited thereto. On the other hand, the insulating layer mentioned in this specification may be silicon nitride, silicon oxide, silicon oxynitride, or other suitable insulating layers, and one insulating layer in the illustrations may contain two or more insulating layers of different materials stacked on top of each other.

[0060] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A touch display device, characterized in that, Comprising: A touch display panel having a display area and a peripheral area, the touch display panel comprising: A substrate; A plurality of gate lines, a plurality of data lines, and a plurality of touch signal lines disposed on the substrate; A plurality of sub-pixels disposed on the substrate and located in the display area, each of the sub-pixels comprising: A thin film transistor disposed on the substrate, the thin film transistor comprising a gate, a drain, and a source, wherein the gate is electrically connected to a corresponding one of the plurality of gate lines, and the source is electrically connected to a corresponding one of the plurality of data lines; A pixel electrode electrically connected to the drain; and A sub-touch electrode electrically connected to a corresponding one of the plurality of touch signal lines, wherein the pixel electrode and the sub-touch electrode of the plurality of sub-pixels are formed from a same transparent conductive layer, the pixel electrode comprises a plurality of first strip electrodes, the sub-touch electrode comprises at least one second strip electrode, wherein in a top view of the transparent conductive layer, the first strip electrodes and the second strip electrode are staggered with each other, and there is a gap between adjacent first strip electrodes and second strip electrodes. 2.The touch display device of claim 1, wherein, During a display period of the touch display panel, the sub-touch electrodes of the plurality of sub-pixels receive a common voltage. 3.The touch display device of claim 1, wherein, The plurality of sub-pixels comprises a first sub-pixel and a second sub-pixel, the plurality of touch signal lines comprises a first touch signal line, and the first touch signal line is located between the first sub-pixel and the second sub-pixel. 4.The touch display device of claim 3, wherein, The sub-touch electrode of at least one of the first sub-pixel and the second sub-pixel has an opening, and the opening overlaps a portion of the first touch signal line. 5.The touch display device of claim 3, wherein, The plurality of gate lines comprises a first gate line, the plurality of data lines comprises a first data line and a second data line, the first sub-pixel and the second sub-pixel are electrically connected to the first gate line, the first sub-pixel and the second sub-pixel are electrically connected to the first data line and the second data line, respectively, and the first sub-pixel and the second sub-pixel are used to display different colors. 6.The touch display device of claim 3, wherein, The plurality of gate lines comprises a first gate line, the plurality of data lines comprises a first data line and a second data line, the first sub-pixel and the second sub-pixel are electrically connected to the first gate line, the first sub-pixel and the second sub-pixel are electrically connected to the first data line and the second data line, respectively, and the first sub-pixel and the second sub-pixel are used to display the same color. 7.The touch display device of claim 3, wherein, The plurality of gate lines comprises a first gate line and a second gate line, the plurality of data lines comprises a first data line and a second data line, the first sub-pixel and the second sub-pixel are electrically connected to the first gate line and the second gate line, respectively, and the first sub-pixel and the second sub-pixel are electrically connected to the first data line and the second data line, respectively. 8.The touch display device of claim 3, wherein, The touch display panel further comprises an electrode line, and the electrode line overlaps at least a portion of the drain of the first sub-pixel and at least a portion of the drain of the second sub-pixel. 9.A method for manufacturing a touch display panel, comprising: Comprising: Providing a substrate; Forming a first metal layer on the substrate, wherein the first metal layer comprises gate lines and gates of thin film transistors; forming a first insulating layer on the first metal layer, wherein the first insulating layer comprises a gate insulating layer of the thin film transistor; forming a second metal layer on the first insulating layer, wherein the second metal layer comprises a data line, a source and a drain of the thin film transistor, and a touch signal line; forming a second insulating layer on the second metal layer; forming a first connection hole and a second connection hole in the second insulating layer, the first connection hole exposes a part of the drain, and the second connection hole exposes a part of the touch signal line; and forming a transparent conductive layer on the second insulating layer, wherein the transparent conductive layer comprises a pixel electrode and a sub touch electrode, the pixel electrode is electrically connected to the drain through the first connection hole, the touch electrode is electrically connected to the touch signal line through the second connection hole, the pixel electrode comprises a plurality of first strip electrodes, the sub touch electrode comprises at least one second strip electrode, wherein in a top view of the transparent conductive layer, the first strip electrodes and the second strip electrodes are staggered with each other, and there is a gap between adjacent first strip electrodes and second strip electrodes.

10. The manufacturing method as described in claim 9, characterized in that, The first metal layer comprises an electrode line, and at least a part of the drain overlaps a part of the electrode line.

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