Techniques for mode detection prefetch information

Abstract

This application is directed to techniques for using pattern detection to prefetch information. Some memory systems can support prefetching information, such as logical-to-physical (L2P) mapping tables, data, or both, in the event that a sequential pattern of read commands is detected. In some instances, the memory system can store a list of logical addresses indicated by received read commands and can determine whether the list corresponds to a sequential pattern independent of intervening like write commands. The list can store previous logical addresses for read commands, allowing the memory system to determine whether subsequent read commands form a sequential pattern. Additionally or alternatively, the memory system can track a ratio of sleep commands to other commands (e.g., sequential read commands) and can refrain from prefetching L2P mapping tables for a detected sequence in the event that the tracked ratio satisfies (e.g., exceeds) a threshold ratio.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 723,096, filed April 18, 2022, entitled "Technologies for Pre-Fetching Information Using Pattern Detection," by Urrinkala et al., and U.S. Provisional Patent Application No. 63 / 181,760, filed April 29, 2021, entitled "Technologies for Pre-Fetching Information Using Pattern Detection," both of which are expressly incorporated herein by reference in their entirety. Technical Field

[0003] The technical field involves techniques for using pattern detection to prefetch information. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any one of the two possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a memory device; and a controller coupled to the memory device and configured such that the apparatus: receives from a host system a plurality of read commands and one or more similar write commands, each of the one or more similar write commands being associated with at least one corresponding write operation performed on the memory device; stores a list of logical addresses indicated by the plurality of read commands according to the execution order of the plurality of read commands; determines whether the list of logical addresses corresponds to a sequential pattern based at least in part on the logical addresses indicated by the plurality of read commands, the corresponding transfer length of the plurality of read commands, or both; and prefetches data from the memory device for use in subsequent read commands based at least in part on the determination that the list of logical addresses corresponds to the sequential pattern.

[0007] Describing another device. The device may include a memory device; and a controller coupled to the memory device and configured such that the device: receives a plurality of read commands and one or more sleep commands; detects a logical address sequence pattern based at least in part on a corresponding logical address indicated by the plurality of read commands, a corresponding transfer length of the plurality of read commands, or both; determines, at least in part in part in whether to prefetch the table from the memory device according to the sequence pattern, based on a ratio of sleep commands to sequential read commands among the plurality of read commands; and executes a subsequent read command based at least in part in determining whether to prefetch the table.

[0008] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive from a host system a plurality of read commands and one or more similar write commands, each of the one or more similar write commands being associated with at least one corresponding write operation performed by a memory device; store a list of logical addresses indicated by the plurality of read commands according to the execution order of the plurality of read commands; determine, at least in part, whether the list of logical addresses corresponds to a sequential pattern based on the logical addresses indicated by the plurality of read commands, the corresponding transfer length of the plurality of read commands, or both; and prefetch data from the memory device for use in subsequent read commands, at least in part based on the determination that the list of logical addresses corresponds to the sequential pattern. Attached Figure Description

[0009] Figure 1 and 2 This document describes examples of systems that support the use of pattern detection prefetching techniques, based on the examples disclosed herein.

[0010] Figure 3 This document describes instances of command sets that support techniques for using pattern detection prefetching information, based on the examples disclosed herein.

[0011] Figure 4 This document describes an example of a process flow that supports techniques for using pattern detection prefetching information, based on the examples disclosed herein.

[0012] Figure 5A and 5B This document describes instances of command sets that support the use of pattern detection prefetching techniques, based on the examples disclosed herein.

[0013] Figure 6 This document describes an example of a process flow that supports the use of pattern detection prefetching techniques, based on the examples disclosed herein.

[0014] Figure 7 A block diagram of a memory system supporting a technique for using pattern detection prefetching information, based on examples disclosed herein, is shown.

[0015] Figure 8 and 9 A flowchart illustrating a method for supporting the use of pattern detection prefetching information based on the examples disclosed herein is shown. Detailed Implementation

[0016] Some memory systems support prefetching information from the memory device. For example, if the memory system detects a read command sequence pattern, it can predict the next read command in the sequence and retrieve information about the predicted read command (e.g., a logical-to-physical (L2P) map, data, or both) before executing the read command. However, some command sequences executed by the memory system can cause inefficiencies in prefetching techniques. For example, whenever the memory system receives a similar write command (e.g., any command involving writing data to the memory device), the pattern detection process can be reset, even if the similar write commands are interleaved within the sequential read command set. Resetting pattern detection due to similar write commands (especially where previous and subsequent read commands correspond to sequential patterns) reduces the amount of prefetching performed by the memory system, thereby effectively reducing the latency increase provided by prefetching techniques. Alternatively, a sleep command can cause the memory system to clear information from the cache, including prefetched information. If the memory system executes a relatively large number of sleep commands compared to sequential read commands (e.g., if the ratio of sleep commands to sequential read commands is greater than a threshold ratio), then the memory system may repeatedly prefetch the L2P mapping table into and out of the cache, thereby increasing the processing overhead associated with the prefetching technique and reducing the performance gains provided by the prefetching technique.

[0017] To support efficient prefetching techniques, memory systems can store sequential read command data (e.g., logical address, command length) before processing the next similar write or non-sequential read command. In some instances, the memory system can store sequential read command data from a list of logical addresses. Instead of resetting pattern detection upon receiving a similar write command, the memory system can maintain the logical address information of at least the most recent sequential read command in the logical address list, allowing the memory system to determine whether a subsequently received read command corresponds to the next command in the sequence. By maintaining pattern detection of the sequential read command set regardless of whether one or more intermediate similar write commands are received, the memory system can increase the likelihood of detecting sequential patterns and, correspondingly, increase the amount of prefetching performed by the memory system. Increasing the amount of prefetching performed by the memory system can improve memory system performance and reduce latency involved in reading sequential data.

[0018] Alternatively, the memory system may track the ratio of sleep commands to other commands (e.g., sequential read commands or any other commands). If the memory system detects a sequential pattern but determines that the ratio of sleep commands to other commands meets (e.g., exceeds) a threshold ratio, the memory system may prevent prefetching information (e.g., L2P mapping tables) to avoid duplicate prefetching and clearing of information. For example, each sleep command may clear any prefetched tables from the cache, allowing the memory system to re-fetch the tables for the next sequential read command. A substantial ratio of sleep commands to sequential read commands can cause duplicate prefetching and clearing of the L2P mapping table. By tracking the ratio and preventing prefetching when the memory system executes a substantial number of sleep commands (e.g., above the threshold ratio), the memory system can reduce redundant or excessive prefetching procedures, improving memory system performance.

[0019] Firstly, in reference Figure 1 and 2 Features of this disclosure are described in the context of the systems and apparatus described. (Referencing...) Figures 3 to 6 The features of this disclosure are further described in the context of the command set and process flow. (See references...) Figures 7 to 9 These and other features of this disclosure are further illustrated and described in the context of the device diagrams and flowcharts relating to the technology of using pattern detection to prefetch information.

[0020] Figure 1 This document describes an example of a system 100 that supports a technique for using pattern detection prefetching information, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0021] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form-factor DIMM (SO-DIMM), or a Non-volatile DIMM (NVDIMM), and other possibilities.

[0022] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0023] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0024] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0025] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0026] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0027] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0028] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0029] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130, and said data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0030] Although Figure 1 The example of memory system 110 described herein includes memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0031] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0032] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0033] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding block set 170, wherein each block 170 may include a corresponding page set 175, and each page 175 may include a set of memory cells.

[0034] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0035] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more limitations, such as the same operation being performed on memory cells within different pages 175 with the same page address within the corresponding plane 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0036] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0038] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise designate data held in the old block 170 as invalid or obsolete, and may update the L2P mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 instead of the old invalid block 170. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old block 170, for example, due to latency or wear and tear considerations. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0039] In some cases, an L2P mapping table can be maintained, and data can be marked as valid or invalid at the page granularity level, and page 175 may contain valid data, invalid data, or no data. Invalid data may be data that has become outdated because a newer or updated version of the data is stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175, but may no longer be associated with a valid logical address, such as a logical address referenced by host system 105. Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has never been written to or has been cleared.

[0040] System 100 may include any number of non-transitory computer-readable media that support techniques for using pattern detection to prefetch information. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access storage instructions (e.g., firmware) to perform one or more non-transitory computer-readable media that pertain to the functions of host system 105, memory system controller 115, or memory device 130 herein. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0041] Some memory systems 110 may support prefetching information (e.g., data, L2P mapping tables) from memory device 130. Prefetching may involve retrieving information for subsequent access commands (e.g., read commands) before executing an access command. For example, if memory system 110 detects that a set of read commands contains sequential read commands, where one read command ends at a first logical address (e.g., LBA) and the next read command begins at the next logical address (e.g., LBA) after the first logical address, then memory system 110 may predict the L2P mapping table, data, or both for the next read command in the sequence. Accordingly, memory system 110 may fetch (e.g., retrieve) the predicted L2P mapping table, data, or both from memory device 130 before executing the next read command and may store the L2P mapping table, data, or both in a cache (e.g., local memory 120 at memory system controller 115). Memory system 110 can reduce the latency involved in executing read commands if the L2P mapping table used for read commands, the data, or both have been prefetched and stored locally in a cache, because reading data from the cache involves relatively lower latency compared to reading data from memory device 130.

[0042] However, some command sequences executed at memory system 110 can cause inefficiencies in prefetching techniques. For example, if prefetching involves detecting sequential LBA modes in sequential commands, then the mode detection process must be reset whenever memory system 110 receives a similar write command (even if the read command received by memory system 110 from host system 105 is sequential). Similar write commands can be instances of any command involving writing data to memory device 130, such as write commands, unmapping commands, formatting unit commands, security protocol output commands, start / stop unit commands, or any other commands involving write operations. Similar write commands can be instances of unmapping commands (e.g., where the command does not indicate a specific logical address in memory device 130). Resetting mode detection (even if the read command corresponds to a sequential mode) reduces the likelihood of memory system 110 triggering prefetching, thereby reducing the latency increase supported by prefetching techniques. Alternatively, a sleep command can cause memory system 110 to clear information from the cache. If the memory system 110 executes a relatively large number of sleep commands compared to sequential read commands (e.g., if the ratio of sleep commands to sequential read commands is greater than a threshold ratio), then the memory system 110 may repeatedly prefetch the L2P mapping table into the cache and clear the table from the cache, thereby reducing the performance increase associated with prefetching techniques.

[0043] To support efficient prefetching techniques, memory system 110 may store sequential read command data (e.g., logical address, command length) before processing the next similar write or non-sequential read command. In some instances, memory system 110 may store sequential read command data at memory system controller 115 (e.g., in local memory 120). Instead of resetting pattern detection upon receiving a similar write command or a non-sequential read command less than a threshold number, memory system 110 may maintain logical address information of at least the most recent sequential read command, allowing memory system 110 to determine whether a subsequently received read command corresponds to the next command in the sequence. By maintaining pattern detection regardless of whether one or more similar write commands, non-sequential read commands, or both are received from host system 105, memory system 110 increases the likelihood of detecting sequential patterns and, correspondingly, triggering data prefetching. Increasing the number of prefetches performed by memory system 110 can improve the performance of memory system 110.

[0044] Alternatively, the memory system 110 may track the ratio of sleep commands to other commands (e.g., sequential read commands or any other commands). If the memory system 110 detects a sequential pattern but determines that the ratio of sleep commands to other commands meets a threshold ratio, then the memory system 110 may prevent prefetching information (e.g., L2P mapping tables, data, or both) to avoid duplicate prefetching and clearing information. Preventing prefetching information when the memory system 110 executes a substantial number of sleep commands (e.g., above the threshold ratio) can improve the performance of the memory system 110 and reduce redundant or excessive prefetching procedures.

[0045] Figure 2 This document describes an example of a system 200 that supports the use of pattern detection prefetching information, based on the examples disclosed herein. System 200 may be a reference. Figure 1 The described system 100 or an example thereof. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may implement references Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0046] Memory system 210 may include memory device 240 to store, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205, as described herein. Memory device 240 may include, as referenced... Figure 1The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0047] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, such as for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may be implemented as described in reference [reference missing]. Figure 1 The aspects of the local controller 135 described.

[0048] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data being transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to translate data between the host system 205 and the memory device 240 (e.g., as shown by data path 250), and can be collectively referred to as the data path components.

[0049] Temporarily storing data using buffer 225 during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling bursts of commands, and buffered data can be stored or transmitted (or both) once the burst has stopped. Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM), or hardware accelerators, or both, to allow for rapid storage of data into and from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0050] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Furthermore, buffer 225 may be a non-cached buffer. That is, host system 205 may not read data directly from buffer 225. For example, a read command may be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0051] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be a reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0052] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, when memory system 210 processes more than one access command from host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, queues (if used) can be located anywhere within memory system 210.

[0053] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components on bus 235 (e.g., using a memory system 210-specific protocol).

[0054] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 can, for example, transmit the command to memory system controller 215 via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0055] The memory system controller 215 may determine that an access command has been received using interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving the command from command queue 260. After, for example, the command has been retrieved from command queue 260 by the memory system controller 215, the command may be removed from command queue 260. In some cases, the memory system controller 215 may cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0056] After confirming that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transmitting the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0057] In either case, the memory system controller 215 may use the buffer 225 for temporary storage of data being received from or sent to the host system 205. The buffer 225 can be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0058] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0059] In some cases, buffer queue 265 can be used to control a stream of commands associated with data stored in buffer 225, the stream of commands including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least some portions of the access commands can be processed in parallel.

[0060] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205 according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the data stored within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0061] Once the written data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, when data transfer to memory devices in memory device set 240 has been completed.

[0062] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain an entry for each access command. In some instances, memory queue 270 may additionally contain: a buffer pointer (e.g., an address) indicating where the data associated with the command is stored in buffer 225; and a memory pointer (e.g., an address) indicating the location of the data associated with the data in memory device 240. In some cases, memory controller 230 can obtain the location of the data to be retrieved from buffer 225 from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the location of stored data in memory device 240 (e.g., for wear leveling, garbage collection, and the like). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is completed, the entry can be removed from the storage queue 270, for example, by the storage controller 230 or the memory system controller 215.

[0063] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0064] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, then memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to buffer 225 has been completed.

[0065] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of data retrieved from the memory device 240 from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location of data stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of stored data in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0066] Once data has been stored in buffer 225 by storage controller 230, it can be transferred from buffer 225 to host system 205. For example, storage system controller 215 can cause interface 220 to retrieve data from buffer 225 using data path 250 and transmit the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that data transfer to host system 205 has been completed.

[0067] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in-first-out order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moved into and stored in buffer 225, the command can remain in buffer queue 265. When the processing of a command is complete (e.g., when the data corresponding to the access command has been transferred out of buffer 225), the command can be removed from buffer queue 265, for example, via the memory system controller 215. If a command is removed from buffer queue 265, the address where the data previously associated with the command was stored can be used to store data associated with the new command.

[0068] The memory system controller 215 may be additionally configured for operations associated with the memory device set 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device set 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more adjacent LBAs may correspond to non-adjacent physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0069] In some instances, the memory system controller 215 of memory system 210 or another component (e.g., buffer 225) may include cache 275. Cache 275 may be an example of an SRAM cache. Cache 275 may temporarily store information for memory system 210 for relatively low-latency retrieval (e.g., compared to retrieving information stored in memory device 240). Memory system 210 may retrieve information from memory device 240 and store the information in cache 275. If a read command instructs the retrieval of information, memory system 210 may retrieve the information from cache 275 instead of memory device 240 to reduce the latency involved in reading the information. For example, memory system 210 may prefetch information (e.g., L2P mapping tables, data, or both) from one or more memory devices 240, store the prefetched information in cache 275, and execute one or more sequential read commands using the information from cache 275.

[0070] Cache 275 may be an instance of a non-persistent memory resource. For example, if memory system 210 loses power or enters a low-power state (e.g., a relatively low-power state where memory system 210 is idle), cache 275 may be unable to maintain information in the memory resource. In some cases, memory system 210 may support hibernation commands. A hibernation command (which may be referred to as an H8 command) can trigger memory system 210 to enter a low-power state to conserve energy. Memory system 210 may execute a hibernation command if memory system 210 is inactive for a threshold duration, if there are no pending access commands in command queue 260, or both. If memory system 210 executes a hibernation command, then memory system 210 may clear information from cache 275 back to one or more memory devices 240 before entering a low-power state. For example, if the information stored in cache 275 differs from the information stored in memory device 240, then memory system 210 can update memory device 240 with the latest information from cache 275 before entering a low-power state. Once memory system 210 enters a low-power state (e.g., in response to executing a hibernation command), memory system 210 can lose the information stored in cache 275, so that cache 275 can be empty after re-entering a high-power state (e.g., a relatively high power state compared to the low-power state). Thus, entering a low-power state can remove prefetched information from cache 275. In some cases, entering a low-power state may involve reducing the clock speed of one or more processing components (e.g., CPU) to reduce the power overhead for memory system 210. Alternatively or concurrently, memory system 210 may store the ratio of executed hibernation commands to other executed commands (e.g., sequential read commands or any other commands) to determine whether to prefetch and store the L2P mapping table in cache 275. In some cases, the ratio may be stored in a holding RAM so that the ratio is maintained when the memory system 210 enters a low-power mode.

[0071] To support efficient prefetching techniques, memory system 210 may store a logical address list 280 to track the sequential pattern of read commands. For example, memory system 210 may store the logical address list 280 at memory system controller 215 (e.g., in SRAM or holding RAM), interface 220 (e.g., firmware front-end), or some other component of memory system 210. If the logical address list 280 is stored in holding RAM, memory system 210 can maintain sequence tracking (e.g., a counter value, the logical address of the latest sequential read command) even when memory system 210 enters a low-power mode. Logical address list 280 may store the LBAs of a read command set, the command size of the read command set, the default command size of the read command set, or some combination thereof. If memory system 210 executes a read command corresponding to the sequence (e.g., reading data from the next set of LBAs following the LBA read for the previous read command), memory system 210 may add the LBA, command size, or both to logical address list 280. If memory system 210 executes one or more similar write commands, one or more non-sequential read commands, or a combination thereof, then memory system 210 may maintain logical address list 280 in memory for a threshold number of non-sequential commands, a threshold duration, or both. Correspondingly, if memory system 210 executes a read command following an LBA pattern in logical address list 280 after one or more non-sequential commands (e.g., similar write commands, non-sequential read commands), then memory system 210 may update logical address list 280 with the read command and may continue to track a number of read commands for detecting sequential patterns (e.g., without resetting the tracking). In some instances, memory system 210 may store a count value (e.g., along with logical address list 280) tracking the number of sequential read commands used for pattern detection. In some such instances, logical address list 280 may contain a single LBA, command size, or both of the most recently executed read command in the sequence. In some other instances, the logical address list 280 may contain multiple time slots of LBA (e.g., the number of time slots equals the number of thresholds for pattern detection), and the memory system 210 may determine that, in the case where the time slots for the logical address list 280 are filled with sequential read commands, the read command corresponds to a sequential pattern.

[0072] If memory system 210 detects a sequential pattern of read commands (e.g., using logical address list 280 to reduce pattern detection interrupts), then memory system 210 can trigger information prefetching for subsequent read commands based on the sequential pattern. For example, using the most recently executed read command in the pattern (e.g., the start LBA and command size or end LBA of the latest read command), memory system 210 can predict the start LBA, command size, or both of the next read command to be executed by memory system 210. Accordingly, memory system 210 can execute a prefetch command and can prefetch (e.g., read) information predicted for the next read command in the sequence (e.g., corresponding L2P mapping table, data to be retrieved) from one or more memory devices 240 and can store the information in cache 275. If memory system 210 executes the next read command in the sequence, then memory system 210 can read the information from cache 275, which reduces the latency involved in executing the read command compared to reading the information from memory device 240.

[0073] Figure 3 This document describes an example of a command set 300 that supports techniques for using pattern detection prefetching information, based on the examples disclosed herein. For example, see reference... Figure 1 and 2 The memory system 110 or 210 described herein can receive and execute command set 300. The memory system can store a logical address list 315 that tracks sequential read commands from command set 300, wherein the logical address list 315 may be a reference... Figure 2 An example of the described logical address list 280. For instance, the memory system may store logical address list 315 in holding RAM and may determine whether command set 300 contains a sequential pattern of read commands. If the memory system detects a sequential pattern, then the memory system may trigger a read command from one or more memory devices (e.g., reference...). Figure 1 and 2 The described memory device 130 or 240 prefetches data.

[0074] In some other systems, pattern detection for sequential read commands may fail if the memory system executes a write command or a non-sequential read command (e.g., a prefetch conflict command). For example, the memory system may remove the executed command from the command buffer once execution is complete, once the next command begins execution, or both. Therefore, the memory system may not maintain information about previously executed commands after subsequent commands have begun execution. The memory system may access the LBA and command size of the command immediately preceding the new command to determine if the new command corresponds to a sequential pattern of read commands, but if the memory system executes any intervening commands (e.g., write commands, non-sequential read commands), the memory system may no longer store the LBA and command size of the latest but not immediately preceding read command in the sequential pattern. For example, the memory system may lose any information currently stored in the cache (e.g., prefetch data, information related to recently executed commands) in response to executing a write command. Accordingly, the memory system may not store information that supports comparisons to determine whether a new read command is placed after the latest sequential read command, thereby causing the memory system to reset mode detection (e.g., resetting the number of sequential read commands to zero).

[0075] In contrast, a memory system using logical address list 315 can maintain pattern detection even when executing one or more similar write commands, non-sequential read commands, or both. The memory system can maintain the read command LBA value, command length, or both in logical address list 315. The size of logical address list 315 can depend on a pattern detection threshold X. For example, if the number of read commands in a sequence is greater than or equal to X, then the memory system can determine that the set of read commands corresponds to a sequential read pattern. Logical address list 315 can contain a length X (e.g., the number of time slots used to store LBA information equal to X). In some instances, the memory system can trigger data prefetching (e.g., prefetching) upon detecting a sequential read pattern. In some other instances, the memory system can trigger data prefetching upon detecting a sequential read pattern and after executing a second threshold number of commands Y (e.g., Y additional sequential read commands following pattern detection or Y total sequential read commands). Detection of a sequential pattern can be independent of the command length of the sequential read commands (e.g., to support any block size used for read operations, such as a maximum buffer size of 1280 kilobytes (kB)). Alternatively, the detection sequence pattern may be independent of memory die misalignment.

[0076] The memory system can use logical address list 315 to track sequential read information. For example, the memory system can receive and execute a first read command 305-a and a second read command 305-b. The memory system can determine whether the second read command 305-b follows the first read command 305-a. A “sequential” read command can correspond to a read command that begins a read operation at an LBA immediately following the last LBA read by the read operation for the previous read command. For example, if the first read command 305-a indicates a start LBA value of 0 and a command length of 512kB (e.g., 128 LBA in the case where LBA corresponds to 4kB), then the last LBA read by the first read command 305-a can be LBA 127. Accordingly, if the second read command 305-b indicates a start LBA value of 128, then the second read command 305-b can follow the first read command 305-a. The memory system may store the LBA 320 (e.g., start LBA or end LBA) of sequential read commands 305 in a logical address list 315. For example, the memory system may determine and store the end LBA 320-a of the first read command 305-a and the end LBA 320-b of the second read command 305-b in the logical address list 315. Alternatively, the memory system may store the start LBA 320-a of the first read command 305-a and the start LBA 320-b of the second read command 305-b, as well as an indication of the command length of the first read command 305-a and the second read command 305-b. In some cases, the memory system may store the command length specific to each read command 305 having a corresponding LBA 320. In some other cases, the memory system may store the default command length of the read commands 305 in the command set 300.

[0077] If the memory system receives a similar write command, it may prevent the sequence mode count from being reset. For example, the memory system may receive and execute similar write command 310-a, similar write command 310-b, or both. The memory system may prevent the mode detection from being reset until a read command (or set of read commands) that fails the sequence condition is received. If the memory system receives a read command 305 following one or more intermediate similar write commands 310, it may check whether the start LBA 320 of this next read command 305-c is after the previous read command 305-b (e.g., due to the memory system saving the read command data of the previous read command 305-b before processing one or more similar write commands 310). The memory system may use information stored in the logical address list 315 (e.g., the LBA 320-b of the most recently executed read command in the sequence mode) to determine whether the read command 305-c following one or more similar write commands 310 is after the previous read command 305-b. In some cases, the memory system can implement Equation 1 to determine whether a new read command 305-c has failed in sequential mode:

[0078] WewCommand·lba! =PreCommand·lba+PreCommand·tranferlen (1)

[0079] PreCommand can correspond to the previous sequential read command 305-b, NewCommand can correspond to the new read command 305-c, lba can indicate the start of each command LBA 320, and transferlen can indicate the command length.

[0080] If the new read command 305-c fails to pass the sequential pattern, the memory system may reset the sequential pattern detection count and, in some cases, remove or overwrite the sequence information stored in the logical address list 315. If the read command 305-c follows the sequential pattern, the memory system may increment the sequential pattern detection count (e.g., to avoid resetting the count in response to an intermediate similar write command 310) and may add the LBA 320-c, command length, or both of the new read command 305-c to the logical address list 315. In some instances, the memory system may determine that a sequential pattern was detected in response to a sequential read command 305-c following one or more similar write commands 310. In some other instances, the memory system may determine whether the count value meets a sequential pattern detection threshold X.

[0081] By maintaining the count of sequential pattern detection using logical address list 315 and disregarding any intermediary similar write commands 310, even if command set 300 contains a mixture of read commands 305 and similar write commands 310, the memory system can still trigger data prefetching (e.g., prefetching) for sequential read commands 305 without waiting for the number of consecutive read commands (without any intermediary similar write commands 310) to meet the X threshold. Therefore, the memory system can operate using prefetching techniques for a larger time proportion (e.g., compared to a system without logical address list 315), thereby improving memory system performance. Additionally, the memory system can prevent the discarding of prefetched data from buffers or caches during the execution of similar write commands 310 to support efficient execution of sequential read commands 305 following similar write commands 310.

[0082] In some instances, if the memory system receives a non-sequential read command 305-d, the memory system can reset the sequential pattern detection count. For example, the memory system can set the count to zero, remove the stored information for the sequential read command 305 from logical address list 315, or both. In other instances, the memory system can support a threshold number of non-sequential read commands without losing sequential pattern tracking. For example, the memory system can determine that read command 305-d precedes read command 305-c. The memory system can prevent the sequential pattern detection count from being incremented but can maintain the information associated with the sequential read command 305 in logical address list 315. If a subsequent read command 305-e follows the latest sequential read command 305-c, the memory system can increment the count, store the LBA 320-d of the sequential read command 305-e, the command length, or both in logical address list 315, or both. Accordingly, the memory system can accommodate up to a threshold number of non-sequential read commands 305 without losing track of sequential patterns (e.g., to handle a one-time or relatively small number of non-sequential read commands 305 interleaved within a sequential pattern of read commands 305).

[0083] Figure 4 This document describes an example of a process flow 400 that supports the use of pattern detection prefetching information, based on the examples disclosed herein. Process flow 400 may be provided by a memory system (e.g., reference...). Figure 1 and 2 The memory system described (110 or 210) executes this. The memory system can use a logical address list to track sequential read commands, as shown in the reference. Figures 1 to 3As described. By using a logical address list, a memory system can maintain read command pattern detection regardless of one or more intermediary similar write commands, non-sequential read commands, or both. In some cases, alternative instances can be implemented, some of which may be performed in a different order than described or not at all. Additionally or alternatively, operations may include additional features not mentioned below, or other procedures may be added.

[0084] At 405, a set of commands is received. For example, the memory system may receive a set of commands from the host system, comprising one or more read commands and one or more similar write commands. Each of the similar write commands may be associated with at least one corresponding write operation performed by the memory device. For example, the one or more similar write commands may include write commands, unmapping commands, formatting unit commands, security protocol output commands, start / stop unit commands, or any combination thereof.

[0085] At 410, a list of logical addresses is stored. For example, the memory system may store a list of logical addresses indicated by a set of read commands, based on the execution order of the read command set. The memory system may store information about the read commands in the list (e.g., in RAM) if the read commands correspond to a sequential pattern of read commands. In some instances, the memory system may store the start LBA of each identified sequential read command in the list of logical addresses. In some cases, the memory system may store a list of corresponding transfer lengths of the read command set together with the list of logical addresses. Alternatively, the memory system may determine a common transfer length of the read command set and may store an indication of the common transfer length together with the list of logical addresses.

[0086] At address 415, a read command is received. For example, the memory system can receive an additional read command after storing the information of the previous sequential read command in the logical address list.

[0087] At 420, it is determined whether the logical address list corresponds to a sequential pattern. For example, the memory system may use the logical address indicated by the read command set, the corresponding transfer length of the read command set, or both to determine whether the logical address list corresponds to a sequential pattern of read commands. In some instances, the memory system may use the logical address list to determine whether the number of sequential read commands in the read command set meets a pattern detection threshold (e.g., X). In some cases, the memory system may track the count of sequential read commands and compare the tracked count to the pattern detection threshold. In other cases, the logical address list may contain a number of time slots equal to the pattern detection threshold, and the memory system may determine whether the list corresponds to a sequential pattern of read commands based on whether each time slot in the list stores a sequential logical address.

[0088] If the memory system determines that the logical address list corresponds to a sequential pattern, then at 425, data for a read command is prefetched. For example, the memory system may prefetch (e.g., pre-fetch) data from the memory device according to the sequential pattern for a subsequent read command. The memory system may read data from the memory device by predicting the data indicated by the subsequent read command before executing the subsequent read command, according to the sequential pattern. For example, the memory system may execute a prefetch command indicating the next LBA according to the sequential pattern and may store the retrieved data in a cache or buffer. In some instances, the memory system may track a second count value for the sequential read command in response to determining that the logical address list corresponds to a sequential pattern and may trigger the prefetch if the second count value satisfies a second threshold (e.g., Y) for prefetch triggering. The memory system may use the prefetched data during the execution of the subsequent read command to reduce execution latency.

[0089] If the memory system determines that the logical address list does not correspond to a sequential pattern, then at 430, data is retrieved according to the logical address indicated by the read command. For example, the memory system may execute a read command and read data from the memory device according to the read command. In some cases, if the read command does not correspond to a sequential read command, then at 435, pattern detection may be reset. For example, the memory system may set the count value used for pattern detection to zero, remove sequential read command information from the logical address list, or both.

[0090] Various aspects of process flow 400 may be implemented by a controller and other components. Alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory system). For example, when executed by a controller (e.g., a memory system controller), the instructions may cause the controller to perform the operation of process flow 400.

[0091] Figure 5A and 5B This document describes an instance of command set 500 that supports the use of pattern detection prefetching techniques, based on the examples disclosed herein. Figure 5A This describes an example of command set 500-a that prevents table prefetching to reduce processing overhead and improve memory system efficiency. For example, see [reference needed]. Figure 1 and 2The memory system 110 or 210 described herein can receive and execute a set of commands 500-a. The memory system can store a ratio of a hibernation command 510 to other commands (e.g., a sequential read command 505) and can determine whether to prefetch an L2P mapping table based on (e.g., using) said ratio. The memory system can determine whether to prevent fetching from one or more memory devices (e.g., referenced memory) in response to comparing the stored ratio with a threshold ratio Y. Figure 1 and 2 The described memory device 130 or 240 prefetches information (e.g., an L2P mapping table).

[0092] The memory system can track the ratio of executed sleep commands 510 to other executed commands. In some instances, the other commands can be any other commands executed by the memory system. In some other instances, the other commands included in the ratio can be subsequent read commands 505. The memory system can determine that the set of read commands 505 corresponds to a sequential pattern of read commands (e.g., using a reference). Figure 3 and 4 (The described technique or other techniques may be used). For example, the memory system may execute sequential read commands that satisfy a threshold X for detecting a sequential pattern. In some cases, the memory system may store a count value for executing a sleep command 510 and a count value for executing subsequent read commands 505, and may use the stored count values ​​to calculate a ratio. In some instances, the memory system may reset the count value for the ratio based on periodicity, in response to the detection of a new sequence of read commands, in response to the detection of a change in the type of command executed at the memory system, or any combination thereof. Alternatively or concurrently, the memory system may use sleep commands executed within a sequence of read commands that satisfy sequential pattern detection to calculate the ratio.

[0093] The memory system can compare the ratio to a threshold ratio (e.g., a threshold) to prefetch a table defining the L2P mapping for the next logical address based on a sequential pattern. If the tracked ratio meets the threshold ratio, the memory system can determine to prefetch the table from one or more memory devices. However, if the tracked ratio fails to meet the threshold ratio, the memory system can prevent the prefetching of the table. For example, the ratio may not meet the threshold ratio if the ratio of sleep command 510 to other commands (e.g., sequential read command 505) is equal to or greater than the threshold ratio. In some instances, the threshold ratio may be 1 (e.g., a 1:1 ratio). In some other instances, the threshold ratio may have other values, where the value of the threshold ratio can be configured statically or determined dynamically. For example, the memory system can execute read command 505-a, sleep command 510-a, read command 505-b, sleep command 510-b, read command 505-c, sleep command 510-c, and read command 505-d. Accordingly, the memory system may store a 3:4 ratio (e.g., sleep command 510 to sequential read command 505). If the threshold ratio is 1:2, the stored ratio may not meet (e.g., be less than) the threshold ratio. Accordingly, the memory system may prevent prefetching the L2P mapping table in response to the ratio failing to meet the threshold ratio. Alternatively, the memory system may fetch or access the table during the execution of the corresponding read command. Since there are a considerable number of sleep commands 510 compared to the sequential read command 505, a memory system that prefetches the L2P table may repeatedly prefetch the table for read command 505 and clear the table from the cache in response to sleep command 510. This repeated prefetching and clearing of the L2P mapping table may involve considerable processing overhead (e.g., above the threshold) and may degrade memory system performance. Alternatively, because the memory system can prevent prefetching the table based on the tracked ratio, the memory system can reduce processing overhead and improve memory system efficiency.

[0094] Figure 5B This describes an instance of command set 500-b that supports prefetching tables to reduce latency associated with sequential read command 505. For example, see [reference needed]. Figure 1 and 2 The memory system 110 or 210 described herein can receive and execute command set 500-b. The memory system can store a ratio of hibernation command 510 to other commands (e.g., sequential read command 505) and can determine whether to prefetch an L2P mapping table based on (e.g., using) said ratio. The memory system can determine whether to prevent fetching from one or more memory devices (e.g., referenced memory) in response to comparing the stored ratio with a threshold ratio Y. Figure 1 and 2The described memory device 130 or 240 prefetches information (e.g., an L2P mapping table).

[0095] The memory system can execute read command 505-e, read command 505-f, sleep command 510-d, read command 505-g, read command 505-h, read command 505-i, and sleep command 510-e. Accordingly, the memory system can calculate and store a ratio of 2:5 between the sleep command 510 and the sequential read command 505. If the threshold ratio is 1:2, then the stored ratio can satisfy (e.g., be less than) the threshold ratio. Accordingly, the memory system can trigger L2P map table prefetching in response to the ratio satisfying the threshold ratio (e.g., in the case of detecting a sequential mode of read command 505). For example, the memory system can prefetch the table if the stored ratio is equal to 0 or less than the threshold ratio (e.g., threshold) Y. The threshold Y can be defined to distinguish between baseline cases and real-world use cases. For example, a ratio less than the threshold can enable an execution mode at the memory system, where the mode of sleep command 510 can be set as baseline and the memory system can retrieve and save the prefetched table data in holding RAM. A ratio greater than or equal to a threshold can enable a power mode at the memory system, where the mode of hibernation command 510 can be set to normal and the memory system can prevent prefetching table data. The prefetched table data is available to the memory system to support the execution of read commands in a read command sequence. For example, a prefetched L2P mapping table can define L2P mappings for one or more memory devices from which data is read. By prefetching the L2P mapping table, the memory system can reduce the latency involved in executing sequential read commands.

[0096] Figure 6 This document describes an example of a process flow 600 that supports the use of pattern detection prefetching information, based on the examples disclosed herein. Process flow 600 may be provided by a memory system (e.g., reference...). Figure 1 and 2 The memory system 110 or 210 described herein executes this. The memory system may use the ratio of hibernation commands to other commands (e.g., sequential read commands) to determine whether to prefetch information from one or more memory devices, as described in reference [reference needed]. Figure 1 , 2 As described in section 5. By tracking, storing, and using the ratio, the memory system can prevent inefficient repetition of prefetching and clearing the L2P mapping table when the memory system frequently enters a sleep state (e.g., above a threshold frequency). In some cases, alternative instances described below may be implemented, some of which may be performed in a different order than described or not at all. Additionally or alternatively, the operations may include additional features not mentioned below, or additional processes may be added.

[0097] At 605, a command set is received. For example, the memory system may receive a read command set and one or more sleep commands. The memory system may use the read command set for sequential mode detection (e.g., using references herein). Figure 3 and 4 (The described technology or other technologies may be used). A hibernation command can trigger the memory system to enter a hibernation state (e.g., H8 state, where the memory system reduces processing power). For example, executing a hibernation command may involve the memory system clearing data from the cache (e.g., clearing it to the memory device) and entering a low-power state.

[0098] At 610, a read command is received. The memory system may receive a read command from the host system. At 615, it is determined whether the read command corresponds to a sequential pattern. For example, the memory system may determine whether the executed read command meets a threshold used for sequential pattern detection.

[0099] If a read command does not correspond to a sequential mode, then at 620, mode detection can be reset. For example, the memory system can reset the counter value used for mode detection if the received read command precedes a previous read command. Alternatively, the memory system can reset one or more counter values, ratios, or both to track the number of sleep commands.

[0100] If the read command corresponds to a sequential pattern, then at 625, it is determined whether to prefetch the L2P mapping table. For example, the memory system may use the corresponding LBA indicated by the read command set, the corresponding transfer length of the read command set, or both, to detect the sequential pattern of the logical address. The memory system may determine whether to prefetch the table from the memory device according to the sequential pattern using a comparison between a threshold (e.g., a threshold ratio, such as 1:1) for prefetching the table defining the L2P address mapping for the next logical address and a ratio tracked by the memory system. The ratio tracked by the memory system may be the ratio of sleep commands to sequential read commands in the command set received at 605. For example, to track the ratio, the memory system may increment a first count value for each sequential read command and increment a second count value for each of one or more sleep commands, wherein the ratio is calculated using the second count value and the first count value.

[0101] If the ratio fails to meet the threshold for prefetching the table, then at 630, the L2P mapping table is retrieved during read command execution. For example, the memory system may prevent table prefetching before executing the read command received at 610 due to the ratio failing to meet the threshold. Alternatively, the memory system may fetch (e.g., read or access) the table during read command execution. At 635, the read command is executed using the L2P mapping table. For example, the memory system may use the L2P mapping defined by the fetched table to retrieve data from the memory device for the read command.

[0102] If the ratio satisfies a threshold for prefetching the table, then at 640, the L2P mapping table is prefetched before the read command is executed. For example, the memory system may prefetch the table before executing the read command received at 610, attributable to the ratio satisfying the threshold. The memory system may store the prefetched table in a cache. At 645, the read command is executed using the prefetched L2P mapping table. For example, the memory system may retrieve data for the read command from the memory device using the L2P mapping defined by the prefetched table stored in the cache.

[0103] Aspects of process flow 600 may be implemented by a controller and other components. Alternatively, aspects of process flow 600 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory system). For example, when executed by a controller (e.g., a memory system controller), the instructions may cause the controller to perform the operation of process flow 600.

[0104] Figure 7 A block diagram 700 illustrates a memory system 720 supporting a technique for using pattern detection prefetching information, according to an example disclosed herein. The memory system 720 may be as described in the reference... Figures 1 to 6 Examples of aspects of the described memory system. Memory system 720 or its various components may be examples of means for performing various aspects of the techniques described herein using pattern detection and prefetching information. For example, memory system 720 may include command receiving component 725, listing component 730, pattern detection component 735, prefetching component 740, command execution component 745, counter tracker 750, cache component 755, data retrieval component 760, table retrieval component 765, clearing component 770, hibernation component 775, sequence reset component 780, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0105] Memory system 720 may include a memory device and a controller coupled to the memory device. The controller may cause memory system 720 to perform one or more operations as described herein with reference to one or more of the components. Command receiving component 725 may be configured to, or otherwise support means for receiving a plurality of read commands and one or more similar write commands from a host system, each of the one or more similar write commands being associated with at least one corresponding write operation performed on the memory device. Listing component 730 may be configured to, or otherwise support means for storing a list of logical addresses indicated by the plurality of read commands according to the execution order of the plurality of read commands. Pattern detection component 735 may be configured to, or otherwise support means for determining whether the list of logical addresses corresponds to a sequential pattern, at least in part based on (e.g., using) the logical addresses indicated by the plurality of read commands, the corresponding transfer lengths of the plurality of read commands, or both. The prefetch component 740 may be configured or otherwise support means for prefetching data from the memory device for use in subsequent read commands, at least in part based on (e.g., in response to) determining that the logical address list corresponds to the sequential pattern.

[0106] In some instances, the pattern detection component 735 may be configured or otherwise support means for determining, at least in part, based on (e.g., using) the logical address list, that the operation of determining the logical address list corresponding to the sequential pattern is at least in part based on (e.g., in response to) the number of sequential read commands satisfying the pattern detection threshold.

[0107] In some instances, to support receiving the plurality of read commands and the one or more similar write commands, the command receiving component 725 may be configured or otherwise supported to provide means for receiving a first subset of sequential read commands and, following the first subset of sequential read commands, receiving at least one similar write command for execution. In some such instances, the command receiving component 725 may be configured or otherwise supported to provide means for receiving a second subset of sequential read commands for execution following the at least one similar write command, wherein the first read command in the second subset of sequential read commands is ordered after the last read command in the first subset of sequential read commands. The pattern detection component 735 may be configured or otherwise supported to provide means for determining, at least in part, based on (e.g., in response to) that the first read command in the second subset of sequential read commands is ordered after the last read command in the first subset of sequential read commands, to determine that the number of sequential read commands includes both the first subset and the second subset of sequential read commands.

[0108] In some instances, the command receiving component 725 may be configured or otherwise supported to provide means for receiving a first read command indicating a first logical address and a first command length. In some instances, the command receiving component 725 may be configured or otherwise supported to provide means for receiving one or more second read commands after the first read command, the one or more second read commands indicating a corresponding second logical address preceding the first logical address according to the first command length, wherein the number of the one or more second read commands satisfies a threshold for reset pattern detection. In some instances, the sequence reset component 780 may be configured or otherwise supported to provide means for resetting the number of sequential read commands at least in part based on (e.g., in response to) the one or more second read commands preceding the first read command and the number of the one or more second read commands satisfying the threshold for reset pattern detection.

[0109] In some instances, the count tracker 750 may be configured or otherwise supported as means for tracking count values ​​for sequential read commands, wherein determining that the number of sequential read commands satisfies the pattern detection threshold is based at least in part on (e.g., in response to) the count values ​​satisfying the pattern detection threshold.

[0110] In some instances, the logical address list contains a number of time slots equal to the pattern detection threshold, and determining that the number of sequential read commands satisfies the pattern detection threshold is based at least in part on (e.g., in response to) storing sequential logical addresses for each time slot of the logical address list.

[0111] In some instances, the counter tracker 750 may be configured or otherwise supported for means of tracking a second counter value for sequential read commands, at least in part based on (e.g., in response to) determining that the logical address list corresponds to the sequence pattern. In some instances, the prefetch component 740 may be configured or otherwise supported for means of triggering the prefetch at least in part based on (e.g., in response to) the second counter value satisfying a second threshold for prefetch triggering.

[0112] In some instances, cache component 755 may be configured or otherwise supported to store the prefetched data in a cache prior to executing the subsequent read command, based at least in part on (e.g., in response to) determining that the logical address list corresponds to the sequence pattern. In some instances, command execution component 745 may be configured or otherwise supported to execute the subsequent read command. In some instances, cache component 755 may be configured or otherwise supported to retrieve the prefetched data from the cache for use in the executed subsequent read command, based at least in part on (e.g., in response to) the subsequent read command satisfying the sequence pattern.

[0113] In some instances, the list component 730 may be configured or otherwise supported as means for storing, together with the logical address list, the respective transfer lengths of the plurality of read commands.

[0114] In some instances, the list component 730 may be configured or otherwise support means for determining the common transfer length of the plurality of read commands. In some instances, the list component 730 may be configured or otherwise support means for storing an indication of the common transfer length together with the logical address list.

[0115] In some instances, the logical address list is stored in RAM (e.g., an SRAM cache). In some instances, one or more similar write commands may include write commands, unmapping commands, format cell commands, security protocol output commands, start / stop cell commands, or any combination thereof.

[0116] In some instances, to support the prefetching of data from the memory device for subsequent read commands, the prefetch component 740 may be configured or otherwise support means for executing a prefetch command that indicates the next LBA according to the sequence pattern.

[0117] Alternatively or concurrently, the command receiving component 725 may be configured to or otherwise support means for receiving a plurality of read commands and one or more sleep commands. In some instances, the pattern detection component 735 may be configured to or otherwise support means for detecting a logical address sequence pattern based at least in part on (e.g., according to) the corresponding logical address indicated by the plurality of read commands, the corresponding transfer length of the plurality of read commands, or both. In some instances, the prefetch component 740 may be configured to or otherwise support means for determining whether to prefetch the table from the memory device according to the sequence pattern based at least in part on (e.g., in response to) comparing a threshold for prefetching a table defining an L2P address mapping for the next logical address with a ratio, the ratio being the ratio of sleep commands to sequential read commands among the plurality of read commands. The command execution component 745 may be configured to or otherwise support means for executing a subsequent read command based at least in part on (e.g., in response to) determining whether to prefetch the table.

[0118] In some instances, the prefetch component 740 may be configured or otherwise supported to prefetch the table at least in part based on (e.g., in response to) the ratio satisfying the threshold for prefetching the table before executing the subsequent read command. In some instances, the cache component 755 may be configured or otherwise supported to store the prefetched table in a cache, wherein, in order to execute the subsequent read command, the data retrieval component 760 may be configured or otherwise supported to retrieve the data from the memory device for the executed subsequent read command at least in part based on (e.g., using) an L2P address mapping defined by the prefetched table stored in the cache.

[0119] In some instances, table retrieval component 765 may be configured or otherwise supported to prevent prefetching of the table prior to execution of the subsequent read command, based at least in part on (e.g., in response to) the ratio failing to meet the threshold for prefetching the table, wherein, in order to execute the subsequent read command, table retrieval component 765 may be configured or otherwise supported to retrieve the table at least in part on (e.g., in response to) the execution of the subsequent read command. In some instances, data retrieval component 760 may be configured or otherwise supported to retrieve data from the memory device for the executed subsequent read command, based at least in part on (e.g., using) the L2P address mapping defined by the retrieved table.

[0120] In some instances, command execution component 745 may be configured or otherwise support means for executing the hibernation command among the one or more hibernation commands. In some instances, clear component 770 may be configured or otherwise support means for clearing data from the cache to the memory device, at least in part based on (e.g., in response to) the execution of the hibernation command. In some instances, hibernation component 775 may be configured or otherwise support means for entering a low-power state, at least in part based on (e.g., in response to) the execution of the hibernation command.

[0121] In some instances, the counter tracker 750 may be configured or otherwise supported to increment a first count value for each of the plurality of read commands. In some instances, the counter tracker 750 may be configured or otherwise supported to increment a second count value for each of the one or more sleep commands, wherein the ratio is determined (e.g., calculated using the second count value and the first count value) based at least in part on the second count value and the first count value.

[0122] In some instances, the threshold used to prefetch the table may be a threshold ratio of 1:1.

[0123] Figure 8 A flowchart illustrating a method 800 for supporting pattern detection prefetching information according to examples disclosed herein is shown. The operation of method 800 may be implemented by a memory system or its components as described herein. For example, the operation of method 800 may be implemented by, as referenced... Figures 1 to 7 The memory system described herein performs the functions described. In some instances, the memory system may execute a set of instructions to control the functional elements of the system to perform the functions described below. Alternatively, the memory system may use dedicated hardware to perform aspects of the functions described below.

[0124] At 805, the method may include receiving a plurality of read commands and one or more similar write commands from a host system, each of the one or more similar write commands being associated with at least one corresponding write operation performed on the memory device. The operation at 805 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described aspect of the command receiving component 725 performing the operation of 805.

[0125] At 810, the method may include storing a list of logical addresses indicated by the plurality of read commands according to the execution order of the read commands. The operation at 810 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described list component 730 performs the operation of 810.

[0126] At 815, the method may include determining whether the list of logical addresses corresponds to a sequential pattern based at least in part on (e.g., using) the logical addresses indicated by the plurality of read commands, the corresponding transfer lengths of the plurality of read commands, or both. The operation of 815 can be performed according to the examples disclosed herein. In some instances, it can be referenced... Figure 7 The described pattern detection component 735 performs the operation of 815.

[0127] At 820, the method may include prefetching data from the memory device for use in subsequent read commands, at least in part based on (e.g., in response to) determining that the logical address list corresponds to the sequential pattern. The operation of 820 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described aspect of the prefetch component 740 performing the operation of 820.

[0128] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving a plurality of read commands and one or more similar write commands from a host system, each of the one or more similar write commands being associated with at least one corresponding write operation performed by the memory device; storing a list of logical addresses indicated by the plurality of read commands according to the execution order of the plurality of read commands; determining whether the list of logical addresses corresponds to a sequential mode based at least in part on (e.g., using) the logical addresses indicated by the plurality of read commands, the corresponding transfer length of the plurality of read commands, or both; and prefetching data from the memory device for use in subsequent read commands based at least in part on (e.g., in response to) determining that the list of logical addresses corresponds to the sequential mode.

[0129] Some examples of the method 800 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining, at least in part, based on (e.g., according to) the logical address list, that the number of sequential read commands among the plurality of read commands satisfies a pattern detection threshold, wherein the operation of determining that the logical address list corresponds to the sequential pattern may be at least in part based on (e.g., in response to) the number of sequential read commands satisfying the pattern detection threshold.

[0130] In some instances of the method 800 and apparatus described herein, operations, features, circuitry, logic, means, or instructions for receiving the plurality of read commands and one or more similar write commands may include operations, features, circuitry, logic, means, or instructions for: receiving a first subset of sequential read commands; receiving at least one similar write command after the first subset of sequential read commands for execution; receiving a second subset of sequential read commands for execution after the at least one similar write command, wherein a first read command in the second subset of sequential read commands may be ordered after the last read command in the first subset of sequential read commands; and determining the number of sequential read commands to include both the first subset of sequential read commands and the second subset of sequential read commands, at least in part based on (e.g., in response to) the first read command in the second subset of sequential read commands being ordered after the last read command in the first subset of sequential read commands.

[0131] Some examples of the methods 800 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: receiving a first read command indicating a first logical address and a first command length; receiving one or more second read commands after the first read command, the one or more second read commands indicating a corresponding second logical address preceding the first logical address according to the first command length, wherein the number of the one or more second read commands satisfies a threshold for resetting pattern detection; and resetting the sequential read command count at least in part based on (e.g., in response to) the one or more second read commands preceding the first read command and the number of the one or more second read commands satisfying the threshold for resetting pattern detection.

[0132] Some examples of the methods 800 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for tracking count values ​​for sequential read commands, wherein determining that the number of sequential read commands satisfies the pattern detection threshold may be based at least in part on (e.g., in response to) the count values ​​satisfying the pattern detection threshold.

[0133] In some instances of the method 800 and device described herein, the logical address list contains a number of time slots equal to the pattern detection threshold, and determining that the number of sequential read commands satisfies the pattern detection threshold may be based at least in part on (e.g., in response to) storing sequential logical addresses for each time slot of the logical address list.

[0134] Some instances of the method 800 and device described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: tracking a second count value for sequential read commands based at least in part on (e.g., in response to) determining that the logical address list corresponds to the sequential pattern, and triggering the prefetch based at least in part on (e.g., in response to) the second count value satisfying a second threshold for prefetch triggering.

[0135] Some instances of the method 800 and apparatus described herein may additionally include operations, features, circuitry, logic, means, or instructions for: storing the prefetched data in a cache prior to executing the subsequent read command, based at least in part on (e.g., in response to) determining that the logical address list corresponds to the sequence pattern; executing the subsequent read command; and retrieving the prefetched data from the cache for use in the executed subsequent read command, based at least in part on (e.g., attribution) that the subsequent read command satisfies the sequence pattern.

[0136] Some instances of the method 800 and device described herein may additionally include operations, features, circuit systems, logic, means, or instructions for storing a list of the respective transmission lengths of the plurality of read commands together with the list of logical addresses.

[0137] Some instances of the method 800 and device described herein may additionally include operations, features, circuitry, logic, means, or instructions for determining a common transmission length of the plurality of read commands and storing an indication of the common transmission length together with the logical address list.

[0138] In some instances of the method 800 and device described herein, the logical address list may be stored in RAM.

[0139] In some instances of the method 800 and device described herein, one or more similar write commands may include write commands, unmapping commands, format unit commands, security protocol output commands, start / stop unit commands, or any combination thereof.

[0140] In some instances of the method 800 and apparatus described herein, prefetching data from the memory device for the subsequent read command may include operations, features, circuitry, logic, means, or instructions for executing a prefetch command that indicates the next LBA according to the sequence pattern.

[0141] Figure 9A flowchart illustrating a method 900 for supporting pattern detection prefetching information according to an example disclosed herein is shown. The operation of method 900 may be implemented by a memory system or its components as described herein. For example, the operation of method 900 may be implemented by, as referenced... Figures 1 to 7 The memory system described herein performs the functions described. In some instances, the memory system may execute a set of instructions to control the functional elements of the system to perform the functions described below. Alternatively, the memory system may use dedicated hardware to perform aspects of the functions described below.

[0142] At 905, the method may include receiving multiple read commands and one or more sleep commands. The operation at 905 can be performed according to the examples disclosed herein. In some instances, it may be provided by reference. Figure 7 The described aspect of the command receiving component 725 performing the operation 905.

[0143] At 910, the method may include determining whether the list of logical addresses corresponds to a sequential pattern based at least in part on (e.g., using) the logical addresses indicated by the plurality of read commands, the corresponding transfer lengths of the plurality of read commands, or both. The operation of 910 can be performed according to the examples disclosed herein. In some instances, it can be referenced... Figure 7 The described pattern detection component 735 performs the operation of 910.

[0144] At 915, the method may include determining, at least in part, whether to prefetch the table from the memory device according to the sequential pattern based on (e.g., in response to) comparing a threshold for prefetching a table defining an L2P address mapping for the next logical address with a ratio, the ratio being the ratio of sleep commands to sequential read commands among the plurality of read commands. The operation of 915 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described aspect of the prefetch component 740 performing the operation 915.

[0145] At 920, the method may include performing a subsequent read command based at least in part on (e.g., in response to) determining whether to prefetch the table. The operation at 920 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The command execution component 745 described performs the operation of 920.

[0146] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: receiving a plurality of read commands and one or more sleep commands; determining, at least in part, whether the list of logical addresses corresponds to a sequential pattern based on the logical address indicated by the plurality of read commands, the corresponding transfer length of the plurality of read commands, or both; determining, at least in part, whether to prefetch the table from the memory device according to the sequential pattern based on a ratio of sleep commands to sequential read commands among the plurality of read commands, based on a threshold for prefetching a table defining an L2P address mapping for the next logical address, at least in part; and executing subsequent read commands based at least in part on determining whether to prefetch the table.

[0147] Some instances of the method 900 and apparatus described herein may additionally include operations, features, circuitry, logic, means, or instructions for: prefetching the table prior to executing the subsequent read command, based at least in part on (e.g., in response to) the ratio satisfying the threshold for prefetching the table; and storing the prefetched table in a cache, wherein executing the subsequent read command may include operations, features, circuitry, logic, means, or instructions for: retrieving the data from the memory device for the executed subsequent read command, based at least in part on (e.g., using) the L2P address mapping defined by the prefetched table stored in the cache.

[0148] Some instances of the method 900 and apparatus described herein may additionally include operations, features, circuitry, logic, means, or instructions for: preventing the prefetching of the table prior to execution of the subsequent read command, at least in part based on (e.g., in response to) the ratio failing to meet the threshold for prefetching the table, wherein execution of the subsequent read command may include operations, features, circuitry, logic, means, or instructions for: fetching the table at least in part based on (e.g., in response to) execution of the subsequent read command; and retrieving the data from the memory device for use in the executed subsequent read command, at least in part based on (e.g., using) the L2P address mapping defined by the fetched table.

[0149] Some examples of the methods 900 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: executing a sleep command among the one or more sleep commands; at least in part based on (e.g., in response to) executing the sleep command, clearing data from a cache to the memory device; and at least in part based on (e.g., in response to) executing the sleep command, entering a low-power state.

[0150] Some examples of the method 900 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: incrementing a first count value for each of the plurality of read commands in a sequential read command; and incrementing a second count value for each of the one or more sleep commands, wherein the ratio may be determined at least in part based on (e.g., using) the second count value and the first count value.

[0151] In some instances of the method 900 and device described herein, the threshold used to prefetch the table may be a threshold ratio of 1:1.

[0152] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0153] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, which may have various bit widths.

[0154] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0155] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0156] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0157] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0158] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0159] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly responding to" such other condition or action.

[0160] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0161] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., most charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0162] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0163] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0164] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0165] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0166] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list followed by phrases such as "at least one of..." or "one or more of..."), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0167] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0168] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising: a memory device; and a controller coupled with the memory device and configured to cause the apparatus to: receive a plurality of read commands and one or more write-like commands from a host system, each of the one or more write-like commands associated with at least one corresponding write operation by the memory device; store a list of logical addresses indicated by a first subset of read commands of the plurality of read commands and a second subset of read commands of the plurality of read commands according to an order of execution of the plurality of read commands, wherein the list of logical addresses is stored based at least in part on the first subset of read commands and the second subset of read commands being spaced apart by at least one of the one or more write-like commands; determine whether the list of logical addresses corresponds to a sequential pattern based at least in part on the logical addresses indicated by the first subset of read commands and the second subset of read commands, respective transfer lengths of the plurality of read commands, or both; and based at least in part on determining that the list of logical addresses corresponds to the sequential pattern, prefetch data from the memory device for use in a subsequent read command.

2. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: determine that a quantity of sequential read commands of the plurality of read commands satisfies a pattern detection threshold based at least in part on the list of logical addresses, wherein the controller is configured to cause the apparatus to determine that the list of logical addresses corresponds to the sequential pattern based at least in part on the quantity of sequential read commands satisfying the pattern detection threshold.

3. The apparatus of claim 2, wherein to receive the plurality of read commands and the one or more write-like commands, the controller is configured to cause the apparatus to: receive the first subset of read commands, wherein the first subset of read commands comprises sequential read commands; receive the at least one write-like command for execution after the first subset of read commands; receive the second subset of read commands for execution after the at least one write-like command, wherein the second subset of read commands comprises sequential read commands, and wherein a first read command of the second subset of read commands follows a last read command of the first subset of read commands; and determine that the quantity of sequential read commands comprises the first subset of read commands and the second subset of read commands based at least in part on the first read command of the second subset of read commands following the last read command of the first subset of read commands.

4. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: receive a first read command indicating a first logical address and a first command length; receiving one or more second read commands after the first read command, the one or more second read commands indicating respective second logical addresses that precede the first logical address according to the first command length, wherein a quantity of the one or more second read commands satisfies a threshold for reset mode detection; and resetting the sequential read command quantity based at least in part on the one or more second read commands preceding the first read command and the quantity of the one or more second read commands satisfying the threshold for reset mode detection.

5. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: track a count value for sequential read commands, wherein the controller is configured to cause the apparatus to determine that the sequential read command quantity satisfies the mode detection threshold based at least in part on the count value satisfying the mode detection threshold.

6. The apparatus of claim 2, wherein the list of logical addresses comprises a number of slots equal to the mode detection threshold, and wherein the controller is configured to cause the apparatus to determine that the sequential read command quantity satisfies the mode detection threshold based at least in part on each slot of the list of logical addresses storing a sequential logical address.

7. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: track a second count value for sequential read commands based at least in part on determining that the list of logical addresses corresponds to the sequential pattern; and trigger the prefetch based at least in part on the second count value satisfying a second threshold for a prefetch trigger.

8. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: store data of the prefetch in a cache prior to executing the subsequent read command based at least in part on determining that the list of logical addresses corresponds to the sequential pattern; execute the subsequent read command; and retrieve the prefetched data from the cache for the executed subsequent read command based at least in part on the subsequent read command satisfying the sequential pattern.

9. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: store a list of the respective transfer lengths of the plurality of read commands with the list of logical addresses.

10. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: determine a common transfer length of the plurality of read commands; and store an indication of the common transfer length with the list of logical addresses.

11. The apparatus of claim 1, wherein: the controller is configured to cause the apparatus to store the list of logical addresses in a random access memory.

12. The apparatus of claim 1, wherein the one or more similar write commands comprise a write command, an unmap command, a format unit command, a secure protocol output command, a start stop unit command, or any combination thereof.

13. The apparatus of claim 1, wherein to prefetch the data from the memory device for the subsequent read command, the controller is configured to cause the apparatus to: execute a prefetch command that is next in a sequence of logical block addresses according to the sequence pattern indication.

14. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a plurality of read commands and one or more similar write commands from a host system, each of the one or more similar write commands associated with at least one corresponding write operation by a memory device; store a list of logical addresses indicated by a first subset of read commands among the plurality of read commands and a second subset of read commands among the plurality of read commands according to an order of execution of the plurality of read commands, wherein the list of logical addresses is stored based at least in part on the first subset of read commands and the second subset of read commands being spaced apart by at least one of the one or more similar write commands; determine whether the list of logical addresses corresponds to a sequential pattern based at least in part on the logical addresses indicated by the first subset of read commands and the second subset of read commands, respective transfer lengths of the plurality of read commands, or both; and prefetch data from the memory device for a subsequent read command based at least in part on determining that the list of logical addresses corresponds to the sequential pattern. ​ ​ ​ ​ ​ ​

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