An in-memory computing array and application circuitry thereof

Abstract

The application relates to an in-memory computing array and an application circuit thereof. The in-memory computing array comprises an input end, a signal processing column, a weight storage column and a comparator; the signal processing column is connected with the input end; the comparator is connected with the signal processing column and the weight storage column, so as to generate a comparison result based on a first output level signal and a second output level signal. Through the simple structure of the signal processing column, the weight storage column and the comparator, time in-memory computing can be realized. The simple structure can ensure that the array area of the in-memory computing is small, the data transmission rate can be improved, and the operation speed can be improved. When applied to classifier operation in a neural network, based on the above structure, the operation speed of the classifier can be improved, and the running speed of the neural network can be further improved.

Description

Technical Field

[0001] This invention relates to the field of electronic unit technology, and in particular to an in-memory computing array and its application circuit. Background Technology

[0002] In neural networks, classifiers have wide applications, typically serving as the last layer. Classifiers distinguish whether input image data and the target object belong to the same class. As the speed requirements for edge computing in neural network classifiers increase, the von Neumann architecture has gradually reached its bottleneck. This led to the concept of in-memory computing, which adds computational structures to existing memory arrays, enabling multiplication and accumulation calculations within the array and significantly reducing power consumption. However, existing in-memory computing methods, when used to accelerate neural network classifiers, are limited by area and cannot achieve satisfactory parallel speeds. Summary of the Invention

[0003] The purpose of this invention is to provide a simple in-memory computing array and its application circuit, which can improve computing speed with a smaller structural area. Furthermore, in accelerating classifier operations in neural networks, it can improve the classifier's computing speed, thereby further enhancing the operating speed of the neural network.

[0004] To achieve the above objectives, the present invention provides the following solution:

[0005] An in-memory computing array, comprising:

[0006] The input terminal is used to acquire the input signal;

[0007] A signal processing column, connected to the input terminal, is used to store first weight data and generate a first output level signal based on the input signal and the first weight data;

[0008] A weight storage column is used to store second weight data and generate a second output level signal based on the second weight data;

[0009] A comparator, connected to the signal processing column and the weight storage column, is used to generate a comparison result based on the first output level signal and the second output level signal.

[0010] Preferably, the signal processing column includes:

[0011] Multiple SRAM cells are provided, with each bit line of the SRAM cell connected to the comparator and each word line of the SRAM cell connected to the input terminal.

[0012] Preferably, the input terminal includes:

[0013] Multiple input signals, each of which corresponds one-to-one with a word line of a SRAM cell.

[0014] Preferably, when the input signal obtained at the input terminal is 1, the SRAM cell storing weight data of 0 in the signal processing column is discharged, and the signal processing column generates the first output level signal.

[0015] Preferably, the weight storage column includes:

[0016] Multiple SRAM cells are provided, with each SRAM cell's bit line connected to the comparator and each SRAM cell's word line used for weighted storage control.

[0017] Preferably, the bit lines of the SRAM cells in the weight storage column are discharged according to the number of weights 0 stored in the SRAM cells to generate the second output level signal.

[0018] Preferably, when the first output level signal is higher than the second output level signal, the comparator generates a comparison result of 1, and when the first output level signal is lower than the second output level signal, the comparator generates a comparison result of 0.

[0019] An application circuit for an in-memory computing array includes: a neural network model and the in-memory computing array provided above;

[0020] The input end of the in-memory computing array is connected to the fully connected layer of the neural network model; the weight storage column of the in-memory computing array is used to store the trained neural network parameters.

[0021] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0022] The in-memory computing array and its application circuit provided by this invention can realize in-memory computing by setting up a simple structure of signal processing column, weight storage column and comparator. Moreover, the simple structure can ensure that the array area of ​​in-memory computing is small, and at the same time, the data transmission rate can be improved, thereby improving the computing speed. When applied to classifier computing in neural networks, it can improve the computing speed of classifiers, thereby further improving the running speed of neural networks. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the in-memory computing array provided by the present invention.

[0025] Explanation of reference numerals in the attached figures:

[0026] 1-Input terminal, 2-Signal processing column, 3-Weight storage column, 4-Comparator. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] The purpose of this invention is to provide a simple in-memory computing array and its application circuit, which can improve computing speed with a smaller structural area. Furthermore, in accelerating classifier operations in neural networks, it can improve the classifier's computing speed, thereby further enhancing the operating speed of the neural network.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] The in-memory computing array provided by the present invention includes: an input terminal 1, a signal processing column 2, a weight storage column 3, and a comparator 4.

[0031] Input terminal 1 is used to acquire the input signal.

[0032] Signal processing column 2 is connected to input terminal 1. Signal processing column 2 stores first weight data and generates a first output level signal based on the input signal and the first weight data. The first weight data is used for inference. The first output level signal represents the accumulated calculation level of signal processing column 2.

[0033] Weight storage column 3 is used to store the second weight data and generate a second output level signal based on the second weight data. The second weight data is used for comparison.

[0034] Comparator 4 is connected to signal processing column 2 and weight storage column 3. Comparator 4 is used to generate a comparison result based on the first output level signal and the second output level signal. For example, when the first output level signal is higher than the second output level signal, the comparison result generated by comparator 4 is 1, and when the first output level signal is lower than the second output level signal, the comparison result generated by comparator 4 is 0.

[0035] Signal processing column 2 includes multiple SRAM cells. The bit lines of each SRAM cell are connected to comparator 4, and the word lines of each SRAM cell are connected to input terminal 1. Based on this structure, signal processing column 2 generates the first output level signal as follows: when the input signal acquired at input terminal 1 is 1, the SRAM cells in signal processing column 2 storing weight data of 0 are discharged, and signal processing column 2 generates the first output level signal.

[0036] Correspondingly, input terminal 1 is also provided with multiple input ports to input multiple input signals, and each input signal corresponds one-to-one with a word line of a multiple SRAM cell.

[0037] The weight storage column 3 includes multiple SRAM cells. The bit lines of each SRAM cell are connected to comparator 4, and the word lines of each SRAM cell are used for weight storage control. Based on this structure, the weight storage column 3 generates a second output level signal by discharging the bit lines of the SRAM cells according to the number of weights 0 stored in the SRAM cells, thus generating the second output level signal.

[0038] In addition, the present invention also provides an application circuit for an in-memory computing array, the circuit comprising: a neural network model and the in-memory computing array provided above.

[0039] The input terminal 1 of the in-memory computation array is connected to the fully connected layer of the neural network model. The weight storage column 3 of the in-memory computation array is used to store the trained neural network parameters.

[0040] The in-memory computing array obtains a result after passing through the fully connected layer. This result is then compared with the pre-trained alignment data. If the alignment is successful, the result is 1; otherwise, it is 0, thereby improving the computational speed of the neural network classifier.

[0041] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0042] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An application circuit of an in-memory computing array, characterized by, The application relates to a neural network model and an in-memory computing array. An input end of the in-memory computing array is connected with a full connection layer of the neural network model. A weight storage column of the in-memory computing array is used for storing trained neural network parameters. The in-memory computing array obtains a result after passing through the full connection layer, and compares the result with trained comparison data; if the comparison is successful, the result is 1, and if the comparison is unsuccessful, the result is 0. The in-memory computing array comprises: An input end is used for acquiring an input signal. A signal processing column is connected with the input end, is used for storing first weight data, and generates a first output level signal based on the input signal and the first weight data. A weight storage column is used for storing second weight data and generating a second output level signal based on the second weight data. A comparator is connected with the signal processing column and the weight storage column, and is used for generating a comparison result based on the first output level signal and the second output level signal. The signal processing column comprises a plurality of SRAM units; when the input signal acquired in the input end is 1, the SRAM units with stored weight data of 0 in the signal processing column are discharged, and the signal processing column generates the first output level signal. The weight storage column comprises a plurality of SRAM units; the bit lines of the SRAM units in the weight storage column are discharged according to the number of stored weight data of 0, and the second output level signal is generated. The bit line of each SRAM unit in the signal processing column is connected with the comparator, and the word line of each SRAM unit is connected with the input end.

2. The application circuit of an in-memory computing array of claim 1, wherein, The input end comprises:

3. The application circuit of an in-memory computing array of claim 2, wherein, A plurality of input signals, and the plurality of input signals correspond to the word lines of the plurality of SRAM units one by one. The bit line of each SRAM unit in the weight storage column is connected with the comparator, and the word line of each SRAM unit is used for weight storage control.

4. The application circuit of an in-memory computing array of claim 1, wherein, When the first output level signal is higher than the second output level signal, the comparison result generated by the comparator is 1; and when the first output level signal is lower than the second output level signal, the comparison result generated by the comparator is 0.

5. The application circuitry of the in-memory computing array of claim 1, wherein, ​

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