High-speed low-precision loss mac array based on resistive random access memory and operating method thereof

Abstract

The application provides a high-speed low-precision loss MAC array based on a resistive memory, 1T1R resistive memory storage units storing the same bit with different weights are distributed on adjacent multiple word lines; 1T1R resistive memory storage units storing different bits with the same weight are distributed on the same bit line, and are spaced by 2 n word lines; each 1T1R resistive memory storage unit comprises a transistor-resistive memory; the resistive memory comprises a resistor connected with the transistor, a word line connected with a gate end of the transistor for transmitting an input signal; a source line is connected with the 1T1R resistive memory storage unit and is used for applying a voltage to the resistor to form a bias current on the bit line; an ADC module is connected with the bit line, and the ADC module is used for converting the bias current in the bit line to form a digital MAC operation result; in this way, there is enough space to configure a higher-precision ADC module, and the use of the high-precision ADC module can realize better optimization of area and power consumption.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and more particularly to a high-speed, low-precision loss MAC array based on resistive random access memory and an operating method thereof. Background Art

[0002] Multiplication and addition (MAC) is the most important calculation method of neural network, which represents the sum of the products of two groups of numbers (A0, A1, A2…) (B0, B1, B2…) (A0·B0+A1·B1+A2·B2+…). Resistive random access memory (RRAM), as a non-volatile memory, uses the resistance state of the device to store information. When voltage is applied to both ends of the device, the input voltage and the device resistance represent 1-bit signals respectively, and the multiplication operation is realized in the form of output current. The sum of multiple output currents represents the sum of the products of multiple 1-bit input signals and 1-bit stored information, that is, the MAC operation. The MAC array based on resistive random access memory (RRAM) has the characteristics of high density, low cost and high energy efficiency. The present invention proposes a MAC operation array architecture based on resistive random access memory, which significantly improves the calculation speed by utilizing the time domain distinction of the input signal while ensuring high calculation accuracy.

[0003] In actual use, the resistive random access memory (MAC) array has the following problems: 1. The actual size is usually larger than 1Mb, and the WL / BL introduces a large amount of parasitic resistance / capacitance, resulting in overlap between the product and the corresponding current range during calculation, causing read errors. To solve this problem, each ADC needs to be modulated separately. This greatly increases the difficulty and testing cost of circuit design under the demand for large computing power and large arrays, and seriously reduces the accuracy of MAC operations. 2. Due to the large array, the charging time required to open the BL and WL is very long, and may even exceed the pulse time required for actual operation. Opening the BL and WL row by row will cause each BL and WL to charge and discharge during the operation, greatly reducing the operation speed. 3. Due to the problem of precision loss, only multiplication and addition operations with limited parallelism can be performed, so the MAC operation speed is limited. Since each BL is equipped with an ADC, the ADC area is limited, and the ADC performance is also restricted.

[0004] Therefore, there is an urgent need for a high-speed, low-precision loss MAC array and operation method based on resistive random access memory that can reduce the calculation error and corresponding difficulty caused by parasitic factors in large arrays, improve area utilization and calculation speed. Summary of the Invention

[0005] In view of the above problems, the present invention aims to provide a high-speed, low-precision loss MAC array based on resistive random access memory (RRAM) to address the following issues: the actual size of a RRAM MAC array is typically larger than 1Mb, the WL / BL introduces a large amount of parasitic resistance / capacitance, resulting in overlap between the product and the corresponding current range during calculation, causing read errors and severely reducing the accuracy of MAC operations; the charging time required to open the BL and WL is very long, even exceeding the pulse time required for actual operation; and the row-by-row opening causes the charging and discharging of each BL and WL during the operation, significantly reducing the operation speed and limiting the MAC operation speed.

[0006] The present invention provides a high-speed, low-precision loss MAC array based on resistive memory, comprising a 1T1R resistive memory cell, a word line, a source line, a bit line, and an ADC module, characterized in that:

[0007] 1T1R resistive memory cells storing the same bit with different weights are distributed on multiple adjacent word lines;

[0008] 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line and are arranged in a 2 n The word lines are spaced apart; wherein n is a positive integer;

[0009] Each 1T1R resistive memory cell includes a transistor-resistive memory;

[0010] The resistive memory includes a resistor, the resistor is connected to the transistor, and the resistance can be high or low;

[0011] The word line is connected to the gate terminal of the transistor, the word line is controlled by a decoder, and the word line is used to transmit an input signal;

[0012] The source line is connected to the 1T1R resistive memory cell, and the source line is used to apply a voltage to the resistor to form a bias current on the bit line;

[0013] The ADC module is connected to the bit line, and is used to convert the bias current in the bit line to form a digital MAC operation result.

[0014] Preferably, the bias current is generated based on the input signal and the voltage, reflecting a product of the input signal and the resistance.

[0015] Preferably, it further comprises a control unit,

[0016] The control unit is used to simultaneously open the interval of 2 nA plurality of word lines and a plurality of bit lines at preset intervals are used to form a total digital MAC operation result of a plurality of 1T1R resistive memory cells, and complete the sum operation of the product of the input signal and the resistance.

[0017] Preferably, the preset interval between the bit lines is 8m; m is a positive integer, and m is less than or equal to 16.

[0018] Preferably, the control unit is further configured to simultaneously open the n Before the multiple word lines, the interval is 2 n Performing set and reset operations on multiple word lines;

[0019] n is a positive integer, and n is less than or equal to 5.

[0020] Preferably, the set operation is: a high voltage is applied to the bit line and the word line, and the source line is grounded;

[0021] The reset operation is as follows: a high voltage is applied to the word line and the source line, and the bit line is grounded.

[0022] Preferably, a voltage value of the word line in the set operation is less than half of a voltage value in the reset operation.

[0023] Preferably, all bit lines are connected to the same ADC module.

[0024] The present invention also provides a method for operating a high-speed, low-precision loss MAC array based on a resistive random access memory, which is implemented based on the high-speed, low-precision loss MAC array based on a resistive random access memory as described above, and includes:

[0025] At the same time, the high-speed low-precision loss MAC array based on resistive memory is opened with an interval of 2 n A plurality of word lines, bit lines and source lines at preset intervals; wherein n is a positive integer;

[0026] Transmitting an input signal based on the word line, applying a voltage to a resistor in the high-speed, low-precision loss MAC array based on the resistive memory based on the source line to form a bias current on the bit line;

[0027] The ADC module in the high-speed and low-precision loss MAC array based on the resistive memory is used to convert the bias current in the bit line to form a digital MAC operation result.

[0028] Preferably, the interval is 2 n Before the multiple word lines, the interval is 2 n The plurality of word lines are set and reset; n is a positive integer, and n is less than or equal to 5;

[0029] The set operation is as follows: a high voltage is applied to the bit line and the word line, and the source line is grounded;

[0030] The reset operation is as follows: a high voltage is applied to the word line and the source line, and the bit line is grounded.

[0031] From the above technical solution, it can be seen that the high-speed, low-precision loss MAC array based on resistive memory provided by the present invention stores 1T1R resistive memory cells of the same bit with different weights distributed on multiple adjacent word lines; 1T1R resistive memory cells of different bits with the same weight are distributed on the same bit line, and are arranged in a 2-bit mode. n The 1T1R resistive memory cell includes a transistor-resistive memory; the resistive memory includes a resistor, which is connected to the transistor and can be high or low; the word line is connected to the gate terminal of the transistor, the word line is controlled by a decoder, and the word line is used to transmit an input signal; the source line is connected to the 1T1R resistive memory cell, and the source line is used to apply a voltage to the resistor to form a bias current on the bit line; the ADC module is connected to the bit line, and the ADC module is used to convert the bias current in the bit line to form a digital MAC operation result. In this way, there is sufficient space to configure a higher-precision ADC module, and the use of a high-precision ADC module can achieve better optimization of area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] By referring to the following description in conjunction with the accompanying drawings, and with a more complete understanding of the present invention, other objects and results of the present invention will become more apparent and easier to understand. In the accompanying drawings:

[0033] Figure 1 A schematic diagram of a high-speed, low-precision loss MAC array based on resistive random access memory according to an embodiment of the present invention;

[0034] Figure 2 Schematic diagram of the operation of a high-speed, low-precision loss MAC array based on resistive random access memory according to an embodiment of the present invention;

[0035] Figure 3 Flowchart of a high-speed, low-precision loss MAC array operation method based on resistive random access memory according to an embodiment of the present invention; DETAILED DESCRIPTION

[0036] The actual size of a resistive random access memory (MAC) array is typically larger than 1Mb. The WL / BL introduces a large amount of parasitic resistance / capacitance, causing the product and the corresponding current range to overlap during calculations, resulting in read errors and severely reducing the accuracy of MAC operations. The charging time required to open the BL and WL is very long, sometimes even exceeding the pulse time required for actual operations. Opening each BL and WL row by row causes the charging and discharging of each BL and WL during the operation, significantly slowing down the operation and limiting the MAC operation speed.

[0037] To address the above problems, the present invention provides a high-speed, low-precision loss MAC array based on resistive random access memory. Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] In order to illustrate the high-speed, low-precision loss MAC array and operation method based on resistive random access memory provided by the present invention, Figure 1 、 Figure 2 The high-speed, low-precision loss MAC array based on resistive random access memory according to an embodiment of the present invention is exemplarily illustrated; Figure 3 The high-speed and low-precision loss MAC array operation method based on resistive random access memory according to an embodiment of the present invention is exemplarily illustrated.

[0039] The following description of exemplary embodiments is merely illustrative in nature and is in no way intended to limit the present invention, its application, or uses. Techniques and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques and devices should be considered part of the specification.

[0040] like Figure 1 As shown, the high-speed, low-precision loss MAC array based on resistive memory according to the embodiment of the present invention includes 1T1R resistive memory cells, word lines, source lines, bit lines, and ADC modules, wherein 1T1R resistive memory cells storing the same bit with different weights are distributed on multiple adjacent word lines; 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line, and 2 nThe word lines are spaced apart; n is a positive integer; in this embodiment, 1T1R units storing the same bit with different weights are distributed on the BL of the same area (multiple adjacent WLs). When performing MAC operations on the same bit, the parasitic parameters between the 1T1R units are very close, reducing the error of the sum of products of the same bit; different bits of the same weight are distributed on the same BL, and are not distributed continuously, but are spaced apart by 4 / 8 / 16 / 32 WLs. Taking 4 WLs as an example, WL0 is connected to the unit corresponding to weight B00, WL4 is connected to the unit corresponding to weight B01, and WL8 is connected to the unit corresponding to weight B02... By distributing different bits with the same weight, the accuracy of high-bit operations is effectively improved. In AI operations, the operation error of low bits can usually be ignored. Therefore, this method can effectively improve the overall operation accuracy.

[0041] exist Figure 1 、 Figure 2 In the embodiment shown, each 1T1R resistive memory cell includes a transistor-resistive memory; the resistive memory includes a resistor, which is connected to the transistor and has a resistance that can be high or low; a word line is connected to the gate terminal of the transistor, controlled by a decoder, and used to transmit an input signal; a source line is connected to the 1T1R resistive memory cell, and the source line is used to apply a voltage to the resistor to form a bias current on the bit line; an ADC module is connected to the bit line, and the ADC module is used to convert the bias current in the bit line to form a digital MAC operation result; in this embodiment, all bit lines are connected to the same ADC, and multiple BLs are connected to the same ADC to implement analog-to-digital conversion of multi-bit product sums of multiple weights and multiple input signals, and a larger-scale summation is performed on the periphery through an adder tree, which can reduce the occupied space, improve space utilization, and increase the operation speed.

[0042] Specifically, each transistor-resistive random access memory (1T1R) unit is used to store one bit of weight, which represents 0 when the R resistance is high and represents 1 when the R resistance is low; the WL (word line) is controlled by the decoder and is used to transmit the input signal; the SL (source line) is used to apply a fixed read voltage and form a bias current on the BL (bit line), which is then processed by the ADC to generate a MAC operation result; when the WL of the 1T1R unit is set to a high level, it indicates that the input signal is 1; since the current is large when the 1T1R unit stores 1, it indicates that the product of the input signal and the 1T1R unit is 1; when the 1T1R unit stores 0 or the WL is not selected, the BL current where the unit is located is very low, indicating that the product of the input signal and the 1T1R unit is 0; in this embodiment, the bias current is generated based on the input signal and the voltage, reflecting the product of the input signal and the resistance. By turning on multiple WLs at the same time, these currents representing the products can be formed into a total current, thereby achieving the summation of the products.

[0043] In the embodiment, a control unit is further included for simultaneously opening a plurality of word lines with an interval of 2 n and a plurality of bit lines with a preset interval to form a total digital MAC operation result of a plurality of 1T1R resistance change type memory cells, to complete the sum operation of the product of the input signal and the resistance; the preset interval of the bit lines is 8m; m is a positive integer and is less than or equal to 16; the control unit is further used for performing a set operation and a reset operation on the plurality of word lines with an interval of 2 n before simultaneously opening the plurality of word lines with an interval of 2 n ; n is a positive integer and is less than or equal to 5; wherein the set operation is that the bit lines and the word lines are applied with a high voltage and the source lines are grounded; the reset operation is that the word lines and the source lines are applied with a high voltage and the bit lines are grounded; wherein the voltage value of the word lines in the set operation is less than half of the voltage value in the reset operation.

[0044] In one specific embodiment, during the operation, a plurality of WLs (4 is taken as an example in the following) are simultaneously opened each time, for example, WL0, WL4, WL8…, which represent the sum of the products of different bits (B00, B01, B02…) of the same weight and the input signal, at this time, the BL and the WL need to be controlled, the BL is a certain bit (AN x ) of the input signal, and the WL is opened for 1, 2, 4 or 8 pulse periods according to the number of bits (the mth bit, the m+1th bit, the m+2th bit, the m+3th bit) of the corresponding weight, so in the time domain, the total charge accumulated by the current flowing through the BL is pulse width*(B00*AN x +2*B01*AN x +4B02*AN x +8*B03*AN x ), that is, the result of B0 4-0 *AN x . After conversion by the ADC sampling capacitor, the sum of the multi-bit MAC operation results can be realized.

[0045] As shown in Figure 1 , the interval of the WLs is 4 and the interval of the BLs is 8, and the actual situation can be adjusted to 4, 8, 16, 32 and the like according to the needs, and the calculation is int8 (which can be adjusted according to the actual application). It can be seen that the 0th bit of B0-B7 is distributed on WL0, and the 0th-7th bit of B0 is distributed on BL0, which is divided on WL0, WL4, WL8, WL12, WL16, WL20, WL24, WL28, and the rest of the weights are calculated in the same way.

[0046] Figure 2 is the operation method of the MAC array in the embodiment, a plurality of WLs are opened each time during calculation, and the int8 type operation of simultaneously opening 4 WLs is taken as an example, Figure 2 Part (a) and Figure 2 Part (b) represents the lower 4 bits and upper 4 bits of B0 respectively. When performing the operation, BL gives the xth bit of input AN (AN x ). In the first operation cycle, WL0, WL4, WL8, and WL12 are turned on, and the given pulse is as follows Figure 2 As shown in part (c) of the figure. It is obvious that opening multiple WLs simultaneously reduces the time spent on WL pre-charging exponentially. By controlling the width of the PW time on the WL, the capacitor at the connection between BL and ADC can be charged. The charge expression is PW*(B00*AN x +2*B01*AN x +4B02*AN x +8*B03*AN x ), which represents B0 3-0 The product of and ANx. Similarly, we can Figure 2 As shown in part (b), calculate B0 7-4 The time required to calculate 4 WLs simultaneously is significantly less than the total time required to open the 4 WLs row by row.

[0047] Furthermore, because the ADC (ADC module) is shared by multiple BLs, the ADC module has more space. For example, in the aforementioned int8-type MAC operation with four WLs simultaneously enabled, for a 3*3 kernel, the charge information processed by each ADC operation represents a 10-bit multiplication-addition result. Since conventional ADC designs with sub-12-bit precision consume nonlinear power, the MAC array architecture and operating mode of the present invention provides ample space for higher-precision ADCs, while using high-precision ADCs can achieve better optimization of area and power consumption.

[0048] As described above, the high-speed, low-precision loss MAC array based on resistive memory provided by the present invention stores 1T1R resistive memory cells of the same bit with different weights distributed on multiple adjacent word lines; 1T1R resistive memory cells of different bits with the same weights distributed on the same bit line, and 2 nThe 1T1R resistive memory cell includes a transistor-resistive memory; the resistive memory includes a resistor, which is connected to the transistor and can be high or low; the word line is connected to the gate terminal of the transistor, the word line is controlled by a decoder, and the word line is used to transmit an input signal; the source line is connected to the 1T1R resistive memory cell, and the source line is used to apply a voltage to the resistor to form a bias current on the bit line; the ADC module is connected to the bit line, and the ADC module is used to convert the bias current in the bit line to form a digital MAC operation result. In this way, there is sufficient space to configure a higher-precision ADC module, and the use of a high-precision ADC module can achieve better optimization of area and power consumption.

[0049] like Figure 2 、 Figure 3 As shown together, the present invention also provides a high-speed, low-precision loss MAC array operation method based on resistive random access memory, which is implemented based on the high-speed, low-precision loss MAC array based on resistive random access memory as described above, including:

[0050] S1: Simultaneously open the high-speed, low-precision loss MAC array based on resistive memory with an interval of 2 n a plurality of word lines, bit lines and source lines at preset intervals;

[0051] S2: transmitting an input signal based on the word line, applying a voltage to the resistors in the high-speed, low-precision loss MAC array based on the resistive random access memory based on the source line, so as to form a bias current on the bit line;

[0052] S3: The ADC module in the high-speed and low-precision MAC array based on the resistive random access memory is used to convert the bias current in the bit line to form a digital MAC operation result.

[0053] At the same time open interval of 2 n Before the multiple word lines, the interval is 2 n The plurality of word lines are set and reset; n is a positive integer and is less than or equal to 5;

[0054] The set operation is as follows: a high voltage is applied to the bit line and the word line, and the source line is grounded;

[0055] The reset operation is as follows: a high voltage is applied to the word line and the source line, and the bit line is grounded.

[0056] Specifically, when operating, multiple WLs are opened at the same time (4 is used as an example below), such as WL0, WL4, WL8..., which means that different bits of the same weight (B00, B01, B02...) are multiplied by the input signal. At this time, both BL and WL need to be controlled. BL is a bit of the input signal (AN x), open, while WL is opened according to the number of corresponding weight bits (mth bit, m+1th bit, m+2th bit, m+3th bit) for 1, 2, 4, 8 pulse periods respectively, so in the time domain, the total charge accumulated by the current flowing through BL is pulse width*(B00*AN x +2*B01*AN x +4B02*AN x +8*B03*AN x ), that is, the result of B0 4-0 *AN x . After conversion by the ADC sampling capacitor, the summation of the multi-bit MAC operation result can be achieved.

[0057] Each time the calculation is performed, multiple WLs are opened, and in this case, the int8 type operation with 4 WLs opened simultaneously is taken as an example, Figure 2 The (a) part and the (b) part in the (b) part of Figure 2 represent the low 4 bits and the high 4 bits of B0 respectively. In the operation, the xth bit of the given input AN (AN x ) is given. In the first operation period, WL0, WL4, WL8 and WL12 are opened, and the given pulse is as shown in the (c) part of Figure 2 . It is obvious that the multiple WLs opened simultaneously multiply the time consumed by the WL pre-charge, and by controlling the width of the PW time on the WL, the capacitor at the connection between the BL and the ADC can be charged, and the charge amount is expressed as PW*(B00*AN x +2*B01*AN x +4B02*AN x +8*B03*AN x ), that is, the product sum of B0 3-0 and ANx. In this way, the product sum of B0 7-4 and ANx can be calculated as shown in the (b) part of Figure 2 . The time required for the simultaneous calculation of 4 WLs is significantly less than the sum of the time required for opening the 4 WLs row by row.

[0058] Since the ADC (ADC module) is shared by multiple BLs, the ADC module has more space. For example, in the int8 type MAC operation with 4 WLs opened simultaneously as described above, for a 3*3 kernel, the charge information processed by the ADC in each operation represents the result of a 10-bit multiplication and summation. Since the power consumption consumed by the commonly used ADC with a precision of 12 bits or less increases nonlinearly, in the MAC array architecture and operation mode of the present application, there is enough space to configure a higher precision ADC, and the use of a high-precision ADC can achieve better optimization of area and power consumption.

[0059] It can be seen from the above embodiments that the high-speed, low-precision loss MAC array operation method based on resistive memory provided by the present invention is implemented based on the high-speed, low-precision loss MAC array based on resistive memory as described above. First, the high-speed, low-precision loss MAC array based on resistive memory is opened at the same time with an interval of 2. n The invention provides a plurality of word lines, bit lines and source lines at preset intervals; transmits input signals based on the word lines, applies voltage to resistors in a high-speed, low-precision loss MAC array based on resistive memory based on the source lines, and forms a bias current on the bit lines; uses an ADC module in the high-speed, low-precision loss MAC array based on resistive memory to convert the bias current in the bit lines to form a digital MAC operation result. In this way, there is sufficient space to configure a higher-precision ADC, and the use of a high-precision ADC can achieve better optimization of area and power consumption.

[0060] The high-speed, low-precision loss MAC array and operating method based on resistive random access memory (RRAM) according to the present invention have been described above by way of example with reference to the accompanying drawings. However, those skilled in the art will appreciate that various improvements may be made to the high-speed, low-precision loss MAC array and operating method based on RRAM without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the contents of the appended claims.

Claims

1. A high-speed, low-precision loss MAC array based on resistive memory, comprising a 1T1R resistive memory cell, a word line, a source line, a bit line, and an ADC module, characterized in that: 1T1R resistive memory cells storing the same bit with different weights are distributed on multiple adjacent word lines; 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line and are arranged in a 2 n The word lines are spaced apart; wherein n is a positive integer; Each 1T1R resistive memory cell includes a transistor-resistive memory; The resistive memory includes a resistor, the resistor is connected to the transistor, and the resistance can be high or low; The word line is connected to the gate terminal of the transistor, the word line is controlled by a decoder, and the word line is used to transmit an input signal; The source line is connected to the 1T1R resistive memory cell, and the source line is used to apply a voltage to the resistor to form a bias current on the bit line; The ADC module is connected to the bit line, and is used to convert the bias current in the bit line to form a digital MAC operation result.

2. The high-speed, low-precision loss MAC array based on resistive random access memory according to claim 1, characterized in that: The bias current is generated based on the input signal and the voltage, reflecting a product of the input signal and the resistance.

3. The high-speed, low-precision loss MAC array based on resistive random access memory according to claim 2, wherein: Also includes a control unit, The control unit is used to simultaneously open the interval of 2 n A plurality of word lines and a plurality of bit lines at preset intervals are used to form a total digital MAC operation result of a plurality of 1T1R resistive memory cells, and complete the sum operation of the product of the input signal and the resistance.

4. The high-speed, low-precision loss MAC array based on resistive random access memory according to claim 3, characterized in that: The preset interval between the bit lines is 8m; m is a positive integer, and m is less than or equal to 16.

5. The high-speed, low-precision loss MAC array based on resistive random access memory according to claim 3, wherein: The control unit is further configured to simultaneously open the n Before the multiple word lines, the interval is 2 n Performing set and reset operations on multiple word lines; n is a positive integer, and n is less than or equal to 5.

6. The high-speed, low-precision loss MAC array based on resistive random access memory according to claim 5, characterized in that: The set operation is as follows: a high voltage is applied to the bit line and the word line, and the source line is grounded; The reset operation is as follows: a high voltage is applied to the word line and the source line, and the bit line is grounded.

7. The high-speed, low-precision loss MAC array based on resistive random access memory according to claim 6, wherein: The voltage value of the word line in the set operation is less than half of the voltage value in the reset operation.

8. The high-speed, low-precision loss MAC array based on resistive random access memory according to claim 1, wherein: All bit lines are connected to the same ADC module.

9. A method for operating a high-speed, low-precision loss MAC array based on resistive random access memory, implemented based on the high-speed, low-precision loss MAC array based on resistive random access memory according to any one of claims 1 to 8, comprising: At the same time, the high-speed low-precision loss MAC array based on resistive memory is opened with an interval of 2 n A plurality of word lines, bit lines and source lines at preset intervals; wherein n is a positive integer; Transmitting an input signal based on the word line, applying a voltage to a resistor in the high-speed, low-precision loss MAC array based on the resistive memory based on the source line to form a bias current on the bit line; The ADC module in the high-speed and low-precision loss MAC array based on the resistive memory is used to convert the bias current in the bit line to form a digital MAC operation result.

10. The high-speed, low-precision loss MAC array operation method based on resistive random access memory according to claim 9, characterized in that: At the same time open interval of 2 n Before the multiple word lines, the interval is 2 n The plurality of word lines are set and reset; n is a positive integer, and n is less than or equal to 5; The set operation is as follows: a high voltage is applied to the bit line and the word line, and the source line is grounded; The reset operation is as follows: a high voltage is applied to the word line and the source line, and the bit line is grounded.

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