Ternary content addressable storage unit and ternary content addressable memory

Abstract

The present invention provides a TCAM unit, belonging to the field of semiconductor integrated circuit design. The TCAM unit of the present invention includes: a CMOS field-effect transistor; a complementary CMOS field-effect transistor; a diode; a complementary diode; a memory cell, whose first end is electrically connected to the drain of the CMOS field-effect transistor and the cathode of the diode and can be in a high resistance state and a low resistance state; a complementary memory cell, whose first end is electrically connected to the drain of the complementary CMOS field-effect transistor and the cathode of the complementary diode; a bit / select line, which is electrically connected to the second end of the memory cell; a complementary bit / select line, which is electrically connected to the second end of the complementary memory cell; a match line, which is electrically connected to the diode and the anode of the complementary diode; a word line, which is electrically connected to the gates of the CMOS field-effect transistor and the complementary CMOS field-effect transistor; and a ground line, which is electrically connected to the source of the CMOS field-effect transistor and the complementary CMOS field-effect transistor. The TCAM unit of the present invention has low leakage current, low power consumption in operation and standby mode, fewer connection lines, and high storage density.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit circuit design, and in particular to a ternary content addressable storage unit and a ternary content addressable memory. Background Art

[0002] TCAM (ternary content addressable memory) is a special type of computer memory. TCAM can perform high-speed parallel data searches, classify and forward search data, and is widely used in 5G networks and artificial intelligence (AI) fields such as network routers, pattern matching, cache controllers, intrusion detection and pattern recognition. 5G networks have large traffic volumes, and the demand for data transmission and storage capacity has increased. At the same time, due to the efficient parallel search capabilities of TCAM, as the computing needs of the artificial intelligence field increase, the market demand for TCAM performance is also increasing, especially in terms of response speed, storage capacity, and search power consumption. Figure 1 As shown, the traditional TCAM is implemented using static random-access memory (SRAM), which usually requires 16 CMOS field-effect transistors and 8 input and output connection lines, namely, 2 bit lines BL and 2 complementary bit lines. 1 select line SL, 1 complementary select line One word line WL and one match line ML. This requires many components, resulting in high power consumption in both operating and standby modes, complex wiring, low storage density, and high cost. Summary of the Invention

[0003] The present invention aims to provide a TCAM cell (ternary content addressable memory cell) and a TCAM. These cells are used in 5G networks and artificial intelligence, and have design features such as high storage density and low power consumption.

[0004] The TCAM unit provided by the present invention includes: a CMOS field-effect transistor; a complementary CMOS field-effect transistor; a diode; a complementary diode; a storage unit, a first end of which is electrically connected to the drain of the CMOS field-effect transistor and the cathode of the diode, and can be in a high resistance state and a low resistance state; a complementary storage unit, a first end of which is electrically connected to the drain of the complementary CMOS field-effect transistor and the cathode of the complementary diode, and can be in a high resistance state and a low resistance state; a bit / select line, which is electrically connected to the second end of the storage unit; a complementary bit / select line, which is electrically connected to the second end of the complementary storage unit; a matching line, which is electrically connected to the diode and the anode of the complementary diode; a word line, which is electrically connected to the gates of the CMOS field-effect transistor and the complementary CMOS field-effect transistor; and a ground line, which is electrically connected to the source of the CMOS field-effect transistor and the complementary CMOS field-effect transistor.

[0005] The present invention also provides a three-state content addressable memory, comprising: a plurality of three-state content addressable memory cells; matching circuits, which are respectively electrically connected to the matching lines of the plurality of three-state content addressable memory cells, and are used to send voltage signals to the matching lines; a bit line decoder, which is respectively electrically connected to the bit / select lines and complementary bit / select lines of the plurality of three-state content addressable memory cells, and is used to send voltage signals to the bit / select lines and complementary bit / select lines; and a word line decoder, which is respectively electrically connected to the word lines of the plurality of three-state content addressable memory cells, and is used to send voltage signals to the word lines.

[0006] The TCAM unit provided by the present invention comprises two CMOS field-effect transistors, two diodes, and two memory cells, for a total of four connecting wires. Fewer CMOS field-effect transistors are required, thereby increasing storage density and reducing both operating and standby power consumption. In particular, due to its non-volatile storage properties, data can be retained even after a power outage, which also reduces the TCAM's standby power consumption. Furthermore, the reduced number of connecting wires enables higher storage array density and a smaller memory chip structure. Furthermore, the use of PN junction diodes as select line devices reduces leakage current and improves search speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic diagram of a TCAM unit circuit design based on SRAM in the prior art;

[0008] Figure 2 This is a schematic diagram of the circuit design of a TCAM unit based on a phase change memory of the present invention;

[0009] Figure 3 This is a schematic diagram of the circuit design of an N-by-M array TCAM based on phase change memory of the present invention.

[0010] Explanation of symbols

[0011] 100 TCAM cells

[0012] 101 bits / select line

[0013] 102 complementary bits / select lines

[0014] 103 Matching Line

[0015] 104 character lines

[0016] 105 CMOS field-effect transistor

[0017] 106 complementary CMOS field-effect transistor

[0018] 107 diode

[0019] 108 complementary diodes

[0020] 109 storage units

[0021] 110 complementary storage cells

[0022] 111 ground wire

[0023] 400 N by M array TCAM

[0024] 401 Matching Line

[0025] 402-bit line decoder

[0026] 403 Character Line Decoder DETAILED DESCRIPTION

[0027] Refer to the following Figures 2 to 3 An embodiment of the present invention is described. Figure 2 Schematic diagram of the circuit design of the TCAM unit of the present invention. Figure 2As shown, the TCAM cell 100 includes a CMOS field effect transistor 105, a complementary CMOS field effect transistor 106, a diode 107, a complementary diode 108, a memory cell 109, a first end of which is electrically connected to the drain of the CMOS field effect transistor 105 and the cathode of the diode 107 and can be in a high resistance state and a low resistance state; a complementary memory cell 110, a first end of which is electrically connected to the drain of the complementary CMOS field effect transistor 106 and the cathode of the complementary diode 108 and can be in a high resistance state and a low resistance state; A bit / select line 101 is electrically connected to the second end of the memory cell 109; a complementary bit / select line 102 is electrically connected to the second end of the complementary memory cell 110; a match line 103 is electrically connected to the anodes of the diode 107 and the complementary diode 108; a word line 104 is electrically connected to the gates of the CMOS field-effect transistor 105 and the complementary CMOS field-effect transistor 106; and a ground line 111 is electrically connected to the sources of the CMOS field-effect transistor 105 and the complementary CMOS field-effect transistor 106.

[0028] The diode 107 and the complementary diode 108 may be PN junction diodes. The memory cell 109 and the complementary memory cell 110 may be, but are not limited to, a phase change memory cell, a magnetoresistive random access memory cell (MRAM), or a resistive random access memory cell (RRAM).

[0029] In one embodiment of the present invention, the TCAM cell 100 is implemented using a phase-change memory (PCM) and can store a single bit of a byte: "0," "1," or "don't care," i.e., "low," "high," or "don't care" tri-states.

[0030] Memory cell 109 and complementary memory cell 110 are two complementary phase-change memories. This phase-change memory can utilize a common semiconductor phase-change material, Germanium-Antimony-Tellurium (GST). When the phase-change material is in the set state (set), it is typically crystalline and has a low resistance value. When the phase-change material is in the reset state (reset), it is typically amorphous and has a high resistance value. The resistance values ​​of the high and low resistors should typically differ by at least ten times.

[0031] Therefore, the TCAM cell 100 can set the memory cell 109 to a low resistance state and the complementary memory cell 110 to a high resistance state to store the low bit "0" of a byte. Conversely, the TCAM cell 100 can set the memory cell 109 to a high resistance state and the complementary memory cell 110 to a low resistance state to store the high bit "1" of a byte. In addition, the TCAM cell 100 can also set both the memory cell 109 and the complementary memory cell 110 to a high resistance state to store a "don't care" state of a byte.

[0032] The operation of the TCAM unit 100 can be divided into two parts: the first is the programming part, and the second is the search part. Table 1 is an assignment table of an embodiment of the TCAM unit based on phase change memory of the present invention.

[0033]

[0034]

[0035] Table 1

[0036] Refer to Table 1 and Figure 2 The following describes the programming state of TCAM cell 100. Initially, the voltage on word line 104 is zero, and CMOS FET 105 and complementary CMOS FET 106 are off. When programming begins, to store a high bit "1," word line 104 is first set to a high voltage "1." This high voltage "1" can be any high voltage applied to the CMOS gate. At this point, CMOS FET 105 and complementary CMOS FET 106 are turned on, and the drain currents of CMOS FET 105 and complementary CMOS FET 106 flow through memory cell 109 and complementary memory cell 110, respectively.

[0037] Then the bit / select line 101 sends a reset high voltage V to the memory cell 109. reset A rapidly falling reset pulse (Reset). When current flows through memory cell 109, the Joule heat generated by the current causes the phase-change material in memory cell 109 to quickly reach its melting point, melting the phase-change material. Subsequently, the current flowing through memory cell 109 rapidly decreases, causing the phase-change material to rapidly cool and anneal, forming an amorphous state. This places memory cell 109 in a high-resistance state.

[0038] At the same time, the complementary bit / select line 102 sends a set low voltage V to the complementary memory cell 110. set The slowly falling set pulse Set. The set low voltage V set Lower than the reset high voltage V resetWhen current flows through complementary memory cell 110, the Joule heat generated by the current causes the phase change material in complementary memory cell 110 to quickly reach its crystallization temperature. Subsequently, the current flowing through complementary memory cell 110 gradually decreases, causing the phase change material to slowly cool and anneal, causing the phase change material to crystallize or grow, forming a crystalline state. This places complementary memory cell 110 in a low-resistance state. In this way, TCAM cell 100 completes the storage of the high bit "1" of a byte.

[0039] On the contrary, when storing a low bit "0", the word line 104 is first set to a high voltage "1". At this time, the CMOS field effect transistor 105 and the complementary CMOS field effect transistor 106 are turned on, and the drain currents of the CMOS field effect transistor 105 and the complementary CMOS field effect transistor 106 flow through the storage unit 109 and the complementary storage unit 110 respectively.

[0040] Then the bit / select line 101 sends a set low voltage V to the memory cell 109. set The slowly falling set pulse Set. As mentioned above, the memory cell 109 is in a low resistance state.

[0041] At the same time, the complementary bit / select line 102 sends a reset high voltage V to the complementary memory cell 110. reset The reset pulse Reset falls rapidly. As mentioned above, the complementary memory cell 110 is in a high resistance state. Thus, the TCAM cell 100 completes the storage of a byte of low-order bits "0".

[0042] In addition, when the stored bit is “don’t care”, the bit / select line 101 sends a reset high voltage V to the memory cell 109. reset The reset pulse Reset falls rapidly, and the complementary bit / select line 102 also sends a reset high voltage V to the complementary memory cell 110. reset The reset pulse Reset falls rapidly. For the reasons mentioned above, the memory cell 109 and the complementary memory cell 110 are both in a high resistance state. In this way, the TCAM cell 100 achieves the "don't care" state of the stored bits.

[0043] In addition, in the programming state of the TCAM cell 100, the match line 103 is set to the set low voltage V set , which can reduce the leakage current through diode 107 and through complementary diode 108.

[0044] The TCAM unit 100 of the present invention uses diodes instead of CMOS field-effect transistors as selection line devices, and can also utilize the high ratio of diode on and off currents and the ideal slope of the diode subthreshold current with respect to voltage to further reduce leakage current and improve search speed.

[0045] Refer to Table 1 and Figure 2The search state of the TCAM cell 100 is described. As shown in Table 1, in the search state, when searching for a high bit "1", the word line 104 is set to a low voltage of zero volts, at which time the CMOS field effect transistor 105 and the complementary CMOS field effect transistor 106 are turned off. Then the match line 103 is set to a match line high voltage V ML The bit / select line 101 is set to a low voltage of zero volts and the complementary bit / select line 102 is set to a voltage lower than the matching line high voltage V ML The selection line high voltage V SL .

[0046] If TCAM cell 100 also stores a high bit "1," memory cell 109 is in a high resistance state and complementary memory cell 110 is in a low resistance state. Consequently, diodes 107 and 108 both conduct low currents. Match line 103 is thus maintained at a high voltage, indicating a search match.

[0047] If TCAM cell 100 stores a low-bit "0," memory cell 109 is in a low-resistance state, and complementary memory cell 110 is in a high-resistance state. Consequently, diode 107 is conductive, and complementary diode 108 conducts a low current. Match line 103 is discharged to a low voltage through diode 107, indicating a search mismatch.

[0048] Furthermore, if TCAM cell 100 stores a "don't care" bit, memory cell 109 is in a high resistance state, and complementary memory cell 110 is also in a high resistance state. Consequently, diode 107 and complementary diode 108 both conduct low currents. Match line 103 is thus maintained at a high voltage, indicating a search match.

[0049] On the contrary, when searching for the low bit "0", the word line 104 is placed at a low voltage of zero volts, at which time the CMOS field effect transistor 105 and the complementary CMOS field effect transistor 106 are turned off. Then the match line 103 is placed at a match line high voltage V ML . Set the bit / select line 101 to the select line high voltage V SL The complementary bit / select line 102 is placed at a low voltage of zero volts.

[0050] If TCAM cell 100 stores a high bit "1," phase-change memory cell 109 is in a high resistance state, while complementary phase-change memory cell 110 is in a low resistance state. Consequently, diode 107 conducts a low current, and complementary diode 108 conducts. Match line 103 is discharged to a low voltage through complementary diode 108, indicating a search mismatch.

[0051] If TCAM cell 100 also stores a low-bit "0," memory cell 109 is in a low-resistance state, and complementary memory cell 110 is in a high-resistance state. Consequently, diodes 107 and 108 both conduct relatively low currents. Match line 103 remains at a high voltage, indicating a search match.

[0052] Furthermore, if TCAM cell 100 stores a "don't care" bit, memory cell 109 is in a high resistance state, and complementary memory cell 110 is also in a high resistance state. Consequently, diode 107 and complementary diode 108 both conduct low currents. Match line 103 is thus maintained at a high voltage, indicating a search match.

[0053] In addition, when the search bit is "don't care", the word line 104 is set to a low voltage of zero volts, at which time the CMOS field effect transistor 105 and the complementary CMOS field effect transistor 106 are turned off. Then the match line 103 is set to a match line high voltage V ML . Place both the bit / select line 101 and the complementary bit / select line 102 at the select line high voltage V SL .

[0054] At this time, no matter the memory cell 109 and the complementary memory cell 110 are in a high resistance state or a low resistance state, the conduction current of the diode 107 and the complementary diode 108 is low. Thus, the match line 103 is maintained at a high voltage, indicating a search match.

[0055] Figure 3 This is a schematic diagram of the circuit design of an N x M array TCAM based on phase change memory according to the present invention. The TCAM 400 includes N x M TCAM cells 100; a match circuit 401 electrically connected to the match lines 103 of each of the TCAM cells 100 for sending voltage signals to the match lines 103; a bitline decoder 402 electrically connected to the bit / select lines 101 and complementary bit / select lines 102 of each of the TCAM cells 100 for sending voltage signals to the bit / select lines 101 and complementary bit / select lines 102; and a wordline decoder 403 electrically connected to the word lines 104 of each of the TCAM cells 100 for sending voltage signals to the word lines 104.

[0056] The TCAM cell 100 provided by the present invention comprises two CMOS field-effect transistors, two diodes, and two memory cells. This requires fewer CMOS field-effect transistors, improves storage density, and reduces both operating and standby power consumption. In particular, due to its non-volatile storage properties, data can be retained even after a power outage, while also reducing the TCAM's standby power consumption, thereby lowering costs.

[0057] Furthermore, through the circuit design of the present invention, each TCAM cell 100 only requires four electrical connection lines: a bit / select line 101, a complementary bit / select line 102, a match line 103, and a word line 104. This reduces the number of electrical connection lines compared to the eight required in the prior art. This circuit design can significantly reduce the total number of leads, particularly for large-capacity TCAM arrays comprising multiple TCAM cells 100. This greatly simplifies wiring when connecting the TCAM array to upper-layer conductors, effectively increasing the TCAM storage density and enabling a smaller memory chip structure.

[0058] Although the present invention has been disclosed in the form of embodiments as described above, they are not intended to limit the present invention. Any professional and technical personnel in this field may make various necessary changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the attached claims.

Claims

1. A ternary content addressable memory cell (100), characterized in that: include: CMOS field effect transistor (105); Complementary CMOS field effect transistor (106); diode (107); complementary diode (108); A storage unit (109), a first end of which is electrically connected to the drain of the CMOS field effect transistor (105) and the cathode of the diode (107), and can be in a high resistance state and a low resistance state; A complementary storage unit (110), a first end of which is electrically connected to the drain of the complementary CMOS field effect transistor (106) and the cathode of the complementary diode (108), and can be in a high resistance state and a low resistance state; a bit / select line (101) electrically connected to a second end of the memory cell (109); a complementary bit / select line (102) electrically connected to the second end of the complementary memory cell (110); a matching line (103) electrically connected to the anodes of the diode (107) and the complementary diode (108); A word line (104) electrically connected to the gates of the CMOS field effect transistor (105) and the complementary CMOS field effect transistor (106); and A ground line (111) is electrically connected to the source electrodes of the CMOS field effect transistor (105) and the complementary CMOS field effect transistor (106).

2. The ternary content addressable memory cell (100) according to claim 1, characterized in that: The memory cell (109) and the complementary memory cell (110) are phase change memory cells.

3. The ternary content addressable memory cell (100) according to claim 2, characterized in that: In the programming state, the match line (103) is set to a set low voltage. When storing a high bit, the word line (104) is set to a high voltage. The bit / select line (101) sends a reset pulse with a high voltage and a fast drop to the storage unit (109), so that the storage unit (109) is in a high resistance state. The complementary bit / select line (102) sends a set pulse with a low voltage and a slow drop to the complementary storage unit (110), so that the complementary storage unit (110) is in a low resistance state.

4. The ternary content addressable memory cell (100) according to claim 2, characterized in that: In the programming state, the match line (103) is set to a set low voltage. When storing a low bit, the word line (104) is set to a high voltage. A set pulse with a low voltage and a slow drop is sent to the bit / select line (101), so that the memory cell (109) is in a low resistance state. A reset pulse with a high voltage and a fast drop is sent to the complementary bit / select line (102), so that the complementary memory cell (110) is in a high resistance state.

5. The ternary content addressable memory cell (100) according to claim 2, characterized in that: In the programming state, the match line (103) is set to a set low voltage. When the storage digit is "don't care", the word line (104) is set to a high voltage, and a reset pulse with a high voltage and a fast drop is sent to the bit / select line (101) and the complementary bit / select line (102), so that the memory cell (109) and the complementary memory cell (110) are in a high resistance state.

6. The ternary content addressable memory cell (100) according to claim 2, characterized in that: In the search state, when searching for a high bit, the word line (104) is set to a low voltage of zero volts, the match line (103) is set to a match line high voltage, the bit / select line (101) is set to a low voltage of zero volts, and the complementary bit / select line (102) is set to a select line high voltage lower than the match line high voltage.

7. The ternary content addressable memory cell (100) according to claim 2, characterized in that: In the search state, when searching for a low bit, the word line (104) is set to a low voltage of zero volts, the match line (103) is set to a match line high voltage, the bit / select line (101) is set to a select line high voltage lower than the match line high voltage, and the complementary bit / select line (102) is set to a low voltage of zero volts.

8. The ternary content addressable memory cell (100) according to claim 2, characterized in that: In the search state, when the search digit is "don't care", the word line (104) is set to a zero volt low voltage, the match line (103) is set to a match line high voltage, and the bit / select line (101) and the complementary bit / select line (102) are set to a select line high voltage lower than the match line high voltage.

9. A ternary content addressable memory, characterized in that: include: A plurality of ternary content addressable memory cells (100) as claimed in claim 1; Matching circuits (401), which are electrically connected to the matching lines (103) of the plurality of tri-state content addressable memory cells (100), respectively, and are used to send voltage signals to the matching lines (103); a bit line decoder (402) electrically connected to the bit / select line (101) and the complementary bit / select line (102) of the plurality of tri-state content addressable memory cells (100), and configured to send voltage signals to the bit / select line (101) and the complementary bit / select line (102); and A word line decoder (403) is electrically connected to the word lines (104) of the plurality of tri-state content addressable memory cells (100) and is used to send a voltage signal to the word lines (104).

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