Novel ternary static memory circuit and its readout circuit

Abstract

The application provides a novel ternary static storage circuit and a reading circuit thereof, which quantizes ternary information into 2'b10, 2'b01 and 2'b00 for storage and reading in a digital manner. In the prior art, ternary information is stored as analog voltage quantities of 0, VDD / 2 and VDD, and is read out, and a large number of transmission gate logics are used to realize the storage and reading of the third state VDD / 2 level. Compared with the ternary storage circuit and the reading circuit thereof in the prior art, the novel ternary static storage circuit and the reading circuit thereof in the embodiment do not need an extra VDD / 2 port in structure, do not need to use a ternary logic inverter to realize VDD / 2, and do not need to select only high threshold transistors to ensure the correct circuit function; in performance, short-circuit power consumption does not exist in the data storage and reading stages in the embodiment, and only static power consumption caused by drain current exists in the storage stage, so that the circuit power consumption is significantly reduced. The circuit of the application also has the advantages of smaller circuit area, good circuit stability and less influence of noise, mismatch and other factors.

Description

Technical Field

[0001] This invention belongs to the field of ternary static memory technology, specifically relating to a novel ternary static memory circuit and its readout circuit. Background Technology

[0002] Multi-valued logic, as a solution that surpasses the miniaturization limits of Moore's Law, offers significant advantages in improving integration density. Ternary logic, unlike commonly used binary logic, can simultaneously provide '0', '1', and '2'. The advantages of lower storage density and the ability to store more data have led to the widespread application of ternary logic in scenarios such as ultra-low power speech recognition.

[0003] At the 53rd IEEE International Midwest Circuits and Systems Symposium in 2010, Zafrullah Kamar's paper "Noise margin-optimized ternary CMOS SRAM delay and sizing characteristics" disclosed a new ternary logic storage circuit capable of storing three states: 0, VDD / 2, and VDD.

[0004] At the 18th International Symposium on SOC Design (ISOCC) in 2021, Minjeong Choi's paper "TernarySense Amplifier Design for Ternary SRAM" announced an amplified readout circuit that can be used in the aforementioned ternary logic storage circuit.

[0005] Storage circuit section such as Figure 3 As shown, PMOS transistors M1 and M3, along with NMOS transistors M2 and M4, form a ternary inverter (STI) I1. PMOS transistors M7 and M9, along with NMOS transistors M8 and M10, form a ternary inverter I2, with the transistors in opposite positions having identical parameters. Taking ternary inverter I1 as an example, M1 and M2 are strong pull-up and strong pull-down, respectively. By adjusting the width-to-length ratio of the transmission gate logic of M3 and M4, it is ensured that the node can be weakly driven to VDD / 2 at any time. The gates of NMOS transistors M5 and M6 are controlled by the WWL signal for writing ternary logic.

[0006] When TLP inputs 0 / VDD and TLP inputs VDD / 0, the strong pull-up and strong pull-down in the ternary inverter interlock structure store a pair of complementary logical data. When TLP inputs VDD / 2 and TLN inputs VDD / 2, VDD / 2 acts as the gate drive for the subsequent high-threshold transistors. Since both the gate and source voltages are below the transistor threshold, the node voltages are maintained at VDD / 2 by the transmission gate logics M3, M4, M8, and M9. This achieves the storage of 0, VDD / 2, and VDD data.

[0007] Readout circuit section such as Figure 4 As shown, PMOS transistors M1 and M3, along with NMOS transistors M2 and M4, form a ternary inverter I1. PMOS transistors M5 and M8, along with NMOS transistors M6 and M7, form a ternary inverter I2, with identical transistor parameters at their respective positions. The start and end ports of I1 and I2 are connected to OUTP and OUTN, respectively. PMOS transistors M9 and M10, with their gates controlled by the SE signal, can precharge the output nodes OUTP and OUTN to VDD. PMOS transistors M11, M12, and M13, with their gates controlled by the PRECHARGE signal, can precharge the differential inputs to VDD / 2 before readout, ensuring that TLP and TLN levels are equal. NMOS transistors M14 and M15 form a pair of differential inputs. NMOS transistor M16, with its gate controlled by the SE signal, serves as a tail current source.

[0008] Before the SE signal transitions from 0 to 1 and the circuit reads the data, M9 and M10 precharge OUTP and OUTN to VDD, while M11 and M12 precharge TLP and TLN to VDD / 2. The WWL storage circuit controls the read operation, and the data on TLP and TLN is the same as that of the storage node. After the SE signal transitions from 0 to 1 and the circuit reads the data, when the differential input signal is VDD / 0, the side with the higher voltage controls the output signal OUTP or OUTN to discharge from VDD to 0 faster, causing positive feedback in the ternary inverters I1 and I2, locking the output signal OUTP / OUTN node at 0 / VDD. When both differential input signals are VDD / 2, the transistors M9 and M10 in the output signal pull-up path are turned off, and the signal discharges through M2 and M6, ultimately maintaining the output level at VDD / 2.

[0009] In terms of storage circuit design, existing technologies utilize the positive feedback characteristics of interlocked ternary inverters and the characteristics of high-threshold transistors to achieve stable storage of 0 and VDD. By leveraging the characteristic of transmission gate logic to conduct at any time, stable storage of VDD / 2 can be achieved without triggering the inverter interlock structure. However, this also has several drawbacks:

[0010] The arbitrary conduction characteristic of transmission gate logic ensures that when storing 0 and VDD, there is always a low-impedance path from VDD to VDD / 2 and from VDD / 2 to 0, resulting in extremely high short-circuit power consumption due to continuous short-circuit current. The introduction of the VDD / 2 port will also increase the additional trace area, increasing the layout and routing complexity of the layout-level memory array.

[0011] To avoid erroneous switching of subsequent transistors when storing VDD / 2, the transistor threshold needs to be greater than VDD / 2. This inevitably leads to extremely low noise margin and poor stability of the transistors at this stage, making them susceptible to noise, mismatch, and other factors. This also limits transistor selection to high-threshold transistors, which have slower turn-on speeds, making ternary logic memory cells unsuitable for high-speed applications.

[0012] In terms of readout circuit design, existing technologies also utilize the positive feedback characteristics of interlocked ternary inverters and the characteristics of high threshold transistors to stabilize the output signal in three analog states: 0, VDD / 2, and VDD.

[0013] Because both use ternary inverters, the readout circuit inherits all the shortcomings of the storage circuit in terms of power consumption, speed, and noise immunity. During pre-charging, a low-resistance path from VDD to GND always exists between the pre-charge transistor and the pull-down transistor of the ternary inverter, resulting in extremely high short-circuit current. When reading out the 0 and VDD states, a low-resistance path also exists inside the ternary inverter, leading to extremely high short-circuit power consumption. When reading out VDD / 2, the static power consumption is also quite significant.

[0014] The essence of multi-stage charging at the input and output nodes is to ensure the quality of the VDD / 2 voltage, which results in higher complexity and larger circuit area of ​​the readout circuit. Summary of the Invention

[0015] This invention is made to solve the above-mentioned problems, and aims to provide a novel ternary static memory circuit and its readout circuit with lower power consumption, faster storage and read speed, and smaller circuit area. The technical solution adopted by this invention is as follows:

[0016] This invention provides a novel ternary static memory circuit, characterized by comprising: two cross-coupled inverters; a write control switch connected to the two inverters and a write word line respectively; and a charge / discharge control module connected to the two inverters, a power supply, and a ground line respectively. The input terminals of the two inverters serve as a LEFT node and a RIGHT node, respectively. The novel ternary static memory circuit uses the digital values ​​stored in the LEFT and RIGHT nodes to represent the three states. The charge / discharge control module includes: charging control logic for controlling the opening and closing of the pull-up charging path between the inverters and the power supply; and discharging control logic for controlling the opening and closing of the pull-down discharging path between the inverters and the ground line.

[0017] The novel ternary static memory circuit provided by this invention may also have the following technical features: one inverter includes a PMOS transistor M1 and an NMOS transistor M2; the other inverter includes a PMOS transistor M3 and an NMOS transistor M4; the write control switch includes NMOS transistors M5, M6, M7, and M8; the charging control logic includes PMOS transistors M9, M10, M11, and M12; the discharging control logic includes NMOS transistors M13 and M14; and the gate of the PMOS transistor M1... The gate of the PMOS transistor M1 is connected to the gate of the NMOS transistor M2 and to the LEFT node. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M2 and to the RIGHT node. The source of the PMOS transistor M1 is connected to the MID node. The source of the NMOS transistor M2 is grounded. The gate of the PMOS transistor M3 is connected to the gate of the NMOS transistor M4 and to the RIGHT node. The drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M4 and to the LEFT node. The source of the PMOS transistor M3 is connected to the MID node. The source of the NMOS transistor M4 is grounded. The gates of NMOS transistors M5 and M6 are both connected to the write word line signal WWL. The source of NMOS transistor M5 is connected to the TLP signal, and the drain of NMOS transistor M5 is connected to the LEFT node. The source of NMOS transistor M6 is connected to the TLN signal, and the drain of NMOS transistor M6 is connected to the RIGHT node. The gate of PMOS transistor M7 is connected to the LEFT node, the source of PMOS transistor M7 is connected to VDD, and the drain of PMOS transistor M7 is connected to the LEFTN signal. The gate of PMOS transistor M8 is connected to the RIGHT node. The source of PMOS transistor M8 is connected to VDD. The drain of PMOS transistor M7 is connected to the RIGHTN signal. The gate of PMOS transistor M9 is connected to the RIGHT node. The source of PMOS transistor M9 is connected to VDD. The drain of PMOS transistor M9 is connected to the source of PMOS transistor M10. The gate of PMOS transistor M10 is connected to the LEFT node. The drain of PMOS transistor M10 is connected to the drain of NMOS transistor M11. The gate of NMOS transistor M11 is connected to the MID node. The source of NMOS transistor M11 is grounded. The gate of PMOS transistor M12 is connected to the CHARGE signal.The source of PMOS transistor M12 is connected to VDD, the drain of PMOS transistor M12 is connected to the drain of NMOS transistor M13, the gate of NMOS transistor M13 is connected to the LEFTN signal, the source of NMOS transistor M13 is connected to the drain of NMOS transistor M14, the gate of NMOS transistor M14 is connected to the RIGHTN signal, and the source of NMOS transistor M14 is grounded.

[0018] This invention provides a readout circuit for the novel ternary static memory circuit described above, characterized in that it includes: a differential comparator having two input terminals and two output terminals, the two input terminals being respectively connected to the LEFT node and the RIGHT node of the novel ternary static memory circuit, and the two output terminals being the OUTP node and the OUTN node; and a pre-charge module connected to the differential comparator for pre-charging the OUTP node and the OUTN node.

[0019] The novel ternary static memory circuit readout circuit provided by this invention may also include the following technical features: a tail current source, which is an NMOS transistor M23. The differential comparator includes NMOS transistors M21 and M22. The pre-charge module includes PMOS transistors M24, M25, and M26. The gate of NMOS transistor M21 is connected to the LEFT node, the drain of NMOS transistor M21 is connected to the OUTP node, the source of NMOS transistor M21 is connected to the drain of NMOS transistor M23, the gate of NMOS transistor M22 is connected to the RIGHT node, and the drain of NMOS transistor M22 is connected to the OUTN node. The source of transistor M22 is connected to the drain of NMOS transistor M23. The gate of NMOS transistor M23 is connected to the read word line signal RWL. The source of NMOS transistor M23 is grounded. The source of PMOS transistor M24 is connected to VDD. The drain of PMOS transistor M24 is connected to the OUTP node. The source of PMOS transistor M25 is connected to VDD. The drain of PMOS transistor M25 is connected to the OUTN node. The source of PMOS transistor M26 is connected to the OUTP node. The drain of PMOS transistor M26 is connected to the OUTN node. The gates of PMOS transistors M24, M25, and M26 are connected together and connected to the PRECHARGE signal.

[0020] Invention Function and Effect

[0021] The novel ternary static storage circuit and its readout circuit according to the present invention employ a digital approach, using the digital quantities stored at the LEFT and RIGHT nodes of two cross-coupled inverters to represent the three states. In the prior art, ternary information is stored as analog voltage values ​​of 0, VDD / 2, and VDD, and then read out, using a large number of transmission gate logic to implement the storage and readout of the third state VDD / 2 level. Compared to the existing ternary storage circuit and its readout circuit, the novel ternary static storage circuit and its readout circuit of this embodiment do not require an additional VDD / 2 port structurally, do not require the use of ternary logic inverters to implement VDD / 2, and do not require only high-threshold transistors to ensure correct circuit function. In terms of performance, there is no short-circuit power consumption in the data storage and readout stages of the present invention, and the storage stage only has static power consumption caused by leakage current, significantly reducing circuit power consumption. Furthermore, the novel ternary static storage circuit and its readout circuit of the present invention also have the advantages of smaller circuit area, better circuit stability, and less susceptibility to noise, mismatch, and other factors. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of the novel ternary static storage circuit in an embodiment of the present invention;

[0023] Figure 2 This is a circuit diagram of the readout circuit of the novel ternary static storage circuit in an embodiment of the present invention;

[0024] Figure 3 This is a circuit diagram of a ternary static memory circuit in the prior art;

[0025] Figure 4 This is a circuit diagram of the readout circuit of a ternary static memory circuit in the prior art. Detailed Implementation

[0026] To make the technical means, creative features, objectives and effects of the present invention easy to understand, the following describes the novel ternary static storage circuit and its readout circuit in detail with reference to embodiments and accompanying drawings.

[0027] <Example>

[0028] This embodiment provides a novel ternary static storage circuit, which uses digital quantities stored in LEFT and RIGHT nodes to represent three states, namely 2'b00, 2'b10, and 2'b01.

[0029] Figure 1 This is a circuit diagram of the novel ternary static memory circuit in this embodiment.

[0030] like Figure 1As shown, the novel ternary static memory circuit includes two cross-coupled inverters, a write control switch, and a charge / discharge control module (or control logic).

[0031] In this circuit, PMOS transistor M1 and NMOS transistor M2 form inverter I1. PMOS transistor M3 and NMOS transistor M4 form inverter I2.

[0032] PMOS transistors M9 and M10, and NMOS transistor M11 form a PMOS-rich logic group. NMOS transistors M13 and M14, and PMOS transistor M12 form an NMOS-rich logic group to control the charging and discharging of the inverter.

[0033] The write control switches include NMOS transistors M5 and M6, and PMOS transistors M7 and M8.

[0034] The charge and discharge control module includes charging control logic and discharging control logic. The charging control logic includes M9, M10, M11, and M12, and the discharging control logic includes M13 and M14.

[0035] In this configuration, the gates of M1 and M2 are connected to the LEFT node, the drains of M1 and M2 are connected to the RIGHT node, the source of M1 is connected to the MID node, and the source of M2 is grounded. The gates of M3 and M4 are connected to the RIGHT node, the drains of M3 and M4 are connected to the LEFT node, the source of M3 is connected to the MID node, and the source of M4 is grounded. The gates of M5 and M6 are both connected to the write word line signal WWL, the source of M5 is connected to the TLP signal, and the drain of M5 is connected to the LEFT node. The source of M6 is connected to the TLN signal, and the drain of M6 is connected to the RIGHT node. The gate of M7 is connected to the LEFT node, the source is connected to VDD, and the drain is connected to the LEFTN signal. The gate of M8 is connected to the RIGHT node, the source is connected to VDD, and the drain is connected to the RIGHTN signal. The gate of M9 is connected to the RIGHT node, the source is connected to VDD, and the drain is connected to the source of M10. The gate of M10 is connected to the LEFT node, and its drain is connected to the drain of M11. The gate of M11 is connected to the MID node, and its source is grounded. The gate of M12 is connected to the CHARGE signal, its source is connected to VDD, and its drain is connected to the drain of M13. The gate of M13 is connected to the LEFTN signal, and its source is connected to the drain of M14. The gate of M14 is connected to the RIGHTN signal, and its source is grounded.

[0036] The main functions of the devices are as follows:

[0037] The write line signal WWL controls M2 and M3 to write data, while the charging signal CHARGE controls M12 to ensure that the MID node has a pull-up path to VDD. Inverters I1 and I2 connected end-to-end ensure that when M12 is on, the left and right nodes can store a pair of complementary data. The charging control logic-related M9, M10, M11, and M12 control the opening and closing of the pull-up charging path. The discharging control logic-related M13 and M14 control the opening and closing of the pull-down discharging path, preventing reverse leakage and charge accumulation between nodes from causing incorrect logic flipping.

[0038] The circuit works as follows:

[0039] The write line signal WWL controls the writing of ternary logic data.

[0040] When 2'b10 is written to the LEFT and RIGHT nodes, the PMOS transistor M3 of inverter I2 turns on. The output of inverter I2 charges the MID node in reverse to 1'b1, triggering the interlocking of M11 and M12. The MID node always has a path to VDD, supplying power to inverters I1 and I2. Therefore, the complementary input data is well stored in the inverter interlocking structure. At this time, the circuit operation state is the same as that of the 6T SRAM, realizing the storage of 2'b10 data in the LEFT and RIGHT nodes.

[0041] When 2'b01 is written to the LEFT and RIGHT nodes, similarly, the PMOS transistor M1 of inverter I1 turns on, and the output of inverter I1 charges the MID node in reverse to 1'b1, triggering the interlocking of M11 and M12. The MID node always has a path to VDD, supplying power to inverters I1 and I2. Therefore, the input complementary data is well stored in the inverter interlocking structure, realizing the storage of 2'b01 data in the LEFT and RIGHT nodes.

[0042] When LEFT and RIGHT nodes write 2'b00, the pull-up charging paths of M9, M10, and M11 are turned on, and the CHARGE level is 1; the pull-down discharging paths of M13 and M14 are turned on, the MID node is 0, and the inverters I1 and I2 are not powered, thus realizing the storage of 2'b00 data in LEFT and RIGHT nodes.

[0043] Figure 2 This is a circuit diagram of the read circuit of the novel ternary static storage circuit in this embodiment.

[0044] like Figure 2 As shown, the read circuit of the novel ternary static memory circuit includes PMOS transistors M24, M25, and M26, and NMOS transistors M21, M22, and M23.

[0045] In this configuration, the gate of M21 is connected to the LEFT node, the drain to the OUTP node, and the source to the drain of M23. The gate of M22 is connected to the RIGHT node, the drain to the OUTN node, and the source to the drain of M23. The gate of M23 is connected to the read word line signal RWL, and its source is grounded. The source of M24 is connected to VDD, and its drain to the OUTP node. The source of M25 is connected to VDD, and its drain to the OUTN node. The source of M26 is connected to the OUTP node, and its drain to the OUTN node. The gates of M24, M25, and M26 are connected together and linked to the PRECHARGE signal.

[0046] The main functions of the devices are as follows:

[0047] PMOS transistors M24, M25, and M26 form a precharge logic circuit. NMOS transistors M21 and M22 are a pair of differential comparators, and NMOS transistor M23 is a tail current source.

[0048] The circuit works as follows:

[0049] The precharge signal PRECHARGE controls M24 and M25 to precharge the OUTP and OUTN nodes, while the voltage balancing transistor M26 ensures consistent voltage across both sides. The inputs of the differential comparator are the LEFT and RIGHT nodes of the aforementioned novel ternary static memory circuit. The read circuit operates when the read word line signal RWL controls the tail current source to turn on. With inputs of 2'b00, 2'b01, and 2'b10, the read values ​​for OUTN and OUTP are 2'b11, 2'b10, and 2'b01, respectively.

[0050] Functions and effects of the embodiments

[0051] According to the novel ternary static storage circuit and its readout circuit provided in this embodiment, ternary information is quantized into 2'b10, 2'b01, and 2'b00 digitally for storage and reading. In the prior art, ternary information is stored as analog voltage values ​​of 0, VDD / 2, and VDD, and then read out, using a large number of transmission gate logic to implement the storage and reading of the third state VDD / 2 level. Compared to the ternary storage circuit and its readout circuit in the prior art, the novel ternary static storage circuit and its readout circuit of this embodiment do not require an additional VDD / 2 port in terms of structure, do not require the application of a ternary logic inverter to implement VDD / 2, and do not require only high-threshold transistors to ensure correct circuit function. In terms of performance, there is no short-circuit power consumption in the data storage and readout stages of this embodiment, and the storage stage only has static power consumption caused by leakage current, significantly reducing circuit power consumption. Furthermore, the novel ternary static storage circuit and its readout circuit of this embodiment also have the advantages of smaller circuit area, better circuit stability, and less susceptibility to noise, mismatch, and other factors.

[0052] The above embodiments are only used to illustrate specific implementations of the present invention, and the present invention is not limited to the scope of the description of the above embodiments.

Claims

1. A novel ternary static memory circuit, characterized in that, include: Two cross-coupled inverters; A write control switch is connected to the two inverters and the write line, respectively. as well as The charge / discharge control module is connected to the two inverters, the power supply, and the ground wire, respectively. In this circuit, the inputs of the two inverters serve as the LEFT node and the RIGHT node, respectively. The novel ternary static memory circuit uses the digital values ​​stored in the LEFT node and the RIGHT node to represent the three states. The charge / discharge control module includes: Charging control logic is used to control the opening and closing of the pull-up charging path between the inverter and the power supply; and The discharge control logic is used to control the opening and closing of the pull-down discharge path between the inverter and the ground wire. One of the inverters includes: PMOS transistor M1 and NMOS transistor M2 Another inverter mentioned above includes: PMOS transistor M3 and NMOS transistor M4 The write control switch includes: NMOS transistor M5, NMOS transistor M6, PMOS transistor M7, PMOS transistor M8, The charging control logic includes: PMOS transistor M9, PMOS transistor M10, NMOS transistor M11, and PMOS transistor M12 The discharge control logic includes: NMOS transistors M13 and M14 The gate of the PMOS transistor M1 is connected to the gate of the NMOS transistor M2 and is connected to the LEFT node. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M2 and is connected to the RIGHT node. The source of the PMOS transistor M1 is connected to the MID node, and the source of the NMOS transistor M2 is grounded. The gate of the PMOS transistor M3 is connected to the gate of the NMOS transistor M4 and is connected to the RIGHT node. The drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M4 and is connected to the LEFT node. The source of the PMOS transistor M3 is connected to the MID node, and the source of the NMOS transistor M4 is grounded. The gates of NMOS transistors M5 and M6 are both connected to the write word line signal WWL. The source of NMOS transistor M5 is connected to the TLP signal, and the drain of NMOS transistor M5 is connected to the LEFT node. The source of NMOS transistor M6 is connected to the TLN signal, and the drain of NMOS transistor M6 is connected to the RIGHT node. The gate of PMOS transistor M7 is connected to the LEFT node, the source of PMOS transistor M7 is connected to VDD, and the drain of PMOS transistor M7 is connected to the LEFTN signal. The gate of PMOS transistor M8 is connected to the RIGHT node, the source of PMOS transistor M8 is connected to VDD, and the drain of PMOS transistor M7 is connected to the RIGHTN signal. The gate of PMOS transistor M9 is connected to the RIGHT node, the source of PMOS transistor M9 is connected to VDD, the drain of PMOS transistor M9 is connected to the source of PMOS transistor M10, the gate of PMOS transistor M10 is connected to the LEFT node, the drain of PMOS transistor M10 is connected to the drain of NMOS transistor M11, the gate of NMOS transistor M11 is connected to the MID node, and the source of NMOS transistor M11 is grounded. The gate of PMOS transistor M12 is connected to the CHARGE signal, the source of PMOS transistor M12 is connected to VDD, the drain of PMOS transistor M12 is connected to the drain of NMOS transistor M13, the gate of NMOS transistor M13 is connected to the LEFTN signal, the source of NMOS transistor M13 is connected to the drain of NMOS transistor M14, the gate of NMOS transistor M14 is connected to the RIGHTN signal, and the source of NMOS transistor M14 is grounded.

2. A readout circuit for a novel ternary static memory circuit as described in claim 1, characterized in that, include: The differential comparator has two input terminals and two output terminals. The two input terminals are respectively connected to the LEFT node and the RIGHT node of the novel ternary static memory circuit, and the two output terminals are the OUTP node and the OUTN node. as well as A pre-charge module, connected to the differential comparator, is used to pre-charge the OUTP node and the OUTN node.

3. The readout circuit according to claim 2, characterized in that, Also includes: Tail current source, including NMOS transistor M23, The differential comparator includes: NMOS transistors M21 and M22 The pre-charging module includes: PMOS transistors M24, M25, and M26 The gate of NMOS transistor M21 is connected to the LEFT node, the drain of NMOS transistor M21 is connected to the OUTP node, the source of NMOS transistor M21 is connected to the drain of NMOS transistor M23, the gate of NMOS transistor M22 is connected to the RIGHT node, the drain of NMOS transistor M22 is connected to the OUTN node, and the source of NMOS transistor M22 is connected to the drain of NMOS transistor M23. The gate of the NMOS transistor M23 is connected to the read word line signal RWL, and the source of the NMOS transistor M23 is grounded. The source of PMOS transistor M24 is connected to VDD, the drain of PMOS transistor M24 is connected to the OUTP node, the source of PMOS transistor M25 is connected to VDD, the drain of PMOS transistor M25 is connected to the OUTN node, the source of PMOS transistor M26 is connected to the OUTP node, the drain of PMOS transistor M26 is connected to the OUTN node, and the gates of PMOS transistors M24, M25, and M26 are connected and linked to the PRECHARGE signal.

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