Semiconductor structure and its manufacturing method and wafer bonding method

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same, as well as a wafer bonding method. The semiconductor structure includes: a substrate; a conductive connection line, the conductive connection line is located in the substrate; a conductive contact pad, the first surface of the conductive contact pad is connected to the conductive connection line, and the second surface of the conductive contact pad is provided with a first area and a second area, the first area corresponds to the position of the conductive connection line, and the second area is the area of ​​the second surface of the conductive contact pad excluding the first area; wherein the first area has a first roughness, the second area has a second roughness, and the first roughness is greater than the second roughness. The embodiments of the present disclosure can improve the uniformity of metal bonding during wafer bonding and optimize the wafer bonding effect.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor structure capable of improving wafer bonding effect, a manufacturing method thereof, and a wafer bonding method. Background Art

[0002] The bonding between wafers is achieved by connecting the metal conductive contact pads on the wafers. The metal conductive contact pads are usually made after the conductive wires are manufactured. Due to process limitations, if the height of the metal conductive contact pads is lower than the substrate surface during the manufacturing process, it will cause connection failure and open circuit; if the height of the metal conductive contact pads is higher than the substrate surface, metal extrusion will occur during the bonding process of the two metal conductive contact pads, causing bond separation or short circuit with adjacent circuits.

[0003] In addition, during the bonding process, since the amount of metal corresponding to each area of ​​the conductive contact pad is different (the amount of metal corresponding to the conductive connection area is large and the metal layer is thick, while the amount of metal in other areas is small and the metal layer is thin), under the same bonding force, the amount of metal extrusion (metal expansion) in each area is different, resulting in uneven metal bonding effects in different areas of the conductive contact pad surface, affecting the bonding strength and conductivity.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a semiconductor structure and a manufacturing method thereof and a wafer bonding method, which are used to at least to some extent solve the problem that metal conductive contact pads are prone to connection failures during the bonding process.

[0006] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a conductive connection, wherein the conductive connection is located in the substrate; and a conductive contact pad, wherein a first surface of the conductive contact pad is connected to the conductive connection, and a second surface of the conductive contact pad is provided with a first region and a second region, wherein the first region corresponds to a position of the conductive connection, and the second region is a region of the second surface of the conductive contact pad excluding the first region; wherein the first region has a first roughness, the second region has a second roughness, and the first roughness is greater than the second roughness.

[0007] In an exemplary embodiment of the present disclosure, the first region includes a plurality of first recesses having a first depth; the second region includes a plurality of second recesses having a second depth, and the second depth is greater than the first depth.

[0008] In an exemplary embodiment of the present disclosure, the bottom of the first recess includes a plane, a curved surface, and an angle, and the bottom of the second recess includes a plane, a curved surface, and an angle. The bottom of the first recess is not completely the same as the bottom of the second recess.

[0009] In an exemplary embodiment of the present disclosure, the top-view shape of the first recess includes a circle, an ellipse, and a parallelogram; the top-view shape of the second recess includes a circle, an ellipse, and a parallelogram, the top-view shape of the first recess is the same as the top-view shape of the second recess, or the top-view shape of the first recess is different from the top-view shape of the second recess.

[0010] In an exemplary embodiment of the present disclosure, the second region includes a third recess, the third recess is located at the interface between the conductive contact pad and the substrate, and the third recess has a third depth, which is greater than the second depth.

[0011] In an exemplary embodiment of the present disclosure, the difference between the first roughness and the second roughness is greater than 5 nm.

[0012] In an exemplary embodiment of the present disclosure, the second roughness is less than 1 nm.

[0013] According to a second aspect of the present disclosure, a wafer bonding method is provided, comprising: providing a first wafer, the first wafer comprising a first substrate, a first conductive line, and a first conductive contact pad, the first conductive line being located in the first substrate, the first surface of the first conductive contact pad being connected to the first conductive line, the second surface of the first conductive contact pad being provided with a first region and a second region, the first region corresponding to a position of the first conductive line, the second region being a region of the second surface of the first conductive contact pad excluding the first region; wherein the first region has a first roughness, the second region has a second roughness, and the first roughness is greater than the second roughness; providing a second wafer, the second wafer comprising a first conductive line. Two substrates, a second conductive line, and a second conductive contact pad, wherein the second conductive line is located in the second substrate, the first surface of the second conductive contact pad is connected to the second conductive line, the second surface of the second conductive contact pad is provided with a third area and a fourth area, the third area corresponds to the position of the second conductive line, and the fourth area is the area of ​​the second surface of the second conductive contact pad excluding the third area; wherein the third area has the first roughness, and the fourth area has the second roughness; the first conductive contact pad is controlled to contact the first area and the third area of ​​the second conductive contact pad, and the second area and the fourth area are controlled to contact, so as to bond the first wafer and the second wafer.

[0014] In an exemplary embodiment of the present disclosure, the first area has a first depression, and a first protrusion is provided between two adjacent first depressions; the second area has a second depression, and a second protrusion is provided between two adjacent second depressions; the third area has a third depression, and a third protrusion is provided between two adjacent third depressions; the fourth area has a fourth depression, and a fourth protrusion is provided between two adjacent fourth depressions, and the controlling of the first conductive contact pad and the second conductive contact pad so that the first area and the third area contact, and the second area and the fourth area contact include: in the process of the first area and the third area contacting, the first protrusion is aligned with the center of the third depression, the third protrusion is aligned with the center of the first depression, the second protrusion is aligned with the center of the fourth depression, and the fourth protrusion is aligned with the center of the second depression.

[0015] In an exemplary embodiment of the present disclosure, the shape and size of the first recess correspond to the shape and size of the third protrusion, the shape and size of the second recess correspond to the shape and size of the fourth protrusion, the shape and size of the third recess correspond to the shape and size of the first protrusion, and the shape and size of the fourth recess correspond to the shape and size of the second protrusion.

[0016] According to a third aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate, wherein a conductive line is formed in the substrate; forming a conductive contact pad on a surface of the conductive line, wherein the cross-sectional area of ​​the conductive contact pad is greater than the cross-sectional area of ​​the conductive line; etching a position in the conductive contact pad corresponding to the conductive line to form a first region, wherein the first region has a first roughness.

[0017] In an exemplary embodiment of the present disclosure, etching the positions in the conductive contact pad corresponding to the conductive lines to form the first region includes: etching the positions in the conductive contact pad corresponding to the conductive lines to form a plurality of first recesses, wherein the first recesses have a first depth.

[0018] In an exemplary embodiment of the present disclosure, the method further includes: etching a position in the conductive contact pad other than the first region to form a second region, wherein the second region has a second roughness that is smaller than the first roughness.

[0019] In an exemplary embodiment of the present disclosure, etching the conductive contact pad except the first region to form a second region includes: etching the conductive contact pad except the first region to form a plurality of second recesses, wherein the second recesses have a second depth.

[0020] In an exemplary embodiment of the present disclosure, an interface between the conductive contact pad and the substrate is etched to form a plurality of third recesses, wherein the third recesses have a third depth.

[0021] The disclosed embodiment provides a larger roughness on the surface of the conductive contact pad at the position corresponding to the conductive line, thereby providing a larger accommodation space for the extruded metal at the position corresponding to the conductive line, thereby effectively solving the problem of uneven metal bonding on the surface of the conductive contact pad during the bonding process in the related art, and effectively optimizing the wafer bonding effect.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 is a schematic diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0025] Figure 2A to Figure 2E They are schematic diagrams of the second surface of the conductive contact pad in the embodiments of the present disclosure.

[0026] Figure 3 yes Figure 1 or Figure 2A to Figure 2E A flow chart of a method for manufacturing a semiconductor structure is shown.

[0027] Figure 4 is a flow chart of a wafer bonding method provided by an exemplary embodiment of the present disclosure.

[0028] Figure 5 It is a schematic diagram of a first wafer and a second wafer before bonding in one embodiment of the present disclosure.

[0029] Figure 6 Schematic diagram of comparison between the first wafer and the second wafer before bonding in another embodiment of the present disclosure.

[0030] Reference numerals:

[0031] 1 Substrate

[0032] 2 Conductive wires

[0033] 3 Conductive contact pads

[0034] 31 First Area

[0035] 32 Second Area

[0036] 311 First Depression

[0037] 321 Second Depression

[0038] 322 The third depression

[0039] 312 The Fourth Depression

[0040] 51 First Wafer

[0041] 510 First Substrate

[0042] 511 First conductive connection

[0043] 512 first conductive contact pad

[0044] 513 First Area

[0045] 514 Second Area

[0046] 5131 First Depression

[0047] 5141 Second Depression

[0048] 52 Second Wafer

[0049] 520 Second substrate

[0050] 521 Second conductive connection

[0051] 522 second conductive contact pad

[0052] 523 Third Area

[0053] 524 Fourth Area

[0054] 5231 The Third Depression

[0055] 5241 The Fourth Depression

[0056] 61 First Wafer

[0057] 610 First Substrate

[0058] 611 First conductive connection

[0059] 612 first conductive contact pad

[0060] 613 First Area

[0061] 614 Second Area

[0062] 6131 First Depression

[0063] 6141 Second Depression

[0064] 62 Second Wafer

[0065] 620 Second substrate

[0066] 621 Second conductive connection

[0067] 622 second conductive contact pad

[0068] 623 Third Area

[0069] 624 Fourth Area

[0070] 6231 The Third Depression

[0071] 6241 The Fourth Depression DETAILED DESCRIPTION

[0072] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0073] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0074] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0075] Figure 1 is a schematic diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0076] refer to Figure 1 , the semiconductor structure 100 may include:

[0077] Substrate 1;

[0078] A conductive connection line 2, wherein the conductive connection line 2 is located in the substrate 1;

[0079] A conductive contact pad 3, wherein the first surface of the conductive contact pad 3 is connected to the conductive connection line 2, and the second surface of the conductive contact pad 3 is provided with a first area 31 and a second area 32, wherein the first area 31 corresponds to the position of the conductive connection line 2, and the second area 32 is the area of ​​the second surface of the conductive contact pad 3 excluding the first area 31; wherein the first area 31 has a first roughness, and the second area 32 has a second roughness, and the first roughness is greater than the second roughness.

[0080] In some embodiments, the first roughness may be greater than 20 nm, for example; in other embodiments, the difference between the first roughness and the second roughness may be greater than 5 nm, for example.

[0081] In order to achieve good contact between the conductive contact pads during the bonding process, the relevant technology usually requires that the metal height be controlled to be between 1 and 5 nm from the substrate surface, which is very difficult to control and has a great impact on production costs and production yields. In addition, since the amount of metal at the position corresponding to the conductive connection line 2 on the conductive contact pad 3 is larger than that in other areas, the metal expansion coefficient at this position is also larger than that in other areas during the bonding process, resulting in uneven fusion of the metal grains of the two conductive contact pads being bonded.

[0082] By setting a first area with a larger roughness at a position corresponding to the conductive connection line 2 on the surface of the conductive contact pad 3, and setting a second area with a smaller roughness at other positions, a larger accommodation space can be provided for metal expansion in the area corresponding to the conductive connection line 2, thereby solving the problem of uneven fusion of metal grains during the bonding process, and avoiding the open circuit problem that is prone to occur during the bonding process and the short circuit problem caused by metal extrusion.

[0083] In the embodiments of the present disclosure, the substrate 1 may include but is not limited to a silicon substrate. For example, the conductive connection 2 may be located in a dielectric layer, in which case the entire semiconductor structure including the dielectric layer is referred to as the substrate 1; in addition, the substrate 1 may also include all or part of other semiconductor structures (such as other conductive connections or active regions of transistors). Since the substrate 1 is not the focus of the description, the present disclosure will not focus on it here. The conductive connection 2 may be, for example, a through silicon via. The material manufacturing material of the conductive connection 2 and the conductive contact pad 3 may include, for example, metals such as copper and tungsten. Among them, the outer insulating material of the conductive connection 2 is, for example, an insulating material such as silicon oxide or silicon nitride, and the cross-section of the conductive connection 2 is, for example, circular, elliptical or rectangular.

[0084] exist Figure 1In the illustrated embodiment, after manufacturing a general conductive contact pad, the surface of the conductive contact pad may be etched in different regions to manufacture a first region 31 and a second region 32 with different roughnesses. The following are some embodiments of the present disclosure.

[0085] Figure 2A to Figure 2E They are schematic diagrams of the second surface of the conductive contact pad 3 in the embodiments of the present disclosure.

[0086] refer to Figure 2A and Figure 2B In one embodiment, the first area 31 of the second surface of the conductive contact pad 3 is provided with a plurality of recesses 311, and the second area 32 is provided with a plurality of second recesses 321, the first recesses 311 have a first depth, and the second recesses 321 have a second depth, and the second depth is less than the first depth.

[0087] exist Figure 2A In the illustrated embodiment, the first recess 311 and the second recess 321 are both circular or elliptical shapes with curved edges.

[0088] exist Figure 2B In the illustrated embodiment, the first recess 311 and the second recess 321 are both in the shape of a rectangle, a rhombus, or other parallelograms.

[0089] exist Figure 2A and Figure 2B In the illustrated embodiment, the cross section of the conductive line 2 is circular, so the first region 31 is circular, and the second region 32 surrounds the first region 31. In other embodiments, the cross section of the conductive line 2 may also be an ellipse, a rectangle, etc., in which case the first region 31 has the same cross-sectional shape as the conductive line 2, and the second region 32 surrounds the first region 31.

[0090] In the embodiment of the present disclosure, the bottom shape of the first recess 311 includes a plane, a curved surface, and an angle, and the bottom shape of the second recess 321 includes a plane, a curved surface, and an angle. The bottom shape of the first recess 311 may be the same as or different from the bottom shape of the second recess 321.

[0091] In other embodiments of the present disclosure, more types of recesses may be provided. For example, the first recess 311 and the second recess 321 may be implemented in other forms such as grooves, which are not listed one by one in the present disclosure.

[0092] In some embodiments, the second region 32 may be a flat region, that is, the second roughness may be less than 1 nm. The machining accuracy of the second region 32 during CMP processing may be reduced (without maintaining the original error limit of 1 to 5 nm), while the roughness of the first region 31 may still be greater than that of the second region 32.

[0093] like Figure 2C In the embodiment shown, the second region 32 is not provided with a depression, but is only a natural interface after the CMP (chemical mechanical polishing) process, and there is no need to deliberately etch to form a rough interface, so the second roughness is low and close to a smooth surface. In the embodiment disclosed herein, since at least the first region 31 needs to be subjected to an etching process later, it is not necessary to accurately control the metal height in the CMP process, and it is only necessary to expose the surface of the substrate 1. In some embodiments, the metal height of the conductive contact pad 3 after the CMP process can be slightly higher than the surface of the substrate 1 by increasing the grinding force on the corresponding position of the substrate 1 and reducing the grinding force on the conductive contact pad 3, so that the metal height of the conductive contact pad 3 can be adjusted by etching grooves in the subsequent etching process. Since there is no need to perform high-precision control of the metal height in the CMP process, the production efficiency can be greatly improved.

[0094] In addition, in some embodiments of the present disclosure, a third recess may be provided at the interface between the conductive contact pad 3 and the substrate 1 to prevent the protrusion made of metal from diffusing to the adjacent substrate 1 .

[0095] refer to Figure 2D In some embodiments, regardless of whether the second region 32 can be provided with the second recess 321, the second region 32 can be provided with the third recess 322, which is located at the junction of the conductive contact pad 3 and the substrate 1 and has a third depth, so as to prevent the metal material from expanding at the junction of the conductive contact pad 3 and the substrate 1 due to insufficient storage space, thereby causing the metal material to extend and diffuse along the horizontal direction of the substrate 1, and eventually causing a short circuit between adjacent conductive contact pads 3. In some cases, the third depth can be equal to the first depth, and the present disclosure does not impose any special restrictions on this.

[0096] refer to Figure 2E In one embodiment, in order to prevent the metal in the conductive connection area 2 from excessively pressing on the metal in other areas, causing the edge metal to deform and overflow, a fourth recess 312 can be set at the edge of the first area 31, and the fourth recess 312 has a fourth depth, which can be greater than the first depth, for example.

[0097] In addition, in other embodiments of the present disclosure, the roughness of the first region 31 may be greater than the roughness of the second region 32 in other ways. For example, the spacing between the first recesses 311 is set to be greater than the spacing between the second recesses 321, or the surface area of ​​the first recess 311 is set to be greater than the surface area of ​​the second recess 321. There are many ways to achieve the difference in roughness, and the present disclosure does not impose any special restrictions on this.

[0098] Figure 3 yes Figure 1 or Figure 2A to Figure 2E A flow chart of a method for manufacturing a semiconductor structure is shown.

[0099] refer to Figure 3 , the manufacturing method 300 may include:

[0100] Step S31, providing a substrate, wherein a conductive line is formed in the substrate;

[0101] Step S32, forming a conductive contact pad on the surface of the conductive connection line, wherein the cross-sectional area of ​​the conductive contact pad is larger than the cross-sectional area of ​​the conductive connection line;

[0102] Step S33 , etching a position of the conductive contact pad corresponding to the conductive line to form a first region, wherein the first region has a first roughness.

[0103] exist Figure 3 In the illustrated embodiment, a wet etching method (such as a HCl+H 2 O 2 mixed solution) or other etching processes may be used multiple times to etch the surface of the conductive contact pad.

[0104] In some embodiments, step S33 may include etching locations in the conductive contact pad corresponding to the conductive lines to form a plurality of first recesses, wherein the first recesses have a first depth.

[0105] After etching the first area, the roughness of the first area is greater than other areas of the conductive contact pad, so during the bonding process, a larger accommodation space can be provided for the extruded metal at the corresponding position of the conductive connection line, providing a more uniform bonding interface.

[0106] Furthermore, in order to provide a better bonding effect, etching may be performed again on the second surface of the conductive contact pad except for the first area to form a second area with a second roughness that is smaller than the first roughness.

[0107] The process of forming the second region, for example, includes etching a location in the conductive contact pad other than the first region to form a plurality of second recesses, wherein the second recesses have a second depth that is smaller than the first depth.

[0108] In one embodiment, the recess depth can be controlled by controlling the etching time or etching concentration. When etching the recess, the first depth and the second depth can be determined according to the surface area ratio of the first recess and the second recess and the cross-sectional area ratio of the conductive line to the conductive contact pad.

[0109] For example, when the ratio of the cross-sectional area of ​​the conductive wire to the conductive contact pad is greater than a first preset value, and the top view of the first recess can be set to be larger (the ratio of the top view area of ​​the first recess to the area of ​​the first region is greater than the second preset value), the first depth can be set to be shallower to reduce the amount of etching on the surface metal and avoid open circuits during the bonding process. When the ratio of the cross-sectional area of ​​the conductive wire to the conductive contact pad is less than or equal to the first preset value, and the top view of the first recess is set to be smaller (the ratio of the top view area of ​​the first recess to the area of ​​the first region is less than or equal to the second preset value), the first depth can be set to be deeper to increase the accommodation space for the extruded metal in the first region.

[0110] Similarly, when the ratio of the cross-sectional area of ​​the conductive line to the conductive contact pad is greater than a first preset value, and the second region accounts for a smaller proportion of the surface area of ​​the conductive contact pad, the difference between the second depth and the first depth can be set to be smaller, so that the second depth is deeper to accommodate more extruded metal in the second region; when the ratio of the cross-sectional area of ​​the conductive line to the conductive contact pad is less than or equal to the first preset value, and the second region accounts for a larger proportion of the surface area of ​​the conductive contact pad, the difference between the second depth and the first depth can be set to be larger, so that the second depth is smaller, so as to reduce the amount of etched metal and avoid open circuits.

[0111] Furthermore, the interface between the conductive contact pad and the substrate can be etched to form a plurality of third recesses, the third recesses having a third depth. In some embodiments, the third depth can be greater than or equal to the first depth to prevent the metal in the conductive contact pad region from extending toward the substrate.

[0112] use Figure 3 The method shown is to manufacture Figure 1 or Figure 2A to Figure 2E The semiconductor structure shown can form a larger accommodation space for the extruded metal at the position corresponding to the conductive line, thereby providing a more uniform bonding interface and optimizing the bonding effect.

[0113] In the above method, there is no need to precisely control the metal height during the CMP process on the surface of the conductive contact pad. Instead, the metal height is controlled during the subsequent etching process. Therefore, the situation in the related art where the surface of the conductive contact pad is lower than the surface of the substrate will not occur. This can effectively avoid the open circuit phenomenon caused by the conductive contact pad being lower than the surface of the substrate during the bonding process.

[0114] It should be noted that in order to prevent the extruded metal from being unable to completely fill the depression and causing a void, the upper surface of the depression may be set larger and the bottom shape of the depression may be set flatter.

[0115] Figure 4 is a flow chart of a wafer bonding method provided by an exemplary embodiment of the present disclosure. Figure 4 The illustrated embodiment can be Figure 1or Figure 2A to Figure 2E The semiconductor structure shown in FIG. Figure 3 The method of the embodiment shown is used for manufacturing.

[0116] refer to Figure 4 , the wafer bonding method 400 may include:

[0117] Step S41, providing a first wafer, wherein the first wafer includes a first substrate, a first conductive line, and a first conductive contact pad, wherein the first conductive line is located in the first substrate, wherein a first surface of the first conductive contact pad is connected to the first conductive line, and wherein a first region and a second region are provided on a second surface of the first conductive contact pad, wherein the first region corresponds to a position of the first conductive line, and the second region is a region of the second surface of the first conductive contact pad excluding the first region; wherein the first region has a first roughness, the second region has a second roughness, and the first roughness is greater than the second roughness;

[0118] Step S42, providing a second wafer, wherein the second wafer includes a second substrate, a second conductive line, and a second conductive contact pad, wherein the second conductive line is located in the second substrate, the first surface of the second conductive contact pad is connected to the second conductive line, and the second surface of the second conductive contact pad is provided with a third region and a fourth region, wherein the third region corresponds to the position of the second conductive line, and the fourth region is a region of the second surface of the second conductive contact pad excluding the third region; wherein the third region has the first roughness, and the fourth region has the second roughness;

[0119] Step S43 , controlling the first conductive contact pad to contact the first region and the third region of the second conductive contact pad, and the second region and the fourth region of the second conductive contact pad, so as to bond the first wafer and the second wafer.

[0120] In the embodiments of the present disclosure, "wafer" refers to semiconductor materials that require bonding processes, and is not limited to silicon substrates. During the bonding process, different wafers are connected through metal contact pads to form complex circuits with multi-layer structures. In order to complete the wafer bonding process, the surfaces of the wafers to be bonded to each other must first be flat, smooth and clean for successful bonding.

[0121] However, in the embodiment of the present disclosure, the surface of the conductive contact pad of the two wafers bonded to each other is set to a rough plane, which is contrary to the general practice of the related art and overcomes the technical prejudice that the surface of the bonding process needs to be flat and smooth to achieve good bonding. By using the relatively rough first area and the third area for bonding, the accommodation space for the extruded metal in the corresponding area of ​​the conductive connection can be increased, thereby improving the uniformity of the bonding interface. Since there is no need to accurately control the metal height in the CMP process part, the problem of the conductive contact pad surface being lower than the substrate surface and the open circuit occurring during the bonding process in the related art can be avoided. Therefore, the wafer bonding method provided in the embodiment of the present disclosure can not only achieve a larger area of ​​bonding through the contact surface of the two conductive contact pads with increased surface area, but also improve the uniformity of the metal distribution at the bonding interface while avoiding the open circuit occurring during the bonding process, thereby optimizing the wafer bonding effect.

[0122] Figure 5 It is a schematic diagram of a first wafer and a second wafer before bonding in one embodiment of the present disclosure.

[0123] refer to Figure 5 A first substrate 510 , a first conductive line 511 , and a first conductive contact pad 512 are disposed on the first wafer 51 ; a second substrate 520 , a second conductive line 521 , and a second conductive contact pad 522 are disposed on the second wafer 52 .

[0124] The surface of the first conductive contact pad 512 is provided with a first region 513 and a second region 514; the surface of the second conductive contact pad 522 is provided with a third region 523 and a fourth region 524. The first region 513 corresponds to the first conductive line 511, and the second region 523 corresponds to the second conductive line 521. The roughness of the first region 513 is greater than that of the second region 514, and the roughness of the third region 523 is greater than that of the fourth region 524.

[0125] In one embodiment, the second surfaces of the first conductive contact pad 512 and the second conductive contact pad 522 have the same shape and area. In another embodiment, the second surfaces of the first conductive contact pad 512 and the second conductive contact pad 522 have the same shape and different areas. In yet another embodiment, the second surfaces of the first conductive contact pad 512 and the second conductive contact pad 522 have different shapes and different areas. The shapes of the second surfaces of the first conductive contact pad 512 and the second conductive contact pad 522 can be, for example, circular, elliptical, rectangular, etc., but the present disclosure is not limited thereto.

[0126] exist Figure 5In the illustrated embodiment, the first region 513 is provided with a first recess 5131, the second region 514 is provided with a second recess 5141, the third region 523 is provided with a third recess 5231, and the fourth region 524 is provided with a fourth recess 5241. The depth of the first recess 5131 is greater than the depth of the second recess 5141, and the depth of the third recess 5231 is greater than the depth of the fourth recess 5241.

[0127] The bottom shapes of the first recess 5131, the second recess 5141, the third recess 5231, and the fourth recess 5241 can be, for example, a plane, an arc surface, an angle, etc., and the present disclosure does not impose any special restrictions on this. The bottom shapes of the first recess 5131, the second recess 5141, the third recess 5231, and the fourth recess 5241 can be the same or different.

[0128] In one embodiment, a first protrusion is provided between two adjacent first recesses 5131 , a second protrusion is provided between two adjacent second recesses 5141 , a third protrusion is provided between two adjacent third recesses 5231 , and a fourth protrusion is provided between two adjacent fourth recesses 5241 .

[0129] Figure 4 Step S43 of the illustrated embodiment may include: during the contact between the first region 513 and the third region 523 and the contact between the second region 514 and the fourth region 524 , the first protrusion contacts the third protrusion and the second protrusion contacts the fourth protrusion.

[0130] In order to achieve better bonding, the first recess 5131 and the fourth recess 5241 may have the same top view shape and the same number, and the second recess 5141 and the third recess 5231 may have the same top view shape and the same number. Thus, by reasonably arranging the recesses on the conductive contact pad, the first conductive contact pad 512 and the second conductive contact pad 522 may contact each other through the side walls between the recesses during the bonding process, thereby creating the shortest contact distance and the largest extruded metal accommodation space during the bonding process, so as to achieve a better bonding effect.

[0131] When the first recess 5131 and the fourth recess 5241, the second recess 5141 and the third recess 5231 are Figure 2A The arc-shaped outer shape shown, Figure 2B When the outer shape of the parallelogram is shown, the first recess 5131 and the fourth recess 5241 have the same top view shape, the same top view shape size, and the same number; the second recess 5141 and the third recess 5231 have the same top view shape, the same top view shape size, and the same number. In this case, the first recess 5131 and the second recess 5141 may have different top view shapes, different top view shape sizes, and different numbers.

[0132] That is, the top-view shapes, top-view shape sizes, and number of the two recesses on the same conductive contact pad can be different. It is only necessary to keep the top-view shapes, top-view shape sizes, and number of the two recesses on the two opposite conductive contact pads aligned in the bonding process the same.

[0133] Of course, in other embodiments, the roughness of the first region 513, the second region 514, the third region 523, and the fourth region 524 may not be achieved through regular patterns, and the second region 514 and the fourth region 524 may also be flat or nearly flat surfaces, and the present disclosure does not impose any special limitations thereon.

[0134] In one embodiment, Figure 4 Step S43 of the illustrated embodiment may also include: during the contact between the first region and the third region, the first protrusion is aligned with the center of the third depression, the third protrusion is aligned with the center of the first depression, the second protrusion is aligned with the center of the fourth depression, and the fourth protrusion is aligned with the center of the second depression. At this time, the shape and size of the first depression correspond to the shape and size of the third protrusion, the shape and size of the second depression correspond to the shape and size of the fourth protrusion, the shape and size of the third depression correspond to the shape and size of the first protrusion, and the shape and size of the fourth depression correspond to the shape and size of the second protrusion.

[0135] Figure 6 Schematic diagram of comparison between the first wafer and the second wafer before bonding in another embodiment of the present disclosure.

[0136] Figure 6 In the illustrated embodiment, a first substrate 610 , a first conductive line 611 , and a first conductive contact pad 612 are disposed on the first wafer 61 ; a second substrate 620 , a second conductive line 621 , and a second conductive contact pad 622 are disposed on the second wafer 62 .

[0137] refer to Figure 6 In another embodiment of the present disclosure, the first recess 6131 can accommodate the third protrusion, the second recess 6141 can accommodate the fourth protrusion, the third recess 6231 can accommodate the first protrusion, and the fourth recess 6241 can accommodate the second protrusion. That is, the first conductive contact pad 612 and the second conductive contact pad 622 are connected in a "zipper" shape.

[0138] exist Figure 6 In the serrated connection embodiment shown, the bottom surface of each recess can still be a plane, an arc surface, an angle, etc., and the top view of each recess can be a straight edge or a curved edge; it can have a smooth edge or a serrated edge.

[0139] In one embodiment, the conductive line 2 , the first conductive line 511 and the second conductive line 521 , the first conductive line 611 and the second conductive line 621 are all through silicon vias (TSV).

[0140] pass Figure 5 or Figure 6 The wafers bonded in the embodiment shown can achieve better bonding effect. Since more extruded metal accommodating spaces are provided at the positions corresponding to the conductive wires, the copper extrusion phenomenon and open circuit phenomenon existing in the related art can be avoided, while the bonding uniformity between the conductive contact pads can be effectively improved to optimize the bonding effect.

[0141] In summary, in order to make the copper conductive contact pads (Bonding Cu Pad) and the copper conductive contact pads (Bonding Cu Pad) better bonded during wafer heterogeneous bonding (Hybrid bonding), and reduce the difficulty of controlling the copper depth (1 to 5 nm), the embodiment of the present disclosure uses a wet etching method (such as a HCl+H2O2 mixed solution) or other methods to form a first area with a larger roughness at a position corresponding to the conductive connection, and more metal expansion space can be reserved at the position corresponding to the conductive connection, so that the metal uniformity of the bonding interface is better; at the same time, this design makes it unnecessary to strictly control the copper depth (1 to 5 nm) during the production of through silicon vias (TSV) like traditional planar bonding designs, so that the product processing yield is higher and the processing speed is faster.

[0142] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A conductive connection, wherein the conductive connection is located in the substrate and is a through silicon via; A conductive contact pad is located above the conductive connection line, the first surface of the conductive contact pad is connected to the conductive connection line, and the second surface of the conductive contact pad is provided with a first area and a second area, the area of ​​the second surface of the conductive contact pad corresponding to the conductive connection line is the first area, and the second area is the area of ​​the second surface of the conductive contact pad excluding the first area; wherein the first area has a first roughness, the second area has a second roughness, and the first roughness is greater than the second roughness.

2. The semiconductor structure according to claim 1, wherein: The first region includes a plurality of first recesses having a first depth; the second region includes a plurality of second recesses having a second depth, wherein the second depth is greater than the first depth.

3. The semiconductor structure according to claim 2, wherein: The second region includes a third recess, the third recess is located at an interface between the conductive contact pad and the substrate, and the third recess has a third depth, which is greater than the second depth.

4. The semiconductor structure according to claim 2, characterized in that The bottom of the first recess includes a plane, a curved surface, and an angle, and the bottom of the second recess includes a plane, a curved surface, and an angle. The bottom of the first recess is not completely the same as the bottom of the second recess.

5. The semiconductor structure according to claim 2, wherein: The top-view shape of the first depression includes a circle, an ellipse, and a parallelogram; the top-view shape of the second depression includes a circle, an ellipse, and a parallelogram. The top-view shape of the first depression is the same as the top-view shape of the second depression, or the top-view shape of the first depression is different from the top-view shape of the second depression.

6. The semiconductor structure according to claim 1, wherein: The difference between the first roughness and the second roughness is greater than 5 nm.

7. The semiconductor structure according to claim 1, wherein: The second roughness is less than 1 nm.

8. A wafer bonding method, characterized in that: include: A first wafer is provided, wherein the first wafer comprises a first substrate, a first conductive line, and a first conductive contact pad, wherein the first conductive line is located in the first substrate, the first conductive contact pad is located above the first conductive line, a first surface of the first conductive contact pad is connected to the first conductive line, a second surface of the first conductive contact pad is provided with a first region and a second region, a region of the second surface of the first conductive contact pad corresponding to the first conductive line is the first region, and the second region is a region of the second surface of the first conductive contact pad excluding the first region; wherein the first region has a first roughness, the second region has a second roughness, and the first roughness is greater than the second roughness; and the first conductive line is a through silicon via; A second wafer is provided, wherein the second wafer comprises a second substrate, a second conductive line, and a second conductive contact pad, wherein the second conductive line is located in the second substrate, the first surface of the second conductive contact pad is connected to the second conductive line, and the second surface of the second conductive contact pad is provided with a third region and a fourth region, wherein the third region corresponds to the position of the second conductive line, and the fourth region is a region of the second surface of the second conductive contact pad excluding the third region; wherein the third region has the first roughness, and the fourth region has the second roughness; The first conductive contact pad is controlled to contact the first region and the third region of the second conductive contact pad and the second region and the fourth region of the second conductive contact pad to bond the first wafer to the second wafer.

9. The wafer bonding method according to claim 8, characterized in that: The first region has a first depression, and a first protrusion is provided between two adjacent first depressions; the second region has a second depression, and a second protrusion is provided between two adjacent second depressions; the third region has a third depression, and a third protrusion is provided between two adjacent third depressions; the fourth region has a fourth depression, and a fourth protrusion is provided between two adjacent fourth depressions, and the controlling of the first conductive contact pad and the second conductive contact pad so that the first region and the third region are in contact, and the second region and the fourth region are in contact comprises: During the contact between the first area and the third area, the first protrusion is aligned with the center of the third recess, the third protrusion is aligned with the center of the first recess, the second protrusion is aligned with the center of the fourth recess, and the fourth protrusion is aligned with the center of the second recess.

10. The wafer bonding method according to claim 9, characterized in that: The shape and size of the first recess correspond to those of the third protrusion, the shape and size of the second recess correspond to those of the fourth protrusion, the shape and size of the third recess correspond to those of the first protrusion, and the shape and size of the fourth recess correspond to those of the second protrusion.

11. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, wherein a conductive line is formed in the substrate, and the conductive line is a through silicon via; A conductive contact pad is formed on the surface of the conductive connection line, the conductive contact pad is located above the conductive connection line, and the cross-sectional area of ​​the conductive contact pad is greater than the cross-sectional area of ​​the conductive connection line; A position of the conductive contact pad corresponding to the conductive line is etched to form a first region, wherein the first region has a first roughness.

12. The manufacturing method according to claim 11, characterized in that: The etching of the position of the conductive contact pad corresponding to the conductive line to form the first region comprises: Positions of the conductive contact pad corresponding to the conductive lines are etched to form a plurality of first recesses, wherein the first recesses have a first depth.

13. The manufacturing method according to claim 11, characterized in that: Also includes: A position of the conductive contact pad other than the first region is etched to form a second region, wherein the second region has a second roughness smaller than the first roughness.

14. The manufacturing method according to claim 13, characterized in that: The etching of the conductive contact pad except the first region to form the second region comprises: The conductive contact pad is etched at a position other than the first region to form a plurality of second recesses, wherein the second recesses have a second depth.

15. The manufacturing method according to claim 14, wherein etching a position other than the first region in the conductive contact pad to form a second region further comprises: The interface between the conductive contact pad and the substrate is etched to form a plurality of third recesses, wherein the third recesses have a third depth.

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