Memory device and method of forming a memory device

Abstract

The present disclosure provides a memory device and a method of forming a memory device. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharge circuits disposed on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharge circuits, and a memory array having a three-dimensional (3D) array of memory cells with a plurality of vertical channels disposed on the one or more CSL layers. Each of the plurality of vertical channels includes a respective memory cell string, and each of the one or more CSL layers is conductively coupled to a corresponding memory cell string. Each of the one or more discharge circuits includes one or more transistors deactivated by one or more corresponding conductive lines passing through the memory array.

Description

Technical Field

[0001] This disclosure relates to a memory device and a method of manufacturing the same, and more particularly to a semiconductor device and a method of manufacturing the same. Background Art

[0002] Memory devices (e.g., high density NAND flash memory devices) can have various structures to increase the density of memory cells and wires on a chip. For example, three-dimensional (3D) NAND structures are attractive due to their ability to increase array density by stacking more layers within a similar footprint. However, a common phenomenon in multi-level semiconductor devices is charge accumulation during plasma processing steps of device fabrication. One detrimental effect of localized charge accumulation is arcing, which can damage metallization lines and destroy semiconductor components, circuits, and chips.

[0003] Disclosure

[0004] This disclosure describes methods, systems, and techniques for a discharge circuit in a memory device (e.g., for self-protection from in-process charging effects).

[0005] One aspect of the present disclosure provides a semiconductor device, comprising: a semiconductor substrate; one or more discharge circuits disposed on the semiconductor substrate; one or more common source line (CSL) layers conductively coupled to the one or more discharge circuits; and a memory array having a three-dimensional (3D) array of memory cells in a plurality of vertical channels disposed on the one or more CSL layers, each of the plurality of vertical channels including a respective memory cell string, and each of the one or more CSL layers being conductively coupled to a corresponding memory cell string. Each discharge circuit of the one or more discharge circuits includes one or more transistors deactivated by one or more corresponding conductive lines passing through the memory array.

[0006] In some embodiments, the one or more transistors include: one or more p-type transistors and n-type transistors. The gate terminal and the source terminal of each of the one or more p-type transistors are conductively coupled together by a corresponding first conductive line passing through the memory array to deactivate the p-type transistor. The n-type transistor has a gate terminal conductively coupled to ground or a negative voltage by a second conductive line passing through the memory array to deactivate the n-type transistor.

[0007] In some embodiments, each discharge circuit of the one or more discharge circuits further includes a second n-type transistor having: a drain terminal conductively coupled to the gate terminal of the n-type transistor via a second conductive line; a gate terminal coupled to a positive voltage; and a source terminal coupled to ground or a negative voltage.

[0008] In some embodiments, one or more p-type transistors include: a plurality of p-type transistors coupled in series, the gate terminals of each of the plurality of p-type transistors being coupled to the bulk terminal of the p-type transistor, the source terminal of the starting p-type transistor among the plurality of p-type transistors being coupled to the corresponding CSL layer of one or more CSL layers, and the drain terminal of the ending p-type transistor among the plurality of p-type transistors being coupled to the gate terminal of an n-type transistor. The drain terminal of the n-type transistor is coupled to the corresponding CSL layer.

[0009] In some embodiments, the drain terminal of the first p-type transistor is coupled to the source terminal of the second p-type transistor immediately following the first p-type transistor among the plurality of p-type transistors.

[0010] In some embodiments, the source terminal and the gate terminal of each of the first p-type transistor and the second p-type transistor are coupled together by a corresponding first conductive line.

[0011] In some embodiments, the semiconductor substrate includes an n-type well region and a p-type well region, and the drain terminal of the ending p-type transistor is in the n-type well region, and the source terminal of the n-type transistor is in the p-type well region.

[0012] In some embodiments, the source terminals and the drain terminals of the plurality of p-type transistors are in the n-type well region, and the source terminal and the drain terminal of the n-type transistor are in the p-type well region.

[0013] In some embodiments, one or more discharge circuits are around the memory array on the semiconductor substrate.

[0014] In some embodiments, the semiconductor device includes an integrated circuit on a semiconductor substrate, the integrated circuit includes one or more discharge circuits, and one or more CSL layers are configured on top of the integrated circuit.

[0015] In some embodiments, the memory array includes a plurality of blocks separated by a plurality of filled channels, each of the plurality of blocks being between two adjacent filled channels and including: conductive layers separated from each other by insulating layers; and vertical channels orthogonally passing through the conductive layers and the insulating layers. The vertical channels and two adjacent filled channels are coupled to the corresponding CSL layer of the block, and each page of the memory cells is coupled to a respective word line, and each memory cell string is conductively coupled to a respective bit line.

[0016] Another aspect of the present disclosure provides a semiconductor device, comprising: a semiconductor substrate; one or more discharge circuits disposed on the semiconductor substrate; one or more common source line (CSL) layers conductively coupled to the one or more discharge circuits; and a plurality of vertical channels extending through a plurality of layers and disposed on the one or more CSL layers, each CSL layer in the one or more CSL layers being conductively coupled to a corresponding vertical channel of the plurality of vertical channels. Each of the one or more discharge circuits comprises: a plurality of p-type transistors serially coupled to a corresponding CSL layer of the one or more CSLs, each p-type transistor of the plurality of p-type transistors having a base port and a gate port coupled together; and an n-type transistor having a drain port coupled to the corresponding CSL layer. The starting p-type transistor among the plurality of p-type transistors has a source port coupled to the corresponding CSL layer, and the ending p-type transistor among the plurality of p-type transistors has a drain port coupled to the gate port of the n-type transistor.

[0017] In some embodiments, the plurality of layers comprise a plurality of alternating pairs of conductive layers and insulating layers.

[0018] In some embodiments, the source port and the gate port of each p-type transistor among the plurality of p-type transistors are conductively coupled by a corresponding first conductive line passing through the plurality of layers to deactivate the p-type transistor. The gate port of the n-type transistor is conductively coupled to ground or a negative voltage by a second conductive line passing through the plurality of layers to deactivate the n-type transistor.

[0019] In some embodiments, the drain port of the first p-type transistor is coupled to the source port of the second p-type transistor immediately following the first p-type transistor among the plurality of p-type transistors.

[0020] In some embodiments, each of the one or more discharge circuits further comprises a second n-type transistor having: a drain port conductively coupled to the gate port of the n-type transistor via a second conductive line; a gate port coupled to a positive voltage; and a source port coupled to ground or a negative voltage.

[0021] In some embodiments, the semiconductor substrate comprises an n-type well region and a p-type well region, and the drain port of the ending p-type transistor is in the n-type well region, and the source port of the n-type transistor is in the p-type well region.

[0022] In some embodiments, the one or more discharge circuits are around the plurality of layers on the semiconductor substrate.

[0023] In some embodiments, the semiconductor device comprises an integrated circuit on the semiconductor substrate, the integrated circuit comprising the one or more discharge circuits. The one or more CSLs may be disposed on top of the integrated circuit.

[0024] In some embodiments, a semiconductor device includes: a memory array having a three-dimensional (3D) array of memory cells configured in a plurality of vertical channels, each of the plurality of vertical channels including a respective memory cell string, and each of one or more CSL layers being conductively coupled to a corresponding memory cell string. The memory array includes a plurality of blocks separated by a plurality of filled channels, each of the plurality of blocks being between two adjacent filled channels. The vertical channels and two adjacent filled channels are coupled to a corresponding CSL layer of the block, and each page of the memory cells is coupled to a respective word line, and each memory cell string is conductively coupled to a respective bit line.

[0025] Another aspect of the present disclosure provides a method of forming a semiconductor device. The method includes: forming one or more discharge circuits on a semiconductor substrate, each of the one or more discharge circuits including one or more transistors; forming one or more common source line (CSL) layers conductively coupled to the one or more discharge circuits; forming a plurality of vertical channels orthogonally through a plurality of layers to conductively couple to the one or more CSL layers, wherein each CSL layer of the one or more CSL layers is configured to conductively couple to a corresponding vertical channel of the plurality of vertical channels such that the one or more discharge circuits release charge generated in the corresponding vertical channel; and after forming the plurality of vertical channels, forming one or more conductive lines through the plurality of layers to deactivate the one or more discharge circuits.

[0026] In some embodiments, the plurality of layers includes a plurality of alternating pairs of conductive layers and insulating layers.

[0027] In some embodiments, the one or more transistors include: a plurality of p-type transistors coupled in series; and an n-type transistor. The base terminals and gate terminals of each of the plurality of p-type transistors are coupled together. The source terminal of the starting p-type transistor among the plurality of p-type transistors and the drain terminal of the n-type transistor are coupled to a corresponding CSL layer of the one or more CSL layers. The drain terminal of the ending p-type transistor among the plurality of p-type transistors is coupled to the gate terminal of the n-type transistor.

[0028] In some embodiments, forming a conductive line through the plurality of layers to deactivate the one or more discharge circuits includes: forming a corresponding first conductive line through the plurality of layers to couple the gate terminal and the source terminal of each p-type transistor among the plurality of p-type transistors together to deactivate the p-type transistors; and forming a second conductive line through the plurality of layers to couple the n-type transistor to ground or a negative voltage to deactivate the n-type transistor.

[0029] In some embodiments, each of one or more discharge circuits includes a second n-type transistor having: a gate port coupled to a positive voltage; a source port coupled to ground or a negative voltage; and a drain port. Forming a second conductive line through multiple layers to couple the n-type transistor to ground or a negative voltage may include: forming the second conductive line to conductively couple the drain port of the second n-type transistor to the gate port of the n-type transistor.

[0030] In some embodiments, the semiconductor substrate includes an n-type well region and a p-type well region. Forming one or more discharge circuits on the semiconductor substrate may include: forming the drain port of an ending p-type transistor in the n-type well region and forming the source port of the n-type transistor in the p-type well region.

[0031] In some embodiments, forming one or more discharge circuits on the semiconductor substrate includes: forming each p-type transistor of a plurality of p-type transistors at least partially in the n-type well region, and forming the n-type transistor at least partially in the p-type well region.

[0032] Another aspect of the present disclosure provides a method of forming a semiconductor device, including: forming one or more discharge circuits on a semiconductor substrate, each of the one or more discharge circuits including a plurality of p-type transistors coupled in series and an n-type transistor coupled to the plurality of p-type transistors; forming one or more common source line (CSL) layers conductively coupled to the one or more discharge circuits; and forming a plurality of vertical channels orthogonally through multiple layers on the one or more CSL layers to conductively couple to the one or more CSL layers, each of the one or more CSL layers being conductively coupled to a corresponding vertical channel of the plurality of vertical channels. For each of the one or more discharge circuits, the base port and the gate port of each p-type transistor of the plurality of p-type transistors are coupled together, the source port of a starting p-type transistor among the plurality of p-type transistors and the drain port of the n-type transistor are coupled to a corresponding CSL layer of the one or more CSL layers, and the drain port of an ending p-type transistor among the plurality of p-type transistors is coupled to the gate port of the n-type transistor.

[0033] In some embodiments, the semiconductor substrate includes an n-type well region and a p-type well region. Forming one or more discharge circuits on the semiconductor substrate may include: forming the drain port of an ending p-type transistor in the n-type well region and forming the source port of the n-type transistor in the p-type well region.

[0034] In some embodiments, forming one or more discharge circuits on the semiconductor substrate includes: forming each p-type transistor of a plurality of p-type transistors at least partially in the n-type well region, and forming the n-type transistor at least partially in the p-type well region.

[0035] In some embodiments, the method further includes forming a conductive line to deactivate one or more discharge circuits.

[0036] In some embodiments, forming conductive lines to deactivate one or more discharge circuits includes: forming corresponding first conductive lines through multiple layers to couple the gate terminals and source terminals of each of the multiple p-type transistors together to deactivate the p-type transistors; and forming second conductive lines through the multiple layers to couple an n-type transistor to ground or a negative voltage to deactivate the n-type transistor.

[0037] In some embodiments, each of the one or more discharge circuits includes a second n-type transistor having: a gate terminal, coupled to a positive voltage; a source terminal, coupled to ground or a negative voltage; and a drain terminal. Forming second conductive lines through the multiple layers to couple the n-type transistor to ground or a negative voltage may include: forming a second conductive line to conductively couple the drain terminal of the second n-type transistor to the gate terminal of the n-type transistor.

[0038] The techniques implemented in the present disclosure may provide a discharge circuit in a memory device (e.g., a 3D NAND memory device) for self-protection from in-process charging effects. For example, the techniques may avoid or eliminate the major challenges of vertical channel (VC) dielectric etching, such as wafer arcing or phase damage phenomena, and may rapidly release the accumulated charge during the fabrication of the memory device, which may also stabilize the plasma and smooth the fabrication process. The techniques may protect the 3D memory array or the metallization lines or semiconductor components, circuits, and chips under the conductive common source line (CSL) layer and thereby improve the yield and reliability of the memory device. The techniques may deactivate the function of the discharge circuit without affecting the internal circuits of the memory device, which may minimize the effect of the presence of the discharge circuit during the normal operation of the memory device. The techniques may reduce the overall area of the discharge circuit by using n-type transistors (e.g., n-type metal-oxide-semiconductor (MOS) (or NMOS) transistors) and p-type transistors (e.g., PMOS transistors). The discharge circuit may be configured in any suitable location in the memory device, such as the memory array periphery.

[0039] The techniques implemented in this disclosure can be applied to any device that requires removal of unwanted charge in the device during, for example, manufacturing and / or operating the device. The techniques implemented in this disclosure can be applied to various memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices, such as two-level cell devices, triple-level cell (TLC) devices, or quad-level cell (QLC) devices. The techniques can be applied to various sizes of memory systems, such as three-dimensional (3D) memory systems. The techniques can be applied to various types of non-volatile memory systems, such as masked read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, and flash memory. Flash memory can include NAND flash memory, NOR flash memory, and others. Additionally or alternatively, the techniques can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSD), embedded systems, media players, mobile devices, and others.

[0040] Details of one or more of the disclosed embodiments are set forth in the following accompanying drawings and description. Other features, examples, and advantages will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1A Illustrate an example of a system including a memory device in accordance with one or more embodiments of the present disclosure.

[0042] Figure 1B Illustrate an example block of two-dimensional (2D) memory in accordance with one or more embodiments of the present disclosure.

[0043] Figure 1C Illustrate an example block of three-dimensional (3D) memory in accordance with one or more embodiments of the present disclosure.

[0044] Figure 2A Illustrate a top view of an example 3D memory device having a discharge circuit in accordance with one or more embodiments of the present disclosure.

[0045] Figure 2B Illustrate an example of Figure 2A in accordance with one or more embodiments of the present disclosure

[0046] Figure 3ADescribe an example semiconductor device having a discharge circuit during the manufacture of a 3D memory device according to one or more embodiments of the present disclosure.

[0047] Figure 3B Is according to one or more embodiments of the present disclosure Figure 3A The equivalent circuit diagram of the discharge circuit of.

[0048] Figure 3C Is a part of the equivalent circuit diagram of the discharge circuit according to one or more embodiments of the present disclosure.

[0049] Figure 4A Describe an example 3D memory device after manufacture having a deactivated discharge circuit according to one or more embodiments of the present disclosure.

[0050] Figure 4B Is according to one or more embodiments of the present disclosure Figure 4A The equivalent circuit diagram of the deactivated discharge circuit of.

[0051] Figure 5 Is a flowchart of a process for forming a semiconductor device having one or more discharge circuits according to one or more embodiments of the present disclosure.

[0052] The same reference numerals and names in the various figures indicate the same elements. It should also be understood that the various illustrative embodiments shown in the figures are illustrative representations only and are not necessarily drawn to scale.

[0053] Description of reference numerals

[0054] 100: System

[0055] 110: Device

[0056] 112: Device controller

[0057] 113: Processor

[0058] 114: Internal memory

[0059] 116: Memory

[0060] 120: Host device

[0061] 140: 2D memory block

[0062] 141, 157, 312: Memory cells

[0063] 142, 152: Unit pages

[0064] 143: String selection transistor (SST)

[0065] 144, 154: Unit strings

[0066] 145: Ground Selection Transistor (GST)

[0067] 146, 156, 236, 316: String Selection Line (SSL)

[0068] 148, 158, 238, 317: Ground Selection Line (GSL)

[0069] 149: Common Source Line (CSL)

[0070] 150: 3D Memory Block

[0071] 160: Common Source Line (CSL)

[0072] 200, 400: 3D Memory Device

[0073] 202, 372: Substrate

[0074] 210: Integrated Circuit

[0075] 212: Decoder

[0076] 214, 214a, 214b, 214c, 320, 320a, 320b, 320c: Discharge Circuit

[0077] 220: Memory Array

[0078] 222, 222a, 222b: Filled Channel

[0079] 230: Portion

[0080] 232, 302: Vertical Channel (VC)

[0081] 234, 314: Common Source Line Layer (CSL Layer)

[0082] 235: Alternating Pair of Conductive Layer and Insulating Layer

[0083] 237, 315: dummy layer (DMY)

[0084] 237a: DMY0

[0085] 237b: DMY1

[0086] 240, 318: WL

[0087] 240 - 0: WL0

[0088] 240 - n: WLn

[0089] 252, BL0, BL1, BLn: Bit Line

[0090] 254: Via Hole

[0091] 300: Semiconductor devices

[0092] 301: Charge

[0093] 310: Block

[0094] 311, 323: Conductive path

[0095] 313, 313a, 313b, 313c: discharge path

[0096] 321: Conductive thread

[0097] 322, 324, 326: p-type transistors

[0098] 325: Diode / Conductive Path

[0099] 327, 329: diode

[0100] 328: n-type transistor

[0101] 330: Second n-type transistor

[0102] 350, 370, 450: Equivalent circuit diagram

[0103] 374: n-type well region

[0104] 376: p-type well region

[0105] 402, 404, 406: first conductive line

[0106] 420: After disabling the discharge circuit

[0107] 430: Second conductive line

[0108] 500: Craftsmanship

[0109] 502, 504, 506, 508, 510: Steps

[0110] BL0, BL1, BLn-1, BLn: row bit lines

[0111] VDD: positive voltage

[0112] Vgs: voltage

[0113] VSS: negative voltage

[0114] Vt: threshold voltage

[0115] WL0, WL1, WLn-1, WLn: column word lines DETAILED DESCRIPTION

[0116] Figure 1ADescribe an example of a system 100 for erasing and / or programming data. System 100 includes a device 110 and a host device 120. Device 110 includes a device controller 112 and a memory 116. Device controller 112 includes a processor 113 and an internal memory 114. In some embodiments, device 110 includes a plurality of memories 116 coupled to device controller 112.

[0117] In some embodiments, device 110 is a storage device. For example, device 110 can be an embedded multimedia card (eMMC), a secure digital (SD) card, a solid state drive (SSD), or some other suitable storage. In some embodiments, device 110 is a smart watch, a digital camera, or a media player. In some embodiments, device 110 is a client device coupled to host device 120. For example, device 110 is an SD card in a digital camera or a media player, and the digital camera or the media player is host device 120.

[0118] Device controller 112 is a general-purpose microprocessor or a special application microcontroller. In some embodiments, device controller 112 is the memory controller of device 110. The following sections describe various techniques based on an embodiment where device controller 112 is a memory controller. However, the techniques described in the following sections are also applicable to embodiments where device controller 112 is another type of controller different from a memory controller.

[0119] Processor 113 is configured to execute instructions and process data. The instructions include firmware instructions and / or other program instructions stored in auxiliary memory as firmware code and / or other program code, respectively. The data includes program data corresponding to the firmware and / or other programs executed by the processor, as well as other suitable data. In some embodiments, processor 113 is a general-purpose microprocessor or a special application microcontroller. Processor 113 is also referred to as a central processing unit.

[0120] Processor 113 accesses instructions and data from internal memory 114. In some embodiments, internal memory 114 is a static random access memory (SRAM) or a dynamic random access memory (DRAM). For example, in some embodiments, when device 110 is an eMMC, an SD card, or a smart watch, internal memory 114 is SRAM. In some embodiments, when device 110 is a digital camera or a media player, internal memory 114 is DRAM.

[0121] In some embodiments, the internal memory is a cache memory included in the device controller 112, as Figure 1A shown in. The internal memory 114 stores instruction codes corresponding to the instructions executed by the processor 113, and / or data requested by the processor 113 during runtime.

[0122] The device controller 112 transfers instruction codes and / or data from the memory 116 to the internal memory 114. The memory 116 can be a semiconductor device. In some embodiments, the memory 116 is a non-volatile memory configured to store instructions and / or data for a long time, for example, a NAND flash memory device or some other suitable non-volatile memory device. In an embodiment where the memory 116 is a NAND flash memory, the device 110 is a flash memory device, for example, a flash memory card, and the device controller 112 is a NAND flash controller. For example, in some embodiments, when the device 110 is an eMMC or an SD card, the memory 116 is NAND flash; in some embodiments, when the device 110 is a digital camera, the memory 116 is an SD card; and in some embodiments, when the device 110 is a media player, the memory 116 is a hard disk drive.

[0123] The memory 116 includes a memory array having a plurality of blocks. The memory 116 can be a two-dimensional (2D) memory or a three-dimensional (3D) memory, and thus each corresponding block can be a 2D block or a 3D block.

[0124] Figure 1B An example configuration of a 2D memory block 140 when the memory 116 is a 2D memory is illustrated. The block 140 includes memory cells 141 that are serially coupled to row bit lines BL0, row bit lines BL1,..., row bit lines BLn-1, and row bit line BLn to form a plurality of cell strings 144, and are coupled to column word lines WL0, column word lines WL1,..., column word lines WLn-1, and column word line WLn to form a plurality of cell pages 142.

[0125] Each memory cell in the block includes a transistor structure having a gate, a drain, a source, and a base defined between the drain and the source. Each memory cell is located at the intersection between a word line and a bit line, where the gate is connected to the word line, the drain is connected to the bit line, and the source is connected to a source line that in turn is connected to a common ground. In some instances, the gate of a flash memory cell has a dual-gate structure that includes a control gate and a floating gate, where the floating gate is suspended between two oxide layers to trap electrons for programming the cell.

[0126] The cell string 144 may include a plurality of memory cells 141 connected in series, a string select transistor (SST) 143, and a ground select transistor (GST) 145. The gate of the SST 143 is connected to the string select line (SSL) 146. The gates of the SSTs in different strings are also connected to the same SSL. The gates of the memory cells 141 are respectively connected to the word lines WL0, WL1, …, WL(n-1), WLn. The cell string 144 or the memory cells 141 are connected to the common source line (CSL) 149 via the GST 145. The CSL 149 may be coupled to ground. The gate of the GST 145 is connected to the ground select line (GSL) 148. The gates of the GSTs in different strings are also connected to the same GSL 148.

[0127] The cell page 142 may include a plurality of memory cells 141. The gates of the memory cells 141 in the cell page 142 are serially coupled to respective word lines (WL). When an input voltage is applied to the word line, the input voltage is also applied to the gates of the memory cells 141 in the cell page 142. To read a specific cell page 142 in the block 140 during a read operation, a lower voltage is applied to the word line corresponding to the specific cell page 142. At the same time, a higher voltage is applied to the other cell pages in the block 140.

[0128] The device 110 may include a Flash Translation Layer (FTL) to manage read, write, and erase operations. The FTL may be stored in the device controller 112, for example, in the internal memory 114. The FTL uses a logical-to-physical (L2P) address mapping table that stores the mapping of logical pages in the logical block to physical pages in the physical block.

[0129] Figure 1C An example 3D memory block 150 is described when the memory 116 is a 3D memory. The memory cells 157 are configured in three dimensions, for example, in an XYZ coordinate system, and are coupled to a plurality of word lines to form a plurality of cell pages 152 and are coupled to a plurality of bit lines to form a plurality of cell strings 154.

[0130] The unit page 152 can be, for example, a layer in the XY plane, and the memory cells 157 on the same layer can be coupled to one word line and have the same voltage. The unit string 154 includes a plurality of memory cells 157 vertically connected in series along the Z direction in a vertical channel (VC). In the unit string 154, the memory cells can be configured as SSTs coupled to the string select line (SSL) 156, and the memory cells can be configured as GSTs coupled to the ground select line (GSL) 158. The unit string 154 of the memory cells 157 is connected to the common source line (CSL) 160 via the GST. The CSL 160 can be a conductive layer formed on the substrate of the 3D memory. The CSL 160 can be coupled to the ground.

[0131] A 3D memory block can be defined between two adjacent filled channels (e.g., along the Z direction). The adjacent filled channels can be conductively coupled to a common source line (CSL) layer formed on the substrate. The CSL layer can be made of any material among polysilicon, epitaxy (Epi), or metal (e.g., tungsten W). In some cases, the adjacent filled channels and the CSL layer are collectively regarded as the CSL.

[0132] To form a 3D array of memory cells on a substrate such as a wafer, a plurality of vertical channels (VCs) can be first formed through a plurality of layers along the vertical direction (e.g., the Z direction). The VCs can include high aspect ratio holes, which can be formed by anisotropic etching (e.g., reactive ion etching (RIE) or plasma etching). However, wafer arcing or plasma damage phenomena can occur during the etching process. Charges (e.g., ions and / or electrons) during plasma processing can accumulate to form a voltage, e.g., a horizontal direct current (DC) voltage on the wafer, which can cause plasma instability or wafer arcing. Arc damage can occur near the metallization lines and the areas underlying and / or surrounding the common source line (CSL) layer on the wafer. Arcing can not only damage the circuits and / or chips already formed on the wafer but also make further processing impractical. Therefore, arc damage to the wafer can be expensive in terms of wafer yield and reliability.

[0133] Embodiments of the present disclosure provide methods and techniques to avoid the above wafer arcing or plasma damage problems in etching the vertical channels (VCs) in forming 3D memories on a substrate. In some embodiments, one or more discharge circuits are conductively coupled to the CSL layer on the boundary or peripheral region of the 3D memory, e.g., as described with other details in Figures 2A to 2B such that the charges accumulated during processing can be quickly removed or released from the VCs to the doped regions in the substrate, e.g., as described with other details in Figures 3A to 3C such that the charges accumulated during processing can be quickly removed or released from the VCs to the doped regions in the substrate, e.g., as described with other details in

[0134] After the processing flow is completed, the metallization wiring above the 3D memory can be connected to the through-array contacts (TACs) to deactivate the discharge circuit without affecting the internal circuit of the 3D memory. For example, as described with other details in Figures 4A to 4B Each discharge circuit may include a plurality of p-type transistors (e.g., PMOS transistors) for releasing positive ions and at least one n-type transistor (e.g., NMOS transistor) for releasing negative electrons to the substrate at the same time. Because there are n-type transistors, the size (e.g., area) of each p-type transistor can be significantly shrunk, which can make the overall area of the discharge circuit smaller. The plurality of p-type transistors (e.g., two or more than two PMOS transistors) are serially coupled, which can avoid the high voltage applied to the 3D memory, for example, during an erase operation.

[0135] Figures 2A to 2B Illustrate an example 3D memory device 200 according to one or more embodiments of the present disclosure. The 3D memory device 200 can be implemented as Figure 1A the memory 116. The 3D memory device 200 can be formed by using the process described in Figure 5 .

[0136] The memory device 200 can be formed on a substrate 202. The substrate 202 can include any underlying material or a material on which devices, circuits, epitaxial layers, or semiconductors can be formed. The substrate 202 can include a layer underlying a semiconductor device or even a base layer forming a semiconductor device. The substrate can include one or any combination of silicon, germanium, silicon germanium, semiconductor compounds, or other semiconductor materials, and can include one or more doped regions that are p-doped, n-doped, or undoped. For example, the substrate 202 can include a silicon substrate, such as a silicon wafer. The substrate 202 can include one or more doped regions, such as a p-type well region and an n-type well region.

[0137] The memory device 200 can include an integrated circuit 210 formed on the substrate 202. The integrated circuit 210 can include any circuit, chip, and / or semiconductor component for the memory device 200. In some embodiments, the integrated circuit 210 includes a decoder 212, e.g., an X-decoder (or column decoder) and / or a Y-decoder (or row decoder). Each memory cell can be coupled to the X-decoder via a respective word line and to the Y-decoder via a respective bit line. Thus, each memory cell can be selected by the X-decoder and the Y-decoder to perform a read operation or a write operation via the respective word line and the respective bit line. The integrated circuit 210 can also include at least one of the following: an interface (e.g., for communicating with, such as Figure 1AThe memory controller of the device controller 112 communicates), data register, data buffer, address generator, clock generator, mode logic, state machine, sense amplifier, or high voltage (HV) generator.

[0138] The memory device 200 includes a memory array 220, such as a 3D array having memory cells, formed on the integrated circuit 210. The memory array 220 is conductively coupled to the integrated circuit 210. The memory array 220 may include a plurality of blocks. As Figure 2B illustrated, the memory array 220 may include a plurality of vertical channels (VCs) 232 formed between two adjacent filled channels 222a, filled channels 222b (commonly referred to as filled channels 222 and individually referred to as filled channel 222). Two adjacent filled channels 222 may define a portion 230 of the memory array 220. The portion 230 may be a block, for example, Figure 1C block 150.

[0139] Each VC 232 includes a memory cell string, for example, Figure 1B cell string 144 or Figure 1C cell string 154, and is coupled to a corresponding bit line (BL) 252 via a corresponding via 254. The VCs 232 and the filled channels 222 in the portion 230 are conductively coupled to a common source line (CSL) layer 234 formed on the integrated circuit 210. Each portion may have a corresponding CSL layer. In some embodiments, the CSL layer 234 includes a plurality of CSLs (e.g., Figure 1B CSL 149) that are conductively coupled to the VCs 232 and the filled channels 222 and isolated by an insulating material. The CSL layer 234 may be coupled to ground.

[0140] The VC 232 extends through a plurality of alternating pairs of conductive layers and insulating layers 235 that may be made of a dielectric material such as silicon oxide (or simply referred to as oxide or OX). The conductive layers may be made of a conductive material (e.g., metal, such as tungsten (W)). The conductive layers may form one or more SSLs (e.g., SSL 236), one or more word lines (WLs) (e.g., WL0 240-0,..., WLn 240-n (commonly referred to as WL 240 and individually referred to as WL 240)), and one or more GSLs 238. The conductive layers may also include one or more dummy (DMY) layers, for example, DMY0 237a and DMY1 237b (commonly referred to as DMY 237 and individually referred to as DMY 237). The conductive layer of the WL 240 surrounding the outer surface of the VC 232 serves as the gate of the memory cell. As Figure 2BAs described, in a read operation, selecting the SSL 236 allows the bit line 252 to select the VC 232 in the block 230. The read voltage from the bit line 252 enters the selected VC 232 and the CSL layer 234 and then enters the filled channel 222a that can be coupled to the periphery of the memory device 200 (e.g., the memory interface in the integrated circuit 210).

[0141] As pointed out above, to form the memory array 220, one or more CSL layers 234 may first be formed on the integrated circuit 210 on the substrate 202. For example, a conductive layer may first be formed to extend across the integrated circuit 210 and then patterned into individual CSL layers for corresponding portions or blocks. The individual CSL layers are isolated from each other. Subsequently, multiple layers are formed on the one or more CSL layers 234, the multiple layers including multiple alternating pairs of two different dielectric layers, e.g., silicon oxide (such as OX 235) and silicon nitride (SiN). Multiple vertical holes (or openings) may be formed through the multiple layers. The holes may be formed in a matrix or an array. The holes may be formed by anisotropically etching through the multiple layers along a vertical direction such as the Z direction using, for example, reactive ion etching (RIE) or plasma etching to the one or more CSL layers 234. Subsequently, the VC 232 may be formed by filling the holes. The holes may be filled with any one of an insulator / trapping or trapping / insulator combination, or only polysilicon (poly) or a polysilicon / insulator combination. In some instances, the VC 232 includes multiple layer oxides / nitrides / oxides (ONO) formed on the inner surface of the hole and polysilicon filled in the middle of the hole. The filled material in each VC may form a memory cell string along the vertical direction. A bit line pad (BLP) may be formed on top of the VC to seal the VC such that the interior of the VC is separated from the external environment during the following processing steps. The BLP is conductive and may be coupled to the bit line, e.g., the bit line 252, via the via 254.

[0142] Subsequently, source line trenches (SLT) may be formed to separate the plurality of VCs 232 into a plurality of portions 230 (e.g., blocks). Two adjacent SLTs define a corresponding portion 230. Thereafter, for example, by using wet etching, a type of dielectric layer such as SiN is selectively removed with an etching solution such as H3PO4, and other types of dielectric layers OX 235 and VCs 232 are retained. A conductive material (e.g., tungsten W) may be deposited to fill the remaining space between the dielectric layers OX 235. The conductive material forms a conductive layer between adjacent dielectric layers OX 235. The conductive material may form the gate of a memory cell. The conductive layer may form a word line 240 connected to the gate of the memory cell. The conductive material may also be formed on the inner surface of the SLT to form a filled trench 222. The filled trench 222 may be isolated from conductive layers such as SSL 236, WL 240, and GSL 238 by an isolation material such as OX.

[0143] As noted above, during the etching of the plurality of dielectric layers (e.g., OX and SiN) to form the holes of the VCs 232, charges may accumulate in the holes along the vertical direction. To remove the charges accumulated during the etching process, as discussed with other details in Figures 3A to 3C one or more discharge circuits 214a, discharge circuit 214b, discharge circuit 214c (generally referred to as discharge circuit 214 and individually referred to as discharge circuit 214) may be formed. For example, before forming the memory array 220, one or more discharge circuits 214 may be formed in the integrated circuit 210. One or more discharge circuits 214 may be around the memory array 220. As Figure 2A illustrated, three discharge circuits 214a, discharge circuit 214b, discharge circuit 214c may be on the boundary of the memory array 220. Although three discharge circuits 214 are shown, one, two, four, or more than four discharge circuits may be implemented for the memory array 220 in the memory device 200.

[0144] Each discharge circuit in the one or more discharge circuits 214 may be conductively coupled to one or more CSL layers 234 in the memory array 220. Each CSL layer 234 may be conductively coupled to a plurality of VCs 232 in a corresponding block, and may be conductively coupled to one or more discharge circuits 214.

[0145] Figures 3A to 3C Illustrate an example semiconductor device 300 during the manufacture of a 3D memory device according to one or more embodiments of the present disclosure. The 3D memory device may be Figures 2A to 2BMemory device 200. The semiconductor device 300 can be an in-process device of a 3D memory device. The semiconductor device 300 can include one or more discharge circuits 320a, discharge circuit 320b, discharge circuit 320c (collectively referred to as discharge circuit 320 and individually as discharge circuit 320). The discharge circuit 320 is configured to release in-process charges accumulated during the manufacturing process to thus avoid wafer arcing. The discharge circuit 320 can be implemented as Figures 2A to 2B discharge circuit 214.

[0146] The semiconductor device 300 can be formed on a substrate 372 (as Figure 3C illustrated) (e.g., Figures 2A to 2B substrate 202). The semiconductor device 300 includes a memory array that can include several blocks 310. The memory array can be similar to Figure 2A memory array 220. The block 310 can be similar to Figure 2B portion 230 or Figure 1C block 150. Each block 310 can include a plurality of memory cells 312 disposed in a plurality of vertical channels 302 (e.g., Figure 1B memory cell 141 or Figure 1C memory cell 157). Each vertical channel 302 (e.g., Figure 2B VC 232) includes a memory cell string that can be conductively coupled to respective bit lines BL0, bit line BL1, …, or bit line BLn (e.g., Figure 2B bit line 252).

[0147] Each VC 302 extends orthogonally through a plurality of layers in the block 310. The plurality of layers can include alternating pairs of conductive layers and isolation layers. Each isolation layer (e.g., Figure 2B oxide layer OX 235) can be between two adjacent conductive layers. The conductive layers can include SSL 316 (e.g., Figure 2B SSL 236), a plurality of word lines WL0, word line WL1, …, word line WLn 318 (e.g., Figure 2B word line 240), dummy layer 315 (e.g. Figure 2B dummy layer 237) and GSL 317 (e.g., Figure 2B GSL 238).

[0148] The plurality of layers are formed on a CSL layer 314 in the block 310 (e.g., Figure 2B CSL layer 234). Each VC 302 is conductively coupled to the CSL layer 314. The CSL layer 314 can be formed on an integrated circuit (e.g., Figures 2A to 2Bon the integrated circuit 210), and the integrated circuit is formed on a substrate. The discharge circuit 320 may be included in the integrated circuit. The CSL layer 314 may be conductively coupled to one or more discharge circuits 320 via conductive lines 321 for discharging charges 301. For example, as Figure 3A illustrated in, the charges 301 accumulated in the VC 302 along the conductive path 311 during the processing of the VC 302 may flow to the CSL layer 314 and then be discharged by the discharge circuits 320a, the discharge circuit 320b, and the discharge circuit 320c via the respective discharge paths 313a, the discharge path 313b, and the discharge path 313c (generally referred to as the discharge path 313 and individually referred to as the discharge path 313). The conductive lines 321 may extend from the edge of the CSL layer 314 to carry the charges laterally from the area below the memory array to the discharge circuits 320 at the edge of the memory array (e.g., as shown by Figure 2A the positions of the memory array 220 and the discharge circuits 214a to 214c in).

[0149] Each discharge circuit 320 may be the same. Each discharge circuit 320 may include one or more transistors, for example, one or more p-type transistors, such as PMOS transistors, and one or more n-type transistors, such as NMOS transistors. As described with other details in Figures 4A to 4B , two or more than two p-type transistors coupled in series may be implemented in the discharge circuit 320 to avoid breakdown during the normal operation (e.g., erase operation) of the 3D memory device.

[0150] In some instances, as illustrated in Figures 3A to 3B , each discharge circuit 320 includes three p-type transistors (P1) 322, a p-type transistor (P2) 324, a p-type transistor (P3) 326, and an n-type transistor (N1) 328. The p-type transistors 322, the p-type transistor 324, and the p-type transistor 326 are coupled in series and are configured to discharge the ions flowing through the conductive path 323 from the conductive lines 321 coupled to the CSL layer 314. The n-type transistor 328 is configured to discharge the electrons flowing through the conductive path 325 from the CSL layer 314 via the conductive lines 321. The n-type transistor 328 may also be coupled to the p-type transistor 326. Thus, the accumulated charges may be discharged, for example, at the same time or simultaneously, by the p-type transistors 322, 324, 326 via the conductive path 323 and by the n-type transistor 328 via the conductive path 325. Thus, the accumulated charges can be discharged more effectively and quickly than in the absence of the n-type transistor 328. Additionally, in the presence of the n-type transistor 328 for discharging electrons, the sizes of each of the p-type transistors 322, the p-type transistor 324, and the p-type transistor 326 can be made smaller, which can reduce the overall area of the discharge circuits 320 in the 3D memory device.

[0151] Figure 3B exhibit Figure 3A The equivalent circuit diagram 350 of the discharge circuit 320 is shown in FIG. Figure 3C A portion of an equivalent circuit diagram 370 is shown. Each p-type transistor can be a floating transistor and can include a gate port (G), a source port (S), a drain port (D), and a base port (B). Substrate 372 can include an n-type well region (or N-well) 374 and a p-type well region (or P-well) 376. P-type transistors 322, 324, 326, and n-type transistor 328 can be at least partially formed in substrate 372, for example, in n-type well region 374 and in p-type well region 376, respectively. For example, the drain and source ports of p-type transistors 322, 324, and 326 can be formed in n-type well region 374, and the drain and source ports of n-type transistor 328 can be formed in p-type well region 376.

[0152] refer to Figure 3B , the source port of the first p-type transistor (e.g., p-type transistor 322) is coupled to the CSL layer 314 via a conductive path 323. Adjacent p-type transistors are coupled together by connecting the drain port of the preceding p-type transistor to the source port of the succeeding p-type transistor. The drain port of the n-type transistor 328 is coupled to the CSL layer 314 via a conductive path 325. The gate port of the n-type transistor 328 is coupled to the drain port of the ending p-type transistor (e.g., p-type transistor 326).

[0153] The gate terminal (G) and base terminal (B) of each of the p-type transistors 322, 324, and 326 can be conductively coupled together so that the first p-type transistor 322 can be turned on when the accumulated charge generates a voltage Vgs that is higher than the threshold voltage Vt of the p-type transistor. For example, the threshold voltage Vt can be approximately 1 volt. After the p-type transistor 322 is turned on, the subsequent p-type transistors 324 and 326 can be turned on in sequence to release ions into the n-type well region 374 in the substrate 372. A diode (or pn interface) 325 can be formed between the n-type well region 374 and the p-type transistor 326.

[0154] Since the drain terminal of the p-type transistor 326 is coupled to the gate terminal of the n-type transistor 328, after the p-type transistor 326 is turned on, the n-type transistor 328 can be turned on to release electrons to the p-type well region 376 in the substrate 372. A diode (or pn junction) 327 can be formed between the p-type well region 376 and the n-type transistor 328.

[0155] The discharge circuit 320 may include a second n-type transistor (N2) 330. As discussed below with other details, when the 3D memory device is to be completed, e.g., when the memory array is completed, the second n-type transistor 330 is configured to deactivate the n-type transistor 328. The second n-type transistor 330 may be formed together with other transistors in the discharge circuit, such as p-type transistors 322, p-type transistors 324, p-type transistors 326, and n-type transistor 328. However, before the memory array is completed and during the processing of the semiconductor device 300, as Figure 3B illustrated, the gate terminal and the drain terminal of the second n-type transistor 330 are not coupled to the n-type transistor 328. The source terminal of the second n-type transistor 330 may be in the p-type well region 376, and a diode (or p-n junction) 329 may be formed between the p-type well region 376 and the second n-type transistor 330.

[0156] Figure 4A An example 3D memory device 400 with a deactivated discharge circuit is illustrated, and Figure 4B is Figure 4A the equivalent circuit diagram 450 of the deactivated discharge circuit for Figure 3A The 3D memory device 400 may be the final product of the semiconductor device 300 of Figures 2A to 2B The 3D memory device 400 may be the memory device 200 of Figure 1A and may be implemented as the memory 116 of

[0157] After the memory array of the 3D memory device 400 (e.g., the memory array 220 of Figure 2A ) is completed, the discharge circuit 320 may be deactivated to become the deactivated discharge circuit 420. In some embodiments, the source terminal and the gate terminal of each of the plurality of p-type transistors 322, p-type transistors 324, p-type transistors 326 may be conductively coupled by forming corresponding first conductive lines 402, first conductive lines 404, first conductive lines 406 through the memory array to deactivate the p-type transistors 322, p-type transistors 324, p-type transistors 326. Each of the first conductive lines 402, first conductive lines 404, first conductive lines 406 may include through-array contacts (TACs) through the memory array and metal wiring on top of the memory array. Since the source terminal, the gate terminal, and the base terminal of each of the p-type transistors 322, p-type transistors 324, p-type transistors 326 are connected, the p-type transistors 322, p-type transistors 324, p-type transistors 326 are deactivated and their function as a discharge circuit stops working.

[0158] In some embodiments, the n-type transistor 328 is deactivated by being conductively coupled to ground or a negative voltage through a second conductive line 430 that passes through the memory array. The second conductive line 430 may also include through-array contacts (TACs) that pass through the memory array and metal wiring on top of the memory array. As illustrated in Figures 4A to 4B , the n-type transistor 328 may be coupled by the second conductive line 430 to a second n-type transistor 330. The gate port of the second n-type transistor 330 is coupled to a positive voltage VDD, and the source port of the second n-type transistor 330 is coupled to ground or a negative voltage VSS. The drain port of the second n-type transistor 330 is conductively coupled through the second conductive line 430 to the gate port of the n-type transistor 328. Thus, the second n-type transistor 330 may transmit a ground or negative voltage to the gate of the n-type transistor 328 through the second conductive line 430 to turn off the n-type transistor 328.

[0159] Since the drain port of the p-type transistor 326 is coupled to the gate port of the n-type transistor 328, the drain port of the p-type transistor 326 is also coupled to ground or a negative voltage. Thus, when a voltage is applied from the CSL layer 314, for example, during an erase operation on the 3D memory device 400, the voltage may be distributed among the p-type transistors. If the p-type transistors are the same, the voltage may be evenly distributed. For example, as illustrated in Figure 4B , when the voltage applied on the CSL layer 314 is about 20 volts (V), each p-type transistor only holds about one-third of the voltage, which is much smaller than the voltage, e.g., 6.6 volts. Although the p-type transistors in the discharge circuit 420 are deactivated and not operating, the p-type transistors may be troubled by the high voltage applied on the CSL layer 314 during a normal erase operation on the memory array. Thus, coupling two or more than two p-type transistors in series (e.g., the p-type transistor 322, the p-type transistor 324, the p-type transistor 326) may avoid breakdown of the p-type transistors. The n-type transistors may have a higher breakdown voltage than the p-type transistors. Thus, one n-type transistor 328 may be implemented in the conductive path 325. In some embodiments, if the voltage in the CSL layer 314 is high, two or more than two n-type transistors may also be used in the conductive path 325.

[0160] Figure 5 FIG. 500 is a flow chart of a process 500 for forming a semiconductor device having one or more discharge circuits according to one or more embodiments of the present disclosure. The semiconductor device may be the memory 116 of Figure 1A , the 3D memory device 200 of Figures 2A to 2B , the semiconductor device 300 of Figures 3A to 3C , or the 3D memory device 400 of Figures 4A to 4B . The semiconductor device may include a memory array, e.g., Figures 2A to 2Bmemory array 220. One or more discharge circuits may be Figures 2A to 2B discharge circuit 214 of Figures 3A to 3B discharge circuit 320 of Figures 4A to 4B discharge circuit 420 of

[0161] At step 502, one or more discharge circuits are formed on a semiconductor substrate. The semiconductor substrate may be Figures 2A to 2B substrate 202 of Figure 3C substrate 372 of. Since the memory array is formed in the central region, and one or more discharge circuits may be disposed on the peripheral region of the semiconductor substrate, for example, as Figure 2A illustrated in. An integrated circuit (e.g., Figures 2A to 2B integrated circuit 210 of

[0162] Each of the one or more discharge circuits may include a plurality of p-type transistors coupled in series (e.g., Figures 3A to 3C and Figures 4A to 4B p-type transistors 322, p-type transistors 324, p-type transistors 326 of Figures 3A to 3C and Figures 4A to 4B n-type transistor 328 coupled to the plurality of p-type transistors). The base terminals and gate terminals of each p-type transistor among the plurality of p-type transistors may be coupled together. The source terminal of the starting p-type transistor (e.g., p-type transistor 322) among the plurality of p-type transistors and the drain terminal of the n-type transistor may be coupled together. The drain terminal of the ending p-type transistor (e.g., p-type transistor 326) among the plurality of p-type transistors may be coupled to the gate terminal of the n-type transistor. For adjacent first p-type transistor and second p-type transistor, the drain terminal of the first p-type transistor is coupled to the source terminal of the second p-type transistor immediately following the first p-type transistor among the plurality of p-type transistors.

[0163] The semiconductor substrate may include an n-type well region, e.g., Figure 3C n-type well region 374 of Figure 3C p-type well region 376 of. Forming one or more discharge circuits on the semiconductor substrate may include forming the drain terminal of the ending p-type transistor in the n-type well region and forming the source terminal of the n-type transistor in the p-type well region. In some embodiments, each p-type transistor and n-type transistor among the plurality of p-type transistors may be at least partially in the n-type well region and p-type well region, respectively. For example, the source terminals and drain terminals of the plurality of p-type transistors may be formed in the n-type well region, and the source terminal and drain terminal of the n-type transistor may be formed in the p-type well region.

[0164] At step 504, one or more common source line (CSL) layers are formed to conductively couple to one or more discharge circuits. One or more CSL layers may be formed on an integrated circuit, for example, as illustrated in Figures 2A to 2B Each CSL layer may be the CSL layer 160 of Figure 1C the CSL layer of Figure 2B the CSL layer of Figures 3A to 3B the CSL layer of Figures 4A to 4B Each CSL layer is conductively coupled to one or more discharge circuits, for example, as illustrated in Figure 3A

[0165] [[ID=1']]At step 506, multiple layers are formed on one or more CSL layers. The multiple layers may include multiple alternating pairs of dielectric layers or isolation layers, such as OX and SiN. At step 508, multiple vertical channels (VCs) are formed to orthogonally pass through the multiple layers to conductively couple to one or more CSL layers. To form the VCs, multiple vertical holes (or openings) through the multiple layers may first be formed, for example, by anisotropically etching through the multiple layers in a vertical direction to one or more CSL layers. The etching may be performed by reactive ion etching (RIE) or plasma etching. Subsequently, the VCs may be formed by filling the holes with any one of an insulator / trapping or trapping / insulator combination or only polysilicon (poly) or a polysilicon / insulator combination. The VCs with the filled material may form a memory cell string in a vertical direction.

[0166] During the etching process step (and / or any other subsequent process step), charge may accumulate in the VCs in a vertical direction, and the charge may be released to a semiconductor substrate via one or more discharge circuits, for example, as illustrated in Figure 3A and Figure 3B In some embodiments, as illustrated in Figure 3B and Figure 3C ions are released into an n-type well region in the semiconductor substrate via a p-type transistor, and electrons are released into a p-type well region in the semiconductor substrate via an n-type transistor. In this way, the phenomena of wafer arcing or plasma damage can be avoided or eliminated. At the same time, since the n-type transistor can release electrons, the discharge speed can be increased. Also, in the presence of the n-type transistor, the size (e.g., area) of the p-type transistor can be made smaller, thereby reducing the overall area of one or more discharge circuits and the overall area of the semiconductor device.

[0167] ​In some embodiments, in the following process steps, a type of dielectric layer (e.g., SiN) is etched and replaced with a conductive material (e.g., metal). Multiple VCs can be separated by multiple filled trenches. Each two adjacent filled trenches define a respective block. Each block can include a conductive layer (made of a conductive material) separated from each other by an insulating layer (another type of dielectric layer, such as OX) and a vertical channel orthogonal to the conductive layer and the insulating layer. The vertical channel and the two adjacent filled trenches are coupled to the corresponding CSL of the block. Each page of memory cells can be coupled to a respective word line (e.g., Figure 2B WL 240 or Figure 3A or Figure 4A 318), and each memory cell string can be conductively coupled to a respective bit line (eg, Figure 2B BL252).

[0168] At step 510, after the semiconductor device is nearly complete, conductive lines are formed through the multiple layers to disable one or more discharge circuits, such as in Figures 4A to 4B For example, after the memory array is completed, for example, when there are one or more top layers or metal wiring to be completed on the memory array, the conductive lines can be formed. The conductive lines can include through-array contacts (TACs) and metal wiring on one or more top layers connecting the TACs.

[0169] To disable each p-type transistor, the corresponding conductive line (eg, Figures 4A to 4B The first conductive line 402, the first conductive line 404, the first conductive line 406) can be formed to connect the gate port and the source port of the p-type transistor, so that the gate port, the source port and the base port are all connected together to turn off the function of the p-type transistor.

[0170] To disable the n-type transistor, each discharge circuit may include a second n-type transistor, e.g. Figures 4A to 4B The second n-type transistor 330 can be formed at step 502 along with other p-type transistors and n-type transistors, for example, as in Figures 3A to 3B , but the second n-type transistor is not coupled to the other p-type transistors and the n-type transistor at that time.

[0171] At step 510, the corresponding conductive line (eg, Figures 4A to 4B The second conductive line 430 may be formed to connect the drain port of the second n-type transistor to the gate port of the n-type transistor, while the gate port of the second n-type transistor is coupled to the positive voltage VDD and the source port of the second n-type transistor is coupled to the ground or negative voltage VSS. Therefore, the second n-type transistor can transmit the ground or negative voltage to the gate of the n-type transistor via the conductive line to turn off the n-type transistor. At the same time, since the end p-type transistor (for example,Figures 4A to 4B The drain port of the p-type transistor 326) is coupled to the gate port of the n-type transistor, and the drain port of the p-type transistor is also coupled to ground or a negative voltage. Thus, when a voltage from the CSL layer 314 is applied during an erase operation on a semiconductor device (e.g., a 3D memory device), the voltage can be distributed, for example, evenly among the series-coupled p-type transistors. In this way, the p-type transistors can be prevented from breaking down during the erase operation.

[0172] The disclosed and other examples can be implemented as one or more computer program products, such as one or more modules of computer program instructions encoded on a computer-readable medium, the one or more modules being executed by, or controlling the operation of, a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination of one or more of them. The term “data processing device” encompasses all devices, apparatuses, and machines for processing data, including, for example, programmable processors, computers, or multiple processors or computers. In addition to hardware, the device can include program code that forms an execution environment for the computer programs being discussed, such as program code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0173] The system can encompass all devices, apparatuses, and machines for processing data, including, for example, programmable processors, computers, or multiple processors or computers. In addition to hardware, the system can include program code that forms an execution environment for the computer programs being discussed, such as program code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0174] A computer program (also known as a program, software, software application, instruction code, or program code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for a computing environment. A computer program does not necessarily correspond to a file in a file system. The program can be stored in a part of a file that holds other programs or data (e.g., one or more instruction codes stored in a markup language document), in a single file dedicated to the program being discussed, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or portions of program code). The computer program can be deployed to execute on one computer or on multiple computers distributed at one site or across multiple sites and interconnected by a communication network.

[0175] The processes and logical flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logical flows can also be performed by, and the apparatus can also be implemented as, special purpose logic circuitry, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0176] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto optical disks or optical disks, or be operatively coupled to receive data from, or transfer data to, or both, one or more mass storage devices. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data may include all forms of non volatile memory, media and memory devices, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0177] Although this document may describe many features, these features should not be construed as limitations on the scope of the claimed or claimable disclosure, but rather as descriptions of features specific to particular embodiments. Certain features that are described in the context of separate embodiments in this document may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented separately or in any suitable sub combination in multiple embodiments. In addition, although the features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be deleted from the combination, and the claimed combination may be directed to a sub combination or variation of a sub combination. Similarly, although the operations may be depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed to achieve a desirable result.

[0178] Only a few examples and embodiments are disclosed. Variations, modifications and enhancements to the described examples and embodiments, and other embodiments, can be made based on the disclosed content.

Claims

1. A semiconductor device, comprising: A semiconductor substrate; One or more discharge circuits disposed on the semiconductor substrate; One or more common source line layers conductively coupled to the one or more discharge circuits; And A memory array having a three-dimensional array of memory cells in a plurality of vertical channels disposed on the one or more common source line layers, each of the plurality of vertical channels including a respective memory cell string, and each of the one or more common source line layers being conductively coupled to a corresponding memory cell string, Wherein each of the one or more discharge circuits includes one or more transistors configured to: release accumulated charge during formation of the plurality of vertical channels; and be deactivated by one or more corresponding conductive lines passing through the memory array after formation of the plurality of vertical channels.

2. The semiconductor device according to claim 1, wherein the one or more transistors include: One or more p-type transistors, wherein the gate terminal and the source terminal of each of the one or more p-type transistors are conductively coupled together by a corresponding first conductive line passing through the memory array to deactivate the p-type transistor; And An n-type transistor having a gate terminal conductively coupled to ground or a negative voltage by a second conductive line passing through the memory array to deactivate the n-type transistor.

3. The semiconductor device according to claim 2, wherein each of the one or more discharge circuits further includes a second n-type transistor having: A drain terminal conductively coupled to the gate terminal of the n-type transistor via the second conductive line; A gate terminal coupled to a positive voltage; And A source terminal coupled to the ground or the negative voltage.

4. The semiconductor device according to claim 2, wherein the one or more p-type transistors include: A plurality of p-type transistors serially coupled, with the gate terminal of each of the plurality of p-type transistors coupled to the base terminal of the p-type transistor, Wherein the starting p-type transistor among the plurality of p-type transistors has a source terminal coupled to a corresponding common source line layer of the one or more common source line layers, and the ending p-type transistor among the plurality of p-type transistors has a drain terminal coupled to the gate terminal of the n-type transistor, and Wherein the drain terminal of the n-type transistor is coupled to the corresponding common source line layer.

5. The semiconductor device according to claim 4, wherein the drain terminal of the first p-type transistor is coupled to the source terminal of the second p-type transistor immediately following the first p-type transistor among the plurality of p-type transistors.

6. The semiconductor device according to claim 4, wherein the semiconductor substrate includes an n-type well region and a p-type well region, and Wherein the drain terminal of the ending p-type transistor is in the n-type well region, and the source terminal of the n-type transistor is in the p-type well region.

7. The semiconductor device according to claim 1, wherein the one or more discharge circuits are around the memory array on the semiconductor substrate.

8. The semiconductor device according to claim 1, further comprising an integrated circuit on the semiconductor substrate, the integrated circuit including the one or more discharge circuits, wherein the one or more common source line layers are configured on top of the integrated circuit.

9. The semiconductor device according to claim 1, wherein the memory array includes a plurality of blocks separated by a plurality of filled channels, each block of the plurality of blocks being between two adjacent filled channels and including: conductive layers separated from each other by insulating layers; and vertical channels orthogonally passing through the conductive layers and the insulating layers, wherein the vertical channels and the two adjacent filled channels are coupled to a corresponding common source line layer of the block, and wherein each page of the memory cells is coupled to a respective word line, and each memory cell string is conductively coupled to a respective bit line.

10. A semiconductor device, comprising: a semiconductor substrate; one or more discharge circuits configured on the semiconductor substrate; one or more common source line layers conductively coupled to the one or more discharge circuits; and a plurality of vertical channels extending through a plurality of layers and configured on the one or more common source line layers, each common source line layer of the one or more common source line layers being conductively coupled to a corresponding vertical channel of the plurality of vertical channels, wherein each of the one or more discharge circuits includes: a plurality of p-type transistors serially coupled to a corresponding common source line layer of the one or more common source lines, each p-type transistor of the plurality of p-type transistors having a base port and a gate port coupled together, and an n-type transistor having a drain port coupled to the corresponding common source line layer, wherein a starting p-type transistor among the plurality of p-type transistors has a source port coupled to the corresponding common source line layer, and an ending p-type transistor among the plurality of p-type transistors has a drain port coupled to the gate port of the n-type transistor, and each discharge circuit is configured to: release accumulated charge during formation of the plurality of vertical channels; be deactivated after formation of the plurality of vertical channels.

11. The semiconductor device according to claim 10, wherein a source port and the gate port of each p-type transistor of the plurality of p-type transistors are conductively coupled by a corresponding first conductive line passing through the plurality of layers to deactivate the p-type transistor; and wherein the gate port of the n-type transistor is conductively coupled to ground or a negative voltage by a second conductive line passing through the plurality of layers to deactivate the n-type transistor.

12. The semiconductor device according to claim 11, wherein each of the one or more discharge circuits further includes a second n-type transistor, the second n-type transistor: a drain port conductively coupled to the gate port of the n-type transistor via the second conductive line; a gate port coupled to a positive voltage; and a source port coupled to the ground or the negative voltage.

13. The semiconductor device according to claim 10, wherein the semiconductor substrate includes an n-type well region and a p-type well region, and wherein the drain port of the ending p-type transistor is in the n-type well region, and the source port of the n-type transistor is in the p-type well region.

14. The semiconductor device according to claim 10, wherein the one or more discharge circuits are around the plurality of layers on the semiconductor substrate.

15. The semiconductor device according to claim 10, comprising: a memory array having a three-dimensional array of memory cells configured in the plurality of vertical channels, each of the plurality of vertical channels including a respective memory cell string, each of the one or more common source line layers being conductively coupled to a corresponding memory cell string, wherein the memory array includes a plurality of blocks separated by a plurality of filled channels, each of the plurality of blocks being between two adjacent filled channels, wherein the vertical channels and the two adjacent filled channels are coupled to a corresponding common source line layer of the block, and wherein each page of the memory cells is coupled to a respective word line, and each memory cell string is conductively coupled to a respective bit line.

16. A method of forming a semiconductor device, the method comprising: forming one or more discharge circuits on a semiconductor substrate, each of the one or more discharge circuits including one or more transistors; forming one or more common source line layers conductively coupled to the one or more discharge circuits; forming a plurality of vertical channels orthogonally passing through a plurality of layers on the one or more common source line layers to conductively couple to the one or more common source line layers, wherein each common source line layer of the one or more common source line layers is configured to conductively couple to a corresponding vertical channel of the plurality of vertical channels such that the one or more discharge circuits release charges generated in the corresponding vertical channel; and after forming the plurality of vertical channels, forming one or more conductive lines passing through the plurality of layers to deactivate the one or more discharge circuits.

17. The method of forming a semiconductor device according to claim 16, wherein the one or more transistors include: a plurality of p-type transistors serially coupled, and an n-type transistor, wherein the base port and the gate port of each p-type transistor of the plurality of p-type transistors are coupled together, wherein the source port of the starting p-type transistor among the plurality of p-type transistors and the drain port of the n-type transistor are coupled to a corresponding common source line layer of the one or more common source line layers, and wherein the drain port of the ending p-type transistor among the plurality of p-type transistors is coupled to the gate port of the n-type transistor.

18. The method of forming a semiconductor device according to claim 17, wherein forming the conductive lines passing through the plurality of layers to deactivate the one or more discharge circuits includes: forming a corresponding first conductive line passing through the plurality of layers to couple the gate port and the source port of each p-type transistor of the plurality of p-type transistors together to deactivate the p-type transistors; and Form a second conductive line through the plurality of layers to couple the n-type transistor to ground or a negative voltage to deactivate the n-type transistor.

19. The method of forming a semiconductor device according to claim 18, wherein each of the one or more discharge circuits includes a second n-type transistor having: a gate port coupled to a positive voltage; a source port coupled to the ground or the negative voltage; and a drain port, wherein forming the second conductive line through the plurality of layers to couple the n-type transistor to the ground or the negative voltage includes: forming the second conductive line to conductively couple the drain port of the second n-type transistor to the gate port of the n-type transistor.

20. The method of forming a semiconductor device according to claim 17, wherein the semiconductor substrate includes an n-type well region and a p-type well region, and wherein forming the one or more discharge circuits on the semiconductor substrate includes: forming the drain port of the terminating p-type transistor in the n-type well region and forming the source port of the n-type transistor in the p-type well region.

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