Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a display area and a non-display area, the display area comprises a first display area and a second display area, the first display area is provided with a plurality of first data lines and a plurality of first connecting lines, the second display area is provided with a plurality of second data lines and a plurality of second connecting lines, the first data lines, the first connecting lines, the second data lines and the second connecting lines all extend along a first direction, and the length of the extension is equal to the width of the display area along the first direction; the display area is provided with a plurality of third connecting lines, the third connecting lines extend along a second direction, and the length of the extension is equal to the width of the display area along the second direction; the third connecting lines comprise first sub connecting lines and second sub connecting lines, wherein the second data lines and the first connecting lines are connected through the first sub connecting lines, and the second connecting lines and the first data lines are connected through the second sub connecting lines. The display panel provided by the application has a better display effect.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more particularly to a display panel and display device. Background Technology

[0002] With the widespread use of electronic devices, various electronic devices equipped with displays are becoming increasingly common, such as mobile phone screens, monitors, and electronic billboards. To obtain a better visual experience, people are demanding higher and higher display quality from these devices.

[0003] In related technologies, the lower bezel of the display panel is designed with a fan-out area, which has multiple fan-out lines. These fan-out lines are used to transmit data signals output by the integrated circuit (IC) to the data lines in the display area. Each column of pixels in the display area has a corresponding data line, which drives multiple pixels in the corresponding column. The multiple fan-out lines are connected one-to-one with the multiple data lines.

[0004] However, the above-mentioned data cable arrangement has an uneven distribution density, which affects the display effect of the display panel. Summary of the Invention

[0005] In view of at least one of the above-mentioned technical problems, the embodiments of this application provide a display panel and a display device with better display effect.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] A first aspect of this application provides a display panel, including a display area and a non-display area at least partially surrounding the display area. The display area includes a first display area and a second display area, the second display area being located on at least one side of the first display area. The non-display area includes a fan-out area, the fan-out area being disposed corresponding to the first display area.

[0008] The first display area has multiple first data lines and multiple first connection lines, and the second display area has multiple second data lines and multiple second connection lines. The first data lines, first connection lines, second data lines and second connection lines all extend along a first direction, and their extension length is equal to the width of the display area along the first direction.

[0009] The display area has multiple third connecting lines, which extend along the second direction and their length is equal to the width of the display area along the second direction. The first and second directions intersect.

[0010] The third connection line includes a first sub-connection line and a second sub-connection line, wherein the second data line and the first connection line are connected through the first sub-connection line, and the second connection line and the first data line are connected through the second sub-connection line.

[0011] This approach not only enhances the narrow bezel effect but also effectively addresses the issue of significant metal density variations across different areas of the display panel in related technologies, thereby improving the display's overall performance. Furthermore, the equal load on the first and second data lines ensures consistent voltage across all pixels, resulting in uniform brightness across the display panel.

[0012] In one possible implementation, the sum of the number of first data lines and the number of second data lines in the display panel provided in this application is equal to the sum of the number of first connecting lines and the number of second connecting lines.

[0013] What can be achieved is that multiple first data lines and multiple first connecting lines are arranged alternately and at intervals along the second direction;

[0014] What can be achieved is that multiple second data lines and multiple second connecting lines are arranged alternately and at intervals along the second direction.

[0015] This helps reduce the difference in metal density across different areas of the display panel, thereby improving the display effect.

[0016] In one possible implementation, the display panel provided in this application has multiple first sub-connecting lines and multiple second sub-connecting lines arranged at intervals along a first direction.

[0017] This helps reduce the difference in metal density in the display panel and improves the display effect.

[0018] In one possible implementation, the number of first sub-connecting lines in the display panel provided by this application is equal to the number of second data lines;

[0019] And / or, the number of second sub-connectors is equal to the number of first data lines.

[0020] This ensures that the first sub-connector is connected to the second data line in a one-to-one correspondence, and the second sub-connector is connected to the first data line in a one-to-one correspondence, thus reducing the load on the first and second data lines.

[0021] In one possible implementation, the display panel provided in this application has two second display areas, which are located on opposite sides of the first display area along the second direction.

[0022] What is possible is that the two second display areas are set symmetrically about the first display area.

[0023] This helps to improve the effect of narrow bezels.

[0024] In one possible implementation, the display panel provided in this application has the first data line and the second data line arranged in the same layer along the film layer stacking direction of the display panel, the first connecting line and the first connecting line arranged in the same layer, and the first sub-connecting line and the second sub-connecting line arranged in the same layer.

[0025] The first data line and the first connecting line are on different layers from the third connecting line.

[0026] This reduces the number of metal layers in the display panel, making it easier to process.

[0027] In one possible implementation, the display panel provided in this application has the first data line and the first connection line arranged on the same layer;

[0028] A dielectric layer is provided between the first data line and the first connecting line and the third connecting line;

[0029] The second data line and the first connection line are respectively connected to the first sub-connection line through a first via on the dielectric layer, and the first data line and the second connection line are respectively connected to the second sub-connection line through a second via on the dielectric layer.

[0030] In this way, the connection between the second data line and the first connecting line and the first sub-connecting line can be achieved, as well as the connection between the first data line and the second connecting line and the second sub-connecting line.

[0031] In one possible implementation, the display panel provided in this application has the first data line and the first connecting line arranged on different layers.

[0032] A dielectric layer is provided between the first data line and the third connection line, as well as between the first connection line and the third connection line;

[0033] The first data line and the second sub-connection line are connected through a third via on the dielectric layer between the first data line and the third connection line, and the second data line and the first sub-connection line are connected through a fourth via on the dielectric layer between the first data line and the third connection line.

[0034] The first connecting line and the first sub-connecting line are connected through a fifth via on the dielectric layer between the first connecting line and the third connecting line, and the second connecting line and the second sub-connecting line are connected through a sixth via on the dielectric layer between the first connecting line and the third connecting line.

[0035] In this way, the second data line and the first connecting line can be connected to the first sub-connecting line, and the first data line and the first connecting line can be connected to the second sub-connecting line.

[0036] In one possible implementation, the display panel provided in this application includes a substrate, a semiconductor layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, a third dielectric layer, a third metal layer, a fourth dielectric layer, and a fourth metal layer, which are sequentially stacked along the film layer stacking direction of the display panel.

[0037] The first data line and the first connecting line are arranged on the same layer. One of the first data line and the third connecting line is located on the third metal layer, and the other is located on the fourth metal layer.

[0038] This reduces the number of metal layers in the display panel and simplifies the manufacturing process.

[0039] Alternatively, a fifth dielectric layer and a fifth metal layer are sequentially stacked on the side of the fourth metal layer away from the substrate; the first data line and the first connection line are disposed on different layers, with the first data line, the first connection line, and the third connection line located on the third metal layer, the second on the fourth metal layer, and the third on the fifth metal layer.

[0040] This reduces the space occupied by wiring in the metal layer, making wiring more flexible.

[0041] A second aspect of this application provides a display device including the display panel provided in the first aspect.

[0042] The display device is made from the aforementioned display panel. This display device has the same technical effect as the aforementioned display panel, namely, while improving the narrow bezel effect, it effectively solves the problem of large differences in metal density at various locations on the display panel in related technologies. Furthermore, the first data line and the second data line have equal loads, and the voltage of each pixel is consistent, thereby improving the display effect of the display panel and the display device using the display panel.

[0043] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a top view of a display panel in the related technology;

[0046] Figure 2 A top view of the display panel provided in an embodiment of this application;

[0047] Figure 3 This is a wiring diagram of a display panel provided in an embodiment of this application;

[0048] Figure 4 for Figure 2 The first type of cross-section along the AA direction;

[0049] Figure 5 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0050] Figure 6 for Figure 2 The second type of cross-section along the AA direction;

[0051] Figure 7 for Figure 2 The third type of cross-section along the AA direction;

[0052] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0053] Explanation of reference numerals in the attached figures:

[0054] 10 - Data lines; 11 - First data line; 12 - Second data line; 20 - Fan-out area; 30 - First zone; 40 - Second zone; 50 - First connecting line;

[0055] 100 - Display panel;

[0056] 110 - Display area; 111 - First display area; 1111 - First data line; 1112 - First connecting line; 112 - Second display area; 1121 - Second data line; 1122 - Second connecting line; 113 - First side; 120 - Non-display area; 121 - Fan-out area; 130 - Third connecting line; 131 - First sub-connecting line; 132 - Second sub-connecting line; 140 - Substrate; 150 - Semiconductor layer; 160 - First dielectric layer; 170 - First metal layer; 180 - Second dielectric layer; 190 - Second metal layer; 1100 - Third dielectric layer; 1110 - Third metal layer; 1120 - Fourth dielectric layer; 1130 - Fourth metal layer; 1140 - Fifth dielectric layer; 1150 - Fifth metal layer; 1160 - Sixth dielectric layer; 1170 - Anode;

[0057] 200, 200a, 200b - First connection point;

[0058] 300, 300a, 300b - Second connection point. Detailed Implementation

[0059] In related technologies, the display area is divided into a first area and a second area. The first area corresponds to the fan-out area, and the second area is offset from the fan-out area. By using the data lines of the second area to lead the data lines of the first area to the fan-out area, the narrow bezel effect can be improved.

[0060] Figure 1 This is a top view of a display panel in related technologies. See also... Figure 1 As shown, the display panel includes multiple data lines 10 extending along a first direction. Each data line 10 includes multiple first data lines 11 and multiple second data lines 12. The first data lines 11 are located in a first area 30, and the second data lines 12 are located in a second area 40. The display panel also includes multiple first connecting lines 50. Fan-out lines are connected to corresponding second data lines 12 via the first connecting lines 50. In other words, the second data lines 12 are led to the fan-out area 20 via the first connecting lines 50.

[0061] The first direction is Figure 1 In the Y direction, the second direction is Figure 1 The X direction in the equation.

[0062] However, as Figure 1 As shown, the first connecting lines 50 are only distributed on the side of the display area near the fan-out area 20, and there is a gap between two first connecting lines 50 at the same position along the Y direction. The intersection of the first connecting line 50 and the second data line 12 is the connection point, i.e. Figure 1 The area indicated by the circle in the middle. The first connecting lines 50 are only distributed on the side facing the first area 30 at their corresponding connection points. That is, the distribution density of the first connecting lines 50 within the display area is not uniform along the Y and X directions. This results in significant differences in metal density across different locations on the display panel, leading to variations in reflectivity. Areas with higher metal density reflect more light, and vice versa, resulting in poor display quality.

[0063] Furthermore, such as Figure 1As shown, the first data line 11 of the first zone 30 is directly connected to the fan-out line, and the second data line 12 of the second zone 40 is led to the fan-out zone 20 via the first connecting line 50. Since the sum of the lengths of the second data line 12 and the first connecting line 50 is greater than the length of the first data line 11, the resistance value on the routing path of the first data line 11 to the fan-out zone is different from the resistance value on the routing path of the second data line 12 to the fan-out zone. Furthermore, parasitic capacitances between the first connecting line 50 and the first data line 11 are formed at the intersection points of their projections onto the display panel plane and the projections of each first data line 11 onto the display panel plane. The same applies to the second data line 12. Because the number of intersection points between the projections of the first connecting line 50 and the projections of each first data line 11 and each second data line 12 onto the display panel plane is different, the parasitic capacitances formed between each first data line 11, each second data line 12, and the first connecting line 50 are different. Therefore, the loads of each first data line 11 and each second data line 12 are different, resulting in differences in the driving voltage of the pixels driven by the first data line 11 and the second data line 12, and uneven display brightness of the display panel.

[0064] To address the aforementioned technical problems, this application provides a display panel and a display device. The display panel includes a display area and a non-display area. The display area includes a first display area and at least one second display area, with the at least one second display area located on one side of the first display area. The non-display area includes a fan-out area, which is correspondingly disposed to the first display area. The first display area has multiple first data lines and multiple first connecting lines. The second display area has multiple second data lines and multiple second connecting lines. The first data lines, first connecting lines, second data lines, and first connecting lines all extend along a first direction, and their extension length is equal to the width of the display area along the first direction. The display area has multiple third connecting lines, which extend along a second direction, and their extension length is equal to the width of the display area along the second direction. The first and second directions intersect. The third connecting lines include first sub-connecting lines and second sub-connecting lines, wherein the second data lines and the first connecting lines are connected through the first sub-connecting lines, and the second connecting lines and the first data lines are connected through the second sub-connecting lines. In this way, the first and second connecting lines are evenly distributed along the first direction, and the third connecting lines are evenly distributed along the second direction. The second data line is led to the fan-out area by means of the third and first connecting lines. While improving the narrow bezel effect, this can effectively solve the problem of large differences in metal density at various positions of the display panel in related technologies, and improve the display effect of the display panel.

[0065] The third connection line includes a first sub-connection line and a second sub-connection line. The second data line and the first connection line are connected through the first sub-connection line, and the second connection line and the first data line are connected through the second sub-connection line. Thus, the sum of the lengths of the second data line, the first connection line, and the first sub-connection line is equal to the sum of the lengths of the second connection line, the first data line, and the second sub-connection line. In other words, the resistance value on the trace path from the first data line to the fan-out area is equal to the resistance value on the trace path from the second data line to the fan-out area.

[0066] The number of overlap points between the orthographic projections of each first data line and the orthographic projections of the third connecting line on the same plane is the same, and the number of overlap points within the same first data line is equal to the number of third connecting lines. The number of overlap points between the orthographic projections of each first connecting line and the orthographic projections of the third connecting line on the same plane is the same, and the number of overlap points within the same first connecting line is equal to the number of third connecting lines. The number of overlap points between the orthographic projections of each third connecting line and the orthographic projections of the first connecting line, second connecting line, first data line, and second data line on the same plane is the same, and the number of overlap points within the same third connecting line is equal to the sum of the numbers of the first connecting line, second connecting line, first data line, and second data line. The number of overlap points between the orthographic projections of each second data line and the orthographic projections of the third connecting line on the same plane is the same, and the number of overlap points within the same second data line is equal to the number of third connecting lines. The number of overlap points between the orthographic projections of each second connecting line on the plane of the display panel and the orthographic projections of the third connecting line on the same plane is the same. Within the same second connecting line, the number of overlap points equals the number of third connecting lines. Therefore, the parasitic capacitances of the first data line and the third connecting line, and the second data line and the third connecting line are equal. Furthermore, the parasitic capacitance of each third connecting line is equal to that of any one of the first connecting line, the second connecting line, the first data line, and the second data line. Thus, the loads on the first data line and the second data line are equal.

[0067] Therefore, connecting the second data line and the first connecting line through the first sub-connecting line, and connecting the second connecting line and the first data line through the second sub-connecting line, ensures that the load of each first data line and each second data line is the same, the driving voltage of each pixel driven by the first data line and the second data line is consistent, and the display brightness of the display panel is uniform.

[0068] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0069] The display panel provided in the embodiments of this application will be described below.

[0070] Figure 2 This is a top view of the display panel provided in an embodiment of this application. Figure 3 This is a wiring diagram of a display panel provided in an embodiment of this application.

[0071] See Figure 2 and Figure 3 As shown, in a first aspect, embodiments of this application provide a display panel 100, including a display area 110 and a non-display area 120 at least partially surrounding the display area 110. The display area 110 includes a first display area 111 and a second display area 112, with the second display area 112 located on at least one side of the first display area 111. The non-display area 120 includes a fan-out area 121, which is correspondingly disposed with respect to the first display area 111.

[0072] The first display area 111 has multiple first data lines 1111 and multiple first connecting lines 1112, and the second display area 112 has multiple second data lines 1121 and multiple second connecting lines 1122. The first data lines 1111, the first connecting lines 1112, the second data lines 1121 and the second connecting lines 1122 all extend along a first direction, and their extension length is equal to the width of the display area 110 along the first direction.

[0073] The display area 110 has multiple third connecting lines 130, which extend along a second direction and have a length equal to the width of the display area 110 along the second direction. The first and second directions intersect.

[0074] The third connection line 130 includes a first sub-connection line 131 and a second sub-connection line 132, wherein the second data line 1121 and the first connection line 1112 are connected through the first sub-connection line 131, and the second connection line 1122 and the first data line 1111 are connected through the second sub-connection line 132.

[0075] It should be noted that the first direction is Figure 2 The Y-axis direction in the coordinate system, the second direction is Figure 2 The X-axis direction in the coordinate system.

[0076] The fan-out area 121 is located in the non-display area 120 and on one side of the display area 110 along the Y-axis. The fan-out area 121 is correspondingly set with the first display area 111. Here, "corresponding" can be understood as the display area 110 including a first side 113 near the fan-out area 121. The orthographic projection of the first display area 111 along the Y-axis onto the first side 113 at least partially overlaps with the orthographic projection of the fan-out area 121 along the Y-axis onto the first side 113.

[0077] In some embodiments, the length of the fan-out area 121 along the X-axis is equal to the length of the first display area 111 along the X-axis, and the two ends of the fan-out area 121 along the X-axis are aligned with the two ends of the first display area 111 along the X-axis in the Y-axis direction.

[0078] It should be noted that the connection point between the second data line 1121 and the first sub-connecting line 131, and the connection point between the first connecting line 1112 and the first sub-connecting line 131, is the first connection point 200. The first connection point 200 is located at... Figure 2 The location indicated by the circle in the middle. The connection point between the second connecting line 1122 and the second sub-connecting line 132, as well as the connection point between the first data line 1111 and the second sub-connecting line 132, is the second connection point 300. The second connection point 300 is located at... Figure 2 The position indicated by the middle triangle.

[0079] See Figure 3 As shown, the wiring has been simplified for ease of explanation. Two third connecting lines 130 are retained in the figure. The two third connecting lines 130 are the first sub-connecting line 131 and the second sub-connecting line 132, respectively. Only one first data line 1111 and one first connecting line 1112 are retained in the first display area 111, and only one second data line 1121 and one second connecting line 1122 are retained in the second display area 112.

[0080] Specifically, the second data line 1121 is connected to the first sub-connecting line 131 through the first connection point 200a, and the first sub-connecting line 131 is connected to the first connecting line 1112 through the first connection point 200b. The first data line 1111 is connected to the second sub-connecting line 132 through the second connection point 300a, and the second sub-connecting line 132 is connected to the second connecting line 1122 through the second connection point 300b.

[0081] The display panel 100 can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro LED or μLED) display panel, or a liquid crystal display (LCD) display panel.

[0082] The display panel 100 may include an array substrate and a light-emitting layer located on the array substrate. Multiple driving units are disposed in the array substrate, and these driving units can be arranged in an array. The driving units are electrically connected to the light-emitting layer and are used to control the light emission of the light-emitting layer. The driving units may include thin-film transistors (TFTs) and capacitor structures. The first data line 1111, the first connection line 1112, the second data line 1121, the second connection line 1122, and the third connection line 130 in this application may all be located in the array substrate.

[0083] The light-emitting layer includes an anode layer, a light-emitting material layer, and a cathode layer stacked sequentially, as well as an electron blocking layer and a hole transport layer located between the anode layer and the light-emitting material layer, and a hole blocking layer and an electron transport layer located between the cathode layer and the light-emitting material layer. The specific structure of the light-emitting layer is not limited in the embodiments of this application.

[0084] An encapsulation layer is disposed on the side of the light-emitting layer facing away from the substrate. The encapsulation layer can employ thin film encapsulation (TFE) technology and may include multiple encapsulation sub-film layers. The encapsulation layer may include inorganic layers and / or organic layers. For example, the encapsulation layer may adopt a film structure of overlapping inorganic / organic / inorganic layers. The inorganic layers are used to effectively block water and oxygen, while the organic layers are used to buffer the stress within the inorganic layers.

[0085] See Figure 2 As shown, the display area 110 occupies most of the area of ​​the display panel 100 and is used for emitting light and displaying images.

[0086] Fan-out area 121 has fan-out lines, which are used to transmit data signals output by the driving circuit to the first data line 1111 and the second data line 1121. Each column of pixels in the first display area 111 is provided with a corresponding first data line 1111, and each column of pixels in the second display area 112 is provided with a corresponding second data line 1121. The first data line 1111 and the second data line 1121 are used to drive multiple pixels in the corresponding column.

[0087] The number of second display areas 112 can be one or two.

[0088] In this embodiment, the display panel 100 has a first data line 1111, a first connecting line 1112, a second data line 1121, and a first connecting line 1112 extending along a first direction, with the length of their extension equal to the width of the display area 110 along the first direction. This ensures that each of the second data lines 1121, first connecting lines 1112, and second connecting lines 1122 is evenly distributed along the first direction. A third connecting line 130 extends along a second direction, with the length of its extension equal to the width of the display area 110 along the second direction. This also ensures that each of the third connecting lines 130 is evenly distributed along the second direction. The second data line 1121 is led to the fan-out area 121 via the third connecting line 130 and the first connecting line 1112. This improves the narrow bezel effect and effectively solves the problem of large differences in metal density at various locations of the display panel 100 in related technologies, thereby improving the display effect of the display panel 100.

[0089] It should be noted that the load of the first data line 1111 includes the resistance on the routing path from the first data line 1111 to the fan-out area 121 and the parasitic capacitance of the routing path from the first data line 1111 to the fan-out area 121 with other wire harnesses. Specifically, the resistance value on the routing path from the first data line 1111 to the fan-out area 121 is determined by the lengths of the first data line 1111, the second connecting line 1122, and the first sub-connecting line 131, which are connected. The parasitic capacitance of the routing path from the first data line 1111 to the fan-out area 121 with other wire harnesses is determined by the number of intersection points of the orthographic projections of the first data line 1111, the second connecting line 1122, and the second sub-connecting line 132 on the plane of the display panel 100 with other wire harnesses (i.e., the third connecting line 130 without connection, or the first data line 1111 and the second connecting line 1122 without connection). Similarly, the load of the second data line 1121 includes the resistance on the routing path of the second data line 1121 to the fan-out area and the parasitic capacitance of the routing path of the second data line 1121 to the fan-out area 121 and other wire harnesses, which will not be elaborated here.

[0090] The second data line 1121 and the first connecting line 1112 are connected by the first sub-connecting line 131, and the second connecting line 1122 and the first data line 1111 are connected by the second sub-connecting line 132. Thus, the sum of the lengths of the second data line 1121, the first connecting line 1112, and the first sub-connecting line 131 is equal to the sum of the lengths of the second connecting line 1122, the first data line 1111, and the second sub-connecting line 132. In other words, the resistance on the trace path from the first data line 1111 to the fan-out area 121 is equal to the resistance on the trace path from the second data line 1121 to the fan-out area 121.

[0091] The number of overlapping points between the orthographic projections of each first data line 1111 on the plane of the display panel 100 and the orthographic projections of the third connecting line 130 on the plane of the display panel 100 is the same, and the number of overlapping points in the same first data line 1111 is equal to the number of third connecting lines 130. Similarly, the number of overlapping points between the orthographic projections of each first connecting line 1112 on the plane of the display panel 100 and the orthographic projections of the third connecting line 130 on the plane of the display panel 100 is the same, and the number of overlapping points in the same first connecting line 1112 is equal to the number of third connecting lines 130.

[0092] The number of overlapping points between the orthographic projection of each third connecting line 130 on the plane of the display panel 100 and the orthographic projection of the first connecting line 1112, the second connecting line 1122, the first data line 1111, and the second data line 1121 on the plane of the display panel 100 is the same. The number of overlapping points in the same third connecting line 130 is equal to the sum of the numbers of the first connecting line 1112, the second connecting line 1122, the first data line 1111, and the second data line 1121.

[0093] The number of overlapping points between the orthographic projection of each second data line 1121 on the plane of the display panel 100 and the orthographic projection of the third connecting line 130 on the plane of the display panel 100 is the same, and the number of overlapping points in the same second data line 1121 is equal to the number of third connecting lines 130.

[0094] The number of overlap points between the orthographic projections of each second connection line 1122 onto the plane of the display panel 100 and the orthographic projections of the third connection line 130 onto the plane of the display panel 100 is the same, and the number of overlap points in the same second connection line 1122 is equal to the number of third connection lines 130. Therefore, the parasitic capacitances of the first data line 1111 and the third connection line 130, and the parasitic capacitances of the second data line 1121 and the third connection line 130 are equal, the parasitic capacitances of the first connection line 1112 and the third connection line 130, and the parasitic capacitances of each third connection line 130 are equal to those of any one of the first connection line 1112, the second connection line 1122, the first data line 1111, and the second data line 1121.

[0095] Therefore, it can be seen that the resistance on the routing path of the first data line 1111 to the fan-out area 121 is equal to the resistance on the routing path of the second data line 1121 to the fan-out area 121. The parasitic capacitance of the routing path of the first data line 1111 to the fan-out area 121 is equal to that of other wire harnesses, and the parasitic capacitance of the routing path of the second data line 1121 to the fan-out area 121 is equal to that of other wire harnesses. That is, the loads of the first data line 1111 and the second data line 1121 are equal. Therefore, connecting the second data line 1121 and the first connecting line 1112 through the first sub-connecting line 131, and connecting the second connecting line 1122 and the first data line 1111 through the second sub-connecting line 132, ensures that the loads of each first data line 1111 and each second data line 1121 are equal, the voltage of each pixel is consistent, and the display brightness of the display panel 100 is uniform.

[0096] In this embodiment, the sum of the number of first data lines 1111 and the number of second data lines 1121 is equal to the sum of the number of first connecting lines 1112 and the number of second connecting lines 1122.

[0097] It is understood that the second data line 1121 and the first connecting line 1112, as well as the second connecting line 1122 and the first data line 1111, are respectively connected by different third connecting lines 130. Two different implementation methods can be included when the sum of the number of first data lines 1111 and the number of second data lines 1121 is equal to the sum of the number of first connecting lines 1112 and the number of second connecting lines 1122.

[0098] In the first implementation, the number of first data lines 1111 and the number of second data lines 1121 are different. For example, there are five first data lines 1111 and six second data lines 1121, six first connecting lines 1112 and five second connecting lines 1122. That is, the second data lines 1121 and 1112 are connected in a one-to-one correspondence, and the second connecting lines 1122 and 1111 are connected in a one-to-one correspondence. This ensures that there are no redundant first connecting lines 1112 and 1122, thus avoiding increasing the load on the first data lines 1111 and 1121.

[0099] In the second implementation, the number of first data lines 1111 and the number of second data lines 1121 are equal. For example, there are five first data lines 1111, five second data lines 1121, five first connecting lines 1112, and five second connecting lines 1122. This reduces the length of the fan-out area along the second direction to half the length of the display area 110 along the second direction, improving the narrow bezel effect.

[0100] Specifically, multiple first data lines 1111 and multiple first connecting lines 1112 are arranged alternately along the second direction. That is, each column of pixels in the first display area 111 is provided with one first data line 1111 and one first connecting line 1112. This helps to reduce the difference in metal density of the display panel 100 and improve the display effect of the display panel 100.

[0101] Specifically, multiple second data lines 1121 and multiple second connecting lines 1122 are arranged alternately along the second direction. That is, each column of pixels in the second display area 112 is provided with one second data line 1121 and one second connecting line 1122. This helps to reduce the difference in metal density of the display panel 100 and improve the display effect of the display panel 100.

[0102] In one possible implementation, multiple first sub-connecting lines 131 and multiple second sub-connecting lines 132 are arranged at intervals along a first direction. This helps to reduce the metal density difference of the display panel 100 and improve the display effect of the display panel 100.

[0103] In this embodiment, the number of first sub-connecting lines 131 is equal to the number of second data lines 1121. This ensures a one-to-one correspondence between the first sub-connecting lines 131 and the second data lines 1121, while reducing the parasitic capacitance between the first data line 1111 and the third connecting line 130, as well as between the second data line 1121 and the third connecting line 130, thereby reducing the load on the first data line 1111 and the second data line 1121.

[0104] In some embodiments, the number of second sub-connecting lines 132 is equal to the number of first data lines 1111. This ensures that the second sub-connecting lines 132 are connected one-to-one with the second data lines 1121, while reducing the parasitic capacitance between the first data lines 1111 and the third connecting line 130, as well as between the second data lines 1121 and the third connecting line 130, thereby reducing the load on the first data lines 1111 and the second data lines 1121.

[0105] In one possible implementation, there are two second display areas 112, which are located on opposite sides of the first display area 111 along the second direction.

[0106] Understandably, this allows the second data lines 1121 in the two second display areas 112 on both sides to be led to the fan-out area 121 through the first sub-connecting line 131 and the first connecting line 1112, thereby improving the narrow bezel effect.

[0107] Specifically, the two second display areas 112 are symmetrically arranged about the first display area 111. In this way, the second data line 1121 and the second connecting line 1122 in the two second display areas 112 are symmetrical about the first display area 111. Thus, the fan-out area 121 is located in the middle area of ​​the non-display area 120, which helps to improve the narrow bezel effect.

[0108] Specifically, the first direction and the second direction are perpendicular to each other. In this way, the length difference between each first data line 1111, each second data line 1121, each first connecting line 1112 and each second connecting line 1122, as well as the length difference between each third connecting line 130, can be reduced, thereby reducing the difference in resistance value on the trace path from the first data line 1111 to the fan-out area and the difference in resistance value on the trace path from the second data line 1121 to the fan-out area.

[0109] In one possible implementation, the display panel 100 provided in this application has the first data line 1111 and the second data line 1121 arranged in the same layer along the film layer stacking direction of the display panel 100; the first connecting line 1112 and the second connecting line 1122 arranged in the same layer; and the first sub-connecting line 131 and the second sub-connecting line 132 arranged in the same layer. This reduces the number of metal layers in the display panel 100, facilitating processing.

[0110] To avoid direct connection between the first data line 1111, the second data line 1121, the first connecting line 1112, the second connecting line 1122 and the third connecting line 130, the first data line 1111 and the first connecting line 1112 are on different layers from the third connecting line 130.

[0111] In some embodiments, the display panel 100 provided in this application has a first data line 1111 and a first connecting line 1112 disposed on the same layer. A dielectric layer is disposed between the first data line 1111 and the first connecting line 1112 and the third connecting line 130. The second data line 1121 and the first connecting line 1112 are respectively connected to the first sub-connecting line 131 through a first via on the dielectric layer, and the first data line 1111 and the first connecting line 1112 are respectively connected to the second sub-connecting line 132 through a second via on the dielectric layer.

[0112] This allows for the connection of the second data line 1121 and the first connecting line 1112 to the first sub-connecting line 131, and the connection of the first data line 1111 and the first connecting line 1112 to the second sub-connecting line 132. Furthermore, it reduces the number of metal layers in the display panel 100 and simplifies the manufacturing process.

[0113] In one possible implementation, the display panel 100 provided in this application has the first data line 1111 and the first connecting line 1112 arranged on different layers. A dielectric layer is provided between the first data line 1111 and the third connecting line 130, and between the first connecting line 1112 and the third connecting line 130.

[0114] The first data line 1111 and the second sub-connection line 132 are connected through a third via on the dielectric layer between the first data line 1111 and the second sub-connection line 132, and the second data line 1121 and the first sub-connection line 131 are connected through a fourth via on the dielectric layer between the first data line 1111 and the third connection line 130.

[0115] The first connecting line 1112 and the first sub-connecting line 131 are connected through a fifth via on the dielectric layer between the first connecting line 1112 and the third connecting line 130, and the second connecting line 1122 and the second sub-connecting line 132 are connected through a sixth via on the dielectric layer between the first connecting line 1112 and the third connecting line 130.

[0116] This allows for the connection of the second data line 1121 and the first connecting line 1112 to the first sub-connecting line 131, and the connection of the first data line 1111 and the first connecting line 1112 to the second sub-connecting line 132. Furthermore, by setting the first data line 1111 and the first connecting line 1112 on different layers, the space occupied by wiring in the metal layer can be reduced, allowing for more flexible wiring.

[0117] Figure 4 for Figure 2 The first type of cross-section along the AA direction. Figure 5 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0118] See Figure 4 and Figure 5 As shown, the display panel 100 includes a substrate 140, a semiconductor layer 150, a first dielectric layer 160, a first metal layer 170, a second dielectric layer 180, a second metal layer 190, a third dielectric layer 1100, a third metal layer 1110, a fourth dielectric layer 1120, and a fourth metal layer 1130, which are sequentially stacked along the film layer stacking direction of the display panel 100.

[0119] The substrate 140 can be a flexible substrate, which is easy to bend. Alternatively, the substrate 140 can be a rigid substrate, such as a glass substrate.

[0120] The semiconductor layer 150 includes an active layer of multiple transistors. A buffer layer is disposed between the substrate 140 and the active layer. The buffer layer may include a first buffer layer and a second buffer layer stacked together. The first buffer layer is located on the side of the second buffer layer closer to the substrate 140.

[0121] The first metal layer 170 forms the gate metal layer, and the third metal layer 1110 forms the source and drain metal layers. The second metal layer 190 forms the capacitor metal layer, and at least a portion of the first metal layer 170 can respectively form the two plates of a capacitor.

[0122] The first dielectric layer 160, the second dielectric layer 180, the third dielectric layer 1100, and the fourth dielectric layer 1120 can be silicon nitride, silicon oxynitride, silicon oxide, or various novel organic insulating materials, or metal oxides with high dielectric constants such as aluminum oxide, tantalum oxide, etc.

[0123] The first data line 1111 and the first connecting line 1112 are arranged in the same layer. One of the first data line 1111 and the third connecting line 130 is located in the third metal layer 1110, and the other is located in the fourth metal layer 1130.

[0124] For example, the first data line 1111, the second data line 1121, the first connecting line 1112 and the second connecting line 1122 are all located in the third metal layer 1110, and the third connecting line 130 is located in the fourth metal layer 1130.

[0125] Understandably, this reduces the number of metal layers in the display panel 100 and simplifies the manufacturing process.

[0126] In some embodiments, a fifth dielectric layer 1140 and an anode 1170 are sequentially stacked on the side of the fourth metal layer 1130 facing away from the substrate 140.

[0127] Figure 6 for Figure 2 The second type of cross-section along the AA direction. Figure 7 for Figure 2 The third type of cross-section along the AA direction. Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0128] See Figures 6 to 8 As shown, the fifth dielectric layer 1140 and the fifth metal layer 1150 are sequentially stacked on the side of the fourth metal layer 1130 away from the substrate 140.

[0129] In this process, a sixth dielectric layer 1160 and an anode 1170 are sequentially stacked on the side of the fifth metal layer 1150 away from the substrate 140.

[0130] The first data line 1111 and the first connecting line 1112 are set in different layers. The first data line 1111, the first connecting line 1112 and the third connecting line 130 are located in the third metal layer 1110, the second connecting line 1112 are located in the fourth metal layer 1130 and the third connecting line 130 are located in the fifth metal layer 1150.

[0131] See Figure 6 As shown, in some embodiments, the first data line 1111 and the first connection line 1112 are located on the same side of the third connection line 130. For example, the third connection line 130 is located on the third metal layer 1110, the first data line 1111 and the second data line 1121 are located on the fourth metal layer 1130, and the first connection line 1112 and the second connection line 1122 are located on the fifth metal layer 1150. The third metal layer 1110 is connected to the fourth metal layer 1130 via a via. The third metal layer 1110 is connected to the fifth metal layer 1150 via a via.

[0132] See Figure 7 As shown, in some other embodiments, the first data line 1111 and the first connecting line 1112 are located on opposite sides of the third connecting line 130. For example, the first data line 1111 and the second data line 1121 are located on the third metal layer 1110, the third connecting line 130 is located on the fourth metal layer 1130, and the first connecting line 1112 and the second connecting line 1122 are located on the fifth metal layer 1150. The fourth metal layer 1130 is connected to the third metal layer 1110 via a via. The fourth metal layer 1130 is connected to the fifth metal layer 1150 via a via. This reduces the drilling depth and helps to reduce the manufacturing difficulty.

[0133] This application provides a display device, which includes a display panel 100. The display device can be a mobile or fixed terminal with a display panel 100, such as an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, supercomputer, or navigator.

[0134] The other technical features of this display device are the same as those of the display panel 100 described above, and can achieve the same technical effect, so they will not be described in detail here.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area that at least partially surrounds the display area. The display area includes a first display area and a second display area, the second display area being located on at least one side of the first display area. The non-display area includes a fan-out area, the fan-out area being disposed corresponding to the first display area. The first display area has multiple first data lines and multiple first connecting lines, and the second display area has multiple second data lines and multiple second connecting lines. The first data lines, the first connecting lines, the second data lines, and the second connecting lines all extend along a first direction, and their extension length is equal to the width of the display area along the first direction. The display area has multiple third connecting lines, which extend along a second direction and their extension length is equal to the width of the display area along the second direction. The first direction and the second direction intersect. The number of overlap points between the orthographic projections of each first data line on the plane of the display panel and the orthographic projections of the third connecting line on the plane of the display panel is the same, and the number of overlap points in the same first data line is equal to the number of the third connecting lines; the number of overlap points between the orthographic projections of each first connecting line on the plane of the display panel and the orthographic projections of the third connecting line on the plane of the display panel is the same, and the number of overlap points in the same first connecting line is equal to the number of the third connecting lines. The third connection line includes a first sub-connection line and a second sub-connection line, wherein the second data line and the first connection line are connected through the first sub-connection line, and the second connection line and the first data line are connected through the second sub-connection line; The sum of the number of the first data lines and the number of the second data lines is equal to the sum of the number of the first connecting lines and the number of the second connecting lines; Multiple first data lines and multiple first connecting lines are arranged alternately and at intervals along the second direction; Multiple second data lines and multiple second connection lines are arranged alternately and at intervals along the second direction.

2. The display panel according to claim 1, characterized in that, Multiple first sub-connecting lines and multiple second sub-connecting lines are arranged at intervals along the first direction.

3. The display panel according to claim 1, characterized in that, The number of the first sub-connecting lines is equal to the number of the second data lines; And / or, the number of the second sub-connecting lines is equal to the number of the first data lines.

4. The display panel according to any one of claims 1 to 3, characterized in that, There are two second display areas, which are located on opposite sides of the first display area along the second direction.

5. The display panel according to claim 4, characterized in that, The two second display areas are symmetrically arranged about the first display area.

6. The display panel according to any one of claims 1 to 3, characterized in that, Along the film layer stacking direction of the display panel, the first data line and the second data line are arranged in the same layer, the first connecting line and the second connecting line are arranged in the same layer, and the first sub-connecting line and the second sub-connecting line are arranged in the same layer; The first data line and the first connecting line are both on different layers from the third connecting line.

7. The display panel according to claim 6, characterized in that, The first data line and the first connecting line are arranged on the same layer; A dielectric layer is provided between the first data line and the first connecting line and the third connecting line; The second data line and the first connecting line are respectively connected to the first sub-connecting line through a first via on the dielectric layer, and the first data line and the second connecting line are respectively connected to the second sub-connecting line through a second via on the dielectric layer.

8. The display panel according to claim 6, characterized in that, The first data line and the first connecting line are arranged on different layers. A dielectric layer is provided between the first data line and the third connection line, and between the first connection line and the third connection line; The first data line and the second sub-connection line are connected through a third via on the dielectric layer between the first data line and the third connection line, and the second data line and the first sub-connection line are connected through a fourth via on the dielectric layer between the first data line and the third connection line. The first connecting line and the first sub-connecting line are connected through a fifth via on the dielectric layer located between the first connecting line and the third connecting line, and the second connecting line and the second sub-connecting line are connected through a sixth via on the dielectric layer located between the first connecting line and the third connecting line.

9. The display panel according to claim 6, characterized in that, The display panel includes a substrate, a semiconductor layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, a third dielectric layer, a third metal layer, a fourth dielectric layer, and a fourth metal layer, which are sequentially stacked along the film layer stacking direction of the display panel. The first data line and the first connecting line are disposed on the same layer, and one of the first data line and the third connecting line is located on the third metal layer, and the other is located on the fourth metal layer; Alternatively, a fifth dielectric layer and a fifth metal layer may be sequentially stacked on the side of the fourth metal layer away from the substrate; the first data line and the first connection line may be disposed on different layers, with the first of the first data line, the first connection line, and the third connection line located on the third metal layer, the second on the fourth metal layer, and the third on the fifth metal layer.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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