Magnetic memory structure and memory

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a magnetic memory structure, comprising at least one magnetic storage unit, the magnetic storage unit comprising: a plurality of first transistors arranged in stacks, the gate of different first transistors being used for connecting different first control lines, and one terminal of the source or the drain of different first transistors being connected to the same first transmission line, and the other terminal of the source or the drain being connected to the same first signal line; and a first magnetic tunnel junction, the bottom of the first magnetic tunnel junction being connected to the first transmission line, and the top of the first magnetic tunnel junction being used for connecting a second signal line, so as to improve the integration density of the magnetic memory structure.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to a magnetic memory structure and memory. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a novel type of solid-state non-volatile memory based on the characteristics of magnetic tunnel junctions (MTJs), offering high-speed read and write capabilities. MRAM stores data using magnetic field polarization rather than electric charge. An MTJ consists of a free layer, a tunneling layer, and a fixed layer. The magnetic field polarization direction of the free layer can change, while the magnetic field direction of the fixed layer remains constant. When the magnetic field directions of the free and fixed layers are the same, the MTJ exhibits low resistance; conversely, it exhibits high resistance. By detecting the resistance of the MTJ, the stored data ("0" or "1") can be determined.

[0003] However, in existing magnetic random access memories (MRAMs), limitations in the arrangement of memory cells and the connection between magnetic tunnel junctions and transistors restrict further improvements in overall performance, thus limiting their widespread application. Therefore, improving the structure of magnetic RAMs to achieve high-density MRAM and enhance overall performance is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This disclosure provides a magnetic memory structure and memory to improve the integration density of the magnetic memory structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a magnetic memory structure, including at least one magnetic memory cell. The magnetic memory cell includes: a plurality of stacked first transistors, the gates of different first transistors being used to connect to different first control lines, and one terminal of the source or drain of different first transistors being connected to the same first transmission line, and the other terminal of the source or drain being connected to the same first signal line; and a first magnetic tunnel junction, the bottom of which is connected to the first transmission line and the top of which is used to connect to a second signal line.

[0006] In some embodiments, the number of first transistors is three, wherein at least two of the first transistors are connected to a first control line that is a write control line.

[0007] In some embodiments, magnetic storage cells are arranged along a first direction and a second direction, wherein a first control line extends along the first direction, and in the first direction, first transistors arranged in the same layer are connected to the same first control line, and first magnetic tunnel junctions in different magnetic storage cells are connected to different second signal lines.

[0008] In some embodiments, the second signal line extends along a second direction, and in the second direction, the first magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line.

[0009] In some embodiments, the second signal line extends along a third direction, and in the third direction, the first magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line, wherein the first direction, the second direction, and the third direction are in the same plane.

[0010] In some embodiments, two adjacent magnetic storage cells are symmetrically arranged in the second direction.

[0011] In some embodiments, the magnetic storage cell further includes: a plurality of stacked second transistors, the gates of different second transistors being used to connect to different second control lines, and one terminal of the source or drain of different second transistors being connected to the same second transmission line, and the other terminal of the source or drain being connected to the same first signal line as the other terminal of the source or drain of the first transistor; and a second magnetic tunnel junction, the bottom of which is connected to the second transmission line and the top of which is used to connect to the second signal line.

[0012] In some embodiments, in a magnetic storage cell, a first transistor and a second transistor arranged on the same layer are symmetrically arranged along a first signal line, and a first control line and a second control line are arranged parallel to each other.

[0013] In some embodiments, magnetic storage cells are arranged along a first direction and a second direction, a first control line and a second control line extend along the first direction, and in the first direction, a first transistor arranged on the same layer is connected to the same first control line, and a second transistor arranged on the same layer is connected to the same second control line.

[0014] In some embodiments, in the same magnetic storage cell, a first magnetic tunnel junction and a second magnetic tunnel junction are connected to the same second signal line, the second signal line extends along a second direction, and in the second direction, the first magnetic tunnel junctions and the second magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line.

[0015] In some embodiments, in the same magnetic storage cell, a first magnetic tunnel junction and a second magnetic tunnel junction are connected to different second signal lines. The second signal lines extend along a third direction. In the third direction, the first magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line, and the second magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line. The first direction, the second direction, and the third direction are in the same plane.

[0016] In some embodiments, the first signal lines of different magnetic storage cells are interconnected.

[0017] In some embodiments, the first transistor includes a channel region connected to the gate of the first transistor, and the gate of the first transistor surrounds the channel region.

[0018] In some embodiments, the first transistor includes a channel region connected to the gate of the first transistor, and the channel region surrounds the gate of the first transistor.

[0019] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory, including any of the magnetic memory structures described in the above embodiments.

[0020] The technical solution provided by the embodiments of this disclosure has at least the following advantages: A magnetic storage cell includes multiple stacked first transistors, with different first transistors connected to different first control lines, thereby controlling the on / off state of the corresponding first transistors through different first control lines; one terminal of the source or drain of different first transistors is connected to the same first transmission line, and the other terminal of the source or drain is connected to the same first signal line; a first magnetic tunnel junction, with its bottom connected to the first transmission line and its top used to connect to the second signal line, can achieve writing or reading of the first magnetic tunnel junction by driving different first transistors, or it can simultaneously drive all the first transistors to achieve writing or reading of the first magnetic tunnel junction, thereby preventing the insufficient driving capability of a single first transistor or a small number of first transistors and improving the driving capability of the magnetic storage cell; wherein, the first transistors are stacked, which can reduce the area of ​​the first transistors and increase the spatial arrangement density of the first transistors, thereby reducing the overall volume of the magnetic storage cell, and thus helping to increase the integration density of the magnetic memory structure.

[0021] In addition, the magnetic storage cells can be arranged in the first direction and the second direction to increase the density of magnetic storage cells in a unit space in the magnetic memory structure, thereby improving the integration density of the magnetic memory structure. The first control line extends along the first direction, and in the first direction, the first transistors arranged in the same layer are connected to the same first control line. The first magnetic tunnel junctions in different magnetic storage cells are connected to different second signal lines, which can reduce the control terminals of the first control line. The second signal line extends along the second direction, and in the second direction, the magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line, which can reduce the control terminals of the second signal line, thereby improving the control capability of the magnetic memory structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of a magnetic storage cell provided in one embodiment of the present disclosure;

[0024] Figures 2 to 4 A schematic diagram of a structure in which various magnetic storage cells are arranged along a first direction and a second direction according to an embodiment of the present disclosure;

[0025] Figure 5 This is a schematic diagram of the structure of another magnetic storage cell provided in an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of another magnetic storage cell arrangement along a first direction and a second direction provided in an embodiment of this disclosure;

[0027] Figure 7 A top view of a magnetic storage cell arranged along a first direction and a second direction, according to an embodiment of this disclosure;

[0028] Figure 8 This is a schematic diagram of a structure in which the first signal lines of different magnetic storage cells are interconnected, according to an embodiment of the present disclosure. Detailed Implementation

[0029] As can be seen from the background technology, how to realize the structure of high-density MRAM has become an urgent problem to be solved.

[0030] Analysis reveals that each magnetic memory cell includes at least one transistor and one magnetic tunnel junction. Individual magnetic memory cells have a relatively large area, and each cell requires at least three control terminals: a control line (word line) connected to the transistor's gate, responsible for turning the transistor on or off; a source or drain connection to a first signal line (source line); and the other connection between the source and drain of the transistor and one terminal of the magnetic tunnel junction, which is then connected to a second signal line (bit line). When the driving capability of a single transistor is insufficient, the number of transistors needs to be increased to improve the driving capability of the magnetic memory cell, thus increasing the size of the cell and the corresponding transistor control terminals. Therefore, improving the integration density of MRAM has become one of the urgent technical problems to be solved.

[0031] According to some embodiments of this disclosure, one aspect of this disclosure is to provide a magnetic memory structure to improve the integration density of the magnetic memory structure.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] Figure 1 This is a schematic diagram of the structure of a magnetic storage cell provided in one embodiment of the present disclosure. Figures 2 to 4 This is a schematic diagram of a structure in which various magnetic storage cells are arranged along a first direction and a second direction, according to an embodiment of the present disclosure. Figure 5 This is a schematic diagram of the structure of another magnetic storage cell provided in an embodiment of the present disclosure. Figure 6 This is a schematic diagram of another magnetic storage cell arrangement along a first direction and a second direction, provided in an embodiment of this disclosure. Figure 7 This is a top view of a magnetic storage cell arranged along a first direction and a second direction, according to an embodiment of the present disclosure. Figure 8 This is a schematic diagram of a structure in which the first signal lines of different magnetic memory cells are interconnected according to an embodiment of the present disclosure. The magnetic memory structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0034] refer to Figure 1A magnetic memory structure includes at least one magnetic memory cell 10. The magnetic memory cell 10 includes: a plurality of stacked first transistors 100, the gates of different first transistors 100 being used to connect to different first control lines 103, and one terminal of the source or drain of different first transistors 100 being connected to the same first transmission line 110, and the other terminal of the source or drain being connected to the same first signal line 101; and a first magnetic tunnel junction 200, the bottom of which is connected to the first transmission line 110, and the top of which is used to connect to a second signal line 102.

[0035] A magnetic storage cell 10 includes multiple stacked first transistors 100. Different first transistors 100 are connected to different first control lines 103, thereby controlling the on / off state of the corresponding first transistors 100 through different first control lines 103. One terminal of the source or drain of different first transistors 100 is connected to the same first transmission line 110, and the other terminal of the source or drain is connected to the same first signal line 101. The bottom of the first magnetic tunnel junction 200 is connected to the first transmission line 110, and the top is connected to the second signal line 102. Writing or reading of the first magnetic tunnel junction 200 can be achieved through different first transistors 100, or all first transistors 100 can be driven simultaneously to achieve writing or reading of the first magnetic tunnel junction 200. This can prevent the insufficient driving capability of a single first transistor 100 or a small number of first transistors 100, and improve the driving capability of the magnetic storage cell 10. The stacked arrangement of the first transistors 100 can reduce the area of ​​the first transistors 100 and increase the spatial arrangement density of the first transistors 100, thereby reducing the overall volume of the magnetic storage cell 10 and thus helping to increase the integration density of the magnetic memory structure.

[0036] It should be noted that in this embodiment, a magnetic storage cell 10 includes three first transistors 100, and correspondingly, the number of first control lines 103 is also three. Figure 1 The letters "a", "b" or "c" following the reference numeral "100" corresponding to the first transistor 100 are only used to distinguish different first transistors 100. The letters "a", "b" or "c" following the reference numeral "103" corresponding to the first control line 103 are only used to distinguish different first control lines 103 and do not constitute a limitation on the number of first control lines 103. In other embodiments, the number of first transistors can also be 4, 6 or 8, and the corresponding number of first control lines can be 4, 6 or 8, to meet the situation where different first magnetic tunnel junctions require a corresponding number of first transistors to drive them.

[0037] It should be noted that in this embodiment, the sources of different first transistors 100 are connected to the same first signal line 101, and the drains of different first transistors are connected to the same first transmission line 110. The specific connection methods of the "source" and "drain" defined above do not constitute a limitation on the embodiments of this application. In other embodiments, the connection method of "drain" replacing "source" and "source" replacing "drain" can be used.

[0038] The first transistor includes a channel region for connecting to the gate of the first transistor. In this embodiment, the channel region of the first transistor surrounds the gate of the first transistor; in other embodiments, the gate of the first transistor may also surround the channel region. By surrounding the gate of the first transistor with the channel region or the gate of the first transistor surrounding the channel region, a first transistor with a fully surrounding gate structure can be formed. This increases the area of ​​the channel region to improve the first transistor's current control capability, thereby improving the performance of the semiconductor structure. At the same time, the fully surrounding gate structure can improve the space utilization of the semiconductor structure, thereby further increasing the integration density of the semiconductor structure.

[0039] In some embodiments, the first transistor can also be a planar transistor or a Fin Field-Effect Transistor (FinFET). The main difference between FinFET and planar transistor is that the channel region of FinFET is composed of high and thin fins protruding from an insulating substrate. The source and drain are located at the two ends of the channel region, respectively, and the three gates are close to the sidewalls and top of the channel region for auxiliary current control. This fin structure increases the area of ​​the gate surrounding the channel region and strengthens the gate's control over the channel region. This can effectively alleviate the short-channel effect that occurs in planar transistors, greatly improve circuit control and reduce leakage current, and also significantly shorten the gate length of the transistor. Therefore, FinFET can effectively reduce the scattering effect of impurity ions and improve the carrier mobility in the channel region without the need for a highly doped channel.

[0040] In some embodiments, the number of first transistors is three, wherein the first control line connected to the gates of at least two of the first transistors is a write control line. That is, in a magnetic memory cell, two first transistors can be used for writing to the magnetic tunnel junction, and one first transistor can be used for reading from the magnetic tunnel junction, thereby distinguishing the read and write paths and facilitating separate optimization of the read and write paths; alternatively, all three first transistors can be used for writing to the magnetic tunnel junction, with at least one first transistor used for reading, meaning at least one first transistor needs to be turned on during both writing and reading from the magnetic tunnel junction. By using the first control line connected to at least two first transistors as a write control line, the insufficient driving capability of a single first transistor can be prevented, improving the driving capability of the magnetic memory cell. When all three first control lines connected to the first transistors are write control lines, and at least one first transistor can be used for both reading and writing simultaneously, the number of first transistors in the magnetic memory cell can be reduced, improving the utilization efficiency of the first transistors in the magnetic memory cell.

[0041] For the first magnetic tunnel junction 200, the magnetic field direction can be rotated based on the spin-movement torque or spin-orbit torque. The first magnetic tunnel junction 200 includes a first free layer 201, a first tunneling layer 202 and a first fixed layer 203 stacked in sequence. The magnetic field polarization direction of the first free layer 201 can be changed, while the magnetic field direction of the first fixed layer 203 remains unchanged. When the magnetic field directions of the first free layer 201 and the first fixed layer 203 are the same, the first magnetic tunnel junction 200 exhibits low resistance; otherwise, the first magnetic tunnel junction 200 exhibits high resistance. By detecting the resistance of the first magnetic tunnel junction 200, it is possible to determine whether the stored data is "0" or "1".

[0042] In some embodiments, the materials of the first free layer 201 and the first fixed layer 203 include any one of cobalt iron boron, cobalt, or nickel iron; the material of the first tunneling layer 202 includes magnesium oxide.

[0043] refer to Figure 2 In some embodiments, the magnetic storage cells 10 can be arranged along a first direction X and a second direction Y, wherein the first control line 103 extends along the first direction X, and the first transistors 100 arranged on the same layer in the first direction X are connected to the same first control line 103, and the first magnetic tunnel junctions 200 in different magnetic storage cells 10 are connected to different second signal lines 102.

[0044] By stacking the first transistors 100 in the magnetic storage cell 10 and arranging them in the first direction X and the second direction Y, the stacking density of the magnetic storage cell 10 can be increased in a unit space, thereby improving the integration density of the magnetic memory structure. Furthermore, the first transistors 100 arranged in the same layer in the magnetic storage cell 10 arranged in the first direction X share the first control line 103, and the first transistors 100 in the same magnetic storage cell 10 share the same first signal line 101, which can reduce the control terminals of the first control line 103 and the first signal line 101, thereby improving the control capability of the magnetic memory structure.

[0045] Further reference Figure 2 The second signal line 102 can extend along the second direction Y, and in the second direction Y, the first magnetic tunnel junctions 200 of different magnetic storage cells 10 are connected to the same second signal line 102. By sharing the same second signal line 102 with the first magnetic tunnel junctions 200 of different magnetic storage cells 10 in the second direction Y, the number of control terminals of the second signal line 102 can be reduced, further reducing the number of control terminals required for the overall magnetic memory structure, thereby further improving the control capability of the magnetic memory structure.

[0046] refer to Figure 3 In other embodiments, the second signal line 102 may also extend along a third direction Z, and along this third direction Z, the first magnetic tunnel junctions 200 of different magnetic storage cells 10 are connected to the same second signal line 102, wherein the first direction X and the third direction Z are in the same plane. By having the first magnetic tunnel junctions 200 in different magnetic storage cells 10 along the third direction Z connected to the same second signal line 102, the extension direction of the second signal line 102 can be adjusted according to actual needs, so that the control terminal of the second signal line 102 can be set along the third direction Z, increasing the layout of the control terminal of the magnetic memory structure and facilitating the design according to actual needs.

[0047] In this embodiment, the magnetic storage cells are arranged in the same orientation in both the first and second directions; in other embodiments, adjacent magnetic storage cells are symmetrically arranged in the second direction. Specifically, refer to... Figure 4 In the second direction Y, two adjacent magnetic storage cells 10 can be symmetrically arranged, that is, the first magnetic tunnel junction 200 in every two magnetic storage cells 10 is arranged adjacently. By arranging the magnetic tunnel junctions adjacently in adjacent magnetic storage cells, the process windows of the magnetic tunnel junctions can be made close, thereby facilitating the fabrication process of the magnetic tunnel junctions and improving the fabrication efficiency of the magnetic memory structure.

[0048] It should be noted that, for ease of explanation of the arrangement of magnetic storage cells, the schematic diagram of the magnetic storage cells arranged along the first and second directions provided in this embodiment is only a structural schematic diagram of a partial arrangement and does not constitute a limitation on the number of magnetic storage cells arranged. Based on the features disclosed in the magnetic memory structure provided in the above embodiments, they can be arbitrarily combined without conflict to obtain new magnetic memory structure embodiments.

[0049] refer to Figure 5 In some embodiments, the magnetic storage cell 10 may further include: a plurality of stacked second transistors 300, the gates of different second transistors 300 being used to connect to different second control lines 303, and one terminal of the source or drain of different second transistors 300 being connected to the same second transmission line 310, and the other terminal of the source or drain being connected to the same first signal line 101 with the other terminal of the source or drain of the first transistor 100; a second magnetic tunnel junction 400, the bottom of which is connected to the second transmission line 310 and the top of which is used to connect to the second signal line 102, wherein the first transistor 100 and the second transistor 300 arranged on the same layer are symmetrically arranged along the first signal line 101, and the first control line 103 is arranged parallel to the second control line 303. By sharing the first signal line 101 with the first transistor 100 and the second transistor 300 symmetrically arranged in the second direction Y, the control terminals of the first signal line 101 can be further reduced. The first transistor 100 controls the reading and writing of the first magnetic tunnel junction 200, and the second transistor 300 controls the reading and writing of the second magnetic tunnel junction 400. In one magnetic memory cell 10, two magnetic tunnel junctions can be written to and read from respectively, which improves the control capability of the magnetic memory cell 10. Furthermore, the sharing of the first signal line 101 between the first transistor 100 and the second transistor 300 can reduce the fabrication process of the first signal line 101 in the magnetic memory structure and improve the fabrication efficiency of the semiconductor structure.

[0050] It should be noted that in this embodiment, a magnetic storage cell 10 includes three second transistors 300, and correspondingly, the number of second control lines 303 is also three. Figure 5 The letters "a", "b", or "c" following the reference numeral "300" corresponding to the second transistor 300 are only used to distinguish different second transistors 300. The letters "a", "b", or "c" following the reference numeral "303" corresponding to the second control line 303 are only used to distinguish different second control lines 303 and do not constitute a limitation on the number of second control lines 303. In other embodiments, the number of second transistors can also be 4, 6, or 8, and the corresponding number of second control lines can be 4, 6, or 8, to meet the situation where different second magnetic tunnel junctions require a corresponding number of second transistors for driving.

[0051] It should be noted that in this embodiment, the sources of different first transistors 100 and the sources of different second transistors 300 are connected to the same first signal line 101, the drains of different first transistors are connected to the same first transmission line 110, and the drains of different second transistors are connected to the same second transmission line 310. The specific connection methods of the "source" and "drain" defined above do not constitute a limitation on the embodiments of this application. In other embodiments, the connection methods of "drain" replacing "source" and "source" replacing "drain" can be used.

[0052] For the second transistor, the channel region of the second transistor is used to connect to the gate of the second transistor. In this embodiment, the channel region of the second transistor surrounds the gate of the second transistor; in other embodiments, the gate of the second transistor may also surround the channel region of the second transistor. By having the channel region of the second transistor surround the gate of the second transistor or the gate of the second transistor surround the channel region of the second transistor, a second transistor with a fully surrounding gate structure can be formed. This increases the area of ​​the channel region to improve the current control capability of the second transistor, thereby improving the performance of the semiconductor structure. At the same time, the fully surrounding gate structure can improve the space utilization of the semiconductor structure, thereby further increasing the integration density of the semiconductor structure.

[0053] In some embodiments, the second transistor can also be a planar transistor or a Fin Field-Effect Transistor (FinFET). The main difference between FinFET and planar transistor is that the channel region of FinFET is composed of high and thin fins protruding from an insulating substrate. The source and drain are located at the two ends of the channel region, respectively, and the three gates are close to the sidewalls and top of the channel region for auxiliary current control. This fin structure increases the area of ​​the gate surrounding the channel region and strengthens the gate's control over the channel region. This can effectively alleviate the short-channel effect that occurs in planar transistors, significantly improve circuit control and reduce leakage current, and also significantly shorten the gate length of the transistor. Therefore, FinFET can effectively reduce the scattering effect of impurity ions and improve the carrier mobility in the channel region without the need for a highly doped channel.

[0054] In some embodiments, the number of second transistors is three, wherein the second control line connected to the gates of at least two second transistors is a write control line. That is, in a magnetic memory cell, two second transistors can be used for writing to the magnetic tunnel junction, and one second transistor can be used for reading from the magnetic tunnel junction, thereby distinguishing the read and write paths and facilitating separate optimization of the read and write paths; alternatively, all three second transistors can be used for writing to the magnetic tunnel junction, with at least one second transistor used for reading, meaning at least one second transistor needs to be turned on during both writing and reading of the magnetic tunnel junction. By using the first control line connected to at least two second transistors as a write control line, the insufficient driving capability of a single second transistor can be prevented, improving the driving capability of the magnetic memory cell. When all three second control lines connected to the second transistors are write control lines, and at least one second transistor can be used for both reading and writing simultaneously, the number of second transistors in the magnetic memory cell can be reduced, improving the utilization efficiency of the second transistors in the magnetic memory cell.

[0055] It should be noted that in this embodiment, the number of first transistors and the number of second transistors are the same and their structures are the same; in other embodiments, the number of first transistors may be different from the number of second transistors, and the structures of first transistors may be different from those of second transistors.

[0056] The second magnetic tunnel junction 400 can rotate the magnetic field direction based on its spin-movement torque or spin-orbit torque. The second magnetic tunnel junction 400 includes a second free layer 401, a second tunneling layer 402, and a second fixed layer 403 stacked sequentially. The magnetic field polarization direction of the second free layer 401 can be changed, while the magnetic field direction of the second fixed layer 403 remains unchanged. When the magnetic field directions of the second free layer 401 and the second fixed layer 403 are the same, the second magnetic tunnel junction 400 exhibits low resistance; otherwise, the second magnetic tunnel junction 400 exhibits high resistance. By detecting the resistance of the second magnetic tunnel junction 400, it is possible to determine whether the stored data is "0" or "1".

[0057] In some embodiments, the materials of the second free layer 401 and the second fixed layer 403 include any one of cobalt iron boron, cobalt, or nickel iron; the material of the second tunneling layer 402 includes magnesium oxide.

[0058] It should be noted that in this embodiment, the structure of the first magnetic tunnel junction is the same as that of the second magnetic tunnel junction; in other embodiments, the structure of the first magnetic tunnel junction may be different from that of the second magnetic tunnel junction.

[0059] Further, refer to Figure 6In some embodiments, the magnetic storage cells 10 are arranged along a first direction X and a second direction Y, the first control line and the second control line extend along the first direction X, and in the first direction X, the first transistors 100 arranged on the same layer are connected to the same first control line 103, and the second transistors 300 arranged on the same layer are connected to the same second control line 303.

[0060] By stacking the first transistor 100 and the second transistor 300 in the magnetic storage cell 10 and arranging them in the first direction X and the second direction Y, the stacking density of the magnetic storage cell 10 can be increased in a unit space, thereby improving the integration density of the magnetic memory structure. In the magnetic storage cells 10 arranged in the first direction X, the first transistors 100 arranged in the same layer share the first control line 103, the second transistors 300 arranged in the same layer share the second control line 303, and the first transistors 100 and the second transistors 300 in the same magnetic storage cell 10 share the same first signal line 101. This can reduce the number of control terminals of the first control line 103, the second control line 303 and the first signal line 101, thereby improving the control capability of the magnetic memory structure.

[0061] Continue to refer to Figure 6 In some embodiments, within the same magnetic storage cell 10, the first magnetic tunnel junction 200 and the second magnetic tunnel junction 400 are connected to the same second signal line 102. The second signal line 102 extends along a second direction Y, and in the second direction Y, the first magnetic tunnel junctions 200 and the second magnetic tunnel junctions 400 of different magnetic storage cells 10 are connected to the same second signal line 102. By having the first and second magnetic tunnel junctions share the same second signal line, and by having different magnetic storage cells connected to the same second signal line in the second direction, the number of control terminals on the second signal line can be reduced, thereby improving the control capability of the magnetic memory structure.

[0062] refer to Figure 7In other embodiments, within the same magnetic storage cell 10, the first magnetic tunnel junction 200 and the second magnetic tunnel junction 400 are connected to different second signal lines 102. The second signal lines 102 extend along a third direction Z. Furthermore, along the third direction Z, the first magnetic tunnel junctions 200 of different magnetic storage cells 10 are connected to the same second signal line 102, and the second magnetic tunnel junctions 400 of different magnetic storage cells 10 are connected to the same second signal line 102. The first direction X, the second direction Y, and the third direction Z are all in the same plane. By arranging the magnetic storage cells in the first and second directions, the first and second magnetic tunnel junctions in different magnetic storage cells can be alternately arranged in the first direction, thereby further reducing the gap between magnetic storage cells and improving the space utilization of the magnetic storage cells. Moreover, the connection of the first magnetic tunnel junctions and the second magnetic tunnel junctions in different magnetic storage cells to the same second signal line along the third direction allows for the distribution of control lines according to actual usage requirements, improving the control capability of the magnetic memory structure.

[0063] In some embodiments, the first signal lines of different magnetic storage cells can be interconnected. For example, see reference... Figure 8Different magnetic storage cells 10 share the same first signal line 101. When writing to a target magnetic storage cell, by applying a conduction voltage to the first control line corresponding to the target magnetic tunnel junction, the first transistor in a row of magnetic storage cells corresponding to the target magnetic tunnel junction can be turned on, further selecting the first signal line. All the first magnetic tunnel junctions in the row of magnetic storage cells corresponding to the target magnetic tunnel junction are in a state ready to be written. The magnetic storage cell containing the target magnetic tunnel junction can be located through the corresponding second signal line. Then, based on the magnitude and direction of the current in the first and second signal lines, writing to the target magnetic tunnel junction is achieved. During the reading process of the magnetic tunnel junction, through... By applying a conduction voltage to the first control line corresponding to the target magnetic tunnel junction, the first transistor in the row of magnetic memory cells corresponding to the target magnetic tunnel junction is turned on. This further selects the first signal line, and all magnetic tunnel junctions in the row of magnetic memory cells corresponding to the target magnetic tunnel junction are in a read-read state. The magnetic memory cell containing the target magnetic tunnel junction can be located through the corresponding second signal line. Then, based on the current in the first and second signal lines, the resistance of the target magnetic tunnel junction is determined, and the data stored in the target magnetic tunnel junction can be determined. If the magnetic tunnel junction is in a high-resistance state, the stored data is "1"; if the magnetic tunnel junction is in a low-resistance state, the stored data is "0". By connecting all the first signal lines of the stacked magnetic memory cells, the number of control terminals of a large number of first signal lines in the magnetic memory array structure can be reduced, while the control capability of the magnetic memory array structure is improved and the manufacturing process of the magnetic memory array structure is simplified.

[0064] It should be noted that, for ease of illustration of the arrangement of magnetic storage cells, the schematic diagrams of the magnetic storage cell arrangement provided in the embodiments of this disclosure are only schematic diagrams of partial arrangements and do not constitute a limitation on the number of magnetic storage cells arranged. Based on the features disclosed in the magnetic memory structure provided in the above embodiments, they can be arbitrarily combined without conflict to obtain new magnetic memory structure embodiments.

[0065] The magnetic memory structure provided in this disclosure includes a plurality of stacked first transistors in a magnetic memory cell. Different first transistors are connected to different first control lines, thereby controlling the on / off state of the corresponding first transistors through different first control lines. One terminal of the source or drain of different first transistors is connected to the same first transmission line, and the other terminal of the source or drain is connected to the same first signal line. A first magnetic tunnel junction is connected to the first transmission line at its bottom and to the second signal line at its top. Writing or reading of the first magnetic tunnel junction can be achieved by driving different first transistors, or all first transistors can be driven simultaneously to achieve writing or reading of the first magnetic tunnel junction. This can prevent insufficient driving capability of a single first transistor or a small number of first transistors and improve the driving capability of the magnetic memory cell. The stacked arrangement of the first transistors can reduce the area of ​​the first transistors and increase the spatial arrangement density of the first transistors, thereby reducing the overall volume of the magnetic memory cell and thus facilitating the increase of the integration density of the magnetic memory structure.

[0066] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory, including any of the magnetic memory structures in the above embodiments, to improve the integration density of the magnetic memory structure.

[0067] Specifically, memory can be a storage cell or device based on a semiconductor device or component. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0068] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A magnetic memory structure, characterized in that, Includes at least one magnetic storage cell, the magnetic storage cell comprising: Multiple stacked first transistors, with the gates of different first transistors used to connect to different first control lines, and one terminal of the source or drain of different first transistors connected to the same first transmission line, and the other terminal of the source or drain connected to the same first signal line; A first magnetic tunnel junction is connected to the first transmission line at the bottom and to the second signal line at the top. The magnetic storage cells are arranged along a first direction and a second direction, wherein the first control line extends along the first direction, and in the first direction, the first transistors arranged on the same layer are connected to the same first control line, and the first magnetic tunnel junctions in different magnetic storage cells are connected to different second signal lines.

2. The magnetic memory structure as described in claim 1, characterized in that, The number of the first transistors is three, wherein at least two of the first transistors are connected to the first control line as write control lines.

3. The magnetic memory structure as described in claim 1, characterized in that, The second signal line extends along the second direction, and in the second direction, the first magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line.

4. The magnetic memory structure as described in claim 1, characterized in that, The second signal line extends along a third direction, and in the third direction, the first magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line, wherein the first direction, the second direction, and the third direction are in the same plane.

5. The magnetic memory structure according to any one of claims 1 to 4, characterized in that, In the second direction, two adjacent magnetic storage cells are symmetrically arranged.

6. The magnetic memory structure as described in claim 1, characterized in that, The magnetic storage unit further includes: Multiple stacked second transistors, with the gates of different second transistors used to connect to different second control lines, and one terminal of the source or drain of different second transistors connected to the same second transmission line, and the other terminal of the source or drain connected to the same first signal line as the other terminal of the source or drain of the first transistor. The second magnetic tunnel junction is connected to the second transmission line at the bottom and to the second signal line at the top.

7. The magnetic memory structure as described in claim 6, characterized in that, In the magnetic storage cell, the first transistor and the second transistor arranged on the same layer are symmetrically arranged along the first signal line, and the first control line and the second control line are arranged parallel to each other.

8. The magnetic memory structure as described in claim 7, characterized in that, The magnetic storage cells are arranged along a first direction and a second direction. The first control line and the second control line extend along the first direction. In the first direction, the first transistors arranged on the same layer are connected to the same first control line, and the second transistors arranged on the same layer are connected to the same second control line.

9. The magnetic memory structure as described in claim 8, characterized in that, In the same magnetic storage cell, the first magnetic tunnel junction and the second magnetic tunnel junction are connected to the same second signal line, the second signal line extends along the second direction, and in the second direction, the first magnetic tunnel junction and the second magnetic tunnel junction of different magnetic storage cells are connected to the same second signal line.

10. The magnetic memory structure as described in claim 8, characterized in that, In the same magnetic storage cell, the first magnetic tunnel junction and the second magnetic tunnel junction are connected to different second signal lines. The second signal lines extend along a third direction. In the third direction, the first magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line, and the second magnetic tunnel junctions of different magnetic storage cells are connected to the same second signal line. The first direction, the second direction, and the third direction are in the same plane.

11. The magnetic memory structure as described in claim 1, characterized in that, The first signal lines of different magnetic storage cells are interconnected.

12. The magnetic memory structure as described in claim 1, characterized in that, The first transistor includes a channel region connected to the gate of the first transistor, and the gate of the first transistor is disposed enclosing the channel region.

13. The magnetic memory structure as described in claim 1, characterized in that, The first transistor includes a channel region connected to the gate of the first transistor, and the channel region is disposed surrounding the gate of the first transistor.

14. A memory comprising the magnetic memory structure according to any one of claims 1 to 13.

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