Display panel and manufacturing method thereof
By designing an overlapping structure of the cathode layer and electron transport layer in the OLED display panel, and electrically connecting them with the wiring layer through the overlap layer, the high cost problem caused by multiple masks is solved, achieving the effect of simplifying the process and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2022-07-15
- Publication Date
- 2026-06-09
AI Technical Summary
In OLED display panels, the manufacturing processes for the electron transport layer and cathode layer are complex and require multiple photomasks, resulting in high production equipment costs.
Design a display panel structure in which the orthographic projections of the cathode layer and the electron transport layer on the plane of the trace layer completely overlap, and are electrically connected to the trace layer through an overlap layer. The electron transport layer and the cathode layer are fabricated simultaneously using a single mask.
The process was simplified, production costs were reduced, and the electrical performance of the display panel was guaranteed.
Smart Images
Figure CN115274788B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Technology
[0002] In OLED display panels, due to limitations in the development of inks for electron transport materials, evaporation processes are still required to sequentially fabricate OLED functional layers such as the electron transport layer and the cathode layer. The cathode layer needs to be connected to the traces in the TFT substrate, making its coverage area larger than that of the electron transport layer. Therefore, two cycle chambers are needed to use different masks to fabricate the electron transport layer and the cathode layer. This results in long inline production lines, complex manufacturing processes, and high production equipment costs. Summary of the Invention
[0003] This application provides a display panel and a method for manufacturing the same, which can ensure the electrical performance of the display panel, simplify the process, and reduce production costs.
[0004] This application embodiment provides a display panel, including a non-display area, wherein the non-display area is provided with:
[0005] wiring layer;
[0006] An electron transport layer is located on the wiring layer;
[0007] A cathode layer is located on the electron transport layer, and the orthographic projections of the cathode layer and the electron transport layer on the plane where the trace layer is located completely overlap.
[0008] An overlap layer is located on the cathode layer and the wiring layer, and the cathode layer is electrically connected to the wiring layer through the overlap layer.
[0009] Optionally, the non-display area is further provided with:
[0010] An electron injection layer is located between the electron transport layer and the cathode layer, and the orthographic projections of the electron injection layer, the cathode layer, and the electron transport layer on the plane where the trace layer is located completely overlap.
[0011] Optionally, the non-display area is further provided with:
[0012] A barrier layer is located on the wiring layer, and a first through-hole is provided in the barrier layer;
[0013] The electron transport layer is located on the barrier layer and extends to the trace layer at the bottom of the first via. The overlap layer is located inside the first via and covers the cathode layer and the trace layer.
[0014] Optionally, the coverage area of the electron transport layer at the bottom of the first through hole accounts for 20% to 50% of the bottom area of the first through hole.
[0015] Optionally, the non-display area is further provided with:
[0016] A protective layer is located between the wiring layer, the electron transport layer, and the overlap layer. The cathode layer is electrically connected to the wiring layer through the overlap layer and the protective layer.
[0017] Optionally, the non-display area is further provided with:
[0018] A passivation layer is located on the trace layer, and a second through-hole is provided in the passivation layer. The protective layer is located on the passivation layer and covers the sidewall of the second through-hole and the trace layer at the bottom of the second through-hole.
[0019] A planarization layer is located on the protective layer, and a third through hole is provided in the planarization layer to communicate with the second through hole. The electron transport layer is located on the planarization layer and extends to the protective layer at the bottom of the second through hole. The overlapping layer is located in the second through hole and the third through hole and covers the cathode layer and the protective layer.
[0020] Optionally, the material of the overlapping layer includes nano-silver or a silver alloy.
[0021] This application embodiment also provides a method for manufacturing a display panel, the display panel including a non-display area, the method comprising:
[0022] A wiring layer is formed in the non-display area;
[0023] An electron transport layer and a cathode layer are sequentially formed on the wiring layer, and the orthographic projections of the cathode layer and the electron transport layer on the plane where the wiring layer is located completely overlap.
[0024] An overlap layer is formed on the cathode layer and the wiring layer, so that the cathode layer is electrically connected to the wiring layer through the overlap layer.
[0025] Optionally, the step of sequentially forming an electron transport layer and a cathode layer on the wiring layer includes:
[0026] A barrier layer is formed on the wiring layer;
[0027] A first through-hole is formed in the barrier layer to expose part of the wiring layer;
[0028] A photomask is provided, the photomask including an opening, the orthographic projection of the opening onto the barrier layer overlapping the first through-hole portion;
[0029] The electron transport layer and the cathode layer are sequentially deposited through the opening onto the barrier layer and the partially exposed trace layer.
[0030] Optionally, the step of forming an overlap layer on the cathode layer and the wiring layer includes:
[0031] The overlap layer is formed on the cathode layer and the remaining exposed wiring layer using inkjet printing or screen printing processes.
[0032] The beneficial effects of this application are as follows: the orthographic projections of the cathode layer and the electron transport layer on the plane where the wiring layer is located completely overlap, and the overlap layer is located on the cathode layer and the wiring layer, so that the cathode layer is electrically connected to the wiring layer through the overlap layer, ensuring the electrical performance of the display panel, and only one mask is needed to make the electron transport layer and the cathode layer, shortening the inline mass production line, simplifying the manufacturing process, and reducing production costs. Attached Figure Description
[0033] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.
[0034] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application.
[0035] Figure 2 Another structural schematic diagram of the display panel provided in an embodiment of this application;
[0036] Figure 3 A schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application;
[0037] Figures 4a to 4d A schematic diagram of a method for manufacturing a display panel according to an embodiment of this application;
[0038] Figure 5 This is a schematic diagram of the structure of the circulation cavity in the method for manufacturing a display panel provided in the embodiments of this application. Detailed Implementation
[0039] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of this application. However, this application may be implemented in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.
[0040] In the description of this application, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.
[0041] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.
[0043] The present application will be further described below with reference to the accompanying drawings and embodiments.
[0044] See Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. The display panel can be an OLED display panel.
[0045] like Figure 1 As shown, the display panel provided in this embodiment of the invention includes a non-display area NA. The display panel may also include a display area (not shown in the figure), and the non-display area NA is disposed around the display area. The display panel includes a wiring layer 1, an electron transport layer 2, a cathode layer 3, and an overlap layer 4.
[0046] The trace layer 1 is located in the non-display area NA. The trace layer 1 includes VSS traces, and the material of the VSS traces includes metal materials such as aluminum and copper. The display panel may also include an array substrate (not shown in the figure), which is located in the display area and the non-display area NA. The trace layer 1 may be located in the non-display area of the array substrate.
[0047] The electron transport layer 2 is located in the display area and the non-display area NA. In the non-display area NA, the electron transport layer 2 is located on the trace layer 1, and the orthographic projection of the electron transport layer 2 on the plane of the trace layer 1 only covers a portion of the trace layer 1. Specifically, the orthographic projection of the electron transport layer 2 on the plane of the trace layer 1 only covers a portion of the VSS traces in the trace layer 1.
[0048] Cathode layer 3 is located in the display area and the non-display area NA. In the non-display area NA, cathode layer 3 is located on electron transport layer 2, and the orthographic projection of cathode layer 3 onto the plane of trace layer 1 completely overlaps with the orthographic projection of electron transport layer 2 onto the plane of trace layer 1, so that the orthographic projection of cathode layer 3 onto the plane of trace layer 1 only covers a portion of the VSS traces in trace layer 1. The material of cathode layer 3 includes conductive materials. Cathode layer 3 can be a single-layer film or a multilayer film; no specific limitation is made here.
[0049] The overlap layer 4 is located in the non-display area NA. Since the orthographic projection of the cathode layer 3 onto the plane of the wiring layer 1 in the non-display area NA only covers a portion of the VSS traces in the wiring layer 1, the overlap layer 4 can be located on both the cathode layer 3 and the wiring layer 1 simultaneously. This allows the cathode layer 3 to be electrically connected to the wiring layer 1 through the overlap layer 4. Specifically, the cathode layer 3 is electrically connected to the VSS traces in the wiring layer 1 through the overlap layer 4, enabling the VSS traces to transmit signals to the cathode layer 3 through the overlap layer 4 to control OLED light emission. The material of the overlap layer 4 includes nano-silver or silver alloys, etc.
[0050] In this embodiment, the orthographic projection of the cathode layer 3 onto the plane of the wiring layer 1 completely overlaps with the orthographic projection of the electron transport layer 2 onto the plane of the wiring layer 1. This allows the cathode layer 3 and the electron transport layer 2 to be fabricated using only one mask, simplifying the process flow and requiring only one circulation chamber, thus shortening the inline mass production line and reducing equipment investment costs. Furthermore, the cathode layer 3 is electrically connected to the wiring layer 1 via the overlap layer 4, ensuring that the electrical performance of the display panel remains unaffected.
[0051] Optionally, such as Figure 4dAs shown, the display panel may also include an electron injection layer 5. The electron injection layer 5 is located in the display area and the non-display area NA. In the non-display area NA, the electron injection layer 5 is located between the electron transport layer 2 and the cathode layer 3, and the orthographic projection of the electron injection layer 5 on the plane of the trace layer 1, the orthographic projection of the cathode layer 3 on the plane of the trace layer 1, and the orthographic projection of the electron transport layer 2 on the plane of the trace layer 1 completely overlap, so that the cathode layer 3, the electron injection layer 5, and the electron transport layer 2 only need to be fabricated using a single mask, further simplifying the process flow.
[0052] Optionally, such as Figure 1 As shown, the display panel may further include a barrier layer 6, located in the display area and the non-display area NA. In the non-display area NA, the barrier layer 6 is located on the wiring layer 1, and a first through-hole 60 is provided in the barrier layer 6, i.e., the first through-hole 60 penetrates the barrier layer 6. The electron transport layer 2 is located on the barrier layer 6 and extends through the sidewall of the first through-hole 60 to the wiring layer 1 at the bottom of the first through-hole 60. The cathode layer 3 is located on the electron transport layer 2 and also extends into the first through-hole 60. It should be noted that in the non-display area NA, the electron transport layer 2 only covers part of the barrier layer 6, part of the sidewall of the first through-hole 60, and part of the wiring layer 1 at the bottom of the first through-hole 60. That is, the orthographic projection of the electron transport layer 2 on the plane where the wiring layer 1 is located only partially overlaps with the orthographic projection of the first through-hole 60 on the plane where the wiring layer 1 is located. The coverage area of the electron transport layer 2 at the bottom of the first through-hole 60 can account for 20% to 50% of the bottom area of the first through-hole 60.
[0053] The overlap layer 4 is located inside the first through hole 60 and covers part of the cathode layer 3 (e.g., the cathode layer 3 located inside the first through hole 60) and part of the wiring layer 1 (e.g., the wiring layer 1 at the bottom of the first through hole 60 that is not covered by the electron transport layer 2), thereby ensuring that the cathode layer 3 can be electrically connected to the wiring layer 1 through the overlap layer 4.
[0054] In some embodiments, such as Figure 2 As shown, the display panel also includes a protective layer 7, located in the display area and the non-display area NA. In the non-display area NA, the protective layer 7 is situated between the trace layer 1 and the electron transport layer 2 and the overlap layer 4; that is, the protective layer 7 is located on the trace layer 1, and the electron transport layer 2 and the overlap layer 4 are located on the protective layer 7. The cathode layer 3 is electrically connected to the VSS traces in the trace layer 1 through the overlap layer 4 and the protective layer 7. The protective layer 7 is used to prevent corrosion of the VSS traces in the trace layer 1, thus avoiding interference with the electrical connection between the VSS traces and the cathode layer 3. The material of the protective layer 7 includes molybdenum titanium dioxide, etc.
[0055] Optionally, such as Figure 2As shown, the display panel may further include a passivation layer 8 and a planarization layer 9. The passivation layer 8 is located in the display area and the non-display area NA. In the non-display area NA, the passivation layer 8 is located on the wiring layer 1, and a second via 80 is provided in the passivation layer 8, that is, the second via 80 penetrates the passivation layer 8. A protective layer 7 is located on the passivation layer 8 and extends through the sidewall of the second via 80 to the wiring layer 1 at the bottom of the second via 80. The protective layer 7 can completely cover the wiring layer 1 at the bottom of the second via 80, so that the protective layer 7 can provide comprehensive protection for the VSS wiring in the wiring layer 1.
[0056] Planarization layer 9 is located in the display area and the non-display area NA. In the non-display area NA, planarization layer 9 is located on the protective layer 7. Planarization layer 9 has a third through-hole 90, which penetrates through planarization layer 9 and is connected to the second through-hole 80. The orthographic projection of the third through-hole 90 on the plane of the routing layer 1 completely covers the orthographic projection of the second through-hole 80 on the plane of the routing layer 1.
[0057] Electron transport layer 2 is located on planarization layer 9 and extends through the sidewall of third via 90 to the trace layer 1 at the bottom of second via 80. Cathode layer 3 is located on electron transport layer 2 and also extends into third via 90 and second via 80. It should be noted that in the non-display area NA, electron transport layer 2 only covers a portion of planarization layer 9, a portion of the sidewall of third via 90, and a portion of the protective layer 7 at the bottom of second via 80. That is, the orthographic projection of electron transport layer 2 onto the plane of trace layer 1 only partially overlaps with the orthographic projection of second via 80 onto the plane of trace layer 1. The coverage area of electron transport layer 2 at the bottom of second via 80 can be 20% to 50% of the bottom area of second via 80.
[0058] The overlap layer 4 is located within the third through hole 90 and the second through hole 80 and covers part of the cathode layer 3 (e.g., the cathode layer 3 located within the third through hole 90 and the second through hole 80) and part of the protective layer 7 (e.g., the protective layer 7 at the bottom of the second through hole 80 that is not covered by the electron transport layer 2), thereby ensuring that the cathode layer 3 can be electrically connected to the wiring layer 1 through the overlap layer 4 and the protective layer 7.
[0059] In some embodiments, the display panel may further include a pixel definition layer (not shown in the figure), which is located in the display area and the non-display area NA. In the non-display area NA, the pixel definition layer is located between the planarization layer 9 and the electron transport layer 2, that is, the pixel definition layer is located on the planarization layer 9 and covers the sidewall of the third via 90, and the electron transport layer 2 is located on the pixel definition layer and extends to the protective layer 7 at the bottom of the second via 80.
[0060] The display panel may further include an anode layer (not shown), a hole injection layer (not shown), a hole transport layer (not shown), and a light-emitting layer (not shown), all located in the display area. In the display area, the anode layer is located on an array substrate, which includes thin-film transistors. The anode layer is electrically connected to the source and drain of the thin-film transistors in the array substrate. The hole injection layer is located on the anode layer, the hole transport layer is located on the hole injection layer, the light-emitting layer is located on the hole transport layer, the electron transport layer is located on the light-emitting layer, the electron injection layer is located on the electron transport layer, and the cathode layer is located on the electron injection layer.
[0061] In this embodiment, the orthographic projections of the cathode layer and the electron transport layer on the plane where the wiring layer is located completely overlap, and the overlap layer is located on the cathode layer and the wiring layer, so that the cathode layer is electrically connected to the wiring layer through the overlap layer, ensuring the electrical performance of the display panel. Moreover, only one mask is needed to fabricate the electron transport layer and the cathode layer, shortening the inline mass production line, simplifying the manufacturing process, and reducing production costs.
[0062] Accordingly, embodiments of the present invention also provide a method for manufacturing a display panel, which can manufacture the display panel described in the above embodiments.
[0063] like Figure 3 As shown in the embodiment of the present invention, the method for manufacturing a display panel can be an OLED display panel. The display panel includes a display area and a non-display area, with the non-display area surrounding the display area.
[0064] The method includes steps 101 to 103, as follows:
[0065] Step 101: Form a wiring layer in the non-display area.
[0066] like Figure 4a As shown, an array substrate (not shown in the figure) can be provided first, and then a wiring layer 1 can be formed in the non-display area NA of the array substrate. The wiring layer 1 includes VSS wiring.
[0067] Step 102: An electron transport layer and a cathode layer are sequentially formed on the trace layer, and the orthographic projections of the cathode layer and the electron transport layer on the plane where the trace layer is located completely overlap.
[0068] An electron transport layer and a cathode layer are sequentially formed on the wiring layer 1 using a photomask. In one embodiment, step 102, which involves sequentially forming the electron transport layer and the cathode layer on the wiring layer, includes:
[0069] A barrier layer is formed on the wiring layer;
[0070] A first through-hole is formed in the barrier layer to expose part of the wiring layer;
[0071] A photomask is provided, the photomask including an opening, the orthographic projection of the opening onto the barrier layer overlapping the first through-hole portion;
[0072] The electron transport layer and the cathode layer are sequentially deposited through the opening onto the barrier layer and the partially exposed trace layer.
[0073] like Figure 4a As shown, in the non-display area NA, a barrier layer 6 is deposited on the wiring layer 1, and a first via 60 is formed in the barrier layer 6. The first via 60 penetrates the barrier layer 6 to expose part of the wiring layer 1, so that the first via 60 can serve as an overlap hole between the cathode layer and the wiring layer 1.
[0074] Then, as Figure 4b As shown, a mask 10 is provided, which includes an opening 11. The opening 11 exposes a portion of the first through hole 60, such that the opening 11 exposes a portion of the routing layer 1 at the bottom of the first through hole 60. That is, the orthographic projection of the opening 11 on the plane of the routing layer 1 overlaps with the orthographic projection of the first through hole 60 on the plane of the routing layer 1. The area of the overlapping portion can account for 20% to 50% of the bottom area of the first through hole 60.
[0075] Then, using a vapor deposition or sputtering process, and through the opening 11, an electron transport layer and a cathode layer are sequentially formed on the barrier layer 6 and the partially exposed trace layer 1 (i.e., the part of the trace layer 1 exposed at the bottom of the first via 60), such that the orthographic projection of the cathode layer on the plane of the trace layer 1 completely overlaps with the orthographic projection of the electron transport layer on the plane of the trace layer 1. In some embodiments, such as Figure 4c As shown, an electron transport layer 2, an electron injection layer 5, and a cathode layer 3 are sequentially formed on the barrier layer 6 and the partially exposed trace layer 1 (i.e., the exposed part of the trace layer 1 at the bottom of the first through hole 60) using a vapor deposition or sputtering process and through the opening 11. This results in the orthographic projection of the electron injection layer 5 onto the plane of the trace layer 1, the orthographic projection of the cathode layer 3 onto the plane of the trace layer 1, and the orthographic projection of the electron transport layer 2 onto the plane of the trace layer 1, all of which completely overlap.
[0076] Since only one mask 10 is used to form the electron transport layer 2, electron injection layer 5, and cathode layer 3, only one circulation cavity needs to be designed, such as... Figure 5 As shown, a circulation chamber includes a mask alignment chamber, a vapor deposition or sputtering chamber, a mask separation chamber, a mask rotation chamber, and a buffer chamber, etc. There is no need to design multiple circulation chambers for different masks, thereby shortening the inline mass production line and reducing the investment cost of production equipment.
[0077] Step 103: Form an overlap layer on the cathode layer and the wiring layer, so that the cathode layer is electrically connected to the wiring layer through the overlap layer.
[0078] Since signal transmission is required between the trace layer 1 and the cathode layer 3, an overlap layer is formed on the cathode layer 3 and the trace layer 1 to ensure that the cathode layer 3 can be electrically connected to the trace layer 1 through the overlap layer.
[0079] Specifically, the step of forming an overlap layer on the cathode layer and the wiring layer in step 103 includes:
[0080] The overlap layer is formed on the cathode layer and the remaining exposed wiring layer using inkjet printing or screen printing processes.
[0081] Since the electron transport layer 2 only covers a portion of the wiring layer 1 at the bottom of the first through-hole 60, the remaining wiring layer 1 at the bottom of the first through-hole 60 is exposed after the mask 10 is removed. Therefore, an overlap layer 4 can be formed on the cathode layer 3 and the remaining wiring layer 1 using inkjet printing or screen printing. This allows the cathode layer 3 to be electrically connected to the wiring layer 1 through the overlap layer 4, ensuring the electrical performance of the display panel. The material of the overlap layer 4 includes nano-silver or silver alloy, etc.
[0082] It should be noted that before forming the electron transport layer 2, an inkjet printing process can be used to sequentially form the anode layer, hole injection layer, hole transport layer and light-emitting layer in the display area of the array substrate.
[0083] In another implementation, such as Figure 2 As shown, after forming the trace layer 1 in the non-display area NA, a passivation layer 8 can be formed on the trace layer 1, and a second via 80 can be formed in the passivation layer 8, allowing the second via 80 to penetrate the passivation layer 8 and expose a portion of the trace layer 1. Then, a protective layer 7 is formed on the passivation layer 8, and the protective layer 7 extends through the sidewall of the second via 80 to the trace layer 1 at the bottom of the second via 80. The protective layer 7 can completely cover the trace layer 1 at the bottom of the second via 80, so that the protective layer 7 can provide comprehensive protection for the VSS traces in the trace layer 1.
[0084] Then, a planarization layer 9 is formed on the protective layer 7, and a third through hole 90 is opened in the planarization layer 9. The third through hole 90 is connected to the second through hole 80, and the orthographic projection of the third through hole 90 on the plane of the routing layer 1 completely covers the orthographic projection of the second through hole 80 on the plane of the routing layer 1.
[0085] A mask is provided, which includes an opening, an exposed portion of a third via 90 and a second via 80, such that the opening exposes a portion of the protective layer 7 at the bottom of the second via 80. That is, the orthographic projection of the opening on the plane of the routing layer 1 overlaps with the orthographic projection of the second via 80 on the plane of the routing layer 1. The area of the overlapping portion can account for 20% to 50% of the bottom area of the second via 80.
[0086] Then, using vapor deposition or sputtering processes, and through openings, an electron transport layer 2, an electron injection layer 5, and a cathode layer 3 are sequentially formed on the planarization layer 9 and the partially exposed protective layer 7 (i.e., the exposed portion of the protective layer 7 at the bottom of the second via 80). This ensures that the orthographic projections of the electron injection layer 5 onto the plane of the trace layer 1, the orthographic projections of the cathode layer 3 onto the plane of the trace layer 1, and the orthographic projections of the electron transport layer 2 onto the plane of the trace layer 1 completely overlap. Using a single mask to form the electron transport layer 2, electron injection layer 5, and cathode layer 3 effectively shortens the inline mass production line and reduces production equipment investment costs.
[0087] Since the electron transport layer 2 only covers part of the protective layer 7 at the bottom of the second through hole 80, the remaining protective layer 7 at the bottom of the second through hole 80 is exposed after the mask is removed. Therefore, an overlap layer 4 can be formed on the cathode layer 3 and the remaining protective layer 7 by inkjet printing or screen printing, so that the cathode layer 3 is electrically connected to the wiring layer 1 through the overlap layer 4 and the protective layer 7, ensuring the electrical performance of the display panel.
[0088] In summary, in the embodiments of this application, the orthographic projections of the cathode layer and the electron transport layer on the plane where the wiring layer is located completely overlap, and the overlap layer is located on the cathode layer and the wiring layer, so that the cathode layer is electrically connected to the wiring layer through the overlap layer, ensuring the electrical performance of the display panel. Moreover, only one mask is needed to fabricate the electron transport layer and the cathode layer, shortening the inline mass production line, simplifying the manufacturing process, and reducing production costs.
[0089] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.
Claims
1. A display panel, characterized in that, Includes a non-display area, wherein the non-display area is provided with: wiring layer; A barrier layer is located on the wiring layer, and a first through-hole is provided in the barrier layer; An electron transport layer is located on the barrier layer and extends to a portion of the trace layer at the bottom of the first via; The cathode layer is located on the electron transport layer. The electron transport layer and the cathode layer are stacked layers formed by a single vapor deposition process using the same mask, and the orthogonal projections of the cathode layer and the electron transport layer on the plane where the trace layer is located completely overlap. An overlap layer is located within the first through-hole and covers the cathode layer and the trace layer at the bottom of the first through-hole that is not covered by the electron transport layer, and the cathode layer is electrically connected to the trace layer through the overlap layer.
2. The display panel as described in claim 1, characterized in that, The non-display area is also provided with: An electron injection layer is located between the electron transport layer and the cathode layer, and the orthographic projections of the electron injection layer, the cathode layer, and the electron transport layer on the plane where the trace layer is located completely overlap.
3. The display panel as described in claim 1, characterized in that, The coverage area of the electron transport layer at the bottom of the first through hole accounts for 20% to 50% of the bottom area of the first through hole.
4. The display panel as described in claim 1, characterized in that, The non-display area is also provided with: A protective layer is located between the wiring layer, the electron transport layer, and the overlap layer. The cathode layer is electrically connected to the wiring layer through the overlap layer and the protective layer.
5. The display panel as described in claim 4, characterized in that, The non-display area is also provided with: A passivation layer is located on the trace layer, and a second through-hole is provided in the passivation layer. The protective layer is located on the passivation layer and covers the sidewall of the second through-hole and the trace layer at the bottom of the second through-hole. A planarization layer is located on the protective layer, and a third through hole is provided in the planarization layer to communicate with the second through hole. The electron transport layer is located on the planarization layer and extends to the protective layer at the bottom of the second through hole. The overlapping layer is located in the second through hole and the third through hole and covers the cathode layer and the protective layer.
6. The display panel as described in claim 1, characterized in that, The material of the overlapping layer includes nano-silver or silver alloy.
7. A method for manufacturing a display panel, characterized in that, The display panel includes a non-display area, and the method includes: A wiring layer is formed in the non-display area; A barrier layer is formed on the wiring layer, and a first via is formed in the barrier layer to expose a portion of the wiring layer; a mask is provided, and through the opening of the mask, an electron transport layer and a cathode layer are sequentially deposited on the barrier layer and on a portion of the wiring layer at the bottom of the first via, and the orthogonal projections of the cathode layer and the electron transport layer on the plane where the wiring layer is located completely overlap. An overlap layer is formed on the cathode layer and the trace layer not covered by the electron transport layer within the first through-hole, so that the cathode layer is electrically connected to the trace layer through the overlap layer.
8. The method for manufacturing a display panel as described in claim 7, characterized in that, The step of forming an overlap layer on the cathode layer and the wiring layer includes: The overlap layer is formed on the cathode layer and the remaining exposed wiring layer using inkjet printing or screen printing processes.