A power-on and power-off sequence control device with adjustable delay time

Abstract

The present invention discloses a power-on and power-off sequence control device with adjustable delay time, comprising one or more delay units connected in series and a switch control unit connected to the delay unit. The one or more delay units are used to achieve delayed opening of the switch control unit, and the delay unit includes an RC delay circuit and a discharge control circuit. The discharge control circuit includes a PNP transistor Q1, an adjustable resistor R1, a resistor R2, and a resistor R3. The emitter of the PNP transistor Q1 is connected to the RC delay circuit, the collector of the PNP transistor Q1 is connected to one end of the adjustable resistor R1, and the other end of the adjustable resistor R1 is connected to GND. The base of the PNP transistor Q1 is connected to one end of the resistor R2 and one end of the resistor R3, respectively. The other end of the resistor R2 is connected to VCC, and the other end of the resistor R3 is connected to GND. The present invention has a fast power-off reset function and has the characteristic of adjustable power-off delay.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a power-up and power-down sequence control device with adjustable delay time. Background Art

[0002] Today's systems are becoming increasingly complex, sometimes requiring the integration of components with diverse characteristics from different disciplines to achieve specific functions. The collaborative relationships between these components are also becoming increasingly stringent, often leading to compatibility issues. This necessitates the implementation of necessary measures to address these incompatibilities and prevent equipment failures and losses. In some electronic systems, controlling the power-on sequence of different components can effectively prevent component damage. For example, in intrusion detection equipment based on fiber-optic sensing technology, the laser path can remain open for hundreds of milliseconds during initial power-up due to the inherent characteristics of some control modules or chips. This can cause continuous laser light to damage back-end optoelectronic equipment, resulting in losses.

[0003] There are various existing solutions for controlling the power-on and power-off sequence, such as using discrete components to leverage the integral and differential characteristics of capacitors to achieve delayed on / off switching, or using dedicated ASIC chips for power-on and power-off control. Each solution has its own advantages, disadvantages, and limitations. However, when implementing a power-on delay, existing solutions increase the capacitance as the delay increases, reducing the load during power-off. This makes it difficult for the capacitor to quickly discharge its stored energy, resulting in a delayed power-off and making it difficult to quickly reset and restart the system. Summary of the Invention

[0004] The object of the present invention is to provide a power-on and power-off sequence control device with adjustable delay time, which has a power-off fast reset function and an adjustable power-off delay characteristic.

[0005] To achieve the above object, the technical solution adopted by the present invention is:

[0006] A power-on / off sequence control device with adjustable delay time, comprising one or more delay units connected in series and a switch control unit connected to the delay unit, wherein the switch control unit is delayed by the one or more delay units, and the delay unit comprises an RC delay circuit and a discharge control circuit, wherein:

[0007] The discharge control circuit includes a PNP transistor Q1, an adjustable resistor R1, a resistor R2 and a resistor R3. The emitter of the PNP transistor Q1 is connected to the RC delay circuit, the collector of the PNP transistor Q1 is connected to one end of the adjustable resistor R1, and the other end of the adjustable resistor R1 is connected to GND. The base of the PNP transistor Q1 is respectively connected to one end of the resistor R2 and the resistor R3, the other end of the resistor R2 is connected to VCC, and the other end of the resistor R3 is connected to GND.

[0008] Several optional methods are also provided below, but they are not intended to be additional limitations on the above-mentioned overall solution. They are merely further supplements or optimizations. Under the premise that there are no technical or logical contradictions, each optional method can be combined separately for the above-mentioned overall solution, or multiple optional methods can be combined.

[0009] Preferably, the switch control unit is connected after any one-stage delay unit, and the switch control unit and the delay unit adopt different power supplies.

[0010] Preferably, the RC delay circuit includes an adjustable resistor R4, an adjustable resistor R5, a capacitor C1 and a logic gate AND-1;

[0011] The logic gate AND-1 is an AND gate. One end of the adjustable resistor R4 is connected to VCC, and the other end of the adjustable resistor R4 is respectively connected to one end of the adjustable resistor R5, the emitter of the PNP transistor Q1, and the capacitor C1. The other end of the adjustable resistor R5 is connected to GND. The capacitor C1 is connected to the adjustable resistor R5 in parallel, and the end of the capacitor C1 connected to the adjustable resistor R4 is also connected to the input end of the logic gate AND-1. The output end of the logic gate AND-1 serves as the input of the next-stage delay unit or the input of the switch control unit to be controlled.

[0012] Preferably, the RC delay circuit includes an adjustable resistor R4, an adjustable resistor R5, a capacitor C1, a capacitor C2, a resistor R6, a resistor R7, a MOS transistor MOS1 and a MOS transistor MOS2;

[0013] One end of the adjustable resistor R4 is connected to VCC, and the other end of the adjustable resistor R4 is respectively connected to one end of the adjustable resistor R5, the emitter of the PNP transistor Q1, and the capacitor C1. The other end of the adjustable resistor R5 is connected to GND. The capacitor C1 is connected in parallel with the adjustable resistor R5, and the end of the capacitor C1 connected to the adjustable resistor R4 is also connected to the gate of MOS2. The source of MOS2 is connected to GND. The drain of MOS2 is connected to the gate of MOS1 through the resistor R7. The capacitor C2 is connected in parallel with the resistor R6, and one end of the parallel connection is connected to VCC and the other end is connected to the gate of MOS1. The source of MOS1 is connected to VCC. The drain output of MOS1 serves as the input of the next-stage delay unit or the input of the switch control unit to be controlled.

[0014] Preferably, the delay time of the RC delay circuit is calculated as follows:

[0015]

[0016] Where t is the delay time of the RC delay circuit, Ω4 is the resistance value of the adjustable resistor R4, F1 is the capacitance value of the capacitor C1, and Ω5 is the resistance value of the adjustable resistor R5.

[0017] Preferably, the switch control unit includes a relay Relay1, the contacts of which are closed when the RC delay circuit outputs a high level, and the power supply voltage applied to the contacts of the relay Relay1 is output to the powered device; the contacts of the relay Relay1 are opened when the RC delay circuit outputs a low level, and the power supply voltage applied to the contacts of the relay Relay1 stops supplying power to the powered device.

[0018] Preferably, the switch control unit includes a relay Relay1, a capacitor C3, a resistor R8, a resistor R9, a MOS transistor MOS3, a resistor R10 and a diode D1;

[0019] One end of the capacitor C3 is connected to GND and the other end is connected to the RC delay circuit, one end of the resistor R9 is connected to GND and the other end is connected to the gate of MOS3, the resistor R8 is respectively connected to one end of the capacitor C3 connected to the RC delay circuit and one end of the resistor R9 connected to the gate of MOS3, the source of MOS3 is connected to GND, the drain of MOS3 is connected to one end of the coil of the relay Relay1 through the resistor R10, the other end of the coil of the relay Relay1 is connected to VCC, the cathode of the diode D1 is connected to VCC, the anode of the diode D1 is connected to one end of the coil of the relay Relay1 connected to the resistor R10, and one of the two contacts of the relay Relay1 is applied with the supply voltage and the other is connected to the powered device.

[0020] Preferably, the switch control unit includes a MOS tube MOS4, which is turned on when the RC delay circuit outputs a high level, and the power supply voltage applied to MOS4 is output to the powered device; the MOS4 is disconnected when the RC delay circuit outputs a low level, and the power supply voltage applied to MOS4 stops supplying power to the powered device.

[0021] Preferably, the switch control unit includes a MOS transistor MOS4, a capacitor C3, a resistor R8, a resistor R9, a MOS transistor MOS3, a resistor R10, a capacitor C4 and a resistor R11;

[0022] One end of the capacitor C3 is connected to GND and the other end is connected to the RC delay circuit, one end of the resistor R9 is connected to GND and the other end is connected to the gate of MOS3, the resistor R8 is respectively connected to one end of the capacitor C3 connected to the RC delay circuit and one end of the resistor R9 connected to the gate of MOS3, the source of MOS3 is connected to GND, the drain of MOS3 is connected to the gate of MOS4 through the resistor R10, the supply voltage is applied to the source of MOS4, the drain of MOS4 is connected to the powered device, the capacitor C4 and the resistor R11 are connected in parallel and one end is connected to the gate of MOS4 and the other end is connected to the source of MOS4.

[0023] The power-on and power-off sequence control device with adjustable delay time provided by the present invention, at the initial power-on, cuts off the laser path by delaying the power-on of specific components, allowing other related components sufficient time to complete initialization and reach a controllable operating state, thereby achieving the purpose of protecting subsequent components. After the device is powered off, it can quickly restore itself to the initialized state, allowing the system to still effectively protect the device components when powered on again. The present invention has a fast power-off reset function and a configurable power-off delay, which effectively solves the problems of existing technical solutions. Compared with dedicated ASIC chips, the present invention has a wider operating voltage and delay adjustment range. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic structural diagram of the power-on and power-off sequence control device with adjustable delay time of the present invention;

[0025] Figure 2 This is a schematic diagram of the circuit structure of an embodiment of the power-up and power-down sequence control device with adjustable delay time of the present invention;

[0026] Figure 3 This is a schematic diagram of the circuit structure of another embodiment of the power-up and power-down sequence control device with adjustable delay time of the present invention;

[0027] Figure 4 It is a structural schematic diagram of a multi-stage delay unit and a multi-stage switch control unit of the present invention;

[0028] Figure 5 This is a schematic diagram of the modular structure of the power-up and power-down sequence control device with adjustable delay time of the present invention;

[0029] Figure 6 A schematic diagram of a practical application of the power-on and power-off sequence control device with adjustable delay time of the present invention;

[0030] Figure 7 For the present invention Figure 6 Schematic diagram of the functional modules in the power-up and power-down sequence control device;

[0031] Figure 8For the present invention Figure 7 Schematic diagram of the status of the control device. DETAILED DESCRIPTION

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0033] It should be noted that when a component is referred to as being "connected" to another component, it may be directly connected to the other component or there may be an intermediate component. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0034] In order to overcome the problems in the prior art of power-on and power-off sequence control such as limited adjustability of the delay range, longer power-off recovery time the longer the delay, and difficulty in adjusting the power-off recovery time, this embodiment provides a power-on and power-off sequence control device with adjustable delay time.

[0035] During initial power-up, the device of this embodiment delays the activation of the downstream circuits long enough to allow some system components to complete initialization and achieve a controllable operating state, thereby protecting the downstream components. Furthermore, after a power outage, the device quickly returns to its initialized state, ensuring continued protection of the device components upon power-up. Furthermore, when controlling the power-down sequence of components is required, parameter adjustment facilitates the setting and control of the power-down sequence for each circuit.

[0036] The device of this embodiment has strong scalability, can easily adjust the delay time and extend the multi-channel input delay, and can easily form a universal solidification module for users to choose and use in combination as needed.

[0037] Specifically, the power-on and power-off sequence control device with adjustable delay time in this embodiment includes one or more stages of delay units connected in series and a switch control unit connected to the delay unit, and the delayed opening of the switch control unit is achieved through the one or more stages of delay units.

[0038] like Figure 1 As shown, for ease of description, in one embodiment, a first-level delay unit is taken as an example for explanation, and the delay unit is connected to a switch control unit to form an upper and lower power sequence control device.

[0039] The delay unit of this embodiment includes an RC delay circuit and a discharge control circuit, wherein the discharge control circuit is used to adjust the recovery time of the delay unit itself when the power is turned off.

[0040] like Figure 2 As shown, in one embodiment, the circuit structure of the delay unit is as follows, where symbol R represents a resistor, symbol C represents a capacitor, symbol AND represents a logic gate, Q represents a transistor, MOS represents a field effect transistor, and symbol P represents a node mark.

[0041] The discharge control circuit includes a PNP transistor Q1, an adjustable resistor R1, a resistor R2 and a resistor R3. The emitter of the PNP transistor Q1 is connected to the RC delay circuit, the collector of the PNP transistor Q1 is connected to one end of the adjustable resistor R1, and the other end of the adjustable resistor R1 is connected to GND. The base of the PNP transistor Q1 is connected to one end of the resistor R2 and the resistor R3 respectively, the other end of the resistor R2 is connected to VCC (i.e., VCC1 in the figure), and the other end of the resistor R3 is connected to GND.

[0042] The RC delay circuit includes an adjustable resistor R4, an adjustable resistor R5, a capacitor C1, and a logic gate AND-1; the logic gate AND-1 is an AND gate, one end of the adjustable resistor R4 is connected to VCC, the other end of the adjustable resistor R4 is connected to one end of the adjustable resistor R5, the emitter of the PNP transistor Q1, and the capacitor C1, respectively; the other end of the adjustable resistor R5 is connected to GND, the capacitor C1 is connected in parallel with the adjustable resistor R5, and the end of the capacitor C1 connected to the adjustable resistor R4 is also connected to the input end of the logic gate AND-1, and the output end of the logic gate AND-1 serves as the input of the next-stage delay unit or the input of the switch control unit to be controlled.

[0043] In this embodiment, resistors R1, R4, and R5 are adjustable resistors, and their functions are described as follows:

[0044] R4, R5: In this embodiment, resistors R4 and R5 form an amplitude adjustment element, used to set different acceptable input voltages. Adjusting the value of resistor R4 changes the delay time. Under the condition determined by resistor R4, adjusting the value of R5 changes the acceptable input voltage range.

[0045] R1: Adjust the resistance of resistor R1 to change the discharge time of capacitor C1.

[0046] Logic gate AND-1: Logic gate AND-1 acts as a decision shaper, determining whether to output a high level or a low level based on the output voltage of the RC circuit.

[0047] The delay time of the RC delay circuit in the delay unit is calculated as follows:

[0048]

[0049] Where t is the delay time of the RC delay circuit, Ω4 is the resistance value of the adjustable resistor R4, F1 is the capacitance value of the capacitor C1, and Ω5 is the resistance value of the adjustable resistor R5.

[0050] In this embodiment, the switch control unit includes a relay Relay1. When the RC delay circuit outputs a high level, the contacts of the relay Relay1 are closed, and the power supply voltage applied to the contacts of the relay Relay1 (i.e., VCC2 in the figure) is output to the powered device; when the RC delay circuit outputs a low level, the contacts of the relay Relay1 are opened, and the power supply voltage applied to the contacts of the relay Relay1 stops supplying power to the powered device.

[0051] Specifically, as shown in the figure, the switch control unit includes a relay Relay1, a capacitor C3, a resistor R8, a resistor R9, a MOS transistor MOS3, a resistor R10 and a diode D1.

[0052] One end of the capacitor C3 is connected to GND and the other end is connected to the RC delay circuit, one end of the resistor R9 is connected to GND and the other end is connected to the gate of MOS3, the resistor R8 is respectively connected to one end of the capacitor C3 connected to the RC delay circuit and one end of the resistor R9 connected to the gate of MOS3, the source of MOS3 is connected to GND, the drain of MOS3 is connected to one end of the coil of the relay Relay1 through the resistor R10, the other end of the coil of the relay Relay1 is connected to VCC, the cathode of the diode D1 is connected to VCC, the anode of the diode D1 is connected to one end of the coil of the relay Relay1 connected to the resistor R10, and one of the two contacts of the relay Relay1 is applied with the supply voltage and the other is connected to the powered device.

[0053] based on Figure 2 The circuit structure shown in FIG. 1 is a flow chart of the power-up and power-down sequence control device of this embodiment as follows:

[0054] Resistors R4 and R5, capacitor C1, and logic gate AND-1 form a first-stage delay circuit. Resistor R5 forms a voltage divider with resistor R4, serving as a parameter for adjusting the input voltage range. Resistor R4, R5, capacitor C1, and logic gate AND-1 collectively determine the delay duration. The value of resistor R4 influences the charging speed of capacitor C1, which in turn affects the delay duration. The voltage divider between resistors R4 and R5 determines the maximum voltage capacitor C1 can reach. The real-time voltage across capacitor C1 is connected to the input of AND gate AND-1. Upon power-up, power supply VCC1 begins charging capacitor C1 through resistor R4. When the voltage across capacitor C1 reaches the high-level decision threshold of AND gate AND-1, its output flips to a high level. At this point, voltage divider resistors R8 and R9 drive MOS3 to conduct, closing relay Relay1. VCC2, through the relay, is output to VCC2_OUT, providing power to the downstream powered device.

[0055] In the discharge control circuit, Q1 is a PNP transistor, which, together with resistors R1, R2, and R3, forms a discharge control circuit for the energy stored in capacitor C1 when power is turned off. When the power supply VCC1 is connected, the base voltage of capacitor Q1 is set by resistors R2 and R3 so that it is not less than the emitter voltage of transistor Q1 (that is, the terminal voltage of capacitor C1). Figure 2 (The voltage of nodes P3 and P4 relative to GND is shown in the figure). Under this condition, transistor Q1 is in the off state. VCC1 continuously charges capacitor C1 through resistor R4. When VCC1 is powered off or disconnected, the voltage at capacitor C1 becomes the voltage at the emitter of transistor Q1. Resistors R4, R2, and R3 form a voltage divider network, which adjusts the voltage at capacitor C1, which is in the energy storage state, to distribute the voltage to the base of transistor Q1, making it lower than the emitter voltage of transistor Q1. This causes the voltage difference between the base and emitter to exceed the turn-on voltage threshold of transistor Q1 and be lower than the maximum withstand voltage of the PN junction between the base and emitter of transistor Q1. Transistor Q1 is then turned on, and capacitor C1 discharges its stored energy through resistor R1. The resistance value of resistor R1 affects the duration of the discharge of the stored energy in capacitor C1. When the energy stored in capacitor C1 is continuously discharged and the terminal voltage drops to the low-level input threshold of AND gate AND-1, the output of AND gate AND-1 flips from high level to low level, MOS3 is cut off, relay Relay1 is disconnected, and VCC2_OUT loses power.

[0056] In this embodiment, in order to achieve electrostatic surge protection and suppress power supply transient overshoot and electrostatic damage to the control device, a transient suppression diode TVS1 is connected between the input terminal VCC1 and GND.

[0057] In order to improve the adaptability of the control device of the present invention, the RC delay circuit and the switch control unit of the present invention are not limited to the structures shown in the above embodiments, and more alternative solutions can be provided in other embodiments. Figure 3As shown, in one embodiment, the RC delay circuit and the switch control unit also have the following design scheme.

[0058] The RC delay circuit includes an adjustable resistor R4, an adjustable resistor R5, a capacitor C1, a capacitor C2, a resistor R6, a resistor R7, a MOS transistor MOS1, and a MOS transistor MOS2. One end of the adjustable resistor R4 is connected to VCC (i.e., VCC1 in the figure), and the other end of the adjustable resistor R4 is respectively connected to one end of the adjustable resistor R5, the emitter of the PNP transistor Q1, and the capacitor C1. The other end of the adjustable resistor R5 is connected to GND. The capacitor C1 is connected in parallel with the adjustable resistor R5, and the end of the capacitor C1 connected to the adjustable resistor R4 is also connected to the gate of MOS2. The source of MOS2 is connected to GND, and the drain of MOS2 is connected to the gate of MOS1 through resistor R7. The capacitor C2 is connected in parallel with the resistor R6, and one end of the parallel connection is connected to VCC and the other end is connected to the gate of MOS1. The source of MOS1 is connected to VCC, and the drain output of MOS1 serves as the input of the next-stage delay unit or the input of the switch control unit to be controlled.

[0059] The switch control unit includes a MOS transistor MOS4, which is turned on when the RC delay circuit outputs a high level, and the power supply voltage applied to MOS4 (i.e., VCC2 in the figure) is output to the powered device; the MOS4 is disconnected when the RC delay circuit outputs a low level, and the power supply voltage applied to MOS4 stops supplying power to the powered device.

[0060] The specific switch control unit includes a MOS tube MOS4, a capacitor C3, a resistor R8, a resistor R9, a MOS tube MOS3, a resistor R10, a capacitor C4 and a resistor R11; one end of the capacitor C3 is connected to GND and the other end is connected to the RC delay circuit, one end of the resistor R9 is connected to GND and the other end is connected to the gate of MOS3, the resistor R8 is respectively connected to one end of the capacitor C3 connected to the RC delay circuit and one end of the resistor R9 connected to the gate of MOS3, the source of MOS3 is connected to GND, the drain of MOS3 is connected to the gate of MOS4 through the resistor R10, the supply voltage is applied to the source of MOS4, the drain of MOS4 is connected to the powered device, the capacitor C4 and the resistor R11 are connected in parallel, and after the parallel connection, one end is connected to the gate of MOS4 and the other end is connected to the source of MOS4.

[0061] It is easy to understand that the RC delay circuit and the switch control unit provided in this embodiment can be replaced independently. Figure 2 The corresponding circuit in the scheme, on this basis, the control device of the present invention has multiple structures.

[0062] For the convenience of description, this embodiment uses Figure 3 The circuit structure in the replacement scheme describes the working process of the control device as follows:

[0063] In this embodiment, MOS1 and MOS2 are used instead Figure 2 The logic gate AND-1 in the circuit is replaced by MOS4. Figure 2 Relay 1 in the circuit. When the charge of capacitor C1 reaches the turn-on threshold of MOS2, MOS2 turns on, MOS1 turns on, VCC1 turns on MOS3 through MOS1, and when MOS3 turns on, MOS4 turns on, and VCC2 powers the subsequent powered device through MOS4.

[0064] When VCC1 is disconnected, capacitor C1 discharges through transistor Q1. When the voltage at the end of capacitor C1 is lower than the turn-on threshold of MOS2, MOS2 is turned off, restoring MOS1 to the disconnected state. MOS3 is turned off, and MOS4 is disconnected, disconnecting the subsequent powered device from the power supply VCC2.

[0065] Compared with the existing delay circuit, the power-on and power-off sequence control device of the present invention provides a fast discharge control circuit when a longer delay time is required, that is, when the R and C values are large. When necessary, the discharge time of the capacitor can be greatly shortened, and the voltage across the capacitor can be quickly reduced, thereby avoiding power-off delay and achieving fast power-off. At the same time, the discharge time of the capacitor can be controlled by adjusting the parameters of the discharge control circuit to achieve control of the length of the power-off delay time.

[0066] Compared with integrated IC chips, the present invention is composed of discrete components, has a wider, broader and more flexible parameter configuration and autonomous control range, and can adapt to more application scenarios.

[0067] In this embodiment, when the delay unit is a single-stage unit, the switch control unit is connected to form a complete power-up and power-down sequence control device. When the delay unit is multi-stage in series, the switch control unit can be connected after any stage of the delay unit, and the switch control unit and the delay unit use different power supplies.

[0068] like Figure 4 As shown, the present invention can be configured with multiple delay units and multiple switch control units according to different application scenarios. Each delay unit can be connected to a switch control unit. For example, in the figure, the first delay unit is connected to switch control unit 1, the second delay unit is connected to switch control unit 2, and so on. Of course, a delay unit does not necessarily have to be connected to a switch control unit. The delay of multiple delay units can be applied to a single switch control unit, making the present invention highly scalable for multi-path delay.

[0069] When applied to power-on control, the present invention implements multi-path delayed-on control by cascading standardized delay modules to output step-by-step delay durations. During power-off, each delay unit incorporates an independent discharge control circuit, enabling rapid power-off when needed. The discharge time of the control capacitor can also be adjusted by adjusting the parameters of the discharge control circuit in each delay unit, thereby controlling the power-off sequence of each powered module. This overcomes the difficulty in adjusting the power-off sequence in existing technologies.

[0070] In one embodiment, in order to match the selection and use of the multi-stage delay unit, the power-up and power-down sequence control device of the present invention is formed into a solidified module. Figure 5 As shown, the delay control module of the present invention can be manufactured into a standard miniaturized module using a COB-like package format. A time configuration interface is reserved, and the delay time is set by connecting an external configuration capacitor. The package module also provides reserved input and output interfaces to facilitate integration with user systems and expansion requirements. A parameter configuration reference sheet or user manual can be provided with the module, indicating the delay time corresponding to different external delay configuration capacitor values.

[0071] like Figure 6 As shown, the application of the present invention in intrusion detection equipment based on optical fiber sensing technology is as follows:

[0072] Application purpose: To protect the photoelectric detector from being damaged when the system is initially powered on.

[0073] Implementation method: Turn off AOM at initial power-up by turning off AOM driver ( Figure 6 The driver) power supply indirectly cuts off the light path for a certain period of time t1.

[0074] Implementation process: The power-up and power-down sequence control device of the present invention (abbreviated as: control device) is connected to the two power supplies VCC1 and VCC2 at the same time. After the power supply VCC1 turns on the output, it delays for a period of time t (time t is between hundreds of milliseconds and several seconds). Then the control device opens the power supply VCC2 path and outputs it to VCC2_OUT to power the AOM driver, completing the driver power-on. The driver outputs a pulse signal to control the opening and closing of the AOM.

[0075] Working state transfer process: Figure 7 As shown, the internal functional unit of the control device is controlled by the delay unit to control whether the relay in the switch control unit is turned on, thereby controlling whether the voltage VCC2 is output to VCC2_OUT to power the Driver. During this period, the power-on and power-off sequence control device goes from the initialization state to the power-on transient state after a delay of t milliseconds as shown in FIG. Figure 8 shown.

[0076] In the figure, Relay represents a relay, SW represents the relay's on / off control signal, and U1 and U2 represent the actual voltage values of VCC1 and VCC2, which can be equal or unequal. VCC1 and VCC2 can be configured to match the power supply requirements for power-up and power-down sequencing. Driver represents other system functional units that require power-up and power-down control. This further illustrates the state transitions and control process of the control device.

[0077] As shown in the figure, in the initialization state of the control device, the voltages VCC1 and VCC2 are both 0V. At this time, the switch control signal of the relay is low, the relay is disconnected, and the output VCC2_OUT through the relay is 0V, and the powered device Driver is not powered. At the moment of power-on, the voltages VCC1 and VCC2 are U1 and U2, respectively. At this time, the switch control signal of the relay is low, the relay is disconnected, and the output VCC2_OUT through the relay is 0V, and the powered device Driver is not powered. After a delay of t milliseconds, the voltages VCC1 and VCC2 are U1 and U2, respectively. At this time, the switch control signal of the relay is high, the relay is closed, and the output VCC2_OUT through the relay is U2, and the powered device Driver is powered. It can be seen that the present invention can effectively control the delayed power-on of the powered device.

[0078] The input power range of the present invention is adjustable, and the power-on delay and power-off delay are adjustable, with great flexibility and adjustable range. In addition, this embodiment provides a discharge control circuit, which can achieve rapid discharge of capacitor energy storage during power-off, rapid power-off, and adjustable discharge time. The present invention can achieve modular structural expansion and step-by-step delay output, which can be flexibly configured according to different application scenarios.

[0079] The present invention has passed the two-stage circuit delay function test. The discharge parameters are set to the fast discharge mode. The two-stage delay parameter setting can achieve a delay of approximately 1 second. In actual lighting tests, the light turns on after a delay of approximately 1 second when the power is turned on, and the light turns off immediately when the power is turned off. There is no visual delay. After powering off and then quickly turning on again, the function still meets the design expectations. Multiple rapid repeated tests can control the on and off of the light normally.

[0080] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The above-described embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A power-on and power-off sequence control device with adjustable delay time, characterized in that: The power-on and power-off sequence control device with adjustable delay time includes one or more delay units connected in series and a switch control unit connected to the delay unit. The switch control unit is delayed by the one or more delay units. The delay unit includes an RC delay circuit and a discharge control circuit, wherein: The discharge control circuit includes a PNP transistor Q1, an adjustable resistor R1, a resistor R2 and a resistor R3, the emitter of the PNP transistor Q1 is connected to the RC delay circuit, the collector of the PNP transistor Q1 is connected to one end of the adjustable resistor R1, the other end of the adjustable resistor R1 is connected to GND, the base of the PNP transistor Q1 is connected to one end of the resistor R2 and the resistor R3 respectively, the other end of the resistor R2 is connected to VCC, and the other end of the resistor R3 is connected to GND; After the switch control unit is connected to any one-level delay unit, the switch control unit and the delay unit use different power supplies. The switch control unit includes a relay Relay1. When the RC delay circuit outputs a high level, the contact of the relay Relay1 is closed, and the power supply voltage applied to the contact of the relay Relay1 is output to the powered device; when the RC delay circuit outputs a low level, the contact of the relay Relay1 is opened, and the power supply voltage applied to the contact of the relay Relay1 stops powering the powered device.

2. The power-on and power-off sequence control device with adjustable delay time according to claim 1, characterized in that: The RC delay circuit includes an adjustable resistor R4, an adjustable resistor R5, a capacitor C1 and a logic gate AND-1; The logic gate AND-1 is an AND gate. One end of the adjustable resistor R4 is connected to VCC, and the other end of the adjustable resistor R4 is respectively connected to one end of the adjustable resistor R5, the emitter of the PNP transistor Q1, and the capacitor C1. The other end of the adjustable resistor R5 is connected to GND. The capacitor C1 is connected to the adjustable resistor R5 in parallel, and the end of the capacitor C1 connected to the adjustable resistor R4 is also connected to the input end of the logic gate AND-1. The output end of the logic gate AND-1 serves as the input of the next-stage delay unit or the input of the switch control unit to be controlled.

3. The power-on and power-off sequence control device with adjustable delay time according to claim 1, characterized in that: The RC delay circuit includes an adjustable resistor R4, an adjustable resistor R5, a capacitor C1, a capacitor C2, a resistor R6, a resistor R7, a MOS transistor MOS1 and a MOS transistor MOS2; One end of the adjustable resistor R4 is connected to VCC, and the other end of the adjustable resistor R4 is respectively connected to one end of the adjustable resistor R5, the emitter of the PNP transistor Q1, and the capacitor C1. The other end of the adjustable resistor R5 is connected to GND. The capacitor C1 is connected in parallel with the adjustable resistor R5, and the end of the capacitor C1 connected to the adjustable resistor R4 is also connected to the gate of MOS2. The source of MOS2 is connected to GND. The drain of MOS2 is connected to the gate of MOS1 through the resistor R7. The capacitor C2 is connected in parallel with the resistor R6, and one end of the parallel connection is connected to VCC and the other end is connected to the gate of MOS1. The source of MOS1 is connected to VCC. The drain output of MOS1 serves as the input of the next-stage delay unit or the input of the switch control unit to be controlled.

4. The power-on and power-off sequence control device with adjustable delay time according to claim 2 or 3, characterized in that: The delay time of the RC delay circuit is calculated as follows: ； Where, is the delay time of the RC delay circuit, is the resistance of the adjustable resistor R4, is the capacitance of capacitor C1, is the resistance value of the adjustable resistor R5.

5. The power-on and power-off sequence control device with adjustable delay time according to claim 1, characterized in that: The switch control unit includes a relay Relay1, a capacitor C3, a resistor R8, a resistor R9, a MOS transistor MOS3, a resistor R10 and a diode D1; One end of the capacitor C3 is connected to GND and the other end is connected to the RC delay circuit, one end of the resistor R9 is connected to GND and the other end is connected to the gate of MOS3, the resistor R8 is respectively connected to one end of the capacitor C3 connected to the RC delay circuit and one end of the resistor R9 connected to the gate of MOS3, the source of MOS3 is connected to GND, the drain of MOS3 is connected to one end of the coil of the relay Relay1 through the resistor R10, the other end of the coil of the relay Relay1 is connected to VCC, the cathode of the diode D1 is connected to VCC, the anode of the diode D1 is connected to one end of the coil of the relay Relay1 connected to the resistor R10, and one of the two contacts of the relay Relay1 is applied with the supply voltage and the other is connected to the powered device.

6. The power-on and power-off sequence control device with adjustable delay time according to claim 1, characterized in that: The switch control unit includes a MOS transistor MOS4, which is turned on when the RC delay circuit outputs a high level, and the power supply voltage applied to MOS4 is output to the powered device; the MOS4 is disconnected when the RC delay circuit outputs a low level, and the power supply voltage applied to MOS4 stops supplying power to the powered device.

7. The power-on and power-off sequence control device with adjustable delay time according to claim 6, characterized in that: The switch control unit includes a MOS transistor MOS4, a capacitor C3, a resistor R8, a resistor R9, a MOS transistor MOS3, a resistor R10, a capacitor C4 and a resistor R11; One end of the capacitor C3 is connected to GND and the other end is connected to the RC delay circuit, one end of the resistor R9 is connected to GND and the other end is connected to the gate of MOS3, the resistor R8 is respectively connected to one end of the capacitor C3 connected to the RC delay circuit and one end of the resistor R9 connected to the gate of MOS3, the source of MOS3 is connected to GND, the drain of MOS3 is connected to the gate of MOS4 through the resistor R10, the supply voltage is applied to the source of MOS4, the drain of MOS4 is connected to the powered device, the capacitor C4 and the resistor R11 are connected in parallel and one end is connected to the gate of MOS4 and the other end is connected to the source of MOS4.

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