Analog-to-digital converters and chips

Abstract

This invention provides an analog-to-digital converter (ADC) comprising: a switched-capacitor array for operating in a first ADC mode or a second ADC mode based on a received timing signal; a first logic unit for outputting a first timing signal to control the switched-capacitor array to operate in the first ADC mode; a second logic unit for outputting a second timing signal to control the switched-capacitor array to operate in the second ADC mode; a control unit for outputting a control signal to control the first logic unit to output the first timing signal and to control the second logic unit to output the second timing signal; and a comparator, the output of which is electrically connected to the first and second logic units to feed back the output voltage of the switched-capacitor array to the control unit through the first and second logic units. This satisfies the requirements for high-precision and fast sampling of signals at different time periods, and reduces the area of ​​the ADC by reusing the switched-capacitor array and the comparator.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital conversion technology, and more particularly to an analog-to-digital converter and chip. Background Technology

[0002] With the rapid development and widespread adoption of digital technology, especially computer technology, analog-to-digital (ADC) technology is increasingly widely used. For example, ADCs are extensively applied in image processing, digital video, and biomedical fields. Commonly used ADCs include Sigma-Delta ADCs, Successive Approximation Register (SAR) ADCs, Pipeline ADCs, Flash ADCs, Ramp ADCs, and so on. Typically, in low-power applications, Sigma-Delta ADCs have a slower sampling rate, such as a few kHz, but higher accuracy, such as 24 bits. SAR ADCs, on the other hand, can achieve sampling rates of several MHz, but with relatively lower accuracy, such as 10 bits. In practical applications, high-precision sampling of the signal is often required for one period, while rapid sampling is needed for another. Currently, this is often achieved by using two ADCs on a single chip, but this results in significant power consumption and area overhead. Summary of the Invention

[0003] The purpose of this invention is to provide an analog-to-digital converter and chip that can solve the above-mentioned problems.

[0004] One aspect of this invention provides an analog-to-digital converter, comprising:

[0005] A switched capacitor array is used to operate in a first analog-to-digital conversion mode or a second analog-to-digital conversion mode according to the received timing signal;

[0006] The first logic unit is electrically connected to the switched capacitor array and is used to output a first timing signal to control the switched capacitor array to operate in the first analog-to-digital conversion mode.

[0007] The second logic unit is electrically connected to the switched capacitor array and is used to output a second timing signal to control the switched capacitor array to operate in the second analog-to-digital conversion mode.

[0008] A control unit is electrically connected to the first logic unit and the second logic unit, and is used to output control signals to control the first logic unit to output the first timing signal and to control the second logic unit to output the second timing signal.

[0009] The comparator includes a non-inverting input, an inverting input, and an output. The non-inverting input is electrically connected to the output of the switched capacitor array, the inverting input is grounded, and the output is electrically connected to the first logic unit and the second logic unit to feed back the output voltage of the switched capacitor array to the control unit through the first logic unit and the second logic unit.

[0010] Optionally, it also includes a first switch electrically connected between the non-inverting input terminal of the comparator and the output terminal of the switched capacitor array;

[0011] The modulator includes an input terminal, an output terminal, and a feedback terminal. The input terminal of the modulator is electrically connected to the output terminal of the switched capacitor array via a second switch. The output terminal of the modulator is electrically connected to the non-inverting input terminal of the comparator via a third switch. The feedback terminal of the modulator is electrically connected to the first logic unit. The first switch, the second switch, and the third switch are controlled by the control unit.

[0012] Optionally, when the control unit controls the first logic unit to output the first timing signal, and the switched capacitor array operates in the first analog-to-digital conversion mode:

[0013] The control unit controls the first switch to open and the second and third switches to open;

[0014] The switched capacitor array outputs a first output voltage to the modulator;

[0015] The modulator performs charge integration on the first output voltage and outputs the result to the non-inverting input of the comparator.

[0016] The comparator outputs a first result to the first logic unit based on the calculation result;

[0017] The first logic unit feeds back the first comparison result to the control unit.

[0018] Optionally, when the control unit controls the second logic unit to output the second timing signal, and the switched capacitor array operates in the second analog-to-digital conversion mode:

[0019] The control unit controls the first switch to be turned on, and the second and third switches to be turned off;

[0020] The switched capacitor array outputs a second output voltage to the non-inverting input terminal of the comparator through a first switch;

[0021] The comparator outputs a second comparison result to the second logic unit based on the second output voltage;

[0022] The second logic unit feeds back the second comparison result to the control unit.

[0023] Optionally, the switched capacitor array includes n groups of switched capacitors, where n ≥ 1, and each group of switched capacitors includes:

[0024] An input switch, with one end connected to the input voltage;

[0025] The first output switch has one end electrically connected to the other end of the input switch, and the other end electrically connected to the non-inverting input terminal of the comparator through the first switch.

[0026] The first capacitor has one end electrically connected to the common terminal of the input switch and the first output switch;

[0027] The second output switch has one end electrically connected to the modulator via the second switch, and the other end electrically connected to the other end of the first capacitor;

[0028] The fourth switch has one end grounded and the other end electrically connected to one end of the first capacitor;

[0029] The fifth switch has one end connected to the first reference voltage and the other end electrically connected to the other end of the first capacitor;

[0030] The sixth switch has one end grounded and the other end electrically connected to the other end of the first capacitor;

[0031] The seventh switch has one end connected to the second reference voltage and the other end electrically connected to the other end of the first capacitor.

[0032] Optionally, when the switched capacitor array operates in the first analog-to-digital conversion mode, the input switch, second output switch, fourth switch, and sixth switch of each group of switched capacitors are activated, while the first output switch, fifth switch, and seventh switch are deactivated, and the switched capacitor array outputs the first output voltage through the second output switch;

[0033] When the switched capacitor array operates in the second analog-to-digital conversion mode, the second output switch, the fourth switch, and the sixth switch of each group of switched capacitors are disconnected, and the input switch, the first output switch, the fifth switch, and the seventh switch are activated. The switched capacitor array outputs the second output voltage through the first output switch.

[0034] Optionally, the modulator includes:

[0035] The first integrator includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal of the first integrator is grounded, and the inverting input terminal is electrically connected to the switched capacitor array through the second switch.

[0036] A voltage conversion unit is electrically connected between the inverting input of the first integrator and the first logic unit;

[0037] The second capacitor is electrically connected between the inverting input terminal and the output terminal of the first integrator.

[0038] The second integrator includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The inverting input terminal of the second integrator is electrically connected to the output terminal of the first integrator through an eighth switch, a third capacitor, and a ninth switch connected in series. The common terminal of the eighth switch and the third capacitor is grounded through a tenth switch, and the common terminal of the ninth switch and the third capacitor is grounded through an eleventh switch. The non-inverting input terminal of the second integrator is grounded. The output terminal of the second integrator is electrically connected to the third switch through a twelfth switch and a fourth capacitor connected in series. The common terminal of the twelfth switch and the fourth capacitor is grounded through a thirteenth switch.

[0039] The fifth capacitor is electrically connected between the inverting input terminal and the output terminal of the second integrator;

[0040] The sixth capacitor has one end electrically connected to the common terminal of the fourth capacitor and the third switch, and the other end electrically connected to the output terminal of the first integrator through the fourteenth switch. One end of the sixth capacitor is also grounded through the fifteenth switch, and the other end of the sixth capacitor is also grounded through the sixteenth switch.

[0041] Optionally, when the switched capacitor array operates in the first analog-to-digital conversion mode:

[0042] The first output voltage output by the switched capacitor array is integrated by the first integrator and the second integrator and then output to the non-inverting input of the comparator.

[0043] The conversion unit converts the signal output by the first logic unit into a feedback voltage and inputs it to the inverting input of the first integrator to form a negative feedback loop.

[0044] Optionally, the control unit has a preset control program, which is used to control the first logic unit or the second logic unit to work respectively during a set time period.

[0045] Another aspect of the present invention provides a chip including any of the analog-to-digital converters described above.

[0046] The analog-to-digital converter and chip provided by this invention control the switched capacitor array to operate in a first analog-to-digital conversion mode (Sigma-Delta mode) by outputting a first timing signal through a first logic unit, and control the switched capacitor array to operate in a second analog-to-digital conversion mode (SAR mode) by outputting a second timing signal through a second logic unit. This satisfies the requirements for high-precision and fast sampling of signals in different time periods. At the same time, by reusing the switched capacitor array and comparator, the area and power consumption of the analog-to-digital converter are reduced.

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. Attached Figure Description

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 A circuit diagram of an analog-to-digital converter according to Embodiment 1 of the present invention is shown schematically.

[0050] Figure 2 A circuit diagram of an analog-to-digital converter according to Embodiment 2 of the present invention is shown schematically.

[0051] Figure 3 The schematic diagram illustrates the circuit diagram of the analog-to-digital converter of Embodiment 2 of the present invention operating in the first analog-to-digital conversion mode.

[0052] Figure 4 The schematic diagram illustrates the timing signals output by the first logic unit when the analog-to-digital converter of Embodiment 2 of the present invention is operating in the first analog-to-digital conversion mode.

[0053] Figure 5 The circuit diagram of the modulator for Embodiment 2 of the present invention is shown schematically.

[0054] Figure 6 The schematic diagram illustrates the circuit diagram of the analog-to-digital converter of Embodiment 2 of the present invention operating in the second analog-to-digital conversion mode.

[0055] Figure 7 The schematic diagram illustrates the timing signals output by the second logic unit when the analog-to-digital converter of Embodiment 2 of the present invention is operating in the second analog-to-digital conversion mode.

[0056] Explanation of key component symbols:

[0057] Analog-to-digital converter 1;

[0058] Switched capacitor array 10;

[0059] First logic unit 20;

[0060] Second logic unit 30;

[0061] Control unit 40;

[0062] Comparator 50;

[0063] Modulator 60;

[0064] First switch K1;

[0065] Second switch K2;

[0066] Third switch K3;

[0067] Switched capacitors 101 and 101n;

[0068] Input switches S1_1 and S1_1n;

[0069] Fourth switches A2_1 and A2_1n;

[0070] Fifth switches B2_1 and B2_1n;

[0071] Sixth switches A3_1 and A3_1n;

[0072] Seventh switches B3_1 and B3_1n;

[0073] First output switches B4_1 and B4_1n;

[0074] Second output switches A4_1 and A4_1n;

[0075] First capacitors C1_1 and C1_1n;

[0076] First integrator U1;

[0077] Voltage conversion unit 601;

[0078] Second capacitor C2;

[0079] Second integrator U2;

[0080] Fifth capacitor C5;

[0081] The sixth capacitor, C6;

[0082] Eighth switch - Sixteenth switch K8-K16;

[0083] First output voltage VON1;

[0084] Second output voltage VON2;

[0085] Input voltage VIN;

[0086] First reference voltage VRP;

[0087] Second reference voltage VRN. Detailed Implementation

[0088] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can be arranged and designed in various different configurations. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present invention more thorough and complete. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0089] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0090] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "electrically connected" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements. It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element present.

[0091] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0092] The terminology involved in this invention is explained as follows:

[0093] ADC: Analog to Digital Converter.

[0094] Sigma-Delta ADC: An analog-to-digital converter characterized by high sampling accuracy but slow sampling rate.

[0095] SAR ADC: Successive Approximation Register ADC, characterized by high sampling rate but low sampling accuracy.

[0096] The inventors have discovered that with the rapid development and widespread adoption of digital technology, especially computer technology, analog-to-digital conversion (ADC) technology is becoming increasingly widely used, such as in image processing, digital video, and biomedicine. Different types of ADCs exhibit significant differences in conversion speed and accuracy. Typically, in low-power applications, Sigma-Delta ADCs have slower sampling rates, such as a few kHz, but higher accuracy, such as 24 bits. SAR ADCs, on the other hand, can achieve sampling rates of several MHz, but with relatively lower accuracy, such as 10 bits. However, in practical applications, high-precision sampling of the signal is required for a certain period, while rapid sampling is needed for another. To achieve both high-precision sampling and rapid sampling, two ADCs must be used in the chip, which significantly increases the chip's power consumption and area.

[0097] The inventors discovered that both Sigma-Delta ADCs and SAR ADCs require a comparator as the final quantizer, and switched-capacitor sampling circuits are classic and commonly used sampling circuits. However, from a noise and performance perspective, the sampling capacitors often occupy a relatively large area. Therefore, the key is how to reuse switched-capacitor sampling circuits to enable analog-to-digital converters to achieve high-precision sampling and fast scaling while saving chip area.

[0098] In view of this, embodiments of the present invention provide an analog-to-digital converter and a chip, thereby enabling the analog-to-digital converter to save chip area while meeting the requirements of high-precision sampling and fast sampling.

[0099] Specifically:

[0100] We provide new analog-to-digital converters and chips.

[0101] Multiplexed switched capacitor array: Operating in Sigma-Delta or SAR mode based on the received timing signal, the analog-to-digital converter (ADC) can achieve high-precision or fast sampling of the signal according to actual needs. Simultaneously, the multiplexing of the switched capacitor array and comparator significantly reduces chip area and power consumption.

[0102] Example 1

[0103] Figure 1 A circuit diagram of an analog-to-digital converter 1 according to Embodiment 1 of the present invention is shown schematically. Figure 1As shown, the analog-to-digital converter 1 of the present invention may include: a switched capacitor array 10, a first logic unit 20, a second logic unit 30, a control unit 40, and a comparator 50.

[0104] In this embodiment, the switched capacitor array 10 operates in either a first analog-to-digital conversion mode or a second analog-to-digital conversion mode according to the received timing signal.

[0105] Specifically, the first analog-to-digital conversion mode is Sigma-Delta mode, and the second analog-to-digital conversion mode is SAR mode. The switched-capacitor array 10 switches between these two different modes, Sigma-Delta mode and SAR mode, depending on the received timing signal. Sigma-Delta ADCs generally have a slower sampling rate, such as several kHz, but higher accuracy, such as 24 bits. SAR ADCs, on the other hand, can achieve sampling rates of several MHz, but their accuracy is relatively lower, such as 10 bits. When the switched-capacitor array 10 operates in Sigma-Delta mode, it meets the requirements for high-precision signal sampling; when operating in Sigma-Delta mode, it meets the requirements for fast signal sampling.

[0106] The first logic unit 20 is electrically connected to the switched capacitor array 10 and is used to output a first timing signal to control the switched capacitor array 10 to operate in the first analog-to-digital conversion mode.

[0107] The second logic unit 30 is electrically connected to the switched capacitor array 10 and is used to output a second timing signal to control the switched capacitor array 10 to operate in the second analog-to-digital conversion mode.

[0108] The control unit 40 is electrically connected to the first logic unit 20 and the second logic unit 30, and is used to output control signals to control the first logic unit 20 to output the first timing signal and to control the second logic unit 30 to output the second timing signal.

[0109] Comparator 50 includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is electrically connected to the output terminal of the switched capacitor array 10, the inverting input terminal is grounded, and the output terminal is electrically connected to a first logic unit 20 and a second logic unit 30 to feed back the output voltage of the switched capacitor array 10 to the control unit 40 through the first logic unit 20 and the second logic unit 30.

[0110] In this embodiment of the invention, the first timing signal output by the first logic unit 20 controls the switched capacitor array 10 to operate in Sigma-Delta mode, and the second timing signal output by the second logic unit 30 controls the switched capacitor array 10 to operate in SAR mode, which satisfies the high-precision sampling requirements and fast sampling requirements of the signal in different time periods. At the same time, since the switched capacitor array 10 and the comparator 50 are reused, the area of ​​the analog-to-digital converter 1 is reduced.

[0111] Example 2

[0112] Figure 2 A circuit diagram of an analog-to-digital converter 1 according to Embodiment 2 of the present invention is shown schematically. Figure 2 As shown, compared to Embodiment 1, the analog-to-digital converter 1 further includes a first switch K1, a modulator 60, a second switch K2, and a third switch K3.

[0113] In this embodiment, the first switch K1 is electrically connected between the non-inverting input terminal of the comparator 50 and the output terminal of the switched capacitor array 10.

[0114] The modulator 60 includes an input terminal, an output terminal, and a feedback terminal. The input terminal of the modulator 60 is electrically connected to the output terminal of the switched capacitor array 10 through a second switch K2. The output terminal of the modulator 60 is electrically connected to the non-inverting input terminal of the comparator 50 through a third switch K3. The feedback terminal of the modulator 60 is electrically connected to the first logic unit 20.

[0115] In this embodiment, the first switch K1, the second switch K2, and the third switch K3 are controlled by the control unit 40. When the control unit 40 controls the first logic unit 20 to output the first timing signal, and the switched capacitor array 10 operates in the first analog-to-digital conversion mode: the control unit 40 controls the first switch K1 to open, and the second switch K2 and the third switch K3 to open; the switched capacitor array 10 outputs a first output voltage VON1 to the modulator 60; the modulator 60 performs charge integration on the first output voltage VON1 and outputs the calculation result to the non-inverting input of the comparator 50; the comparator 50 outputs a first result to the first logic unit 20 according to the calculation result; the first logic unit 20 feeds back the first comparison result to the control unit 40.

[0116] When the control unit 40 controls the second logic unit 30 to output the second timing signal, and the switched capacitor array 10 operates in the second analog-to-digital conversion mode: the control unit 40 controls the first switch K1 to be turned on, and the second switch K2 and the third switch K3 to be turned off; the switched capacitor array 10 outputs the second output voltage VON2 to the non-inverting input terminal of the comparator 50 through the first switch K1; the comparator 50 outputs the second comparison result to the second logic unit 30 according to the second output voltage VON2; the second logic unit 30 feeds back the second comparison result to the control unit 40.

[0117] In practical applications, the control unit 40 can be pre-programmed with a control program. This program controls the first logic unit 20 or the second logic unit 30 to operate separately within a set time period. For example, the control program might set the first logic unit 20 to operate for 5ms, and then the second logic unit 30 to operate for 10ms, alternating between them so that they do not operate simultaneously. It is understood that this is merely an example, and the operating time periods of the first logic unit 20 and the second logic unit 30 can be determined according to actual needs.

[0118] like Figure 2 As shown, in this embodiment, the switched capacitor array 10 includes n groups of switched capacitors 101, where n ≥ 1. Each group of switched capacitors 101 has the same structure. The following description uses the first group of switched capacitors 101 as an example. Each group of switched capacitors 101 may include an input switch S1_1, a fourth switch A2_1, a fifth switch B2_1, a sixth switch A3_1, a seventh switch B3_1, a first output switch B4_1, a second output switch A4_1, and a first capacitor C1_1. In practical applications, the total capacitance value of the n capacitors in the switched capacitor array 10 needs to be determined based on the accuracy and linearity of the Sigma-Delta ADC, while the size ratio of each capacitor needs to be determined according to the accuracy and linearity of the SAR ADC. For example, the required accuracy for analog-to-digital conversion is 10-bit or 16-bit. Compared to 10-bit accuracy, 16-bit accuracy requires a larger total capacitance value. Therefore, the total capacitance value of the n capacitors and the size ratio of each capacitor can be determined according to actual application requirements and are not limited here.

[0119] Specifically, input switch S1_1 is connected to the input voltage VIN at one end. First output switch B4_1 is electrically connected at one end to the other end of input switch S1_1, and at the other end is electrically connected to the non-inverting input of comparator 50 via first switch K1. First capacitor C1_1 is electrically connected at one end to the common terminal of input switch S1_1 and first output switch B4_1. Second output switch A4_1 is electrically connected at one end to modulator 60 via second switch K2, and at the other end to the other end of first capacitor C1_1. Fourth switch A2_1 is grounded at one end, and electrically connected to one end of first capacitor C1_1 at the other. Fifth switch B2_1 is connected to the first reference voltage VRP at one end, and electrically connected to the other end of first capacitor C1_1 at the other. Sixth switch A3_1 is grounded at one end, and electrically connected to the other end of first capacitor C1_1 at the other. Seventh switch B3_1 is connected to the second reference voltage VRN at one end, and electrically connected to the other end of first capacitor C1_1 at the other.

[0120] In this embodiment, input switch S1_1, fourth switch A2_1, sixth switch A3_1, and second output switch A4_1 are controlled by the first logic unit 20. Input switch S1_1, fifth switch B2_1, seventh switch B3_1, and first output switch B4_1 are controlled by the second logic unit 30.

[0121] Combination Figure 3 , Figure 3 This is a circuit diagram of the switched capacitor array 10 operating in the first analog-to-digital conversion mode. Under the control of the control unit 40, the first logic unit 20 operates, the second switch K2 and the third switch K3 are turned on, the second logic unit 30 is not operating, and the first switch K1 is turned off. When the switched capacitor array 10 operates in the first analog-to-digital conversion mode according to the first timing signal output by the first logic unit 20, the input switch S1_1, the second output switch A4_1, the fourth switch A2_1, and the sixth switch A3_1 of each group of switched capacitors 101 operate, that is, the input switch S1_1, the second output switch A4_1, the fourth switch A2_1, and the sixth switch A3_1 are turned on or off according to the first timing signal output by the first logic unit 20; the first output switch B4_1, the fifth switch B2_1, and the seventh switch B3_1 are turned off, and the switched capacitor array 10 outputs the first output voltage VON1 through the second output switch A4_1. Figure 4 As shown, Figure 4 When the switched capacitor array 10 is operating in the first analog-to-digital conversion mode, the timing signals output by the first logic unit 20 act on the input switch S1_1, the fourth switch A2_1, the sixth switch A3_1, and the second output switch A4_1.

[0122] Combination Figure 5 , Figure 5The specific circuit structure of modulator 60 is shown. Modulator 60 includes a two-stage switched capacitor integrator, specifically including a first integrator U1, a voltage conversion unit 601, a second capacitor C2, a second integrator U2, a fifth capacitor C5, a sixth capacitor C6, and eighth switches K8 to sixteenth switches K16. Specifically:

[0123] The first integrator U1 includes a non-inverting input, an inverting input, and an output. The non-inverting input of the first integrator U1 is grounded, and the inverting input is electrically connected to the switched capacitor array 10 through the second switch K2. A voltage conversion unit 601 is electrically connected between the inverting input of the first integrator U1 and the first logic unit 20. A second capacitor C2 is electrically connected between the inverting input and the output of the first integrator U1. The second integrator U2 includes a non-inverting input, an inverting input, and an output. The inverting input of the second integrator U2 is connected to the output of the first integrator U1 through the eighth switch K8, the third capacitor C3, and the ninth switch K9, which are connected in series. The common terminal of the eighth switch K8 and the third capacitor C3 is grounded through the tenth switch K10, and the common terminal of the ninth switch K9 and the third capacitor C3 is grounded through the eleventh switch K11. The non-inverting input of the second integrator U2 is grounded. The output of the second integrator U2 is electrically connected to the third switch K3 via a series-connected twelfth switch K12 and fourth capacitor C4. The common terminal of the twelfth switch K12 and fourth capacitor C4 is grounded via the thirteenth switch K13. The fifth capacitor C5 is electrically connected between the inverting input and output of the second integrator U2. The sixth capacitor C6 has one end electrically connected to the common terminal of the fourth capacitor C4 and third switch K3, and the other end electrically connected to the output of the first integrator U1 via the fourteenth switch K14. One end of the sixth capacitor C6 is also grounded via the fifteenth switch K15, and the other end is also grounded via the sixteenth switch K16. The eighth to sixteenth switches K8 are controlled by the control unit 40. By controlling the eighth to sixteenth switches K8, the charging and discharging states of the third capacitor C3, fourth capacitor C4, and sixth capacitor C6 are switched, thus changing the equivalent resistance value of the integrator. The conversion unit 601 converts the signal output by the first logic unit 20 into a feedback voltage and inputs it to the inverting input of the first integrator U1 to form a negative feedback loop.

[0124] In the first analog-to-digital conversion mode, the first output voltage VON1 output by the switched capacitor array 10 is integrated by the first integrator U1 and the second integrator U2 and then output to the non-inverting input of the comparator 50. The comparator 50 outputs the first result to the first logic unit 20 according to the calculation result so as to feed the first comparison result back to the control unit 40, thus completing the analog-to-digital conversion in the Sigma-Delta mode.

[0125] Combination Figure 6 , Figure 6This is a circuit diagram of the switched capacitor array 10 operating in the second analog-to-digital conversion mode. Under the control of the control unit 40, the first logic unit 20 is not working, the second switch K2 and the third switch K3 are open, the second logic unit 30 is working, and the first switch K1 is conducting. When the switched capacitor array 10 operates in the second analog-to-digital conversion mode according to the second timing signal output by the second logic unit 30, the second output switch A4_1, the fourth switch A2_1, and the sixth switch A3_1 of each group of switched capacitors 101 are open; the input switch S1_1, the first output switch B4_1, the fifth switch B2_1, and the seventh switch B3_1 are working, that is, the input switch S1_1, the first output switch B4_1, the fifth switch B2_1, and the seventh switch B3_1 are turned on or off according to the second timing signal output by the second logic unit 30. (Combined with...) Figure 7 As shown, Figure 7 When the switched capacitor array 10 operates in the second analog-to-digital conversion mode, the second logic unit 30 outputs timing signals acting on the input switch S1_1, the first output switch B4_1, the fifth switch B2_1, and the seventh switch B3_1. The switched capacitor array 10 outputs the second output voltage VON2 to the comparator 50 through the first output switch B4_1. The comparator 50 outputs a second comparison result based on the second output voltage VON2 to the second logic unit 30 to feed the second comparison result back to the control unit 40, thus completing the analog-to-digital conversion in SAR mode.

[0126] Example 3

[0127] Based on the advantages of the above-mentioned analog-to-digital converter in achieving high-precision and fast sampling while saving chip area, the present invention also provides a chip including the above-mentioned analog-to-digital converter. The content and effects are the same as those in the above embodiments and will not be repeated here.

[0128] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An analog-to-digital converter, characterized in that, include: A switched capacitor array is used to operate in a first analog-to-digital conversion mode or a second analog-to-digital conversion mode according to the received timing signal; The first logic unit is electrically connected to the switched capacitor array and is used to output a first timing signal to control the switched capacitor array to operate in the first analog-to-digital conversion mode. The second logic unit is electrically connected to the switched capacitor array and is used to output a second timing signal to control the switched capacitor array to operate in the second analog-to-digital conversion mode. A control unit is electrically connected to the first logic unit and the second logic unit, and is used to output control signals to control the first logic unit to output the first timing signal and to control the second logic unit to output the second timing signal. The comparator includes a non-inverting input, an inverting input, and an output. The non-inverting input is electrically connected to the output of the switched capacitor array, the inverting input is grounded, and the output is electrically connected to the first logic unit and the second logic unit to feed back the output voltage of the switched capacitor array to the control unit through the first logic unit and the second logic unit. The first switch is electrically connected between the non-inverting input terminal of the comparator and the output terminal of the switched capacitor array; The modulator includes an input terminal, an output terminal, and a feedback terminal. The input terminal of the modulator is electrically connected to the output terminal of the switched capacitor array via a second switch. The output terminal of the modulator is electrically connected to the non-inverting input terminal of the comparator via a third switch. The feedback terminal of the modulator is electrically connected to the first logic unit. The first switch, the second switch, and the third switch are controlled by the control unit.

2. The analog-to-digital converter according to claim 1, characterized in that, When the control unit controls the first logic unit to output the first timing signal, and the switched capacitor array operates in the first analog-to-digital conversion mode: The control unit controls the first switch to open and the second and third switches to open; The switched capacitor array outputs a first output voltage to the modulator; The modulator performs charge integration on the first output voltage and outputs the result to the non-inverting input of the comparator. The comparator outputs a first result to the first logic unit based on the calculation result; The first logic unit feeds back the first comparison result to the control unit.

3. The analog-to-digital converter according to claim 1, characterized in that, When the control unit controls the second logic unit to output the second timing signal, and the switched capacitor array operates in the second analog-to-digital conversion mode: The control unit controls the first switch to be turned on, and the second and third switches to be turned off; The switched capacitor array outputs a second output voltage to the non-inverting input terminal of the comparator through a first switch; The comparator outputs a second comparison result to the second logic unit based on the second output voltage; The second logic unit feeds back the second comparison result to the control unit.

4. The analog-to-digital converter according to claim 1, characterized in that, The switched capacitor array includes n groups of switched capacitors, where n ≥ 1, and each group of switched capacitors includes: An input switch, with one end connected to the input voltage; The first output switch has one end electrically connected to the other end of the input switch, and the other end electrically connected to the non-inverting input terminal of the comparator through the first switch. The first capacitor has one end electrically connected to the common terminal of the input switch and the first output switch; The second output switch has one end electrically connected to the modulator via the second switch, and the other end electrically connected to the other end of the first capacitor; The fourth switch has one end grounded and the other end electrically connected to one end of the first capacitor; The fifth switch has one end connected to the first reference voltage and the other end electrically connected to the other end of the first capacitor; The sixth switch has one end grounded and the other end electrically connected to the other end of the first capacitor; The seventh switch has one end connected to the second reference voltage and the other end electrically connected to the other end of the first capacitor.

5. The analog-to-digital converter according to claim 4, characterized in that: When the switched capacitor array operates in the first analog-to-digital conversion mode, the input switch, second output switch, fourth switch, and sixth switch of each group of switched capacitors are activated, the first output switch, fifth switch, and seventh switch are deactivated, and the switched capacitor array outputs the first output voltage through the second output switch; When the switched capacitor array operates in the second analog-to-digital conversion mode, the second output switch, the fourth switch, and the sixth switch of each group of switched capacitors are disconnected, and the input switch, the first output switch, the fifth switch, and the seventh switch are activated. The switched capacitor array outputs the second output voltage through the first output switch.

6. The analog-to-digital converter according to claim 1, characterized in that, The modulator includes: The first integrator includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal of the first integrator is grounded, and the inverting input terminal is electrically connected to the switched capacitor array through the second switch. A voltage conversion unit is electrically connected between the inverting input of the first integrator and the first logic unit; The second capacitor is electrically connected between the inverting input terminal and the output terminal of the first integrator. The second integrator includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The inverting input terminal of the second integrator is electrically connected to the output terminal of the first integrator through an eighth switch, a third capacitor, and a ninth switch connected in series. The common terminal of the eighth switch and the third capacitor is grounded through a tenth switch, and the common terminal of the ninth switch and the third capacitor is grounded through an eleventh switch. The non-inverting input terminal of the second integrator is grounded. The output terminal of the second integrator is electrically connected to the third switch through a twelfth switch and a fourth capacitor connected in series. The common terminal of the twelfth switch and the fourth capacitor is grounded through a thirteenth switch. The fifth capacitor is electrically connected between the inverting input terminal and the output terminal of the second integrator; The sixth capacitor has one end electrically connected to the common terminal of the fourth capacitor and the third switch, and the other end electrically connected to the output terminal of the first integrator through the fourteenth switch. One end of the sixth capacitor is also grounded through the fifteenth switch, and the other end of the sixth capacitor is also grounded through the sixteenth switch.

7. The analog-to-digital converter according to claim 6, characterized in that, When the switched capacitor array operates in the first analog-to-digital conversion mode: The first output voltage of the switched capacitor array is integrated by the first integrator and the second integrator and then output to the non-inverting input of the comparator. The conversion unit converts the signal output by the first logic unit into a feedback voltage and inputs it to the inverting input of the first integrator to form a negative feedback loop.

8. The analog-to-digital converter according to claim 1, characterized in that, The control unit is pre-programmed with a control program, which is used to control the first logic unit or the second logic unit to work respectively within a set time period.

9. A chip, characterized in that, Including the analog-to-digital converter as described in any one of claims 1-8.

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