Hybrid readout package for quantum multi-chip junctions

Abstract

Systems and techniques are provided that facilitate hybrid readout packages for quantum multi-chip junctions. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, readout resonators (e.g., input / output ports) of one or more qubits on the first quantum chip can be routed to an interior portion of the interposer. In various instances, the interior portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonators to the interior portion can reduce the number of crossings and / or intersections between input / output lines on the interposer and connection buses between the qubits on the interposer.

Description

BACKGROUND

[0001] The present disclosure relates to readout packaging for quantum chips, and more particularly, to hybrid readout packaging for quantum multi-chip joining.

[0002] In quantum computing, a greater quantum volume can be achieved for a given quantum computer by increasing the number of qubits on one or more quantum chips of the quantum computer. However, as the size of the quantum chip is increased to accommodate such an increased number of qubits, more qubits on the quantum chip can be encircled, which can result in overcrowding of readout lines in the area of the quantum chip.

[0003] Multi-chip joining can address this problem by decomposing the quantum chip. Quantum multi-chip joining can involve joining multiple smaller quantum chips to a large interposer, such that the entire interposer-quantum-chip module can accommodate the increased number of qubits. In various cases, quantum multi-chip joining can be viewed as joining multiple smaller than full-size quantum chips to an interposer, rather than using a full-size quantum chip that experiences readout overcrowding. In various aspects, multi-chip joining can result in better junction thickness control, can avoid box modes, and / or can facilitate higher yield.

[0004] However, quantum multi-chip joining has its own challenges. Conventional quantum multi-chip joining requires cross-chip resonators (e.g., connection buses) on (e.g., at least partially on) the interposer that couple the various quantum chips together, and involves routing all readout lines of the quantum chips to a peripheral portion (e.g., a peripheral and / or edge region) of the interposer. When a large interposer is used, readout lines of qubits located near the center of the interposer can conflict (e.g., cross, intersect) with these cross-chip resonators, which can be undesirable.

[0005] Accordingly, there is a need for a solution for quantum multi-chip joining that can address (e.g., reduce) the problem of readout lines conflicting with cross-chip resonators. SUMMARY

[0006] The following summary is provided to give a basic understanding of one or more embodiments of the application. This summary is not intended to identify key or critical elements, or delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to introduce, in brief, a selection of concepts that are represented more fully below in the detailed description section. In one or more embodiments described herein, apparatuses, systems, computer- implemented methods, devices, and / or computer program products that facilitate hybrid readout packaging for quantum multi-chip joining are described.

[0007] According to one or more embodiments, an apparatus is provided. The apparatus can include an interposer having a first quantum chip and a second quantum chip. In various aspects, the apparatus can further include a readout resonator of the first quantum chip. In various cases, the readout resonator can be routed to an interior portion of the interposer. In various embodiments, the interior portion can be located between the first quantum chip and the second quantum chip. In various embodiments, the apparatus can further include at least two connection buses coupling the first quantum chip and the second quantum chip. In some cases, the at least two connection buses can be located on the interior portion. In various aspects, the readout resonator can be located between the at least two connection buses. In various embodiments, the readout resonator can be coupled to a printed circuit board by an electrical conductor that is skewed with respect to the at least two connection buses. In various embodiments, the apparatus can further include a second readout resonator of the first quantum chip. In some cases, the second readout resonator can be located on a peripheral portion of the interposer that surrounds the first quantum chip and the second quantum chip.

[0008] According to one or more embodiments, a method of manufacturing the above apparatus is provided.

[0009] According to one or more embodiments, an apparatus is provided. The apparatus can include a substrate. In some cases, the substrate can have one or more qubit chips. In various aspects, the apparatus can further include one or more resonators coupled to qubits of the one or more qubit chips. In various cases, the one or more resonators can be routed to one or more interior regions of the substrate. In some cases, the one or more interior regions can be positioned between one or more pairs of adjacent chips of the one or more qubit chips. In various embodiments, the one or more pairs of adjacent chips of the one or more qubit chips can be coupled together by a plurality of buses positioned on the one or more interior regions. In various cases, the one or more resonators can be positioned between the buses. In various embodiments, the one or more resonators can be coupled to a printed circuit board by one or more conductors that are skewed with respect to the buses.

[0010] According to one or more embodiments, a method of manufacturing the above apparatus is provided.

[0011] According to one or more embodiments, an interposer is provided. In various aspects, the interposer can include a quantum chip. In various cases, the interposer can further include quantum input / output (I / O) ports. In various cases, the quantum I / O ports can be routed between adjacent pairs of quantum chips. In various embodiments, the interposer can further include cross-chip lines connecting the adjacent pairs of quantum chips. In various cases, the cross-chip lines can be located between the adjacent pairs of quantum chips. In various aspects, the quantum I / O ports can be located between the cross-chip lines. In various embodiments, a printed circuit board can be coupled to the quantum I / O ports with a plurality of pins that are skewed relative to the cross-chip lines.

[0012] As noted above, quantum multi-chip junctions include interposers with quantum chips joined thereto, where the quantum chips are coupled together through cross-chip resonators (e.g., connection buses that extend along and / or at least partially along the plane of the interposer and couple together qubits of two or more quantum chips). Conventional quantum multi-chip junctions route / wire all readout resonators (e.g., input / output ports) of the quantum chips to the peripheral portions of the interposers to facilitate wire bonding and / or bump bonding of the readout resonators to printed circuit boards (e.g., joining and / or routing the readout resonators close to the edges of the interposers so that they can be easily coupled to printed circuit boards). Conventionally, even readout resonators of quantum bits that are located centrally (e.g., quantum bits that are located near the center and / or interior of the interposer topology rather than near the periphery and / or edges of the interposer topology) are routed and / or wired to the peripheral portions of the interposers. This can cause the readout lines (e.g., readout lines that couple quantum bits on the quantum chips to their readout resonators / ports) to be crowded, cross, intersect, and / or otherwise interfere with the cross-chip resonators. For example, it is often the case that any routing path from a given centrally located quantum bit to the peripheral portions of the interposer is blocked by one or more cross-chip resonators, such that wiring of a readout line from the given centrally located quantum bit to the peripheral portions of the interposer requires the readout line to cross, intersect, and / or otherwise interfere with the one or more blocking cross-chip resonators. Such crowding, crossing, and / or intersecting can be undesirable (e.g., can make it more difficult to provide correct inputs to and / or read correct outputs from the quantum bits on the quantum chips).

[0013] Various embodiments of the present invention can address these issues in the prior art. In various aspects, embodiments of the present invention can provide hybrid readout packages for quantum multi-chip junctions. In various cases, a hybrid readout package for quantum multi-chip junctions can include an interposer having a plurality of quantum chips coupled thereto, each quantum chip having one or more qubits. In various aspects, pairs of adjacent quantum chips can be coupled together via a connection bus (e.g., a cross-chip resonator) that extends along (e.g., at least partially along) a plane of the interposer. In various cases, qubits that are located at a periphery (e.g., qubits that are positioned near a periphery and / or edge of the interposer, such that they have an unobstructed routing path to the periphery and / or edge of the interposer) can have readout resonators (e.g., input / output ports) that are routed / wired to a peripheral portion of the interposer. In various aspects, qubits that are located at a center (e.g., qubits that are positioned away from a periphery / edge of the interposer, such that they do not have an unobstructed routing path to the periphery and / or edge of the interposer) can have readout resonators that are routed / wired to inner portions of the interposer. In various cases, the inner portions of the interposer can be defined as those regions of the interposer that are substantially between pairs of adjacent quantum chips. By positioning at least some readout resonators on these inner portions, readout lines (e.g., input / output lines) associated with these readout resonators can be wired / routed to the inner portions of the interposer rather than to the peripheral portions of the interposer. As noted above, it is often the case that any routing path from a given center-located qubit to a peripheral portion of the interposer is obstructed by one or more cross-chip resonators. However, in various aspects, there can be instances where one or more paths from a given center-located qubit to a corresponding inner portion (e.g., an inner portion of the interposer that is between the quantum chip on which the given center-located qubit is located and an adjacent quantum chip) are not obstructed by one or more connection buses. Thus, in various aspects, wiring / routing at least some readout resonators to these inner portions (e.g., placing at least some input / output ports on these inner portions) can reduce the amount of crosstalk required to implement a quantum multi-chip junction as compared to wiring all readout resonators to peripheral portions of the interposer. In various aspects, the amount of crosstalk that is reduced and / or eliminated by various embodiments of the present invention can be significant, and can increase as the number of quantum chips on the interposer increases. In various aspects, wiring at least some readout resonators to these inner portions can reduce the amount of wiring material required to implement a quantum multi-chip junction (e.g., a given center-located qubit can be physically closer to an associated inner portion between the quantum chip on which it is located and an adjacent quantum chip than to a peripheral portion of the interposer, such that wiring a readout line to the associated inner portion requires less wiring material than wiring a readout line to a peripheral portion).

[0014] In various cases, the quantum chip can be bonded (e.g., bump bonded) to the interposer. In various aspects, the quantum chip can have some qubits on it that are peripherally located and can have some qubits on it that are centrally located. In various aspects, the peripherally located qubits can be seated on the quantum chip such that they are oriented toward and / or have unobstructed routing / wiring paths to peripheral portions of the interposer. That is, in various cases, there can be routing / wiring paths from the peripherally located qubits on the quantum chip to the peripheral portions of the interposer that do not cross one or more connection buses. In various aspects, the centrally located qubits can be seated on the quantum chip such that they are oriented away from and / or do not have unobstructed routing / wiring paths to the peripheral portions of the interposer. That is, in various cases, all routing / wiring paths from the centrally located qubits on the quantum chip to the peripheral portions of the interposer can include crossing one or more connection buses. Thus, in some instances, it can be beneficial to route and / or wire the readout resonators of those centrally located qubits onto the associated interior portions of the interposer (e.g., place and / or position the input / output ports of those centrally located qubits on the associated interior portions of the interposer), thereby avoiding the need for such crossings.

[0015] In various cases, the quantum chip can be bonded (e.g., bump bonded) to the interposer. In various cases, resonators (e.g., buses) can be patterned on the quantum chip and the interposer by lithography prior to bonding, continuous paths from the qubits on the quantum chip to their readout ports can be formed after the quantum chip is bonded to the interposer. In various aspects, further connections of these readout ports to the outside world can be provided as needed.

[0016] Various embodiments of the present invention can provide hybrid readout packages for quantum multichip junctions that can include routing, connections, and / or wiring to one or more readout resonators (e.g., input / output ports) of a peripheral portion of an interposer as well as routing, connections, and / or wiring to one or more readout resonators (e.g., input / output ports) of one or more internal portions of the interposer. In various cases, such quantum multichip junction structures can provide one or more of the following benefits and / or technical improvements. In various cases, such hybrid readout packages can be interposer-quantum chip structures that exhibit less readout congestion (e.g., lower input / output port density at the periphery of the interposer and / or lower input / output line density on the interposer) as compared to conventional quantum multichip junctions. In various cases, such hybrid readout packages can be interposer-quantum chip structures that exhibit less crossing, intersection, and / or interference between readout lines and cross-chip resonators (e.g., less instances of input / output lines on the interposer conflicting with interposer layer on quantum bit interconnect buses) as compared to conventional quantum multichip junctions. In various cases, such hybrid readout packages can be interposer-quantum chip structures that provide better chip real estate, reduce overall congestion in chip designs, and / or reduce the number of crossings required to implement a multichip junction design. In various aspects, such benefits can scale with the number of quantum chips implemented on the interposer. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A block diagram illustrating an example, non-limiting quantum multichip junction device that facilitates hybrid readout packages for quantum multichip junctions in accordance with one or more embodiments described herein is shown.

[0018] Figure 2 A flow diagram illustrating an example, non-limiting method of fabricating a quantum multichip junction device that facilitates hybrid readout packages for quantum multichip junctions in accordance with one or more embodiments described herein is shown.

[0019] Figure 3 A block diagram illustrating an example, non-limiting interposer that facilitates hybrid readout packages for quantum multichip junctions in accordance with one or more embodiments described herein is shown.

[0020] Figure 4 A block diagram illustrating an example, non-limiting quantum multichip junction device that facilitates hybrid readout packages for quantum multichip junctions including pogo pins in accordance with one or more embodiments described herein is shown.

[0021] Figure 5A block diagram of an example, non-limiting quantum multi-chip-joined device facilitating a hybrid readout package for quantum multi-chip-joining is shown, in accordance with one or more embodiments described herein.

[0022] Figure 6 A block diagram of an example, non-limiting quantum multi-chip-joined device facilitating a hybrid readout package for quantum multi-chip-joining is shown, in accordance with one or more embodiments described herein.

[0023] Figure 7 A block diagram of an example, non-limiting quantum multi-chip-joined device facilitating a hybrid readout package for quantum multi-chip-joining is shown, in accordance with one or more embodiments described herein.

[0024] Figures 8 to 10 A flow diagram of an example, non-limiting method of fabricating a quantum multi-chip-joined device facilitating a hybrid readout package for quantum multi-chip-joining is shown, in accordance with one or more embodiments described herein.

[0025] Figures 11 to 12 A flow diagram of an example, non-limiting method of fabricating a quantum multi-chip-joined device facilitating a hybrid readout package for quantum multi-chip-joining is shown, in accordance with one or more embodiments described herein.

[0026] Figure 13 A block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated is shown. DETAILED DESCRIPTION

[0027] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments and / or the application or use of embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Background, Summary or Abstract sections, or the Detailed Description section.

[0028] One or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It is evident, however, that one or more embodiments can be practiced without these specific details.

[0029] Improvements in the processing power of quantum computers (e.g., increased quantum volume) can be facilitated by increasing the number of qubits on one or more quantum chips of a given quantum computing system. However, as noted above, this can result in the size of the quantum chip increasing such that more qubits on the quantum chip are fenced in by other qubits. The result can be that readout lines on the quantum chip become overcrowded.

[0030] Quantum multi-chip interconnects can improve this problem. As described above, quantum multi-chip interconnects involve connecting multiple quantum chips (e.g., smaller than full-size quantum chips) to a large internal plug (e.g., a substrate that may be supported by a handle and / or reinforcement) and coupling the quantum chips together via one or more interconnect buses (e.g., cross-chip resonators).

[0031] As mentioned above, quantum multi-chip interconnects may face their own challenges. Specifically, traditional quantum multi-chip interconnects involve routing all the readout lines (e.g., input / output lines) of the quantum chip to the peripheral portions (e.g., edges, peripheries, off-center, and / or non-internal regions) of the inner module. This often requires the quantum chip's readout lines to be crowded, crossed, intersected, and / or otherwise interfere with the cross-chip resonators, making it difficult to perform quantum readouts correctly.

[0032] Various embodiments of the present invention can reduce the number of such crosses in quantum multi-chip interconnects. Specifically, various embodiments of the present invention can provide hybrid readout packages for quantum multi-chip interconnects (e.g., in-plug-in quantum chip structures) that require fewer crosses between readout lines and cross-chip resonators compared to conventional quantum multi-chip interconnects, thereby providing improved performance.

[0033] In various aspects, hybrid readout packages for quantum multi-chip interconnection may include an inner module to which quantum chips are coupled, wherein adjacent quantum chips may be coupled together via one or more interconnect buses (e.g., cross-chip resonators). For simplicity and ease of explanation, embodiments of an inner module comprising an array of rectangular quantum chips are explicitly discussed and illustrated in this disclosure. However, it should be appreciated that in various embodiments, the quantum chips may be arranged on the inner module in any suitable shape, pattern, and / or manner.

[0034] In various instances, the interposer can have quantum chips located at a periphery and quantum chips located at a center. In various aspects, the quantum chips located at the periphery can be quantum chips that are adjacent to a peripheral portion of the interposer and / or are not separated from the peripheral portion of the interposer by one or more other quantum chips. In various aspects, the quantum chips located at the center can be quantum chips that are not adjacent to a peripheral portion of the interposer and / or are separated from the peripheral portion of the interposer by one or more other quantum chips. For example, consider a 5x6 array of quantum chips coupled to an interposer (e.g., a total of 30 quantum chips). In various aspects, the 18 quantum chips that make up the perimeter of the 5x6 array can be considered to be quantum chips located at the periphery because, for each of these 18 quantum chips, there are no other quantum chips between it and the peripheral portion of the interposer. In various aspects, the 12 quantum chips in the interior of the 5x6 array can be considered to be quantum chips located at the center because, for each of these 12 quantum chips, there is at least one other quantum chip between it and the peripheral portion of the interposer.

[0035] In various instances, adjacent quantum chips on the interposer can be coupled together by one or more connection buses (e.g., also referred to as cross-chip resonators). In various instances, the one or more connection buses can be located on and / or at least partially located on the interposer (e.g., can extend on and / or at least partially on a plane of the interposer) and can couple pairs of adjacent quantum chips together (e.g., can couple qubits on one quantum chip to qubits on an adjacent quantum chip). For example, consider the above example of an interposer with a 5x6 array of quantum chips. In various instances, each of the twelve quantum chips located at the center can be connected to four (and / or fewer) quantum chips because each of these twelve quantum chips is adjacent to four other quantum chips. In various instances, the four quantum chips that make up the corners of the 5x6 array (e.g., four of the 18 quantum chips located at the periphery) can be coupled to two (and / or fewer) quantum chips because each of these four corner quantum chips is adjacent to two other quantum chips. In various instances, the remaining fourteen quantum chips located at the periphery can be coupled to three (and / or fewer) quantum chips because each of these fourteen quantum chips located at the periphery is adjacent to three other quantum chips. In various embodiments, any suitable quantum chip on the interposer can be coupled to any other suitable quantum chip on the interposer in any suitable number (e.g., in some instances, a quantum chip can be coupled to more than four other quantum chips; in some instances, non-adjacent quantum chips can be coupled together).

[0036] In various examples, each quantum chip can have one or more qubits, where each qubit is associated with or corresponds to a readout resonator (e.g., an input / output port that provides input to and / or receives output from the qubit) that is coupled to the interposer. For example, in some cases, a first quantum chip on the interposer can have 29 qubits. In various aspects, each of the 29 qubits can have a corresponding readout resonator (e.g., input / output port) that is coupled to the interposer, for a total of 29 readout resonators (e.g., 29 input / output ports) corresponding to the first quantum chip. In some cases, a second quantum chip on the interposer can have 13 qubits. In various examples, each of the 13 qubits can have a corresponding readout resonator (e.g., input / output port) that is coupled to the interposer, for a total of 13 readout resonators (e.g., 13 input / output ports) corresponding to the second quantum chip. In various aspects, each qubit can be coupled to its corresponding readout resonator by a readout line (e.g., input / output line). In various cases, each readout line can be located on the interposer (e.g., can extend on the plane of the interposer). As described above, various embodiments of the present disclosure can reduce the number of crossings and / or interference between these readout lines and the connection bus compared to conventional quantum multi-chip coupling.

[0037] In some examples, input (e.g., drive) to a qubit and output (e.g., readout) from a qubit can be combined in a single line and routed / wired to the same port on the interposer. In other examples, input (e.g., drive) to a qubit and output (e.g., readout) from a qubit can be on different lines and thus can be routed / wired to different ports on the interposer. In various examples, readout of two or more qubits can be combined and routed / wired to a single port on the interposer (e.g., one readout port on the interposer chip can be connected to more than one qubit through multiplexing).

[0038] In various aspects, the interposer can have a peripheral portion and one or more interior portions. In various cases, the peripheral portion can be the area of the interposer that surrounds and / or encircles the edges, periphery, and / or non-interior regions of the quantum chips on the interposer. In various cases, the one or more interior portions can be those regions of the interposer that are between pairs of adjacent quantum chips. Consider the above example of an interposer having a 5x6 array of quantum chips. In some cases, the peripheral portion can be the area of the interposer that substantially surrounds the edges and / or periphery of the 5x6 array of quantum chips (e.g., a rectangular ring of the interposer). In some cases, the 5x6 array of quantum chips can define 49 interior portions of the interposer (e.g., the interposer can have 49 regions that are physically between and / or sandwiched between two adjacent quantum chips in the 5x6 array of quantum chips).

[0039] In various embodiments, readout resonators corresponding to on-center quantum chips can be routed / wired to one or more interior portions of the interposer (e.g., input / output ports of on-center quantum chips can be placed, disposed, positioned, and / or joined at one or more interior portions of the interposer) rather than to peripheral portions. This can reduce the number of crossings needed to couple quantum bits of on-center quantum chips to their corresponding readout resonators. For example, consider the 5x6 quantum chip array in the example above. In particular, consider a first quantum chip at position (2, 3) (e.g., second row from the top, third column from the left) in the 5x6 array and a second quantum chip at position (2, 4) in the 5x6 array. Assume that the first and second quantum chips are coupled by one or more connection buses. The first and second quantum chips are on-center and adjacent to one another. In various aspects, there can be an interior portion of the interposer that is physically between the first and second quantum chips (e.g., a surface of the interposer that is physically bounded in one direction by position (2, 3) and position (2, 4) and in an orthogonal direction by the width of the first and second quantum chips). In various aspects, the readout resonators of the first quantum chip can be routed and / or wired to this interior portion of the interposer (e.g., input / output ports of the first quantum chip can be placed between the first and second quantum chips). Because the path from the first quantum chip to the interior portion can be unobstructed (e.g., the first quantum chip is directly adjacent to the interior portion and there are no other quantum chips between the first quantum chip and the interior portion), the first quantum chip can be coupled to the readout resonators without crossing the connection bus that couples the first and second quantum chips and without crossing any other connection buses on the interposer. In contrast, a conventional alternative would be to wire / route the readout resonators of the first quantum chip to a peripheral portion of the interposer. However, this can require crossing the connection bus that couples the first and second quantum chips and crossing other connection buses that couple other quantum chips together on the interposer. After all, because the first quantum chip is on-center, the readout lines from the first quantum chip to the peripheral portion will have to cross connection buses of quantum bits in higher-numbered and / or lower-numbered rows and / or higher-numbered and / or lower-numbered columns (e.g., to get from position (2, 3) to the peripheral portion, one would have to traverse a row of quantum chips above position (2, 3), or three rows of quantum chips below position (2, 3), or two columns of quantum chips to the left of position (2, 3), or three columns of quantum chips to the right of position (2, 3)). By wiring / routing the readout resonators to these interior portions of the interposer, the number of crossings between the readout lines and the connection buses can be reduced.Reducing the number of crossings constitutes a technical improvement over conventional quantum multi-chip linkages because crossings, intersections, and / or interference of readout lines with connection buses can make effective qubit readout difficult and / or challenging.

[0040] In various aspects, some readout resonators of quantum chips located at the periphery can be routed / wired to a peripheral portion of the interposer (e.g., some qubits of quantum chips located at the periphery can have unobstructed paths to the peripheral portion; such qubits can be referred to as peripheral qubits, and in such cases, it can be acceptable to route / wire the readout resonators of these peripheral qubits to the peripheral portion of the interposer). In various aspects, some readout resonators of quantum chips located at the periphery can be routed / wired to one or more interior portions (e.g., some qubits of quantum chips located at the periphery can be facing away from the peripheral portion such that they do not have unobstructed paths to the peripheral portion; such qubits can be referred to as central qubits, and in such cases, the readout resonators of these central qubits can be routed / wired to appropriate interior portions of the interposer). In various aspects, a quantum chip located at the center can have only central qubits (e.g., qubits that do not have unobstructed paths to the peripheral portion of the interposer). In various aspects, a quantum chip located at the periphery can have both central qubits (e.g., qubits that do not have unobstructed paths to the peripheral portion of the interposer) and peripheral qubits (e.g., qubits that have unobstructed paths to the peripheral portion of the interposer).

[0041] In various embodiments, readout resonators on the interposer can be coupled to a printed circuit board (e.g., to electrodes of a printed circuit board) by any suitable electrical coupling technique (e.g., wire bonding and / or bump bonding). In various aspects, readout resonators of central qubits can be coupled to a printed circuit board by electrical conductors that are skewed relative to connection buses on the interposer (e.g., the electrical conductors can be substantially orthogonal to the interposer and / or can extend out of and / or away from the interposer so as to not intersect any connection buses). In various cases, the electrical conductors can be pogo pins, land grid arrays, through-silicon vias, and / or any other suitable electrical conductors and / or combinations of electrical conductors.

[0042] Various embodiments of the present invention include a new novel physical structure of a quantum multi-chip junction module that is not an abstract idea, not a natural phenomenon, not a law of nature, and cannot be performed by a human as a series of intellectual activity acts. Rather, various embodiments of the present invention include a physical design of a quantum multi-chip junction module that provides improved quantum readout by reducing the number of crossings and / or intersections between quantum readout lines (e.g., input / output lines) and quantum connection buses (e.g., cross-chip resonators) as compared to conventional quantum multi-chip junctions. Since such crossings can degrade the performance of quantum readout, chip designs that eliminate and / or reduce such crossings can improve the functionality of quantum computing systems (e.g., improve the performance and / or accuracy of quantum readout), thereby constituting a specific technical improvement over the prior art. Various embodiments of the present invention can achieve this technical improvement by providing a hybrid readout package for performing quantum multi-chip junctions. In various aspects, the readout resonators of quantum bits located at the center can be positioned at and / or routed / wired to one or more interior portions on the interposer. The interior portions can be defined as those regions of the surface of the interposer that are physically between adjacent quantum chips. Since there can be an unobstructed path from a quantum bit located at the center to at least one of these interior portions, coupling the quantum bit to its readout resonator at one of these interior portions does not require crossing and / or intersecting any connection buses on the interposer. Rather, conventional quantum multi-chip junctions require positioning all readout resonators at and / or wiring / routing to the peripheral portions of the interposer. In some cases, there is no unobstructed path from at least one quantum bit located at the center to the peripheral portions. In such cases, wiring all readout lines to the peripheral portions can require a greater number of crossings, which can be undesirable. Thus, embodiments of the present invention provide a novel hybrid readout package for performing quantum multi-chip junctions that improves the functionality of quantum computing systems, thereby constituting a specific technical improvement over the prior art.

[0043] In various aspects, it should be understood that the drawings of the present disclosure are merely illustrative and not restrictive, and are not necessarily drawn to scale.

[0044] Figure 1 A block diagram of an example, non-limiting quantum multi-chip junction device 100 that can facilitate a hybrid readout package for performing quantum multi-chip junctions in accordance with one or more embodiments described herein is shown. As shown, an interposer 102 can have a first quantum chip 104 that is junctioned to the interposer 102 and a second quantum chip 106 that is junctioned to the interposer 102. In various examples, the first quantum chip 104 and the second quantum chip 106 can be bump-junctioned to the interposer 102. In various aspects, any other suitable junctioning technique can be implemented.

[0045] As shown, in various cases, the first quantum chip 104 can include one or more qubits (e.g., qubits Q1-Q13), and, in various aspects, the second quantum chip 106 can include one or more qubits (e.g., qubits Q14-Q26). In various examples, any suitable type and / or any suitable number of qubits can be on the first quantum chip 104, and any suitable type and / or any suitable number of qubits can be on the second quantum chip 106. In various examples, the qubits Q1-Q13 can be arranged in any suitable pattern, shape, and / or manner on the first quantum chip 104. In various cases, the qubits Q14-Q26 can be arranged in any suitable pattern, shape, and / or manner on the second quantum chip 106.

[0046] In various examples, the first quantum chip 104 can be communicatively coupled to the second quantum chip 106 by one or more connection buses 108 (e.g., which can be cross-chip resonators). In the illustrated, non-limiting example, there are two connection buses 108 that couple the first quantum chip 104 to the second quantum chip 106 (e.g., a first connection bus 108 couples Q12 to Q17, and a second connection bus 108 couples Q10 to Q15). In various examples, any suitable type and / or any suitable number of connection buses 108 can couple the first quantum chip 104 to the second quantum chip 106. As shown, a portion of the one or more connection buses 108 can extend along a surface of the interposer 102. In various embodiments, the one or more connection buses 108 can include any suitable material for communicatively and / or electrically coupling qubits and / or quantum chips.

[0047] In various examples, the qubits Q1-Q13 of the first quantum chip 104 can be communicatively coupled to one another by one or more inter-qubit connectors 110 in any suitable arrangement. Similarly, the qubits Q14-Q26 of the second quantum chip 106 can be communicatively coupled to one another by one or more inter-qubit connectors 110 in any suitable arrangement. In various aspects, the one or more inter-qubit connectors 110 can include any suitable material for electrically and / or communicatively coupling qubits. As shown, in various examples, the one or more inter-qubit connectors 110 can extend along a surface of the first quantum chip 104 and the second quantum chip 106, rather than on a surface of the interposer 102.

[0048] In various instances, each of the qubits Q1-Q13 of the first quantum chip 104 can have an associated and / or corresponding readout resonator 114 (e.g., which can be an input / output port for providing input to and / or receiving output from each qubit). Similarly, each of the qubits Q14-Q26 of the second quantum chip 106 can have an associated and / or corresponding readout resonator 114 (e.g., input / output port). In various embodiments, the one or more readout resonators 114 can comprise any suitable material that facilitates providing and / or receiving quantum input and output. In various aspects, each of the qubits Q1-Q26 can have a corresponding readout resonator 114. In various aspects, each of the qubits Q1-Q26 can have any suitable number and / or any suitable type of readout resonator 114.

[0049] In various cases, each of the qubits Q1-Q26 can be coupled to its corresponding readout resonator 114 by a readout line 112 (e.g., which can be an input / output line). In various aspects, the readout line 112 can comprise any suitable material for communicatively and / or electrically coupling a qubit to a readout resonator. As shown, in various cases, the readout line 112 can have a portion that extends along a surface of the first quantum chip 104 and the second quantum chip 106, and a portion that extends along a surface of the interposer 102.

[0050] As noted above, conventional quantum multi-chip bonding involves routing / wiring all of the readout resonators 114 to a peripheral portion 116 of the interposer 102 (e.g., the peripheral portion 116 is a surface area of the interposer 102 that belongs to and / or is proximate to an edge and / or periphery of the interposer 102 Figure 1 As shown, the peripheral portion 116 can be a physical area and / or portion of the surface area of the interposer 102 that belongs to and / or is proximate to an edge and / or periphery of the interposer 102. In various aspects, the interposer 102 can comprise any suitable shape (e.g., a rectangular chip, a circular chip, a triangular chip, and / or any other suitable shaped chip). In various aspects, the peripheral portion 116 can be an annular surface area that corresponds to the shape of the interposer 102 (e.g., a rectangular annulus for a rectangular interposer 102, a circular annulus for a circular interposer 102, a triangular annulus for a triangular interposer 102).

[0051] As shown, some of the readout resonators 114 can be routed / wired to the peripheral portion 116 of the interposer 102 (e.g., some of the readout resonators 114 can be located, positioned, situate, and / or be joined on the peripheral portion 116). Thus, the readout lines 112 of these readout resonators 114 can be routed to the peripheral portion 116 in order to couple these readout resonators 114 to their corresponding qubits. As shown, this can not be a problem for qubits that are facing the peripheral portion 116 and / or for other qubits that have an unobstructed path to the peripheral portion 116 (e.g., for peripheral qubits). For example, qubits Ql, Q2, Q3, Q4, Q8, Q9, and Q13 of the first quantum chip 104 are all facing the peripheral portion 116 and have an unobstructed path to the peripheral portion 116 (e.g., the readout lines 112 from qubits Ql, Q2, Q3, Q4, Q8, Q9, and Q13 can be routed to the peripheral portion 116 without having to cross the connection bus 108 and / or the inter-qubit connectors 110). Similarly, qubits Q14, Q18, Q19, Q23, Q24, Q25, and Q26 of the second quantum chip 106 are all facing the peripheral portion 116 and have an unobstructed path to the peripheral portion 116 (e.g., the readout lines 112 from qubits Q14, Q18, Q19, Q23, Q24, Q25, and Q26 can be routed to the peripheral portion 116 without having to cross the connection bus 108 and / or the inter-qubit connectors 110). In various cases, qubits Ql, Q2, Q3, Q4, Q8, Q9, Q13, Q14, Q18, Q19, Q23, Q24, Q25, and Q26 can be considered peripheral qubits. However, qubits Q6 and Ql l of the first quantum chip 104 and qubits Q16 and Q21 of the second quantum chip 106 do not have such unobstructed paths to the peripheral portion 116 (e.g., they can be considered central qubits). Thus, the readout lines 112 from qubits Q6, Ql l, Q16, and Q21 all have to cross, intersect, and / or otherwise interfere with at least one connection bus 108 and / or at least one inter-qubit connector 110 in order to be routed to the peripheral portion 116.

[0052] In particular, consider qubit Ql l of the first quantum chip 104 and qubit Q16 of the second quantum chip 106. As shown by the dashed reference number 118, in order to wire / route the readout resonator 114 of qubit Ql l to the peripheral portion 116, the readout line of qubit Ql l has to cross at least one connection bus 108 (e.g., the readout line 112 of qubit Ql l has to cross the connection bus 108 between the first quantum chip 104 and the second quantum chip 106). Similarly, in order to wire / route the readout resonator 114 of qubit Q16 to the peripheral portion 116, the readout line of qubit Q16 has to cross at least one connection bus 108 (e.g., the readout line 112 of qubit Q16 has to cross the connection bus 108 between the first quantum chip 104 and the second quantum chip 106). Figure 1with at least one inter-quantum bit connector 110. Similarly, as shown by dashed reference number 120, if the readout resonator 114 of quantum bit Q16 is to be routed to the peripheral portion 116, then the readout line of quantum bit Q16 has to cross at least one connection bus 108 or cross at least one inter-quantum bit connector 110 (e.g., Figure 1 with at least one inter-quantum bit connector 110. Similarly, as shown by dashed reference number 120, if the readout resonator 114 of quantum bit Q16 is to be routed to the peripheral portion 116, then the readout line of quantum bit Q16 has to cross at least one connection bus 108 or cross at least one inter-quantum bit connector 110 (e.g.,

[0053] As shown, in various embodiments, some of the readout resonators 114 can be routed to an interior portion 126 of the interposer 102. In various aspects, the interior portion 126 can be a region and / or surface area of the interposer 102 that is physically between and / or sandwiched between the first quantum chip 104 and the second quantum chip 106. As shown, the readout resonator 114 of quantum bit Q11 (e.g., denoted as readout resonator 128) can be located / positioned on the interior portion 126. As shown, the readout line 112 of quantum bit Q11 (e.g., denoted as readout line 130) can be routed so as to couple quantum bit Q11 to the readout resonator 128. Similarly, as shown, the readout resonator 114 of quantum bit Q16 (e.g., denoted as readout resonator 132) can be located / positioned on the interior portion 126. As shown, the readout line 112 of quantum bit Q16 (e.g., denoted as readout line 134) can be routed so as to couple quantum bit Q16 to the readout resonator 132.

[0054] As explained above, routing / wiring the readout of qubit Q11 to the peripheral portion 116 (e.g., indicated by dashed reference numeral 118) would cause the readout line of qubit Q11 to cross at least one of the connection buses 108 (e.g., indicated by reference numeral 122). Similarly, routing / wiring the readout of qubit Q16 to the peripheral portion 116 (e.g., indicated by dashed reference numeral 120) would cause the readout line of qubit Q16 to cross and / or be congested with at least one inter-qubit connector 110 (e.g., indicated by reference numeral 124). However, as shown, by wiring / routing the readout resonators 128 and 132 to the internal portion 126, the crossovers shown by reference numerals 122 and 124 can be eliminated and / or avoided. In fact, as shown, readout line 130 can avoid crossing with connection bus 108 and / or inter-qubit connector 110, and readout line 134 can similarly avoid crossing with connection bus 108 and / or inter-qubit connector 110. This is achievable because qubits Q11 and Q16 can have unobstructed paths to the internal portion 126 (e.g., paths not blocked by at least one connection bus 108 and / or at least one inter-qubit connector 110) and may lack unobstructed paths to the peripheral portion 116. Therefore, in various aspects, wiring and / or routing at least one readout resonator 114 of the first quantum chip 104 and / or the second quantum chip 106 to the internal portion 126 can help reduce the number of crossovers required for quantum multi-chip interconnection. Since crossovers can be detrimental to the accuracy of quantum inputs / outputs, a chip design with a reduced number of crossovers can improve the performance of the quantum computing system, thereby constituting a specific technical improvement relative to the prior art.

[0055] In various embodiments, as shown, at least two connection buses 108 can couple the first quantum chip 104 to the second quantum chip 106. In various aspects, the at least two connection buses 108 may be located on the internal portion 126 of the inner plug-in 102. In various cases, the readout resonator 128 and / or the readout resonator 132 may be located / positioned / connected to the internal portion 126 of the inner plug-in 102 such that the readout resonator 128 and / or the readout resonator 132 are located / positioned between the at least two connection buses 108.

[0056] In various embodiments, the readout resonator 128 and / or the readout resonator 132 can be connected via an electrical conductor (to be discussed later). Figures 4-6 (As shown in the diagram) coupled to a printed circuit board (e.g., one or more electrodes coupled to a printed circuit board). In various aspects, the electrical conductors may be skewed relative to the at least two connection buses 108 (e.g., not parallel and not intersecting). In various aspects, the electrical conductors may extend out of and / or away from the inner plug-in 102 (e.g., may extend out of...). Figure 1to the interposer 102. In some aspects, the electrical conductors can be routed and / or wired such that the electrical conductors are substantially orthogonal and / or perpendicular to the interposer 102.

[0057] In various aspects, the readout resonators 114 can be routed and / or wired to the peripheral portion 116 or the interior portion 126 in order to minimize the number of crossings between the readout lines 112 and the connection bus 108 and / or between the readout lines 112 and the inter-qubit connectors 110. For example, some of the readout resonators 114 can be routed and / or wired to the peripheral portion 116 (e.g., readout resonators 114 of qubits located at the periphery that have unobstructed paths to the peripheral portion 116, and / or readout resonators 114 of qubits that do not have paths to the interior portion 126 that involve fewer crossings). Thus, in various cases, the hybrid readout package for quantum multi-chip interfacing can include routing some of the readout resonators 114 to the peripheral portion 116, and can include routing other readout resonators 114 to the interior portion 126 in order to reduce the number of crossings between the readout lines 112 and the connection bus 108 and / or between the readout lines 112 and the inter-qubit connectors 110. Moreover, such a design can also reduce the density of the readout resonators 114 on the peripheral portion 116. In contrast, conventional quantum multi-chip interfacing includes wiring all of the readout resonators 114 to the peripheral portion 116, which can result in a greater number of undesirable crossings between the readout lines 112 and the connection bus 108 and / or between the readout lines 112 and the inter-qubit connectors 110, and can result in overcrowding and / or increased density of the readout resonators 114 on the peripheral portion 116. In various aspects, the disclosed hybrid readout package for quantum multi-chip interfacing can facilitate benefits and / or technical improvements that are proportional to the number of quantum chips. For example, the number of crossings in conventional designs increases rapidly with the number of quantum chips on the interposer (e.g., more quantum chips are encircled and / or centrally located on the interposer), which can mean that implementing the hybrid readout package on an interposer with a large number of quantum chips can eliminate / avoid an increasing number of crossings.

[0058] Figure 2A flowchart of an example, non-limiting method 200 that can facilitate a quantum multichip-joined hybrid readout package for quantum multichip joining is shown in accordance with one or more embodiments described herein. In various aspects, the method 200 can be used to create the device 100. In various embodiments, operation 202 can include joining quantum chips (e.g., 104 and / or 106) to an interposer (e.g., 102). In various embodiments, operation 204 can include routing and / or wiring at least one readout resonator (e.g., 128 / 130 and / or 132 / 134) of the quantum chips to an internal portion (e.g., 126) of the interposer (e.g., disposing at least one input / output port on the internal portion), the internal portion being between the quantum chips. As described above, constructing / creating a quantum multichip-joined module in this manner can reduce the number of crossings between input / output lines (e.g., readout lines) of the quantum chips and connection buses (e.g., cross-chip resonators) of the quantum chips. Reducing the number of such crossings can improve the accuracy and / or performance of quantum readout, which can improve the functionality of a quantum computing system.

[0059] Figure 3 A block diagram of an example, non-limiting interposer 302 that can facilitate a hybrid readout package for quantum multichip joining is shown in accordance with one or more embodiments described herein. As shown, the interposer 302 can have quantum chips (e.g., quantum chip 304 and quantum chip 306) joined thereto. In various embodiments, any suitable number of quantum chips can be arranged on the interposer 302 in any suitable pattern, shape, and / or manner. In various aspects, the quantum chip 304 and / or the quantum chip 306 can have any suitable number and / or any suitable type of qubits (as described in Figure 1 As shown in FIG. 3, for brevity, the quantum chip 304 and the quantum chip 306 are not shown in Figure 3 As shown in FIG. 3, for brevity, the quantum chip 304 and the quantum chip 306 are not shown in

[0060] As shown, in various cases, the interposer 302 can have a peripheral region 308 and an interior region 310. In various aspects, the peripheral region 308 can be an annular and / or peripheral surface region of the interposer 302 that substantially surrounds and / or encircles the quantum chips on the interposer 302 (e.g., in the example shown, the peripheral region 308 can be the edge / periphery of the interposer 302 that surrounds and / or encircles the quantum chip 304 and the quantum chip 306). In various aspects, the interior region 310 can be a surface region of the interposer 302 that is physically located between adjacent quantum chips (e.g., the quantum chip 304 on the interposer 302 is adjacent to the quantum chip 306, the surface region of the interposer 302 that is physically located / positioned / situated between the quantum chip 304 and the quantum chip 306 can be considered the interior region 310).

[0061] As shown, the quantum chip 304 and the quantum chip 306 can be coupled together by any suitable number of cross-chip lines (e.g., 312-316). In various aspects, these cross-chip lines 312-316 can exhibit any suitable shape and / or can include any suitable material for communicatively and / or electrically coupling the quantum chip 304 to the quantum chip 306.

[0062] As shown, in various cases, some of the quantum I / O ports 330 of the quantum chip 304 and the quantum chip 306 can be routed and / or wired to the peripheral region 308. As shown, in various cases, other quantum I / O ports of the quantum I / O ports 330 of the quantum chip 304 and the quantum chip 306 can be routed and / or wired to the interior region 310 (e.g., such that the quantum I / O ports 318-322 of the quantum chip 304 are located / positioned / situated on the interior region 310, such that the quantum I / O ports 324-328 of the quantum chip 306 are located / positioned / situated on the interior region 310). In various aspects, routing, wiring, coupling, positioning, situating, and / or disposing the quantum I / O ports 318-328 on the interior region 310 can reduce the number of crossings between quantum I / O lines and cross-chip lines 312-316. For example, if instead the quantum I / O port 318 were coupled to the peripheral region 308, then quantum I / O lines coupling the quantum chip 304 to the quantum I / O port 318 would have to either traverse the cross-chip line 312, or traverse the cross-chip lines 314 and 316, or traverse inter-qubit couplings on the quantum chip 304 itself. In various cases, if instead the quantum I / O port 320 were coupled to the peripheral region 308, then quantum I / O lines coupling the quantum chip 304 to the quantum I / O port 320 would have to either traverse the cross-chip lines 312 and 314, or traverse the cross-chip line 316, or traverse inter-qubit couplings on the quantum chip 304 itself. Similarly, if instead the quantum I / O port 326 were coupled to the peripheral region 308, then quantum I / O lines coupling the quantum chip 306 to the quantum I / O port 326 would have to either traverse the cross-chip line 312, or traverse the cross-chip lines 314 and 316, or traverse inter-qubit couplings on the quantum chip 306 itself. In various cases, if instead the quantum I / O port 328 were coupled to the peripheral region 308, then quantum I / O lines coupling the quantum chip 306 to the quantum I / O port 328 would have to either traverse the cross-chip lines 312 and 314, or traverse the cross-chip line 316, or traverse inter-qubit couplings on the quantum chip 306 itself. In various embodiments, such crossings / traversals can be reduced by disposing the quantum I / O ports 318-328 on the interior region 310 (e.g., as shown, quantum I / O lines coupling the quantum I / O ports 318-322 to the quantum chip 304 do not cross and / or intersect the cross-chip lines 312-316, and quantum I / O lines coupling the quantum I / O ports 324-328 to the quantum chip 306 do not cross and / or intersect the cross-chip lines 312-316).In various cases, as shown, quantum I / O ports 322 and 324 can not be constrained by cross-chip lines 312-316 (e.g., there can be unobstructed paths to peripheral region 308). Thus, in various embodiments, quantum I / O ports 322 and 324 can be disposed on peripheral region 308 without intersecting at least one of cross-chip lines 312-316 or at least one inter-qubit coupling on quantum chip 304 or on quantum chip 306.

[0063] In various embodiments, electrodes of a printed circuit board can be coupled to quantum I / O ports 318-328 by pins that are skewed (e.g., not parallel and not intersecting) relative to cross-chip lines 312-316 (e.g., one end of a conductive pin can be coupled to one of quantum I / O ports 318-328, another end of the conductive pin can be coupled to an electrode of the printed circuit board, and the conductive pin can extend away from interposer 302 at any suitable non-zero elevation angle). As a result, conductive pins associated with quantum I / O ports 318-328 and quantum I / O lines can not cross and / or intersect cross-chip lines 312-316.

[0064] In various embodiments, interposer 302 can have quantum chips. In various aspects, interposer 302 can have quantum I / O ports between adjacent pairs of quantum chips. In various cases, the interposer can include cross-chip lines that couple adjacent pairs of quantum chips, which can be located between the adjacent pairs of quantum chips. In some aspects, quantum I / O ports can be located between cross-chip lines. In various embodiments, a printed circuit board can be coupled to quantum I / O ports by pins that are skewed (e.g., not parallel and not intersecting) relative to the cross-chip lines.

[0065] In various embodiments, a hybrid readout package for performing quantum multi-chip junctions can include electrical conductors that couple readout resonators on an interior portion of an interposer to electrodes of a printed circuit board. In various cases, the electrical conductors can be skewed (e.g., not parallel and not intersecting) relative to connection buses on the interposer. In various aspects, the electrical conductors can include pogo pins, land grid arrays, and / or through-silicon vias.

[0066] Figure 4 A block diagram of an example, non-limiting quantum multi-chip junction device 400 including hybrid readout package pogo pins that can facilitate performing quantum multi-chip junctions is shown in accordance with one or more embodiments described herein. In various cases, Figure 4A cross-sectional and / or cut-away view of a hybrid readout package for quantum multi-chip joining can be shown. As shown, an interposer 402 can have a quantum chip 404 and a quantum chip 406. In various instances, there can be any suitable number and / or arrangement of quantum chips on the interposer 402. In various aspects, the quantum chip 404 and the quantum chip 406 can be joined (e.g., bump-joined by bumps 412 and / or joined by any other suitable technique) to the interposer 402. In various cases, the interposer 402 can have one or more quantum input / output ports 408 (e.g., readout resonators) disposed on an interior portion of the interposer 402 between the quantum chip 404 and the quantum chip 406. In various aspects, the interposer 402 can have one or more quantum input / output ports 410 (e.g., readout resonators) disposed on a peripheral portion of the interposer 402. In various aspects, the interposer 402 can have a front side 416 and a back side 414.

[0067] In various cases, the quantum input / output ports 408 can be coupled to corresponding electrodes on a printed circuit board 418. In various aspects, such coupling can be facilitated by one or more pogo pins 420. For example, in some cases, each of the quantum input / output ports 408 can be coupled to one end of a corresponding pogo pin, and the other end of the corresponding pogo pin can be coupled to a corresponding electrode on the printed circuit board 418. In various aspects, the pogo pins 420 can extend out of and / or away from the interposer 402 at any suitable angle, such that the pogo pins are not coplanar with the interposer 402. This can allow the pogo pins 420 to not cross and / or intersect any connection buses and / or cross-chip resonators on the interposer 402. As shown, in some cases, the printed circuit board 418 can be substantially parallel to the interposer 402, and can be opposite the front side 416 of the interposer 402.

[0068] In various cases, the quantum input / output ports 410 (e.g., on the peripheral portion of the interposer 402) can be joined to corresponding electrodes of the printed circuit board 418 by any suitable joining technique (e.g., bump joining as shown, wire bonding, pogo pins, and / or any other suitable technique).

[0069] Figure 5 A block diagram of an example, non-limiting quantum multi-chip joining apparatus 500 including a land grid array that can facilitate a hybrid readout package for quantum multi-chip joining in accordance with one or more embodiments described herein is shown. In various cases, Figure 5A cross-sectional and / or cut-away view of a hybrid readout package for quantum multi-chip interfacing can be shown. As shown, the interposer 402 can have a quantum chip 404 and a quantum chip 406. In various cases, the interposer 402 can have one or more quantum input / output ports 408 (e.g., readout resonators) disposed on an interior portion of the interposer 402 between the quantum chip 404 and the quantum chip 406. In various aspects, the interposer 402 can have one or more quantum input / output ports 410 (e.g., readout resonators) disposed on a peripheral portion of the interposer 402. In various aspects, the interposer 402 can have a front side 416 and a back side 414.

[0070] In various cases, the quantum input / output ports 408 and 410 can be coupled to corresponding electrodes on a printed circuit board 418. In various aspects, such coupling can be facilitated by a land grid array 502. In various cases, the land grid array 502 can include a socket 504 (e.g., cut-out) for the quantum chip 404 and a socket 506 (e.g., cut-out) for the quantum chip 406. In various aspects, the land grid array 502 can include pins 508 corresponding to the quantum input / output ports 408 (e.g., on an interior portion of the interposer 402) that couple the quantum input / output ports 408 to corresponding electrodes on the printed circuit board 418. In various aspects, the land grid array 502 can include pins 510 corresponding to the quantum input / output ports 410 (e.g., on a peripheral portion of the interposer 402) that couple the quantum input / output ports 410 to corresponding electrodes on the printed circuit board 418. As shown, in various cases, the printed circuit board 418 can be substantially parallel to the interposer 402 and can be opposite the front side 416 of the interposer 402.

[0071] Figure 6 A block diagram of an example, non-limiting quantum multi-chip interfacing device 600 including through-silicon vias that can facilitate a hybrid readout package for quantum multi-chip interfacing in accordance with one or more embodiments described herein is shown. In various cases, Figure 6A cross-sectional and / or cutaway view of a hybrid readout package for quantum multi-chip junction can be shown. As shown, an interposer 402 can have a quantum chip 404 and a quantum chip 406. In various cases, the interposer 402 can have one or more quantum input / output ports 408 (e.g., readout resonators) disposed on an interior portion of the interposer 402 between the quantum chip 404 and the quantum chip 406. In various aspects, the interposer 402 can have one or more quantum input / output ports 410 (e.g., readout resonators) disposed on a peripheral portion of the interposer 402. In various aspects, the interposer 402 can have a front side 416 and a back side 414.

[0072] In various examples, the quantum input / output ports 408 and 410 can be coupled to corresponding electrodes on a printed circuit board 418. In various aspects, such coupling can be facilitated by through-silicon vias 602 and 604. In various cases, one or more through-silicon vias 602 can correspond to one or more quantum input / output ports 408 (e.g., on an interior portion of the interposer 402). In such cases, the through-silicon vias 602 can pass through the interposer 402 from the front side 416 to the back side 414. Similarly, one or more through-silicon vias 604 can correspond to one or more quantum input / output ports 410 (e.g., on a peripheral portion of the interposer 402). In such cases, the through-silicon vias 604 can pass through the interposer 402 from the front side 416 to the back side 414. In various aspects, this can facilitate coupling the printed circuit board 418 to the back side 414 of the interposer 402, rather than to the front side 416 of the interposer 402. In various aspects, corresponding electrodes of the printed circuit board 418 can be joined (e.g., bump-joined and / or joined by any other suitable technique) to the through-silicon vias 602 and 604 such that the printed circuit board 418 is substantially parallel to the interposer 402 and such that the printed circuit board 418 is opposite the back side 414 of the interposer 402.

[0073] Figure 7 A block diagram of an example, non-limiting quantum multi-chip junction apparatus 700 that can facilitate a hybrid readout package for quantum multi-chip junction in accordance with one or more embodiments described herein is shown. As shown, a substrate 702 can have one or more qubit chips 704-718 joined thereto. In various aspects, each of the qubit chips 704-718 can have one or more qubits joined thereto. As shown, the qubit chips 704-718 can be arranged in a 2x4 array on the substrate 702. In various embodiments, any suitable number of qubit chips can be disposed on the substrate 702 in any suitable shape, pattern, and / or manner.

[0074] In various aspects, the substrate 702 can have a peripheral region 740 and one or more interior regions 720-738. In various cases, the peripheral region 740 can be a surface region of the substrate 702 that substantially surrounds the one or more qubit chips 704-718. In various cases, the one or more interior regions 720-738 can be one or more surface regions of the substrate 702 that are physically located between adjacent pairs of qubit chips among the qubit chips 704-718. For example, the qubit chip 704 is adjacent to the qubit chip 706. Thus, the qubit chip 704 and the qubit chip 706 can define an interior region 720 that is physically located between the qubit chip 704 and the qubit chip 706. Further, as shown, the qubit chip 704 is also adjacent to the qubit chip 712. Thus, the qubit chip 704 and the qubit chip 712 can define an interior region 732 that is physically located between the qubit chip 704 and the qubit chip 712. As another example, consider the qubit chip 716. The qubit chip 716 is adjacent to the qubit chip 714, adjacent to the qubit chip 708, and adjacent to the qubit chip 718. Thus, the qubit chip 716 and the qubit chip 714 can define an interior region 728, the qubit chip 716 and the qubit chip 708 can define an interior region 736, and the qubit chip 716 and the qubit chip 718 can define an interior region 730. In this way, adjacent pairs of qubit chips among the qubit chips 704-718 on the substrate 702 can define one or more interior regions 720-738.

[0075] As shown, adjacent pairs of qubit chips among the one or more qubit chips 704-718 can be coupled together by buses 742 located on the one or more interior regions 720-738. For example, the qubit chip 714 is adjacent to the qubit chip 712, the qubit chip 706, and the qubit chip 716. Thus, the qubit chip 714 can be coupled to the qubit chip 712 by one or more buses 742 (e.g., in the illustrated example, three buses 742 couple the qubit chip 714 to the qubit chip 712), the qubit chip 714 can be coupled to the qubit chip 706 by one or more buses 742 (e.g., in the illustrated example, two buses 742 couple the qubit chip 714 to the qubit chip 706), and the qubit chip 714 can be coupled to the qubit chip 716 by one or more buses 742 (e.g., in the illustrated example, three buses 742 couple the qubit chip 714 to the qubit chip 716). In some cases, non-adjacent qubit chips can be coupled together.

[0076] In various aspects, each of one or more qubit chips 704-718 may have one or more resonators 744 (e.g., input / output ports) for providing input to and / or receiving output from qubits on one or more qubit chips 704-718. In various embodiments, some of the resonators 744 may be routed / wired to a peripheral region 740 (e.g., input / output ports of qubits with unobstructed paths to the peripheral region 740 and / or without alternative paths with fewer crossings). In various embodiments, some of the resonators 744 may be routed / wired to one or more internal regions 720-738 (e.g., input / output ports of qubits without unobstructed paths to the peripheral region 740). As explained in detail above, this reduces the number of crossings between the input / output lines on substrate 702 and bus 742, thus improving the quantum computing performance of the quantum multi-chip interconnect device 700.

[0077] In various cases, as shown in the figure, one or more resonators 744 can be routed / wired to internal regions 720-738 such that they are located between buses 742. This can be advantageous because, in various cases, there can be unobstructed paths from different qubits of the qubit chip to at least one of the internal regions 720-738. For example, consider qubit chip 704. As shown in the figure, qubit chip 704 is coupled to qubit chip 712 via two buses 742. As shown in the figure, resonators 744 of qubit chip 704 can be located in internal region 732 such that resonators 744 are located between these two buses 742. If, instead, the resonator 744 is routed / wired to the peripheral region 740, then the readout line coupling the resonator 744 to qubit chip 704 would either have to cross / traverse one of the two buses 742 and / or have to cross / traverse the inter-qubit coupling located on qubit chip 704 itself. In various cases, such crossovers can be avoided by routing / wiring the resonator 744 to the internal region 732 between the two buses 742.

[0078] In various embodiments, one or more resonators 744 can be skewed relative to bus 742 (e.g., not intersecting with and not parallel to bus 742) (e.g., as... Figures 4-6 (As shown) One or more conductors are coupled to the printed circuit board (e.g., electrodes coupled to the printed circuit board). In various cases, one or more conductors may be any of the following: spring pins, connection disk grid arrays, through-silicon vias, any other suitable electrical couplings, and / or any suitable combination thereof.

[0079] In various embodiments, the size of the interposer / substrate can be increased to accommodate more quantum / quantum bit chips. In various instances, the size of the quantum / quantum bit chips can fit within a stepper field of exposure (e.g., each quantum / quantum bit chip can have less than about 50 and / or 60 quantum bits). In various cases, any suitable number of quantum bits and any suitable number of quantum / quantum bit chips can be implemented.

[0080] Figures 8-10 Flowcharts illustrating example, non-limiting methods 800, 900, and 1000 of fabricating a quantum multi-chip bonded device that can facilitate a hybrid readout package for quantum multi-chip bonding in accordance with one or more embodiments described herein are shown.

[0081] In various embodiments, operation 802 can include bonding a first quantum chip (e.g., 104 and / or 304) and a second quantum chip (e.g., 106 and / or 306) to an interposer (e.g., 102 and / or 302).

[0082] In various aspects, operation 804 can include routing and / or wiring a readout resonator (e.g., 128 and / or 318) of the first quantum chip to an interior portion (e.g., 126 and / or 310) of the interposer. In various instances, the interior portion can be located between the first quantum chip and the second quantum chip.

[0083] In various aspects, operation 806 can include coupling the first quantum chip and the second quantum chip by at least two connection buses (e.g., 108 and / or 312-316) located on the interior portion. In various aspects, the readout resonator can be located between the at least two connection buses.

[0084] In various embodiments, operation 902 can include coupling the readout resonator to a printed circuit board (e.g., 418) by an electrical conductor (e.g., 420, 508, and / or 602) that is skewed relative to the at least two connection buses.

[0085] In various embodiments, operation 1002 can include routing and / or wiring a second readout resonator of the first quantum chip to a peripheral portion (e.g., 116 and / or 308) of the interposer that surrounds the first quantum chip and the second quantum chip.

[0086] Figures 11-12 Flowcharts illustrating example, non-limiting methods 1100 and 1200 of fabricating a quantum multi-chip bonded device that can facilitate a hybrid readout package for quantum multi-chip bonding in accordance with one or more embodiments described herein are shown.

[0087] In various embodiments, operation 1102 can include bonding one or more qubit chips (e.g., 704-718) to a substrate (e.g., 702).

[0088] In various aspects, operation 1104 can include routing and / or wiring one or more resonators (e.g., 744) of the one or more qubit chips to one or more interior regions (e.g., 720-738) of the substrate, the one or more interior regions being located between one or more pairs of adjacent chips in the one or more qubit chips.

[0089] In various instances, operation 1106 can include coupling one or more pairs of adjacent chips in the one or more qubit chips together by a bus (e.g., 742) located on the one or more interior regions, wherein the one or more resonators are located between the bus.

[0090] In various examples, operation 1202 can include coupling one or more resonators to a printed circuit board (e.g., 418) by one or more conductors (e.g., 420, 508, and / or 602) that are skewed relative to the bus.

[0091] To provide additional context for various embodiments described herein, Figure 13 And the following discussion is intended to provide a general description of a suitable computing environment 1300 in which various embodiments can be implemented. While the above has been described in the general context of computer-executable instructions of a computer program that runs on a computer, those skilled in the art will recognize that the embodiments also can be implemented in combination with other program modules and / or as a combination of hardware and software.

[0092] Generally, program modules include routines, programs, components, data structures, etc., that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, hand-held computing devices, microprocessor-based or programmable consumer electronics, and the like, each of which can be operatively coupled to one or more associated devices.

[0093] The illustrated embodiments herein also can be practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0094] Computing devices typically include a variety of media, which can include computer-readable storage media, machine-readable storage media, and / or communications media, which two terms are used herein differently from one another. Computer-readable storage media or machine- readable storage media can be any available storage media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. By way of example, and not limitation, computer-readable storage media or machine-readable storage media can be implemented in connection with any method or technology for storage of information such as computer-readable or machine-readable instructions, program modules, program data, or

[0095] Computer-readable storage media can include, but are not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital versatile disk (DVD), Blu-ray disc (BD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, solid state drives or other solid state storage devices, or other tangible and / or non-transitory media which can be used to store desired information. In this regard, the terms “tangible” or “non-transitory” herein as applied to storage, memory or computer-readable media, are to be understood to exclude only propagating transitory signals per se as modifiers and do not negate the

[0096] Computer-readable storage media can be accessed by one or more local or remote computing devices, e.g., via access requests, queries or other data retrieval protocols, for various operations with respect to the information stored by the media.

[0097] Communication media typically embody computer-readable instructions, data structures, program modules or other structured or unstructured data in a modulated data signal such as a carrier wave or other transport mechanism, and includes any information delivery or transport media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.

[0098] Referring again to Figure 13The exemplary environment 1300 for implementing various embodiments of the aspects described herein includes a computer 1302, which includes a processing unit 1304, a system memory 1306, and a system bus 1308. The system bus 1308 couples system components including, but not limited to, the system memory 1306 to the processing unit 1304. The processing unit 1304 can be any of various commercially available processors. Dual microprocessors and other multi-processor architectures can also be employed as the processing unit 1304.

[0099] The system bus 1308 can be any of several types of bus structures including an address bus, a data bus, a control bus, and a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. The system memory 1306 includes ROM 1310 and RAM 1312. A basic input / output system (BIOS) can be stored in a non-volatile memory such as ROM, erasable programmable read-only memory (EPROM), EEPROM, flash memory, or the like, which BIOS contains the basic routines that help to transfer information between elements within the computer 1302, such as during start-up. The RAM 1312 can also include a high-speed RAM such as static RAM for caching data.

[0100] The computer 1302 further includes an internal hard disk drive (HDD) 1314 (e.g., EIDE, SATA), one or more external storage devices 1316 (e.g., a magnetic floppy disk drive (FDD) 1316, a memory stick or flash drive reader, a memory card reader, etc.), and a drive 1320 (e.g., such as a solid state drive, an optical disk drive, which can read or write from a disk 1322 such as a CD-ROM disk, a DVD, a BD, etc.). Alternatively, in cases involving a solid state drive, a disk 1322 will not be included unless separate. While the internal HDD 1314 is illustrated as being within the computer 1302, the internal HDD 1314 can also be configured for external use in an appropriate chassis (not shown). Additionally, although not shown in the environment 1300, a solid state drive (SSD) can be used in addition to or in place of the HDD 1314. The HDD 1314, external storage devices 1316, and drive 1320 can be connected to the system bus 1308 by a HDD interface 1324, an external storage interface 1326, and a drive interface 1328, respectively. The interface 1324 for external drive implementations can include at least one or both Universal Serial Bus (USB) and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technology. Other external drive connection technology is within the contemplation of the embodiments described herein.

[0101] The drive and its associated computer-readable storage medium provide non-volatile storage of data, data structures, computer-executable instructions, etc. For computer 1302, the drive and storage medium accommodate storage of data in any suitable digital format. Although the above description of computer-readable storage media refers to corresponding types of storage devices, those skilled in the art will understand that other types of computer-readable storage media (whether currently existing or developed in the future) may also be used in the example operating environment, and further, any such storage medium may contain computer-executable instructions for performing the methods described herein.

[0102] Multiple program modules may be stored in the drive and RAM 1312, including an operating system 1330, one or more application programs 1332, other program modules 1334, and program data 1336. All or part of the operating system, application programs, modules, and / or data may also be cached in RAM 1312. The systems and methods described herein can be implemented using various commercially available operating systems or combinations of operating systems.

[0103] Computer 1302 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate the hardware environment used for operating system 1330, and the emulated hardware may optionally be compatible with... Figure 13 The hardware shown is different. In this embodiment, the operating system 1330 may include one of a plurality of virtual machines (VMs) hosted at the computer 1302. Furthermore, the operating system 1330 may provide a runtime environment for the application 1332, such as the Java Runtime Environment or the .NET Framework. A runtime environment is a consistent execution environment that allows the application 1332 to run on any operating system that includes a runtime environment. Similarly, the operating system 1330 may support containers, and the application 1332 may be in the form of containers, which are lightweight, standalone, executable software packages that include, for example, code, runtime, system tools, system libraries, and application settings.

[0104] Furthermore, computer 1302 can enable security modules, such as a Trusted Processing Module (TPM). For example, with TPM, before loading the next boot component, the boot component hashes the next boot component and waits for the result to match a security value. This process can occur at any layer of the computer 1302's code execution stack, such as at the application execution level or the operating system (OS) kernel level, thereby achieving security at any code execution level.

[0105] A user can enter commands and information into the computer 1302 through one or more wire / wireless input devices, e.g., a keyboard 1338, a touch screen 1340, and a pointing device, such as a mouse 1342. Other input devices (not shown) can include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, an optical-fiber remote control, or other remote control, a joystick, a virtual reality controller and / or virtual reality headset, a gamepad, a stylus, an image input device, e.g., camera, a gesture sensor input device, a visual movement sensor input device, an emotional or facial detection device, a biometric input device, e.g., fingerprint or iris scanner, or the like. These and other input devices are often connected to the processing unit 1304 through an input device interface 1344 that can be coupled to the system bus 1308, but can be connected by other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, a Bluetooth® interface, etc.

[0106] A monitor 1346 or other type of display device can also be connected to the system bus 1308 via an interface, such as a video adapter 1348. In addition to the monitor 1346, a computer typically includes other peripheral output devices (not shown), such as speakers, printers, etc.

[0107] The computer 1302 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer(s) 1350. The remote computer(s) 1350 can be a workstation, a server computer, a router, a personal computer, portable computer, microprocessor-based entertainment appliance, a peer device or other common network node, and typically includes many or all of the elements described relative to the computer 1302, although, for purposes of brevity, only a memory / storage device 1352 is illustrated. The logical connections depicted include wire / wireless connectivity to a local area network (LAN) 1354 and / or larger networks, e.g., a wide area network (WAN) 1356. Such LAN and WAN networking environments are commonplace in offices and companies and facilitate enterprise-wide computer networks, such as intranets, all of which can connect to a global communications network, e.g., the Internet.

[0108] When used in a LAN networking environment, the computer 1302 can be connected to the local network 1354 through a wire / wireless communication network interface or adapter 1358. The adapter 1358 can facilitate wire or wireless communication to the LAN 1354, which can also include a wireless access point (AP) disposed therein for communicating with the adapter 1358 in wireless mode.

[0109] When used in a WAN networking environment, computer 1302 may include modem 1360 or may be connected to a communication server on WAN 1356 via other means (such as via the Internet) for establishing communication on WAN 1356. Modem 1360 (which may be an internal or external wired or wireless device) may be connected to system bus 1308 via input device interface 1344. In a networking environment, program modules depicted relative to computer 1302 or parts thereof may be stored in remote memory / storage device 1352. It should be understood that the network connection shown is an example, and other means for establishing communication links between computers may be used.

[0110] When used in a LAN or WAN networking environment, computer 1302 can access cloud storage systems or other network-based storage systems as a supplement to or alternative to the external storage device 1316 described above, such as, but not limited to, network virtual machines that provide one or more aspects of information storage or processing. Generally, the connection between computer 1302 and the cloud storage system can be established, for example, via adapter 1358 or modem 1360 through LAN 1354 or WAN 1356 respectively. When computer 1302 is connected to the associated cloud storage system, external storage interface 1326 can manage the storage provided by the cloud storage system by means of adapter 1358 and / or modem 1360, just like other types of external storage. For example, external storage interface 1326 can be configured to provide access to cloud storage sources as if these sources were physically connected to computer 1302.

[0111] Computer 1302 may be operable to communicate with any wireless device or entity operatively positioned in wireless communication, such as a printer, scanner, desktop and / or laptop computer, portable data assistant, communications satellite, any device or location associated with a wirelessly detectable tag (e.g., self-service terminal, newsstand, store shelf, etc.), and telephone. This may include Wi-Fi and Wireless technology. Therefore, communication can be a predefined structure like a traditional network, or simply self-organizing communication between at least two devices.

[0112] The present application can be a system, a method, an apparatus and / or a computer program product at any possible technical detail of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application. The computer readable storage medium can be a tangible device that can retain and store instructions for execution by a processor. The computer readable storage medium can be, for example but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non- exhaustive list of more specific examples of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0113] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device. Computer readable program instructions for carrying out operations of the present application can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computing / processing device, partly on the user's computing / processing device, as a stand-alone software package, partly on the user's computing / processing device and partly on a remote computing / processing device or entirely on the remote computing / processing device or server. In the latter scenario, the remote computing / processing device can be connected to the user's computing / processing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application

[0114] The present invention has been described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions that implement aspects of the functions / actions specified in the blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0115] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0116] While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and / or computer system, those skilled in the art will recognize that the disclosure also can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputers, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, etc. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all, aspects of this disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0117] As used in this application, the terms “component,” “system,” “platform,” “interface,” and the like can refer to and / or can include a computer-related entity or an entity that is related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, co-resident, and / or distributed amongst one computer and / or across two or more computers. In another example, a component can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by an electric or electronic circuit, which is operated by a software or firmware application running in a processor. In such a case, the processor can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, wherein the electronic components can include a processor or other means for executing at least a portion of the software or firmware that conveys at least a portion of its functionality.

[0118] Moreover, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. Moreover, articles “a” and “an” as used in the subject specification and annexed drawings should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. As used herein, the terms “example” and / or “exemplary” are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as an “example” and / or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques for performing the same functions.

[0119] As employed in this specification, the term "processor" can refer to substantially any computing processing unit or device comprising, but not limited to, a single-core processor; a single processor with software multithread execution capability; a multi-core processor; a multi-core processor with software multithread execution capability; a multi-core processor with hardware multithread technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field- programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a processor can utilize nano- scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor can also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," data storage," "database," and substantially any other information storage component relevant to operation and functionality of a component are utilized to refer to "memory components," entities embodied in a "memory," or component including memory. It is appreciated that memory and / or memory components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include, for example, RAM that can act as external cache memory. By way of example, and not limitation, RAM can be obtained from any number of sources, such as Synchronous Dynamic RAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), and Rambus dynamic RAM (RDRAM). Further, memory components of systems or computer-implemented methods disclosed herein are intended to include, without being limited to, these and any other suitable types of memory.

[0120] The above-described examples merely include examples of systems and computer-implemented methods. Of course, it is impossible to describe every conceivable combination or computer-implemented method of components for the purposes of describing the present disclosure, but one of ordinary skill in the art can recognize that many further combinations and permutations of the disclosure are possible. Moreover, to the extent that the terms "including", "having", "possessing", and the like are used in the detailed description, claims, appendices and drawings, they are intended to be inclusive and to be construed in the manner as set forth in the above- referenced U.S. Patent No. 8,623,530.

[0121] The description of the various embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technology found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A hybrid readout package device for quantum multi-chip interconnection, comprising: The internal component contains a first quantum chip and a second quantum chip; The readout resonator of the first quantum chip is routed to an internal portion of the inner plug-in located between the first quantum chip and the second quantum chip; as well as At least two connection buses are coupled to the first quantum chip and the second quantum chip, the at least two connection buses being located on the internal portion, wherein a readout resonator is located between the at least two connection buses.

2. The device according to claim 1, wherein, The readout resonator is coupled to the printed circuit board via an electrical conductor that is skewed relative to the at least two connection buses.

3. The device according to claim 2, wherein, The electrical conductor is a spring pin, and the printed circuit board is parallel to the inner plug and opposite to the front side of the inner plug.

4. The device according to claim 2, wherein, The electrical conductor is a pad grid array, and the printed circuit board is parallel to the inner plug and opposite to the front side of the inner plug.

5. The device according to claim 2, wherein, The electrical conductor is a through-silicon via, and the printed circuit board is parallel to the inner plug-in and opposite to the rear side of the inner plug-in.

6. The device according to any one of claims 1-5, further comprising: The second readout resonator of the first quantum chip is routed to the outer portion of the inner plug-in, the outer portion surrounding the first and second quantum chips.

7. A method for hybrid readout packaging for quantum multi-chip interconnects, comprising: Connect the first and second quantum chips to the internal plug-in; The readout resonator of the first quantum chip is routed to the internal portion of the inner module, which is located between the first quantum chip and the second quantum chip; as well as The first quantum chip and the second quantum chip are coupled through at least two connection buses located on an internal portion, wherein a readout resonator is located between the at least two connection buses.

8. The method of claim 7, further comprising: The readout resonator is coupled to the printed circuit board via an electrical conductor that is skewed relative to the at least two connection buses.

9. The method according to claim 8, wherein, The electrical conductor is a spring pin, and the printed circuit board is parallel to the inner plug and opposite to the front side of the inner plug.

10. The method according to claim 9, wherein, The electrical conductor is a pad grid array, and the printed circuit board is parallel to the inner plug and opposite to the front side of the inner plug.

11. The method according to claim 9, wherein, The electrical conductor is a through-silicon via, and the printed circuit board is parallel to the inner plug-in and opposite to the rear side of the inner plug-in.

12. The method according to any one of claims 8 to 11, further comprising: The second readout resonator of the first quantum chip is routed to the outer portion of the inner plug-in, which surrounds the first and second quantum chips.

13. A hybrid readout package for quantum multi-chip interconnection, comprising: A substrate having one or more qubit chips; as well as One or more resonators coupled to the qubits on the one or more qubit chips, the one or more resonators being routed to one or more internal regions of the substrate, the one or more internal regions being located between one or more pairs of adjacent chips of the one or more qubit chips. The one or more pairs of adjacent chips of the one or more qubit chips are coupled together by at least two connection buses located on the one or more internal regions, wherein the one or more resonators are located between the at least two connection buses.

14. The device according to claim 13, wherein, The one or more resonators are coupled to the printed circuit board via one or more conductors that are skewed relative to the at least two connection buses.

15. The device according to claim 14, wherein, The one or more conductors include at least one of spring pins, a connecting disk grid array, or a through-silicon via.

16. A method for hybrid readout packaging for quantum multi-chip interconnection, comprising: Connect one or more qubit chips to a substrate; One or more resonators of the one or more qubit chips are routed to one or more internal regions of the substrate, the one or more internal regions being located between one or more pairs of adjacent chips of the one or more qubit chips; as well as The one or more pairs of adjacent chips of the one or more qubit chips are coupled together by at least two connection buses located on the one or more internal regions, wherein the one or more resonators are located between the at least two connection buses.

17. The method of claim 16, further comprising: The one or more resonators are coupled to the printed circuit board via one or more conductors that are skewed relative to the at least two connection buses.

18. The method according to claim 17, wherein, The one or more conductors include at least one of spring pins, a connecting disk grid array, or a through-silicon via.

19. An internal component product for a hybrid readout package for quantum multi-chip interconnection, comprising: Quantum chips; Quantum input / output ports routed between adjacent pairs of quantum chips; as well as At least two cross-chip lines are coupled to adjacent quantum chip pairs, the at least two cross-chip lines being located between adjacent quantum chip pairs, wherein the quantum input / output ports are located between the at least two cross-chip lines.

20. The plug-in product according to claim 19, wherein, The printed circuit board is coupled to the quantum input / output port via pins that are skewed relative to the at least two cross-chip lines.

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