A PCM master-to-master communication method and a programmable logic device

Abstract

The present invention relates to a PCM master-to-master communication method and a programmable logic device, in which the communication between two PCM master devices is realized by a programmable logic device; the configuration process of the programmable logic device includes: defining the pins of the programmable logic device, including: a pin connected to the communication signal of the first master device, a pin connected to the communication signal of the second master device, and a reset pin for receiving a reset signal; inverting the clock signals received to the first master device and the second master device respectively to obtain the internal reverse clock signals of the first master device and the second master device; respectively constructing the internal counting state machine, data receiving state machine and data sending state machine corresponding to the first master device and the second master device. The present invention can realize the non-delayed conversion of PCM master to master, and can also realize the time slot allocation and data shifting of the bus, and adapt to the differences in PCM interfaces of different manufacturers.

Description

Technical Field

[0001] The invention relates to the field of PCM communication, and in particular to a PCM master-to-master communication method and a programmable logic device. Background Art

[0002] Existing PCMs are all master-slave communication interfaces. Since the master device needs to provide a clock signal and a frame synchronization signal, two master devices cannot exist on a bus at the same time, and communication between master devices cannot be achieved. Summary of the invention

[0003] In order to solve the above problems, the present invention proposes a PCM master-to-master communication method and a programmable logic device.

[0004] The specific plan is as follows:

[0005] A PCM master-to-master communication method realizes communication between two PCM master devices through a programmable logic device; the configuration process of the programmable logic device includes:

[0006] Define the pins of the programmable logic device, including: a pin connected to the communication signal of the first master device, a pin connected to the communication signal of the second master device, and a reset pin for receiving a reset signal;

[0007] Reverse the clock signals received from the first master device and the second master device to obtain internal reverse clock signals of the first master device and the second master device;

[0008] Constructing internal counting state machines, data receiving state machines and data sending state machines corresponding to the first master device and the second master device respectively;

[0009] When the internal reverse clock signal triggers the rising edge, the internal counting state machine counts according to the different values ​​of the state variables of the internal counting state machine, and assigns a value to the master device receiving data enable signal when the count value reaches the count threshold;

[0010] When the clock signal of the master device triggers the falling edge, the data receiving state machine receives the data of the master device according to the different values ​​of the state variables of the data receiving state machine and stores them in the data cache;

[0011] When the clock signal of the master device triggers the rising edge, the data sending state machine sends the data in the data cache to the master device according to the different values ​​of the state variables of the data sending state machine and the different values ​​of the master device's receive data enable signal, and sets the pin for sending data to the master device to a high configuration when idle.

[0012] Furthermore, the pins of the programmable logic device include PCM1_DOUT, PCM1_DIN, PCM1_CLK, PCM1_FS, PCM1_DOUT, PCM1_DIN, PCM1_CLK, PCM1_FS and RESET; wherein PCM1_DOUT, PCM1_DIN, PCM1_CLK, PCM1_FS are respectively connected one-to-one with the data receiving signal, data sending signal, clock signal and frame synchronization signal of the first master device PCM1; PCM2_DOUT, PCM2_DIN, PCM2_CLK, PCM2_FS are respectively connected one-to-one with the data receiving signal, data sending signal, clock signal and frame synchronization signal of the second master device PCM2; RESET is a reset pin.

[0013] Furthermore, the construction process of the internal counting state machine of the first master device PCM1 includes the following steps:

[0014] S301: Define variables PCM1_COUNTER, PCM1_COUN_STATE, PCM1_ENABLE and pcm1_fs_pr. Among them:

[0015] PCM1_COUNTER represents the counter corresponding to the first master device PCM1;

[0016] PCM1_COUN_STATE indicates the state of the internal counting state machine corresponding to the first master device PCM1. The values ​​include IDLE, COUNTER_EN and others. IDLE indicates the idle state, COUNTER_EN indicates the counting state, and others indicates other states except IDLE and COUNTER_EN.

[0017] PCM1_ENABLE indicates the enablement of the first master device PCM1 to start collecting data, that is, when PCM1_ENABLE is 1, the first master device PCM1 starts collecting data, and when PCM1_ENABLE is 0, the first master device PCM1 stops collecting data;

[0018] pcm1_fs_pr indicates the trigger flag of the frame synchronization signal corresponding to the first master device PCM1, and the value is 0 or 1;

[0019] S302: Determine whether the signal received by the RESET pin indicates a reset state. If yes, proceed to S303; otherwise, proceed to S304;

[0020] S303: Assign the following values ​​to the variables:

[0021] Set PCM1_COUNTER to 0;

[0022] Set PCM1_COUN_STATE to IDLE;

[0023] Set PCM1_ENABLE to 0;

[0024] Assign pcm1_fs_pr a value of 1;

[0025] S304: Determine whether PCM1_COUNTER_CLK triggers a rising edge. If so, perform the following operations according to the value of the state variable PCM1_COUN_STATE of the internal counting state machine:

[0026] (1) When PCM1_COUN_STATE = IDLE, determine whether: PCM1_FS = 1 and pcm1_fs_pr = 0,

[0027] If satisfied, the variable is assigned the following value:

[0028] Set PCM1_COUNTER to 0;

[0029] Assign PCM1_COUN_STATE to COUNTER_EN;

[0030] Set PCM1_ENABLE to 0;

[0031] Assign pcm1_fs_pr to 0;

[0032] If not satisfied, assign the following value to the variable:

[0033] Set PCM1_COUNTER to 0;

[0034] Set PCM1_ENABLE to 0;

[0035] Assign pcm1_fs_pr to PCM1_FS;

[0036] (2) When PCM1_COUN_STATE = COUNTER_EN, determine whether the value of PCM1_COUNTER is equal to the counting threshold.

[0037] If satisfied, the variable is assigned the following value:

[0038] Set PCM1_COUNTER to 0;

[0039] Set PCM1_COUN_STATE to IDLE;

[0040] Set PCM1_ENABLE to 1;

[0041] If not satisfied, assign the following value to the variable:

[0042] In addition, PCM1_COUNTER increases by one;

[0043] Set PCM1_ENABLE to 0;

[0044] (3) When PCM1_COUN_STATE = others, the variables are assigned the following values:

[0045] Set PCM1_COUNTER to 0;

[0046] Set PCM1_COUN_STATE to IDLE;

[0047] Set PCM1_ENABLE to 0.

[0048] Furthermore, the construction process of the data receiving state machine of the first master device PCM1 includes the following steps:

[0049] S401: Define variables PCM1_TX_BUF, PCM1_TX_STATE, PCM1_TX_COUNTER and PCM1_TO_PCM2_BUF. Among them:

[0050] PCM1_TX_BUF represents the data transmission buffer corresponding to the first master device PCM1;

[0051] PCM1_TX_STATE indicates the state of the data receiving state machine corresponding to the first master device PCM1. The values ​​include: IDLE, DATA, SWITCH and others. Among them, IDLE indicates the idle state, DATA indicates the data receiving state, SWITCH indicates the data exchange state, and others indicates other states except IDLE, DATA and SWITCH.

[0052] PCM1_TX_COUNTER represents the data receiving counter corresponding to the first master device PCM1;

[0053] PCM1_TO_PCM2_BUF represents the corresponding data buffer when the first master device PCM1 sends data to the second master device PCM2.

[0054] S402: Determine whether the signal received by the RESET pin indicates a reset state. If yes, proceed to S403; otherwise, proceed to S404;

[0055] S403: Assign the following values ​​to the variables:

[0056] Set PCM1_TX_BUF to 0;

[0057] Set PCM1_TX_COUNTER to 0;

[0058] Set PCM1_TX_STATE to IDLE;

[0059] S404: Determine whether PCM1_CLK triggers a falling edge. If so, perform the following operations according to the value of the state variable PCM1_TX_STATE of the data receiving state machine:

[0060] (1) When PCM1_TX_STATE = IDLE, determine whether PCM1_FS = 1 is satisfied. If so, assign the following values ​​to the variables:

[0061] Assign PCM1_TX_BUF to the signal received by the PCM1_DOUT pin;

[0062] Let PCM1_TX_COUNTER increase by 1;

[0063] Set PCM1_TX_STATE to DATA;

[0064] If not satisfied, assign the following value to the variable:

[0065] Set PCM1_TX_BUF to 0;

[0066] Set PCM1_TX_COUNTER to 0;

[0067] Set PCM1_TX_STATE to IDLE;

[0068] (2) When PCM1_TX_STATE = DATA, determine whether the value of PCM1_TX_COUNTER is equal to the cache data count threshold.

[0069] If satisfied, the variable is assigned the following value:

[0070] Assign PCM1_TX_BUF to the signal received by the PCM1_DOUT pin;

[0071] Set PCM1_TX_COUNTER to 0;

[0072] Set PCM1_TX_STATE to SWITCH;

[0073] If not satisfied, assign the following value to the variable:

[0074] Assign PCM1_TX_BUF to the signal received by the PCM1_DOUT pin;

[0075] Let PCM1_TX_COUNTER increase by 1;

[0076] (3) When PCM1_TX_STATE = SWITCH, the following assignments are made to the variables:

[0077] Assign the value of PCM1_TX_BUF to PCM1_TO_PCM2_BUF;

[0078] Set PCM1_TX_STATE to IDLE;

[0079] (4) When PCM1_TX_STATE = others, the following assignments are made to the variables:

[0080] Set PCM1_TX_COUNTER to 0;

[0081] Set PCM1_TX_STATE to IDLE.

[0082] Furthermore, the construction process of the data transmission state machine of the first master device PCM1 includes the following steps:

[0083] S501: define variables PCM1_RX_COUNTER, PCM1_RX_STATE and PCM1_RX_BUF. Among them:

[0084] PCM1_RX_STATE indicates the state of the data transmission state machine corresponding to the first master device PCM1. The values ​​include: IDLE, DATA, and others. IDLE indicates the idle state, DATA indicates the data receiving state, and others indicates other states except IDLE and DATA.

[0085] PCM1_RX_COUNTER represents the data transmission counter corresponding to the first master device PCM1;

[0086] PCM1_RX_BUF represents the data receiving buffer corresponding to the first master device PCM1;

[0087] S502: Determine whether the signal received by the RESET pin indicates a reset state. If yes, proceed to S503; otherwise, proceed to S504;

[0088] S503: Assign the following values ​​to the variables:

[0089] Set the PCM1_DIN pin to high impedance state;

[0090] Set PCM1_RX_COUNTER to 0;

[0091] Set PCM1_RX_STATE to IDLE;

[0092] S504: Determine whether PCM1_CLK triggers a rising edge. If so, perform the following operations according to the value of the state variable PCM1_RX_STATE of the data transmission state machine:

[0093] (1) When PCM1_RX_STATE = IDLE, determine whether PCM1_ENABLE = 1.

[0094] If satisfied, the variable is assigned the following value:

[0095] Assign PCM2_TO_PCM1_BUF to PCM1_RX_BUF;

[0096] Set PCM1_RX_STATE to DATA;

[0097] If not satisfied, assign the following value to the variable:

[0098] Set the PCM1_DIN pin to high impedance state;

[0099] Set PCM1_RX_COUNTER to 0;

[0100] Set PCM1_RX_STATE to IDLE;

[0101] (2) When PCM1_RX_STATE = DATA, determine whether the value of PCM1_TX_COUNTER is equal to the cache data count threshold.

[0102] If satisfied, the variable is assigned the following value:

[0103] Assign the value of PCM1_RX_BUF to the PCM1_DIN pin;

[0104] Set PCM1_TX_COUNTER to 0;

[0105] Set PCM1_TX_STATE to IDLE;

[0106] If not satisfied, assign the following value to the variable:

[0107] Assign the value of PCM1_RX_BUF to the PCM1_DIN pin;

[0108] Let PCM1_RX_COUNTER increase by 1;

[0109] Set PCM1_RX_STATE to DATA;

[0110] (3) When PCM1_RX_STATE = others, the following assignments are made to the variables:

[0111] Set PCM1_RX_COUNTER to 0;

[0112] Set the PCM1_DIN pin to high impedance state;

[0113] Set PCM1_RX_STATE to IDLE.

[0114] A programmable logic device is configured by the steps of the above method in an embodiment of the present invention.

[0115] Furthermore, the programmable logic device is of CPLD type.

[0116] The present invention adopts the above technical solution to achieve non-delayed conversion of PCM master to master, and can also achieve bus time slot allocation and data shifting, adapting to the differences in PCM interfaces of different manufacturers. BRIEF DESCRIPTION OF THE DRAWINGS

[0117] Figure 1 Shown is a flow chart of an embodiment of the present invention.

[0118] Figure 2 FIG. 2 is a circuit diagram of a programmable logic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0119] To further illustrate various embodiments, the present invention provides drawings. These drawings are part of the disclosure of the present invention, which are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in this field should be able to understand other possible implementations and advantages of the present invention.

[0120] The present invention will now be further described with reference to the accompanying drawings and specific implementation methods.

[0121] The embodiment of the present invention provides a PCM master-to-master communication method, which implements communication between two PCM master devices through a programmable logic device. The programmable logic device can be a CPLD, FPGA, etc. In this embodiment, a CPLD is selected. Figure 1 As shown, the configuration of a programmable logic device includes the following steps:

[0122] S1: Define 9 external signal access pins in the programmable logic device, namely: PCM1_DOUT, PCM1_DIN, PCM1_CLK, PCM1_FS, PCM1_DOUT, PCM1_DIN, PCM1_CLK, PCM1_FS and RESET, refer to Figure 2As shown. Among them, PCM1_DOUT, PCM1_DIN, PCM1_CLK, PCM1_FS are respectively connected to the data receiving signal, data sending signal, clock signal, and frame synchronization signal of the first master device PCM1 in one-to-one correspondence; PCM2_DOUT, PCM2_DIN, PCM2_CLK, PCM2_FS are respectively connected to the data receiving signal, data sending signal, clock signal, and frame synchronization signal of the second master device PCM2 in one-to-one correspondence; RESET is connected to the reset signal and is used to receive the reset signal.

[0123] S2: Construct an internal reverse clock signal PCM1_COUNTER_CLK of the first master device PCM1 and an internal reverse clock signal PCM2_COUNTER_CLK of the second master device PCM2, and invert the signal input from the PCM1_CLK pin and assign it to PCM1_COUNTER_CLK, and invert the signal input from the PCM2_CLK pin and assign it to PCM2_COUNTER_CLK.

[0124] If the operation is not inverted, data cannot be collected from the same clock edge, but needs to be advanced by half a clock. Therefore, the inverted operation is adopted in this embodiment.

[0125] S3: Construct internal counting state machines of the first master device PCM1 and the second master device PCM2 respectively.

[0126] The internal counting state machine of the first master device PCM1 and the internal counting state machine of the second master device PCM2 are constructed in the same manner. The internal counting state machine of the first master device PCM1 is taken as an example for explanation below, and the construction manner of the internal counting state machine of the second master device PCM2 is not repeated here.

[0127] The construction process of the internal counting state machine of the first master device PCM1 includes the following steps:

[0128] S301: Define variables PCM1_COUNTER, PCM1_COUN_STATE, PCM1_ENABLE and pcm1_fs_pr. Among them:

[0129] PCM1_COUNTER represents the counter corresponding to the first master device PCM1;

[0130] PCM1_COUN_STATE indicates the state of the internal counting state machine corresponding to the first master device PCM1. The values ​​include IDLE, COUNTER_EN and others. IDLE indicates the idle state, COUNTER_EN indicates the counting state, and others indicates other states except IDLE and COUNTER_EN.

[0131] PCM1_ENABLE indicates the enablement of the first master device PCM1 to start collecting data, that is, when PCM1_ENABLE is 1, the first master device PCM1 starts collecting data, and when PCM1_ENABLE is 0, the first master device PCM1 stops collecting data;

[0132] pcm1_fs_pr represents the trigger flag of the frame synchronization signal corresponding to the first master device PCM1, and the value is 0 or 1.

[0133] S302: Determine whether the signal received by the RESET pin indicates a reset state, if yes, proceed to S303; otherwise, proceed to S304.

[0134] S303: Assign the following values ​​to the variables:

[0135] Set PCM1_COUNTER to 0;

[0136] Set PCM1_COUN_STATE to IDLE;

[0137] Set PCM1_ENABLE to 0;

[0138] Assign pcm1_fs_pr a value of 1.

[0139] S304: Determine whether PCM1_COUNTER_CLK triggers a rising edge. If so, perform the following operations according to the value of the state variable PCM1_COUN_STATE of the internal counting state machine:

[0140] The method for judging whether PCM1_COUNTER_CLK triggers a rising edge is: when PCM1_COUNTER_CLK jumps and the PCM1_COUNTER_CLK value is 1, it is judged that PCM1_COUNTER_CLK triggers a rising edge.

[0141] (1) When PCM1_COUN_STATE = IDLE, determine whether: PCM1_FS = 1 and pcm1_fs_pr = 0,

[0142] If satisfied, the variable is assigned the following value:

[0143] Set PCM1_COUNTER to 0;

[0144] Assign PCM1_COUN_STATE to COUNTER_EN;

[0145] Set PCM1_ENABLE to 0;

[0146] Assign pcm1_fs_pr to 0;

[0147] If not satisfied, assign the following value to the variable:

[0148] Set PCM1_COUNTER to 0;

[0149] Set PCM1_ENABLE to 0;

[0150] Assign pcm1_fs_pr the value of PCM1_FS.

[0151] (2) When PCM1_COUN_STATE=COUNTER_EN, determine whether the value of PCM1_COUNTER is equal to the counting threshold (the counting threshold is set to "011111101" (binary) in this embodiment).

[0152] If satisfied, the variable is assigned the following value:

[0153] Set PCM1_COUNTER to 0;

[0154] Set PCM1_COUN_STATE to IDLE;

[0155] Set PCM1_ENABLE to 1;

[0156] If not satisfied, assign the following value to the variable:

[0157] In addition, PCM1_COUNTER increases by one;

[0158] Set PCM1_ENABLE to 0.

[0159] (3) When PCM1_COUN_STATE = others, the variables are assigned the following values:

[0160] Set PCM1_COUNTER to 0;

[0161] Set PCM1_COUN_STATE to IDLE;

[0162] Set PCM1_ENABLE to 0.

[0163] S4: Construct data receiving state machines of the first master device PCM1 and the second master device PCM2 respectively.

[0164] The data receiving state machine of the first master device PCM1 is used for receiving data sent by the first master device PCM1 and forwarding the data to the sending buffer corresponding to the second master device PCM2.

[0165] The data receiving state machine of the second master device PCM2 is used for receiving data sent by the second master device PCM2 and forwarding the data to the sending buffer corresponding to the first master device PCM1.

[0166] The construction process of the data receiving state machine of the first master device PCM1 includes the following steps:

[0167] S401: Define variables PCM1_TX_BUF, PCM1_TX_STATE, PCM1_TX_COUNTER and PCM1_TO_PCM2_BUF. Among them:

[0168] PCM1_TX_BUF represents the data transmission buffer corresponding to the first master device PCM1;

[0169] PCM1_TX_STATE indicates the state of the data receiving state machine corresponding to the first master device PCM1. The values ​​include: IDLE, DATA, SWITCH and others. Among them, IDLE indicates the idle state, DATA indicates the data receiving state, SWITCH indicates the data exchange state, and others indicates other states except IDLE, DATA and SWITCH.

[0170] PCM1_TX_COUNTER represents the data receiving counter corresponding to the first master device PCM1;

[0171] PCM1_TO_PCM2_BUF represents the corresponding data buffer when the first master device PCM1 sends data to the second master device PCM2.

[0172] S402: Determine whether the signal received by the RESET pin indicates a reset state, if so, proceed to S403; otherwise, proceed to S404.

[0173] S403: Assign the following values ​​to the variables:

[0174] Set PCM1_TX_BUF to 0;

[0175] Set PCM1_TX_COUNTER to 0;

[0176] Set PCM1_TX_STATE to IDLE.

[0177] S404: Determine whether PCM1_CLK triggers a falling edge. If so, perform the following operations according to the value of the state variable PCM1_TX_STATE of the data receiving state machine:

[0178] The method for judging whether PCM1_CLK triggers a falling edge is as follows: when PCM1_CLK changes and the PCM1_CLK value is 0, it is judged that PCM1_CLK triggers a falling edge.

[0179] (1) When PCM1_TX_STATE = IDLE, determine whether PCM1_FS = 1.

[0180] If satisfied, the variable is assigned the following value:

[0181] Assign PCM1_TX_BUF to the signal received by the PCM1_DOUT pin;

[0182] Let PCM1_TX_COUNTER increase by 1;

[0183] Set PCM1_TX_STATE to DATA;

[0184] If not satisfied, assign the following value to the variable:

[0185] Set PCM1_TX_BUF to 0;

[0186] Set PCM1_TX_COUNTER to 0;

[0187] Set PCM1_TX_STATE to IDLE.

[0188] (2) When PCM1_TX_STATE=DATA, determine whether the value of PCM1_TX_COUNTER is equal to the cache data count threshold (the cache data count threshold is set to binary "1111" according to the cache size in this embodiment, and in other embodiments, those skilled in the art can set other values ​​as needed, which is not limited here).

[0189] If satisfied, the variable is assigned the following value:

[0190] Assign PCM1_TX_BUF to the signal received by the PCM1_DOUT pin;

[0191] Set PCM1_TX_COUNTER to 0;

[0192] Set PCM1_TX_STATE to SWITCH;

[0193] If not satisfied, assign the following value to the variable:

[0194] Assign PCM1_TX_BUF to the signal received by the PCM1_DOUT pin;

[0195] Increment PCM1_TX_COUNTER by one.

[0196] (3) When PCM1_TX_STATE = SWITCH, the following assignments are made to the variables:

[0197] Assign the value of PCM1_TX_BUF to PCM1_TO_PCM2_BUF;

[0198] Set PCM1_TX_STATE to IDLE.

[0199] (4) When PCM1_TX_STATE = others, the following assignments are made to the variables:

[0200] Set PCM1_TX_COUNTER to 0;

[0201] Set PCM1_TX_STATE to IDLE.

[0202] The construction process of the data receiving state machine of the second master device PCM2 is similar to that of the data receiving state machine of the first master device PCM1. The difference lies in the definition of the variable PCM2_TX_BUF representing the transmission buffer corresponding to the second master device PCM2 and the variable PCM2_TO_PCM1_BUF representing the data buffer corresponding to when the second master device PCM2 sends data to the first master device PCM1. When the state of the data receiving state machine is SWITCH, the value of PCM2_TX_BUF is assigned to PCM2_TO_PCM1_BUF, and the specific construction process is not repeated here.

[0203] S5: Construct data sending state machines of the first master device PCM1 and the second master device PCM2 respectively.

[0204] The construction process of the data transmission state machine of the first master device PCM1 includes the following steps:

[0205] S501: define variables PCM1_RX_COUNTER, PCM1_RX_STATE and PCM1_RX_BUF. Among them:

[0206] PCM1_RX_STATE indicates the state of the data transmission state machine corresponding to the first master device PCM1. The values ​​include: IDLE, DATA, and others. IDLE indicates the idle state, DATA indicates the data receiving state, and others indicates other states except IDLE and DATA.

[0207] PCM1_RX_COUNTER represents the data transmission counter corresponding to the first master device PCM1;

[0208] PCM1_RX_BUF represents the data receiving buffer corresponding to the first master device PCM1.

[0209] S502: Determine whether the signal received by the RESET pin indicates a reset state. If yes, proceed to S503; otherwise, proceed to S504;

[0210] S503: Assign the following values ​​to the variables:

[0211] Set the PCM1_DIN pin to high impedance state;

[0212] Set PCM1_RX_COUNTER to 0;

[0213] Set PCM1_RX_STATE to IDLE.

[0214] S504: Determine whether PCM1_CLK triggers a rising edge. If so, perform the following operations according to the value of the state variable PCM1_RX_STATE of the data transmission state machine:

[0215] (1) When PCM1_RX_STATE = IDLE, determine whether PCM1_ENABLE = 1.

[0216] If satisfied, the variable is assigned the following value:

[0217] Assign PCM2_TO_PCM1_BUF to PCM1_RX_BUF;

[0218] Set PCM1_RX_STATE to DATA;

[0219] If not satisfied, assign the following value to the variable:

[0220] Set the PCM1_DIN pin to high impedance state;

[0221] Set PCM1_RX_COUNTER to 0;

[0222] Set PCM1_RX_STATE to IDLE.

[0223] (2) When PCM1_RX_STATE = DATA, determine whether the value of PCM1_TX_COUNTER is equal to the cache data count threshold.

[0224] If satisfied, the variable is assigned the following value:

[0225] Assign the value of PCM1_RX_BUF to the PCM1_DIN pin;

[0226] Set PCM1_TX_COUNTER to 0;

[0227] Set PCM1_TX_STATE to IDLE;

[0228] If not satisfied, assign the following value to the variable:

[0229] Assign the value of PCM1_RX_BUF to the PCM1_DIN pin;

[0230] Let PCM1_RX_COUNTER increase by 1;

[0231] Set PCM1_RX_STATE to DATA.

[0232] (3) When PCM1_RX_STATE = others, the following assignments are made to the variables:

[0233] Set PCM1_RX_COUNTER to 0;

[0234] Set the PCM1_DIN pin to high impedance state;

[0235] Set PCM1_RX_STATE to IDLE.

[0236] The construction process of the data transmission state machine of the second master device PCM2 is similar to the construction process of the data transmission state machine of the first master device PCM1, and will not be described in detail here.

[0237] The entire process of this embodiment is triggered by the clock and frame synchronization signal of the master device (PCM1 and PCM2) itself, without the need for an external clock, etc., to achieve synchronization of different sources; because the logic code of the CPLD itself is signal triggered or processed in parallel, there is no system delay and other problems, and PCM master-to-master non-delay conversion can be achieved; because the CPLD is a signal logic, only one time slot data needs to be cached, and a large cache is not required. Interface level conversion can be achieved through GPIOs of different groups of CPLD.

[0238] Although the present invention has been specifically shown and described in conjunction with the preferred embodiments, it should be understood by those skilled in the art that various changes may be made to the present invention in form and details without departing from the spirit and scope of the present invention as defined by the appended claims, all of which are within the scope of protection of the present invention.

Claims

1. A PCM master-to-master communication method, characterized in that: Communication between two PCM master devices is achieved through programmable logic devices; The configuration process of a programmable logic device includes: Define the pins of the programmable logic device, including: a pin connected to the communication signal of the first master device, a pin connected to the communication signal of the second master device, and a reset pin for receiving a reset signal; Reverse the clock signals received from the first master device and the second master device to obtain internal reverse clock signals of the first master device and the second master device; Constructing internal counting state machines, data receiving state machines and data sending state machines corresponding to the first master device and the second master device respectively; When the internal reverse clock signal triggers the rising edge, the internal counting state machine counts according to the different values ​​of the state variables of the internal counting state machine, and assigns a value to the master device receiving data enable signal when the count value reaches the count threshold; When the clock signal of the master device triggers the falling edge, the data receiving state machine receives the data of the master device according to the different values ​​of the state variables of the data receiving state machine and stores them in the data cache; When the clock signal of the master device triggers the rising edge, the data sending state machine sends the data in the data cache to the master device according to the different values ​​of the state variables of the data sending state machine and the different values ​​of the master device's receive data enable signal, and sets the pin that sends data to the master device to a high-impedance state when idle.

2. The PCM master-to-master communication method according to claim 1, characterized in that: The pins of the programmable logic device include PCM1_DOUT, PCM1_DIN, PCM1_CLK, PCM1_FS, PCM1_DOUT, PCM1_DIN, PCM1_CLK, PCM1_FS and RESET; among them, PCM1_DOUT, PCM1_DIN, PCM1_CLK, PCM1_FS are respectively connected to the data receiving signal, data sending signal, clock signal and frame synchronization signal of the first master device PCM1 in one-to-one correspondence; PCM2_DOUT, PCM2_DIN, PCM2_CLK, PCM2_FS are respectively connected to the data receiving signal, data sending signal, clock signal and frame synchronization signal of the second master device PCM2 in one-to-one correspondence; RESET is a reset pin.

3. The PCM master-to-master communication method according to claim 2, characterized in that: The construction process of the internal counting state machine of the first master device PCM1 includes the following steps: S301: define variables PCM1_COUNTER, PCM1_COUN_STATE, PCM1_ENABLE and pcm1_fs_pr; where: PCM1_COUNTER represents the counter corresponding to the first master device PCM1; PCM1_COUN_STATE indicates the state of the internal counting state machine corresponding to the first master device PCM1. The values ​​include IDLE, COUNTER_EN and others. IDLE indicates the idle state, COUNTER_EN indicates the counting state, and others indicates other states except IDLE and COUNTER_EN. PCM1_ENABLE indicates the enablement of the first master device PCM1 to start collecting data, that is, when PCM1_ENABLE is 1, the first master device PCM1 starts collecting data, and when PCM1_ENABLE is 0, the first master device PCM1 stops collecting data; pcm1_fs_pr indicates the trigger flag of the frame synchronization signal corresponding to the first master device PCM1, and the value is 0 or 1; S302: Determine whether the signal received by the RESET pin indicates a reset state. If yes, proceed to S303; otherwise, proceed to S304; S303: Assign the following values ​​to the variables: Set PCM1_COUNTER to 0; Set PCM1_COUN_STATE to IDLE; Set PCM1_ENABLE to 0; Assign pcm1_fs_pr a value of 1; S304: Determine whether PCM1_COUNTER_CLK triggers a rising edge. If so, perform the following operations according to the value of the state variable PCM1_COUN_STATE of the internal counting state machine: (1) When PCM1_COUN_STATE = IDLE, determine whether: PCM1_FS = 1 and pcm1_fs_pr = 0, If satisfied, the variable is assigned the following value: Set PCM1_COUNTER to 0; Assign PCM1_COUN_STATE to COUNTER_EN; Set PCM1_ENABLE to 0; Assign pcm1_fs_pr to 0; If not satisfied, assign the following value to the variable: Set PCM1_COUNTER to 0; Set PCM1_ENABLE to 0; Assign pcm1_fs_pr to PCM1_FS; (2) When PCM1_COUN_STATE = COUNTER_EN, determine whether the value of PCM1_COUNTER is equal to the counting threshold. If satisfied, the variable is assigned the following value: Set PCM1_COUNTER to 0; Set PCM1_COUN_STATE to IDLE; Set PCM1_ENABLE to 1; If not satisfied, assign the following value to the variable: In addition, PCM1_COUNTER increases by one; Set PCM1_ENABLE to 0; (3) When PCM1_COUN_STATE = others, the variables are assigned the following values: Set PCM1_COUNTER to 0; Set PCM1_COUN_STATE to IDLE; Set PCM1_ENABLE to 0.

4. The PCM master-to-master communication method according to claim 2, characterized in that: The construction process of the data receiving state machine of the first master device PCM1 includes the following steps: S401: define variables PCM1_TX_BUF, PCM1_TX_STATE, PCM1_TX_COUNTER and PCM1_TO_PCM2_BUF; where: PCM1_TX_BUF represents the data transmission buffer corresponding to the first master device PCM1; PCM1_TX_STATE indicates the state of the data receiving state machine corresponding to the first master device PCM1. The values ​​include: IDLE, DATA, SWITCH and others. Among them, IDLE indicates the idle state, DATA indicates the data receiving state, SWITCH indicates the data exchange state, and others indicates other states except IDLE, DATA and SWITCH. PCM1_TX_COUNTER represents the data receiving counter corresponding to the first master device PCM1; PCM1_TO_PCM2_BUF indicates the corresponding data buffer when the first master device PCM1 sends data to the second master device PCM2; S402: Determine whether the signal received by the RESET pin indicates a reset state. If yes, proceed to S403; otherwise, proceed to S404; S403: Assign the following values ​​to the variables: Set PCM1_TX_BUF to 0; Set PCM1_TX_COUNTER to 0; Set PCM1_TX_STATE to IDLE; S404: Determine whether PCM1_CLK triggers a falling edge. If so, perform the following operations according to the value of the state variable PCM1_TX_STATE of the data receiving state machine: (1) When PCM1_TX_STATE = IDLE, determine whether PCM1_FS = 1. If satisfied, the variable is assigned the following value: Assign PCM1_TX_BUF to the signal received by the PCM1_DOUT pin; Let PCM1_TX_COUNTER increase by 1; Set PCM1_TX_STATE to DATA; If not satisfied, assign the following value to the variable: Set PCM1_TX_BUF to 0; Set PCM1_TX_COUNTER to 0; Set PCM1_TX_STATE to IDLE; (2) When PCM1_TX_STATE = DATA, determine whether the value of PCM1_TX_COUNTER is equal to the cache data count threshold. If satisfied, the variable is assigned the following value: Assign PCM1_TX_BUF to the signal received by the PCM1_DOUT pin; Set PCM1_TX_COUNTER to 0; Set PCM1_TX_STATE to SWITCH; If not satisfied, assign the following value to the variable: Assign PCM1_TX_BUF to the signal received by the PCM1_DOUT pin; Let PCM1_TX_COUNTER increase by 1; (3) When PCM1_TX_STATE = SWITCH, the following assignments are made to the variables: Assign the value of PCM1_TX_BUF to PCM1_TO_PCM2_BUF; Set PCM1_TX_STATE to IDLE; (4) When PCM1_TX_STATE = others, the following assignments are made to the variables: Set PCM1_TX_COUNTER to 0; Set PCM1_TX_STATE to IDLE.

5. The PCM master-to-master communication method according to claim 2, characterized in that: The construction process of the data transmission state machine of the first master device PCM1 includes the following steps: S501: define variables PCM1_RX_COUNTER, PCM1_RX_STATE and PCM1_RX_BUF; where: PCM1_RX_STATE indicates the state of the data transmission state machine corresponding to the first master device PCM1. The values ​​include: IDLE, DATA, and others. IDLE indicates the idle state, DATA indicates the data receiving state, and others indicates other states except IDLE and DATA. PCM1_RX_COUNTER represents the data transmission counter corresponding to the first master device PCM1; PCM1_RX_BUF represents the data receiving buffer corresponding to the first master device PCM1; S502: Determine whether the signal received by the RESET pin indicates a reset state. If yes, proceed to S503; otherwise, proceed to S504; S503: Assign the following values ​​to the variables: Set the PCM1_DIN pin to high impedance state; Set PCM1_RX_COUNTER to 0; Set PCM1_RX_STATE to IDLE; S504: Determine whether PCM1_CLK triggers a rising edge. If so, perform the following operations according to the value of the state variable PCM1_RX_STATE of the data transmission state machine: (1) When PCM1_RX_STATE = IDLE, determine whether PCM1_ENABLE = 1. If satisfied, the variable is assigned the following value: Assign PCM2_TO_PCM1_BUF to PCM1_RX_BUF; Set PCM1_RX_STATE to DATA; If not satisfied, assign the following value to the variable: Set the PCM1_DIN pin to high impedance state; Set PCM1_RX_COUNTER to 0; Set PCM1_RX_STATE to IDLE; (2) When PCM1_RX_STATE = DATA, determine whether the value of PCM1_TX_COUNTER is equal to the cache data count threshold. If satisfied, the variable is assigned the following value: Assign the value of PCM1_RX_BUF to the PCM1_DIN pin; Set PCM1_TX_COUNTER to 0; Set PCM1_TX_STATE to IDLE; If not satisfied, assign the following value to the variable: Assign the value of PCM1_RX_BUF to the PCM1_DIN pin; Let PCM1_RX_COUNTER increase by 1; Set PCM1_RX_STATE to DATA; (3) When PCM1_RX_STATE = others, the following assignments are made to the variables: Set PCM1_RX_COUNTER to 0; Set the PCM1_DIN pin to high impedance state; Set PCM1_RX_STATE to IDLE.

6. A programmable logic device, characterized in that: The configuration is performed by the method as claimed in any one of claims 1 to 5.

7. The programmable logic device according to claim 6, characterized in that: The programmable logic device is of CPLD type.

Images