Mlvds bus system and control method therefor

Abstract

The present application relates to the technical field of power generation, power transformation and power distribution, and provides an MLVDS bus system and a control method therefor. The MLVDS bus system comprises an MLVDS data bus, a transceiving control arbitration line, an address bus, and a processor assembly; the processor assembly comprises two or more processor modules; each processor module comprises a processor unit, an MLVDS driving unit, a state transceiving unit, and an address bus processing unit; the MLVDS data bus is connected to the processor unit by means of the MLVDS driving unit; the transceiving control arbitration line is connected to the processor unit by means of the state transceiving unit; and the address bus is connected to the processor unit by means of the address bus processing unit. The MLVDS bus system can achieve the technical effect of high-speed and low-power-consumption MLVDS bus data communication.

Description

MLVDS bus system and control method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application entitled “A MLVDS bus system and its control method” filed on November 15, 2023 (Application No.: 2023115272690), the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the technical fields of power generation, transformation, and distribution, and in particular to an MLVDS bus system and a control method thereof. Background Art

[0004] MLVDS (Multipoint low Voltage Differential Signaling) is a new member of LVDS (Low-Voltage Differential Signaling). MLVDS can be used to optimize multi-point interconnect applications. Multi-point applications refer to interconnect applications in which multiple drivers or receivers share a single physical link. Such applications require the drivers to have sufficient driving power to drive multiple loads and to be able to withstand load changes on the physical bus caused by hot-swapping of boards.

[0005] Generally, point-to-point LVDS communication requires a higher rate by occupying more signal lines. For example, for a CPU (Central Processing Unit) connected to a bus, communication between the mainboard and 15 daughterboards requires 30 pairs of differential signals (both on the transceiver side). Including the backup CPU board, this adds up to 60 pairs of differential signals, requiring 120 corresponding transceiver driver chips. However, some daughterboards actually have a high idle rate during communication and do not support bus multiplexing, resulting in high costs and very high power consumption.

[0006] Summary of the Invention

[0007] The purpose of this application is to provide an MLVDS bus system, a control method, a control device, an electronic device, and a computer-readable storage medium, which can achieve the technical effect of high-speed and low-power MLVDS bus data communication.

[0008] In a first aspect, the present application provides an MLVDS bus system, including an MLVDS data bus, a transceiver control arbitration line, an address bus, and a processor component, wherein the processor component includes two or more processor modules, each of which includes a processor unit, an MLVDS driver unit, a status transceiver unit, and an address bus processing unit;

[0009] The MLVDS data bus is connected to the processor unit via the MLVDS driver unit;

[0010] The transceiver control arbitration line is connected to the processor unit through the status transceiver unit;

[0011] The address bus is connected to the processor unit through the address bus processing unit.

[0012] Among them, the status transceiver unit is used to monitor the communication status of the MLVDS data bus through the transceiver control arbitration line. When the MLVDS data bus is in an idle state, the processor unit sends the target address of the target processor module to the address bus through the address bus processing unit. The target processor module matches the link according to the target address, so that the processor unit is communicated with the target processor module through the MLVDS driver unit and the MLVDS data bus.

[0013] In the above implementation process, the MLVDS bus system sets up a transceiver control arbitration line and an address bus, and sets up a corresponding state transceiver unit and an address bus processing unit in the processor module. Through bus monitoring, when the MLVDS data bus is in an idle state, it is linked to the target processor module based on the target address matching, thereby realizing data interaction between the processor module and the target processor module; thereby, multiple processor modules on the MLVDS bus system can be adjusted to a low-power state when no data transmission and reception is required. When a processor module needs data communication, the child node (target processor module) to which the data is to be transmitted can be accurately found through the target address, and the MLVDS driving unit of the child node is finally activated through hardware, thereby waking up the target processor module from the low-power state to the normal communication mode, thereby making the target processor module enter the signal receiving state; thereby, the MLVDS bus system can realize a high-speed and low-power MLVDS bus architecture based on target address matching wake-up, and realize the technical effect of high-speed and low-power MLVDS bus data communication.

[0014] Furthermore, the processor module also includes an address logic processing unit, the MLVDS driver unit is connected to the address bus processing unit through the address logic processing unit, the address logic processing unit is configured with the address data of the processor module, the address logic processing unit receives the target address through the address bus processing unit, and the address logic processing unit is used to wake up the MLVDS driver unit when the address data and the target address match successfully.

[0015] In the above implementation process, the MLVDS driver unit is connected to the address bus processing unit through the address logic processing unit. The address logic processing unit is configured with the address data of the processor module. The address logic processing unit receives the target address through the address bus processing unit. The address logic processing unit is used to wake up the MLVDS driver unit when the address data and the target address match successfully.

[0016] Furthermore, the address logic processing unit includes a multi-channel comparator, which is configured with the address data of the processor module. The multi-channel comparator is connected to the address bus, and is used to match the address data with the target address received through the address bus processing unit, and send a matching success signal to the MLVDS driving unit when the address data successfully matches the target address.

[0017] In the above implementation process, by setting a multi-channel comparator, the address data can be matched with the target address received through the address bus processing unit. If the match is unsuccessful, no response will be given; if the match is successful, a match success signal will be sent to the MLVDS driver unit, thereby waking up the MLVDS driver unit and switching the MLVDS driver unit from a low-power state to a normal communication mode.

[0018] Furthermore, the address bus is configured with a broadcast address control line, and the address logic processing unit also includes an OR logic processor, the input end of the OR logic processor is respectively connected to the broadcast address control line and the multi-channel comparator, and the output end of the OR logic processor is connected to the MLVDS driving unit.

[0019] In the above implementation process, by setting the broadcast address control line and the OR logic processor, the MLVDS driver units of all other sub-nodes on the MLVDS bus system can be finally awakened through broadcast control to enter the normal communication mode.

[0020] Furthermore, the OR logic processor includes a first OR logic processor and a second OR logic processor, the input end of the first OR logic processor is connected to the broadcast address control line and the multi-channel comparator respectively, and the output end of the first OR logic processor is connected to the input end of the second OR logic processor;

[0021] The input end of the second or logic processor is also connected to the processor unit, and the output end of the second or logic processor is connected to the MLVDS driving unit.

[0022] In the above implementation process, by setting the first or logical processor and the second or logical processor, the MLVDS driver unit can be awakened directly by the processor unit, awakened by broadcast control, or awakened after the address data matches the target address.

[0023] Furthermore, the status transceiver unit is further configured to:

[0024] When the MLVDS data bus is in an idle state, an application is made to the transceiver control arbitration line to occupy the bus based on a preset arbitration mechanism, and after the application is successful, the processor module is switched to a sending state.

[0025] In the above implementation process, when the processor module needs to send data, it applies to the transceiver control arbitration line based on the preset arbitration mechanism to occupy the bus, thereby competing for bus control. After arbitration, the processor module that obtains control becomes the master node from a child node and switches to the sending state.

[0026] Furthermore, the status transceiver unit is further configured to:

[0027] When the MLVDS data bus is in an idle state, the processor module applies to the transceiver control arbitration line to occupy the bus based on a preset sequence or a preset logic token ring mechanism, and switches the processor module to a sending state after the application is successful.

[0028] In the above implementation process, the MLVDS bus system can also implement a communication mode based on a sequential rotation mechanism or a logical token ring mechanism, and the mode selection is diversified.

[0029] Furthermore, the MLVDS driver unit includes two or more MLVDS driver chips, the MLVDS driver unit is connected to the processor unit and the MLVDS data bus respectively, and the two or more MLVDS driver chips are arranged in parallel.

[0030] In the above implementation process, the number of MLVDS driver chips determines the data channel width of the MLVDS bus system. The more MLVDS driver chips there are, the faster the data channel width is and the stronger the data transmission capability is.

[0031] In a second aspect, the present application provides a method for controlling an MLVDS bus, which is applied to the MLVDS bus system described in the first aspect. The control method includes:

[0032] Controlling the processor module to an initialization state, in which the MLVDS driving unit and the address bus processing unit of the processor module are in a waiting state;

[0033] When the MLVDS data bus is in an idle state, applying for bus occupation through the status transceiver unit;

[0034] After the application is successful, the target address is sent to the target processor module through the address bus processing unit, and the target processor module is matched and linked with the processor module after the target address is successfully matched;

[0035] The processor unit is communicatively connected to the target processor module via the MLVDS driver unit and the MLVDS data bus.

[0036] In a third aspect, the present application provides a control device for an MLVDS bus, which is applied to the MLVDS bus system according to any one of the first aspects, and the control device includes:

[0037] An initialization module, configured to control the processor module to be in an initialization state, in which the MLVDS driving unit and the address bus processing unit of the processor module are in a waiting state;

[0038] An application module for applying for bus occupation when the MLVDS data bus is in an idle state, using the status transceiver unit;

[0039] A matching module, configured to send the target address to the target processor module through the address bus processing unit after the application is successful, and the target processor module matches and links with the processor module after the target address is successfully matched;

[0040] The communication module is used for the processor unit to communicate with the target processor module through the MLVDS driver unit and the MLVDS data bus.

[0041] In a fourth aspect, the present application provides an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method described in any one of the second aspects when executing the computer program.

[0042] In a fifth aspect, the present application provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed on a computer, the computer executes the method as described in any one of the second aspects.

[0043] In a sixth aspect, the present application provides a computer program product, which, when running on a computer, enables the computer to execute the method as described in any one of the first aspects.

[0044] Other features and advantages disclosed in the present application will be described in the following description, or some features and advantages can be inferred or determined without doubt from the description, or can be learned by implementing the above-mentioned technology disclosed in the present application.

[0045] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0047] FIG1 is a schematic structural diagram of an MLVDS bus system provided in an embodiment of the present application;

[0048] FIG2 is a schematic structural diagram of another MLVDS bus system provided in an embodiment of the present application;

[0049] FIG3 is a processing diagram of an address logic processing unit provided in an embodiment of the present application;

[0050] FIG4 is a flow chart of a method for controlling an MLVDS bus according to an embodiment of the present application;

[0051] FIG5 is a structural block diagram of a control device for an MLVDS bus provided in an embodiment of the present application;

[0052] FIG6 is a structural block diagram of an electronic device provided in an embodiment of the present application.

[0053] Icons: MLVDS data bus 100; transceiver control arbitration line 200; address bus 300; processor module 410; processor unit 411; MLVDS driver unit 412; status transceiver unit 413; address bus processing unit 414; initialization module 101; application and occupation module 102; matching module 103; communication module 104; processor 510; communication interface 520; memory 530; communication bus 540. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0055] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0056] CAN, short for Controller Area Network (CAN), was developed by BOSCH, a German company renowned for its development and production of automotive electronics. It eventually became an international standard (ISO 11898) and is one of the most widely used fieldbuses worldwide. With the advancement of communication technology, more and more CAN buses are adopting the high-speed MLVDS interface for communication. In common MLVDS-based high-speed bus systems, the motherboard and various daughterboards are connected via a backplane. Power signals, low-speed control single-ended signals, and management signals are communicated via 485 or CAN signals. Medium-speed, high-real-time data is communicated via point-to-point LVDS signals at 100Mbps to 1Gbps, and higher speeds utilize GTX 2.5Gbps point-to-point transmission. Data transmission in the MLVDS bus architecture is based on the bus arbitration mechanism of the CAN physical layer and link protocol layer. The CAN physical layer monitors the signal's logic level. A logic high indicates a recessive state, indicating the bus is idle. Authorized child nodes gain control and control the CAN bus output, shifting it to a dominant logic low, thereby occupying the bus. The data can be transmitted through the MLVDS bus;

[0057] However, point-to-point LVDS communication requires a higher rate, which first occupies more signal lines. For example, the communication between the main board and 15 boards requires 30 pairs of differential signals (both the transceiver and the receiver). Adding the spare CPU board, it is 60 pairs of differential signals, and 120 corresponding transceiver driver chips are needed, which is costly and consumes a lot of power. In fact, when some daughter boards communicate, the idle rate is high and the bus multiplexing mechanism is not supported. In addition, based on the logical token ring mechanism, the logical token ring needs to send token messages to the next node and the message confirmation process in the process of handing over control rights, which wastes time and affects the real-time performance and transmission rate of the data. Based on the sequential rotation mechanism, the bus control right is obtained according to the pre-assigned sequence number rotation. The child node that needs to send data in time may miss the sending cycle until the next sequential cycle, resulting in the data not being sent in time.

[0058] In order to solve the above-mentioned technical problems, the present application proposes an MLVDS bus system and a control method thereof. The MLVDS bus system sets a transceiver control arbitration line and an address bus, and sets corresponding status transceiver units and address bus processing units in the processor module. Through bus monitoring, when the MLVDS data bus is in an idle state, it is linked to the target processor module based on the target address matching, thereby realizing data interaction between the processor module and the target processor module. Please refer to Figure 1, which is a structural schematic diagram of an MLVDS bus system provided by an embodiment of the present application. The MLVDS bus system includes an MLVDS data bus 100, a transceiver control arbitration line 200, an address bus 300 and a processor assembly. The processor assembly includes two or more processor modules 410. Each processor module 410 includes a processor unit 411, an MLVDS driver unit 412, a status transceiver unit 413 and an address bus processing unit 414.

[0059] Exemplarily, the MLVDS data bus 100 is connected to the processor unit 411 via the MLVDS driver unit 412 ; the transceiver control arbitration line 200 is connected to the processor unit 411 via the status transceiver unit 413 ; and the address bus 300 is connected to the processor unit 411 via the address bus processing unit 414 .

[0060] Optionally, the transceiver control arbitration line 200 is a CAN control line, and correspondingly, the status transceiver unit 413 is a CAN transceiver unit; it should be noted that the transceiver control arbitration line 200 can also be other types of control lines, which is only used as an example and not as a limitation.

[0061] Exemplarily, the status transceiver unit 413 is used to monitor the communication status of the MLVDS data bus 100 through the transceiver control arbitration line 200. When the MLVDS data bus 100 is in an idle state, the processor unit 411 sends the target address of the target processor module to the address bus 300 through the address bus processing unit 414. The target processor module matches the link according to the target address, so that the processor unit 411 is communicated with the target processor module through the MLVDS driver unit 412 and the MLVDS data bus 100, wherein the target processor module is other processor modules in the processor component 410.

[0062] For example, in the embodiment of the present application, each processor module is configured with corresponding address data; in some implementations, a unique processor module can be matched in the MLVDS bus system through the address data.

[0063] Illustratively, the address bus processing unit 414 is responsible for sending and receiving addresses, and also has address comparison, matching, and logic processing functions; wherein the MLVDS driver unit 412 can serve as a transceiver driver unit of the MLVDS data bus 100 .

[0064] Exemplarily, the processor unit 411 is connected to the MLVDS data bus 100 through the MLVDS driver unit 412; the processor unit 411 can exchange data with the target processor module through the MLVDS driver unit 412; wherein, the target processor module is other processor modules on the MLVDS data bus 100, and the target address is the address data corresponding to the target processor module.

[0065] Exemplarily, the processor unit 411 is connected to the transceiver control arbitration line 200 through the status transceiver unit; the communication status of the MLVDS data bus can be monitored through the status transceiver unit 413; when the MLVDS data bus is in an idle state, the processor module 410 can apply to occupy the MLVDS data bus through the status transceiver unit 413;

[0066] Exemplarily, the processor unit 411 is connected to the address bus 300 through the address bus processing unit 414; after successfully applying to occupy the MLVDS data bus, the target address of the target processor module can be sent to other processor modules on the MLVDS bus system through the address bus 300; as an example, except for the target processor module corresponding to the target address, other processor modules on the MLVDS bus system will not respond to the target address.

[0067] The MLVDS bus system of the embodiment of the present application sets a transceiver control arbitration line and an address bus, and sets a corresponding state transceiver unit and an address bus processing unit in the processor module. Through bus monitoring, when the MLVDS data bus is in an idle state, it is linked to the target processor module based on the target address matching, thereby realizing data interaction between the processor module and the target processor module; thereby, multiple processor modules on the MLVDS bus system can be adjusted to a low-power state when there is no need to send and receive data. When a certain processor module needs data communication, the child node (target processor module) to which the data is to be transmitted can be accurately found through the target address, and the MLVDS driving unit of the child node is finally activated through hardware, and the target processor module is awakened from the low-power state and switched to the normal communication mode, thereby causing the target processor module to enter the signal receiving state; thereby, the MLVDS bus system can realize a high-speed and low-power MLVDS bus architecture based on target address matching wake-up, and realize the technical effect of high-speed and low-power MLVDS bus data communication.

[0068] In some embodiments, each processor module 410 on the MLVDS bus system can serve as a master node; for example, when one of the processor modules 410 on the MLVDS bus system needs to send data, the processor module 410 is activated as the master node, and the target processor module to which the processor module 410 wants to transmit data is designated as a child node.

[0069] Please refer to FIG. 2 , which is a schematic structural diagram of another MLVDS bus system provided in an embodiment of the present application.

[0070] As shown in FIG2 , the processor unit 411 uses an FPGA (Field Programmable Gate Array) chip, the CAN Device is a status transceiver unit 413, and the Buffer is an address bus processing unit 414. Optionally, the MLVDS driver unit uses two MLVD040 chips to implement an 8-channel data channel. The Data Bus is the MLVDS data bus 100, the Bus Transceiver Arbitration is the transceiver control arbitration line 200, and the Addr Bus is the address bus 300.

[0071] Exemplarily, the processor module 410 also includes an address logic processing unit (the ADDR Logic Unit shown in FIG2 ), and the MLVDS driver unit is connected to the address bus processing unit 414 through the address logic processing unit. The address logic processing unit is configured with the address data of the processor module and the target address received by the address logic processing unit through the address bus processing unit. The address logic processing unit is used to wake up the MLVDS driver unit when the address data and the target address match successfully.

[0072] Exemplarily, after receiving the target address transmitted on the address bus, the address logic processing unit of the processor module matches it with the address data configured by itself. If the match is unsuccessful, no processing is performed; if the match is successful, it means that the target processor module pointed to by the target address is the processor module, thereby waking up the MLVDS driver unit of the processor module, and converting the MLVDS driver unit from a low-power state to a normal communication mode, thereby establishing a communication connection with the master node (the processor module that sends the target address).

[0073] Please refer to Figure 3, which is a processing diagram of the address logic processing unit provided in an embodiment of the present application.

[0074] Exemplarily, the address logic processing unit includes a multi-channel comparator, which is configured with the address data of the processor module 410. The multi-channel comparator is connected to the address bus. The multi-channel comparator is used to match the address data with the target address received through the address bus processing unit, and send a match success signal to the MLVDS driving unit when the address data successfully matches the target address.

[0075] For example, by setting up a multi-channel comparator, the address data can be matched with the target address received through the address bus processing unit. If the match is unsuccessful, no response will be given; if the match is successful, a match success signal will be sent to the MLVDS driving unit, thereby waking up the MLVDS driving unit and switching the MLVDS driving unit from a low power consumption state to a normal communication mode.

[0076] Exemplarily, the address bus is configured with a broadcast address control line, and the address logic processing unit further includes a logic processor, the input end of the logic processor is respectively connected to the broadcast address control line and the multi-channel comparator, or the output end of the logic processor is connected to the MLVDS driving unit.

[0077] For example, by setting a broadcast address control line and / or a logic processor, the MLVDS driver units of all other sub-nodes on the MLVDS bus system can be eventually awakened through broadcast control to enter a normal communication mode.

[0078] In some embodiments, a broadcast mode is entered through broadcast control. In the broadcast mode, one processor module in the MLVDS bus system acts as a master node to send data, and the other processor modules act as slave nodes to receive data.

[0079] Exemplarily, the OR logic processor includes a first OR logic processor and a second OR logic processor, the input end of the first OR logic processor is respectively connected to the broadcast address control line and the multi-channel comparator, and the output end of the first OR logic processor is connected to the input end of the second OR logic processor;

[0080] The input end of the second or logic processor is also connected to the processor unit, and the output end of the second or logic processor is connected to the MLVDS driving unit.

[0081] Exemplarily, by setting the first or logical processor and the second or logical processor, the MLVDS driver unit can be directly awakened by the processor unit, awakened by broadcast control, or awakened after address data matches the target address.

[0082] Exemplarily, the status transceiver unit is further configured to:

[0083] When the MLVDS data bus is in an idle state, the processor module applies to the transceiver control arbitration line to occupy the bus based on a preset arbitration mechanism, and switches the processor module to a transmitting state after the application is successful.

[0084] For example, when the processor module needs to send data, it applies to the transceiver control arbitration line based on a preset arbitration mechanism to occupy the bus, thereby competing for bus control. After arbitration, the processor module that obtains control becomes the master node from a child node and switches to the sending state.

[0085] As shown in Figures 1 through 3, the ADDR Logic Unit (ADU) includes a multi-channel bit comparator or logic device processing unit. Optionally, all processor modules on the MLVDS bus system are assigned fixed binary-coded slot numbers B1 through B4 based on the address hardware. This embodiment is designed for 15 boards, with addresses 0001, 0010, 0011, ..., 1111. On the backplane bus, signals are fixedly pulled up to the power supply and pulled down to GND to implement logic 1s and 0s. The slot addresses are internally connected to the FPGA master control chip and the ADDR Logic Unit. The addresses A1~A4 received by the buffer are compared with the slot addresses inside the ADDR Logic Unit by the B1~B4 bit comparators. Only when they match will the logic signal address match consistency signal ADDR_Comp be output. ADDR_Comp and the broadcast address Busbroadcast are wired ORed to output the address enable ADDR_EN. ADDR_EN and FPGA_LVDS_EN are wired ORed to output the PDN power consumption enable pin of MLVDS to enable the MLVDS device.

[0086] Exemplarily, the status transceiver unit is further configured to:

[0087] When the MLVDS data bus is in an idle state, it applies to the transceiver control arbitration line to occupy the bus based on a preset sequence or a preset logic token ring mechanism, and switches the processor module to a sending state after the application is successful.

[0088] Exemplarily, the MLVDS bus system may also implement a communication mode based on a sequential round-robin mechanism or a logical token ring mechanism, with diversified mode selection.

[0089] Exemplarily, the MLVDS driver unit includes two or more MLVDS driver chips. The MLVDS driver unit is connected to the processor unit and the MLVDS data bus respectively, and the two or more MLVDS driver chips are arranged in parallel.

[0090] For example, the number of MLVDS driver chips determines the data channel width of the MLVDS bus system. The more MLVDS driver chips there are, the faster the data channel width is and the stronger the data transmission capability is.

[0091] In conjunction with Figures 1 to 3, the MLVDS bus system provided by the embodiment of the present application is a high-speed, low-power MLVDS bus architecture based on target address matching wake-up. The MLVDS bus system utilizes the physical layer and protocol layer of CAN to implement a competitive preemption mechanism, sequential rotation, and logical token ring mechanism for MLVDS serial bus data transmission. This application uses a competitive preemption mechanism as an example. By monitoring the CAN bus, when the processor module on the MLVDS bus system needs to send data, it applies to the transceiver control arbitration line based on a preset arbitration mechanism to occupy the bus, thereby competing for bus control. After arbitration, the processor module that obtains control becomes a master node from a child node and switches to the sending state.

[0092] For example, the MLVDS bus system provided in the embodiment of the present application can accurately find the processor module as the transmission target on the MLVDS bus system by adding an address bus;

[0093] Optionally, the embodiment of the present application takes 4 address buses as an example, and can achieve address matching of up to 15 processor modules, and can accurately find the child node that wants to transmit data, and finally enable the Power Down pin of the MLVDS driver unit of the child node through hardware, thereby waking up the MLVDS driver unit from the low power state to the normal mode, thereby entering the signal receiving state; by adding a broadcast address control line, the MLVS chips of all other child nodes can be finally awakened to enter the receiving state based on the broadcast control; as shown in Table 1, the hardware address loading coding table includes the address information of 15 processor modules and the broadcast address:

[0094] Table 1 - Hardware address loading encoding table

[0095] In some embodiments, the MLVDS bus system provided in the embodiments of the present application is a multiplexed MLVDS bus that supports preemption, sequential rotation, logical token ring, and broadcast mechanisms. Compared to the traditional MLVDS bus, the MLVDS bus system provided in the present application implements a communication architecture based on hardware circuit address matching. This allows point-to-point communication on the multiplexed bus without requiring other processor modules to participate in monitoring and decoding, thereby controlling the MLVDS driver chips of other processor modules to enter a low-power mode. Furthermore, because the processor modules participating in the point-to-point communication as child nodes use hardware address matching, they also do not need software decoding of message addresses and can directly receive data for processing. The response speed is achieved within 20ns for hardware-implemented wake-up communication, bringing the real-time performance of communication on the multiplexed bus to a new level.

[0096] Please refer to FIG4 , which is a flow chart of a method for controlling an MLVDS bus provided in an embodiment of the present application. The method for controlling an MLVDS bus is applied to the MLVDS bus system shown in FIG1 to FIG3 , and includes the following steps:

[0097] S100: Control the processor module to an initialization state, in which the MLVDS driver unit and the address bus processing unit of the processor module are in a waiting state;

[0098] S200: When the MLVDS data bus is in an idle state, applying for bus occupation through the status transceiver unit;

[0099] S300: After the application is successful, the target address is sent to the target processor module through the address bus processing unit. The target processor module matches and links with the processor module after the target address is successfully matched.

[0100] S400: The processor unit is communicatively connected to the target processor module via the MLVDS driver unit and the MLVDS data bus.

[0101] 1 to 4 , the control method of the MLVDS bus provided in the embodiment of the present application has the following specific implementation steps:

[0102] Step 1: All processor modules on the MLVDS bus system are in the initialization state. In the initialization state, the MLVDS driver unit of the processor module is in a low power consumption state, and the address bus processing unit is in a waiting state.

[0103] Step 2: One of the processor modules on the MLVDS bus system has data to send (denoted as processor module A). The communication target of processor module A is processor module B. Then, processor module A monitors the communication status of the MLVDS data bus through the status transceiver unit.

[0104] Step 3: When the MLVDS data bus is in an idle state, the processor module A applies to the transceiver control arbitration line to occupy the bus through the status transceiver unit;

[0105] Step 4: After the arbitration application is successfully occupied, processor module A wakes up the MLVDS driver unit through the processor unit and sends the target address (corresponding to the address data or broadcast address of processor module B) to the address bus through the address bus processing unit;

[0106] Step 5: The address bus processing unit on processor module B receives the target address from the address bus and matches it successfully. Processor module B wakes up its own MLVDS driver unit, thereby establishing data communication between processor module A and processor module B.

[0107] Step 6: After the communication between processor module A and processor module B is completed, all processor modules on the MLVDS bus system are reinitialized.

[0108] Please refer to FIG5 , which is a structural block diagram of a control device for an MLVDS bus provided in an embodiment of the present application. The control device for the MLVDS bus is applied to the MLVDS bus system shown in FIG1 to FIG3 , and the control device includes:

[0109] The initialization module 101 is used to control the processor module to be in an initialization state. In the initialization state, the MLVDS driving unit and the address bus processing unit of the processor module are in a waiting state.

[0110] The application module 102 is used to apply for bus occupation through the status transceiver unit when the MLVDS data bus is in an idle state;

[0111] Matching module 103, used for sending the target address to the target processor module through the address bus processing unit after the application is successful, and the target processor module is matched and linked with the processor module after the target address is successfully matched;

[0112] The communication module 104 is used for the processor unit to communicate with the target processor module through the MLVDS driver unit and the MLVDS data bus.

[0113] The present application also provides an electronic device. Please refer to Figure 6, which is a structural block diagram of an electronic device provided in an embodiment of the present application. The electronic device may include a processor 510, a communication interface 520, a memory 530, and at least one communication bus 540. Among them, the communication bus 540 is used to realize direct connection and communication between these components. Among them, the communication interface 520 of the electronic device in the embodiment of the present application is used to communicate signaling or data with other node devices. The processor 510 can be an integrated circuit chip with signal processing capabilities.

[0114] The processor 510 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor, or the processor 510 can also be any conventional processor.

[0115] The memory 530 may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory 530 stores computer-readable instructions. When the processor 510 executes the computer-readable instructions, the electronic device may perform the steps of the method embodiment of FIG. 4 .

[0116] Optionally, the electronic device may further include a storage controller and an input / output unit.

[0117] The memory 530, storage controller, processor 510, peripheral interface, and input / output units are electrically connected to each other directly or indirectly to enable data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses 540. The processor 510 is used to execute executable modules stored in the memory 530, such as software function modules or computer programs included in the electronic device.

[0118] The input and output unit is used to provide users with the ability to create tasks and to create optional time periods or preset execution times for the tasks to enable interaction between the user and the server. The input and output unit can be, but is not limited to, a mouse and a keyboard.

[0119] It is understood that the structure shown in Figure 6 is merely illustrative, and the electronic device may include more or fewer components than shown in Figure 6, or have a configuration different from that shown in Figure 6. Each component shown in Figure 6 may be implemented using hardware, software, or a combination thereof.

[0120] An embodiment of the present application further provides a storage medium having instructions stored thereon. When the instructions are run on a computer, the computer program is executed by a processor to implement the method described in the method embodiment. To avoid repetition, details are not given here.

[0121] The present application also provides a computer program product, which, when running on a computer, enables the computer to execute the method described in the method embodiment.

[0122] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0123] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0124] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0125] The foregoing is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0126] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0127] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

Claims

1. An MLVDS bus system, characterized in that: It includes an MLVDS data bus, a transceiver control arbitration line, an address bus and a processor component, wherein the processor component includes two or more processor modules, each of which includes a processor unit, an MLVDS driver unit, a state transceiver unit and an address bus processing unit; The MLVDS data bus is connected to the processor unit via the MLVDS driving unit; The transceiver control arbitration line is connected to the processor unit through the status transceiver unit; The address bus is connected to the processor unit through the address bus processing unit.

2. The MLVDS bus system according to claim 1, characterized in that: The processor module further includes an address logic processing unit, through which the MLVDS driving unit is connected to the address bus processing unit, the address logic processing unit is configured with address data of the processor module, and the address logic processing unit receives the target address through the address bus processing unit.

3. The MLVDS bus system according to claim 2, characterized in that: The address logic processing unit includes a multi-channel comparator, the multi-channel comparator is configured with address data of the processor module, and the multi-channel comparator is connected to the address bus.

4. The MLVDS bus system according to claim 3, characterized in that: The address bus is configured with a broadcast address control line, and the address logic processing unit further includes an OR logic processor, the input end of the OR logic processor is respectively connected to the broadcast address control line and the multi-channel comparator, and the output end of the OR logic processor is connected to the MLVDS driving unit.

5. The MLVDS bus system according to claim 4, characterized in that: The OR logic processor comprises a first OR logic processor and a second OR logic processor, the input end of the first OR logic processor is respectively connected to the broadcast address control line and the multi-channel comparator, and the output end of the first OR logic processor is connected to the input end of the second OR logic processor; The input end of the second or logic processor is also connected to the processor unit, and the output end of the second or logic processor is connected to the MLVDS driving unit.

6. The MLVDS bus system according to claim 1, characterized in that: The status transceiver unit applies to the transceiver control arbitration line for occupying the bus based on a preset arbitration mechanism.

7. The MLVDS bus system according to claim 1, characterized in that: The state transceiver unit applies to the transceiver control arbitration line to occupy the bus based on a preset sequence or a preset logic token ring mechanism.

8. The MLVDS bus system according to claim 7, characterized in that: The MLVDS driving unit includes two or more MLVDS driving chips, the MLVDS driving unit is connected to the processor unit and the MLVDS data bus respectively, and the two or more MLVDS driving chips are arranged in parallel.

9. A method for controlling an MLVDS bus, characterized in that: Applied to the MLVDS bus system according to any one of claims 1 to 8, the control method comprises: Controlling the processor module to be in an initialization state, in which the MLVDS driving unit and the address bus processing unit of the processor module are in a waiting state; When the MLVDS data bus is in an idle state, applying for bus occupation through the state transceiver unit; After the application is successful, the target address is sent to the target processor module through the address bus processing unit, and the target processor module matches and links with the processor module after the target address is successfully matched; The processor unit is communicatively connected with the target processor module via the MLVDS driving unit and the MLVDS data bus.

10. A control device for an MLVDS bus, characterized in that: Applicable to the MLVDS bus system according to any one of claims 1 to 8, the control device comprises: An initialization module, used for controlling the processor module to be in an initialization state, in which the MLVDS driving unit and the address bus processing unit of the processor module are in a waiting state; An application module for occupying the MLVDS data bus, used for applying for occupying the bus through the status transceiver unit when the MLVDS data bus is in an idle state; A matching module, used for sending the target address to the target processor module through the address bus processing unit after the application is successful, and the target processor module matches and links with the processor module after the target address is successfully matched; The communication module is used for the processor unit to communicate with the target processor module through the MLVDS driving unit and the MLVDS data bus.

11. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the MLVDS bus control method according to claim 9 when executing the computer program.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the computer executes the MLVDS bus control method according to claim 9 .

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