A gate-level netlist cross-clock domain automatic analysis method and system

By performing automated cross-clock domain analysis on gate-level netlists, the problem of difficulty in detecting cross-clock domain issues in existing technologies is solved, enabling early location and repair of design defects and improving product reliability.

CN115293084BActive Publication Date: 2026-07-17BEIJING XUANYU INFORMATION TECH CO LTD
View PDF 2 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
BEIJING XUANYU INFORMATION TECH CO LTD
Filing Date
2022-06-29
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

In existing technologies, cross-clock domain issues are not easily detected during the code design phase and product factory testing and experimentation, making it difficult to detect and fix metastable issues in the design in a timely manner, thus affecting product reliability.

Method used

By abstracting the simulation library files, extracting the gate-level netlist design structure, analyzing the clock tree and reset tree, identifying cross-clock domain behavior, matching fault modes, and displaying violation information, automated cross-clock domain analysis of the gate-level netlist is achieved.

Benefits of technology

It can detect and fix cross-clock domain issues during the code design phase, avoid device anomalies caused by metastability propagation, improve product reliability, and detect the effectiveness of synchronizers and the correctness of cross-clock domain paths.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN115293084B_ABST
    Figure CN115293084B_ABST
Patent Text Reader

Abstract

A gate-level netlist cross-clock domain automatic analysis method and system, through including simulation library automatic abstraction module, Verilog program analysis module, gate-level netlist clock tree and reset tree inference module, cross-clock domain feature identification module, violation display module, carries out Verilog language analysis, simulation library automatic abstraction, gate-level netlist clock tree inference, gate-level netlist reset tree inference, cross-clock domain feature circuit identification and violation display step, can analyze the cross-clock domain risk of programmable logic design gate-level netlist by the method of static analysis and accurately locate the design defects, improve the programmable logic design reliability.
Need to check novelty before this filing date? Find Prior Art