Method for reducing static power consumption in verification stage of digital chip physical design

Abstract

The application provides a method for reducing static power consumption in a verification stage of a digital chip physical design. In the verification stage of the digital chip physical design, in addition to optimizing power consumption on a data path, threshold voltage of a standard cell on a clock tree is lowered and a channel length is increased to further reduce static power consumption. The method saves a large amount of time cost without increasing additional chip area, and realizes 5%-10% reduction of static power consumption.

Description

Technical Field

[0001] This invention belongs to the field of digital chip physical design, and in particular, it is a method for reducing static power consumption during the verification stage of digital chip physical design. Background Technology

[0002] The total power consumption of a chip is divided into static power consumption and dynamic power consumption.

[0003] Dynamic power consumption can be further divided into switching power consumption and short-circuit power consumption. Switching power consumption is the power consumption generated by the charging and discharging of the load capacitor when a gate in a CMOS circuit switches, such as... Figure 1 As shown:

[0004] The switching power consumption can be expressed by the following formula:

[0005] P switch =αCV DD 2 f

[0006] α is called the activity factor, which is the probability that a circuit node transitions from 0 to 1. The activity factor for a clock is 1 because it has both a rise and a fall in each cycle. The activity factor for most data is 0.5, transitioning only once per cycle. C is called the load capacitance, V DD is the power supply voltage, and f is the operating frequency.

[0007] Short-circuit power consumption occurs when the input flips and the transistor is partially short-circuited and conducts. Ideally, CMOS transistors change instantaneously during flipping, with no delay. However, in actual circuits, a propagation delay exists, and it is not an ideal step signal, such as... Figure 2 As shown:

[0008] When V is satisfied thn <V in <V DD -|V thp At this time, both the pull-up and pull-down networks will be partially turned on simultaneously, forming a short-circuit current. Among them, V thn V is the threshold voltage of the NMOS transistor. thp V is the threshold voltage of the PMOS transistor. in The input signal is the signal itself. If the input signal's switching rate is slow, both networks will conduct simultaneously for a longer period, resulting in significant short-circuit power consumption. Increasing the load capacitance can effectively reduce short-circuit power consumption. In summary, this is the principle behind dynamic power consumption. Based on this, the main methods to reduce dynamic power consumption are as follows:

[0009] (1) Gated clock technology. By using a gated clock unit to cut off clock signals that are not constantly on, the flip-flops are reduced and the activity factor is reduced to near 0, which can greatly reduce dynamic power consumption.

[0010] (2) Reduce glitch generation. Reducing glitch generation will significantly lower the activity factor value and reduce dynamic power consumption.

[0011] (3) Multi-voltage domain technology. Dynamic power consumption has a square relationship with the power supply voltage. Different voltage values ​​are set for power supply networks in areas with different performance requirements. In low voltage areas, power consumption decreases in a square relationship.

[0012] (4) Dynamic Voltage Regulation (DVS) technology. The module voltage and power consumption are dynamically adjusted according to the task load. For tasks with low performance requirements, the clock frequency can be reduced to the minimum value sufficient to complete the task in the predetermined time, and the voltage can be reduced to the minimum value required to operate at that frequency, which can effectively reduce power consumption.

[0013] (5) Reduce frequency. Power consumption is directly proportional to frequency, and reducing the frequency can effectively reduce power consumption. However, this method will cause a decrease in performance and slow down the transmission rate, making it a double-edged sword.

[0014] Static power consumption, also known as leakage power consumption, is the power consumption caused by leakage current inside the transistor when the circuit is inactive or not in operation. Transistor leakage current can be mainly divided into: subthreshold leakage current Ik. sub (Sub-threshold Leakage), Gate Leakage Current I gate (Gate Leakage), Gate-induced drain current I GIDL (GateInduced Drain Leakage) and reverse-biased PN junction leakage current I REV (Reverse Bias Junction Leakage), such as Figure 3 As shown.

[0015] Subthreshold leakage current is one of the main sources of leakage current. The smaller the threshold voltage of a transistor, the larger the leakage current and the greater the static power consumption. With the continuous advancement of semiconductor technology, chip size is decreasing and gate thickness is decreasing, leading to a gradual increase in gate leakage current. Therefore, high-dielectric-constant dielectrics and finned field-effect transistors (FETs) are introduced to reduce gate leakage current. Currently, the main methods for reducing static power consumption are multi-threshold voltage technology, gated power supply technology, and body bias technology.

[0016] The clock tree can account for up to 30% of the power consumption of a chip, and reducing the power consumption of the clock tree can significantly reduce the overall power consumption of the chip. Because the standard cells in the clock tree need to perform many fast signal transitions, standard cells with low latency are generally chosen to construct the clock tree to quickly transmit clock signals. However, this results in an increase in static power consumption. Standard cells exhibit a trade-off between speed and power consumption, requiring designers to find a balance to achieve optimal timing and power efficiency.

[0017] Typically, the methods mentioned above for reducing static and dynamic power consumption need to be designed before placement and routing. Subsequent stages only require clearing remaining timing and physical rule violations, and reducing static power consumption by replacing the threshold voltage and channel length of standard cells on data paths with remaining timing margins. This invention, however, further reduces static power consumption by replacing standard cells on the clock tree during the verification stage. Summary of the Invention

[0018] The purpose of this invention is to solve the problem and provide a method for reducing static power consumption during the verification stage of digital chip physical design.

[0019] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0020] A method for reducing static power consumption during the verification phase of digital chip physical design. In the verification phase of digital chip physical design, in addition to optimizing the power consumption on the data path, the static power consumption is further reduced by lowering the threshold voltage of the standard cell on the clock tree and increasing the channel length.

[0021] As a preferred approach, static power consumption is reduced by using standard cells with different threshold voltages on different timing paths. LVT and SLVT standard cells are used on timing critical paths, while RVT and HVT standard cells are used on non-critical paths. The critical path refers to the timing path in synchronous logic circuits where combinational logic and routing delays are the largest and have a decisive impact on design performance. The remaining timing paths are considered non-critical paths.

[0022] Multi-threshold voltage devices are classified according to the magnitude of the threshold voltage into: high-threshold devices (Regular Voltage Threshold, abbreviated as HVT), standard-threshold devices (Regular Voltage Threshold, abbreviated as RVT), low-threshold devices (Low threshold device, abbreviated as LVT), and ultra-low-threshold devices (Super Low threshold device, abbreviated as SLVT); the relationship of their speeds is: HVT < RVT < LVT < SLVT, and the corresponding relationship of static power consumption is: HVT < RVT < LVT < SLVT; at the same time, the standard cell library also provides standard cells with different channel lengths. The longer the channel length, the slower the turn-on speed and the smaller the static power consumption; different combinations of different threshold voltages and different channel lengths form different standard cells, where the priority of the threshold voltage is higher than that of the channel length. That is, relatively speaking, the turn-on speed and power consumption of the LVT standard cell with a shorter channel length are smaller than those of the SLVT standard cell with a longer channel length. Different combinations of standard cells are selected during design to achieve a balance between speed and power consumption performance; during the placement and routing stage, the standard cells with the combination of SLVT and the shortest channel length are used to construct the clock tree. Its turn-on speed is the fastest, but the power consumption is also the largest. The use of SVT-type standard cells is prohibited in the rest to reduce static power consumption. As a preferred method, after completing the placement and routing work, select the version with the best data to complete the final verification, and then enter the verification stage; in this stage, the remaining timing violations and physical rule violations need to be cleared, and the static power consumption is reduced by changing the threshold voltage, channel length, and drive size of the standard cells on the data path with remaining timing margins.

[0023] As a preferred method, this method is used to further reduce the static power consumption of the chip in the physical design of digital chips when it has already entered the verification stage and does not support returning to the placement and routing stage again due to time requirements.

[0024] As a preferred method, all standard cells on the clock tree are found and replaced through the following steps:

[0025] (1) According to the description of the chip clock in the timing constraint file, confirm all clock input ports as the root nodes of the clock tree;

[0026] (2) By means of逐级扇出 (gradual fan-out), find all the standard cells on the timing paths starting from the root node of the clock tree, including the standard cells on the timing paths passing through the excitation clock sources created by the clock root node;

[0027] (3) Screen out the end points reached by the timing paths among all the standard cells found above, that is, the registers and macro cell modules among them. The remaining part is all the standard cells required on the clock tree;

[0028] It should be noted that the term "逐级扇出" in step (2) is a literal translation and may need to be adjusted according to the specific context for a more accurate and professional expression.(4) Replace the combination of threshold voltage and channel length of all standard cells on the clock tree found above with standard cells with lower power consumption in the standard cell library.

[0029] As a preferred method, the following steps are included:

[0030] (1) During the placement and routing phase, the standard cell with the fastest turn-on speed, namely the standard cell with SLVT and the shortest channel length combination, is used on the clock tree. The standard cell with SLVT is disabled on the data path to reduce power consumption.

[0031] (2) After completing the layout and wiring design, enter the verification stage and first fix signal integrity violations;

[0032] (3) Use multi-process analysis technology DMSA to repair setup time violations until the setup time timing requirements are met;

[0033] (4) Optimize power consumption by replacing the standard cell threshold voltage, channel length and drive size on the path with sufficient timing margin;

[0034] (5) Fan out the clock input ports according to the timing constraint file to find all standard units on the clock tree and filter out the registers and macro unit modules;

[0035] (6) Replace all standard cells in the clock tree obtained in the previous step with SLVT standard cells with longer channel lengths from the standard cell library using regular expression matching. This reduces static power consumption by 6% to 10% compared to before the replacement.

[0036] (7) Repair the remaining setup time violations until the setup time timing requirements are met; Since the static power consumption was reduced by sacrificing timing after replacing the standard cell on the clock tree in the previous step, the setup time violations need to be repaired again.

[0037] (8) Use multi-process analysis technology DMSA to repair hold time violations and make the timing meet the signing requirements; at this time, the static power consumption of data is reduced by 5% to 9% compared with the standard unit of the clock tree without replacing it, and the effect of reducing static power consumption is significant.

[0038] The beneficial effects of this invention are as follows: In the physical design of digital chips, in addition to optimizing power consumption on the data path during the verification stage, this invention further reduces static power consumption by lowering the threshold voltage of standard cells on the clock tree and increasing the channel length. This method saves a significant amount of time without increasing the chip area, achieving a 5% to 10% reduction in static power consumption. Attached Figure Description

[0039] Figure 1 It is the source of power consumption during CMOS inverter switching;

[0040] Figure 2 This is a schematic diagram of the short-circuit power consumption of a CMOS inverter;

[0041] Figure 3 This is a diagram showing the source of leakage current;

[0042] Figure 4 This is a graph showing the relationship between threshold voltage, static power consumption, and transistor delay.

[0043] Figure 5 This is a flowchart of the design process of this invention. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] Example 1

[0046] This embodiment provides a method for reducing static power consumption during the verification stage of digital chip physical design. In the verification stage of digital chip physical design, in addition to optimizing the power consumption on the data path, static power consumption is further reduced by lowering the threshold voltage of the standard cell on the clock tree and increasing the channel length.

[0047] Static power consumption is reduced by using standard cells with different threshold voltages on different timing paths. LVT and SLVT standard cells are used on timing critical paths, while RVT and HVT standard cells are used on non-critical paths. The critical path is the timing path in synchronous logic circuits with the largest combinational logic and routing delay, which has a decisive impact on design performance. The other timing paths are considered non-critical paths.

[0048] Multi-threshold voltage devices are classified according to the magnitude of the threshold voltage into: high-threshold devices Regular Voltage Threshold, abbreviated as HVT, standard-threshold devices Regular Voltage Threshold, abbreviated as RVT, low-threshold devices Lowthreshold device, abbreviated as LVT, and ultra-low-threshold devices Super Low threshold device, abbreviated as SLVT; the relationship of their speeds is: HVT < RVT < LVT < SLVT, and the corresponding relationship of static power consumption is: HVT < RVT < LVT < SLVT; at the same time, the standard cell library also provides standard cells with different channel lengths. The longer the channel length, the slower the turn-on speed and the smaller the static power consumption; different combinations of different threshold voltages and different channel lengths form different standard cells, where the priority of the threshold voltage is higher than that of the channel length, that is, relatively speaking, the turn-on speed and power consumption of the LVT standard cell with a shorter channel length are smaller than those of the SLVT standard cell with a longer channel length. Different combinations of standard cells are selected during design to achieve a balance between speed and power consumption performance; during the placement and routing stage, the clock tree is constructed using standard cells with the SLVT and shortest channel length combination. Its turn-on speed is the fastest, but the power consumption is also the largest. The use of SVT type standard cells is prohibited in the rest to reduce static power consumption. After completing the placement and routing work, select the version with the best data to complete the final verification, and then enter the verification stage; this stage needs to clear the remaining timing violations and physical rule violations, and reduce the static power consumption by changing the threshold voltage, channel length, and drive size of the standard cells on the data path with remaining timing margins.

[0049] This method is used to further reduce the static power consumption of a digital chip in the physical design when it is already in the verification stage and does not support returning to the placement and routing stage again due to time requirements.

[0050] This method finds all the standard cells on the clock tree and replaces them through the following steps:

[0051] (1) According to the description of the chip clock in the timing constraint file, confirm all the input ports of the clocks as the root nodes of the clock tree;

[0052] (2) By the way of fan-out level by level, find all the standard cells on the timing paths starting from the root nodes of the clock tree, including the standard cells on the timing paths passing through the excitation clock sources created by the clock root nodes;

[0053] (3) Screen out the end points reached by the timing paths among all the above-found standard cells, that is, the registers and macro cell modules among them. The remaining part is all the standard cells required on the clock tree;

[0054] (4) Replace the combination of threshold voltage and channel length of all standard cells on the clock tree found above with standard cells with lower power consumption in the standard cell library.

[0055] Example 2

[0056] This embodiment provides a method for reducing static power consumption during the verification phase of digital chip physical design, including the following steps:

[0057] (1) During the placement and routing phase, the standard cell with the fastest turn-on speed, namely the standard cell with SLVT and the shortest channel length combination, is used on the clock tree. The standard cell with SLVT is disabled on the data path to reduce power consumption.

[0058] (2) After completing the layout and wiring design, enter the verification stage and first fix signal integrity violations;

[0059] (3) Use multi-process analysis technology DMSA to repair setup time violations until the setup time timing requirements are met;

[0060] (4) Optimize power consumption by replacing the standard cell threshold voltage, channel length and drive size on the path with sufficient timing margin;

[0061] (5) Fan out the clock input ports according to the timing constraint file to find all standard units on the clock tree and filter out the registers and macro unit modules;

[0062] (6) Replace all standard cells in the clock tree obtained in the previous step with SLVT standard cells with longer channel lengths from the standard cell library using regular expression matching. This reduces static power consumption by 6% to 10% compared to before the replacement.

[0063] (7) Repair the remaining setup time violations until the setup time timing requirements are met; Since the static power consumption was reduced by sacrificing timing after replacing the standard cell on the clock tree in the previous step, the setup time violations need to be repaired again.

[0064] (8) Use multi-process analysis technology DMSA to repair hold time violations and make the timing meet the signing requirements; at this time, the static power consumption of data is reduced by 5% to 9% compared with the standard unit of the clock tree without replacing it, and the effect of reducing static power consumption is significant.

[0065] Example 3

[0066] This embodiment uses multi-threshold voltage technology and multi-channel length technology to reduce static power consumption. As described in the technical background section of the specification, leakage current is the cause of static power consumption; the larger the leakage current, the greater the static power consumption. Subthreshold leakage current is a major component of static power consumption, and its calculation formula is as follows:

[0067]

[0068] Where μ is the mobility at room temperature; C OX It is a gate oxide capacitor; This is the thermal voltage (25.9mV at room temperature); W and L are the dimensions of the MOSFET; parameter n typically ranges from 1.0 to 2.5, depending on the device manufacturing process; V GS It is the gate-source voltage; V TH This is the threshold voltage. As can be seen from the above formula, the leakage current decreases exponentially with increasing threshold voltage, and the transistor's turn-on speed is inversely related to its power consumption. Figure 4 As shown:

[0069] Therefore, static power consumption is reduced by using standard cells with different threshold voltages on different timing paths. Standard cells with low threshold voltages are used on timing-critical paths, while standard cells with high threshold voltages are used on non-critical paths. This is the multi-threshold voltage technique.

[0070] In addition, different channel lengths also affect the threshold voltage, and a proper selection can also reduce static power consumption. In transistors with shorter channels, the low depletion region between the drain and source occupies most of the channel, making it easier to conduct, resulting in a lower threshold voltage and increased static power consumption. Conversely, in long-channel transistors, the effective channel length increases beyond the depletion region between the drain and source, making conduction more difficult, thus increasing the threshold voltage and decreasing static power consumption. Although long-channel standard cells result in a certain increase in area, their power reduction effect is significant.

[0071] This embodiment process provides three types of standard cells with different thresholds: RVT (Regular Voltage Threshold standard threshold device), LVT (Low threshold device), and SLVT (Super Low threshold device). It also provides two different channel lengths of 14nm and 16nm. Different thresholds and different channel lengths can be combined pairwise to obtain six different standard cells. The relationship of their speeds is: RVT_C16 < RVT_C14 < LVT_C16 < LVT_C14 < SLVT_C16 < SLVT_C14, and the corresponding relationship of static power consumption is: RVT_C16 < RVT_C14 < LVT_C16 < LVT_C14 < SLVT_C16 < SLVT_C14. Therefore, the standard cell of SLVT_C14 is used to construct the clock tree. It has the fastest startup speed but also the largest power consumption. The use of SVT type standard cells is prohibited in other parts to reduce static power consumption. The above steps need to be set during the placement and routing stage, adjust the layout, and select the optimal version of data to complete the final verification. At this time, it enters the verification stage. This stage needs to clear the remaining timing violations and physical rule violations. The static power consumption can be reduced by changing the threshold voltage, channel length, and drive size of the standard cells on the data path with remaining timing margins, but the reduction of power consumption is relatively limited. In addition to the above common means, the present invention further reduces the static power consumption by appropriately increasing the threshold voltage or increasing the channel length of the standard cells on the clock tree during the verification stage.

[0072] The following takes the module of Samsung's 11nm process as an example for technical explanation:

[0073] During the placement and routing stage, the fastest (SLVT_C14) standard cell is used to create the clock tree on the clock tree. The 14 in SLVT_C14 represents the channel length, and SLVT represents the lowest threshold voltage. The standard cells of SLVT are disabled on the data path to reduce power consumption;

[0074] After completing the placement and routing design and entering the verification stage, first repair the violations in the signal integrity part, including crosstalk, noise, and minimum period violations;

[0075] (1) Use the multi-process analysis technology DMSA to repair the setup time violations until the setup time timing requirements are basically met;

[0076] (2) Optimize the power consumption and change the threshold voltage, channel length, and drive size of the standard cells on the path with sufficient timing margins.

[0077] (3) Based on the clock tree root node defined in the timing constraint file, create_clock-name*-period*[get_ports"*"], find all standard cells on the clock tree. This invention uses a fan-out method of all_fanout-from[get_ports{clock_port}]-flat-only_cells-continue_trace generated_clock_source to obtain all standard cells on the clock tree, and filters out registers through -filter"design_type==lib_cell&&ref_name!~*DF*".

[0078] (4) Use the `size_cell` command to change the type of all standard cells in the clock tree obtained in the previous step to SLVT_C16, such as `size_cell BUF_X3N_*SL_C14 BUF_X3N_*SL_C16`. Only the channel length is changed in this case. The power consumption changes after the change are as follows: compared to before the change, the power consumption of SLVT_C14 is reduced. The timing results and power comparison are as follows:

[0079] Table 1 shows the timing violations for the SLVT_C14 standard cell on the clock tree.

[0080]

[0081] Table 2: Timing Violations When Replacing Clock Tree with SLVT_C16 Standard Cells

[0082]

[0083] Table 3. Comparison of power consumption before and after optimization.

[0084] Leakage Dynamic Total SLVT_C14(tc_ctypical_setup) 8.098e-04 0.0616 0.06240 SLVT_C16(tc_ctypical_setup) 7.484e-04 0.0616 0.06234

[0085] As can be seen, compared with SLVT_C14, the setup time remains basically unchanged, the hold time worsens, clock crosstalk and other issues are not increased, and the static power consumption is reduced by 7.5%.

[0086] (1) Repair the remaining setup time violations until the setup time timing requirements are basically met. Since the impact of replacing the standard cell on the clock tree in the previous step on the setup time is small, the increase in power consumption caused by repairing setup time violations in this step is not significant.

[0087] (2) The hold-time violation was repaired using the multi-process analysis technique DMSA. Timing results and power consumption comparison are as follows:

[0088] Table 4 shows the timing violations for the SLVT_C14 standard cell on the clock tree after the hold time was repaired.

[0089]

[0090] Table 5 shows the timing violations after fixing the hold time and replacing the clock tree with the SLVT_C16 standard cell.

[0091]

[0092] Table 6. Power Consumption Comparison After Repair Retention Time

[0093] Leakage / Mw Dynamic / Mw Total / Mw SLVT_C14(tc_ctypical_setup) 7.502e-04 0.0616 0.06235 SLVT_C16(tc_ctypical_setup) 6.981e-04 0.0616 0.06229

[0094] As can be seen, although there are still a few timing violations, the timing results of SLVT_C14 and SLVT_C16 are basically the same. Compared with SLVT_C14, the optimized static power consumption is reduced by 6.9%. Therefore, the method proposed in this invention is effective in reducing static power consumption during the verification stage.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for reducing static power consumption during the verification phase of digital chip physical design, characterized in that: In the physical design of digital chips, in addition to optimizing the power consumption on the data path during the verification phase, static power consumption is further reduced by lowering the threshold voltage of the standard cell on the clock tree and increasing the channel length. Static power consumption is reduced by using standard cells with different threshold voltages on different timing paths. LVT and SLVT standard cells are used on timing critical paths, while RVT and HVT standard cells are used on non-critical paths. The critical path is the timing path in synchronous logic circuits with the largest combinational logic and routing delay, which has a decisive impact on design performance. The other timing paths are considered non-critical paths. Multi-threshold voltage devices are classified according to their threshold voltage magnitude: High Threshold (HVT), Standard Threshold (RVT), Low Threshold (LVT), and Super Low Threshold (SLVT). Their speed relationships are: HVT < RVT < LVT < SLVT, and their static power consumption relationships are: HVT < RVT < LVT < SLVT. SLVT; The standard cell library also provides standard cells with different channel lengths. The longer the channel length, the slower the turn-on speed and the lower the static power consumption. Different threshold voltages and different channel lengths are combined in pairs to form different standard cells. The threshold voltage has higher priority than the channel length. That is, the turn-on speed and power consumption of a shorter channel length LVT standard cell are relatively lower than those of a longer channel length SLVT standard cell. Different combinations of standard cells are selected during the design to achieve a balance between speed and power consumption performance. During the placement and routing stage, the clock tree is constructed using standard cells with the combination of SLVT and the shortest channel length, which has the fastest turn-on speed but also the highest power consumption. The use of SVT type standard cells is prohibited in other parts to reduce static power consumption.

2. The method for reducing static power consumption during the verification stage of digital chip physical design according to claim 1, characterized in that: After completing the layout and routing work, select the version with the best data to complete the final verification, which is the verification stage. In this stage, the remaining timing violations and physical rule violations need to be cleared. Static power consumption is reduced by replacing the threshold voltage, channel length and drive size of the standard cells on the data path with remaining timing margin.

3. The method for reducing static power consumption during the verification stage of digital chip physical design according to claim 1, characterized in that: This method is used in digital chip physical design where the chip is already in the verification stage and time constraints prevent a return to the placement and routing stage, thus further reducing the chip's static power consumption.

4. The method for reducing static power consumption during the verification stage of digital chip physical design according to claim 1, characterized in that: Locate and replace all standard cells on the clock tree using the following steps: (1) Based on the description of the chip clock in the timing constraint file, identify the input ports of all clocks and use them as the root node of the clock tree; (2) By fanning out step by step, find all standard cells on the timing path from the root node of the clock tree, including standard cells on the timing path that passes through the excitation clock source created by the root node of the clock tree. (3) Filter out the endpoints reached by the timing path from all the standard units found above, namely the registers and macro unit modules. The remaining part is all the standard units on the required clock tree. (4) Replace the combination of threshold voltage and channel length of all standard cells on the clock tree found above with standard cells with lower power consumption in the standard cell library.

5. The method for reducing static power consumption during the verification stage of digital chip physical design according to claim 1, characterized in that... The steps include the following: (1) During the placement and routing phase, the standard cell with the fastest turn-on speed, namely the standard cell with SLVT and the shortest channel length combination, is used on the clock tree. The standard cell with SLVT is disabled on the data path to reduce power consumption. (2) After completing the layout and wiring design, proceed to the verification stage and first fix signal integrity violations; (3) Use multi-process analysis technology DMSA to repair setup time violations until the setup time timing requirements are met; (4) Optimize power consumption by replacing the threshold voltage, channel length, and drive size of the standard cell on the path with sufficient timing margin; (5) Based on the clock input ports defined in the timing constraint file, fan out level by level to find all standard units on the clock tree, and filter out the registers and macro unit modules among them; (6) Replace all standard cells in the clock tree obtained in the previous step with SLVT standard cells with longer channel lengths from the standard cell library using regular expression matching. This reduces static power consumption by 6% to 10% compared to before the replacement. (7) Repair the remaining setup time violations until the setup time timing requirements are met; Since the static power consumption was reduced by sacrificing timing after replacing the standard cell on the clock tree in the previous step, the setup time violations need to be repaired again. (8) Use multi-process analysis technology DMSA to repair hold time violations and make the timing meet the approval requirements; at this time, the data static power consumption is reduced by 5% to 9% compared with the standard cell without changing the clock tree.

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