Method, system, and storage medium for processor clock tree deskewing and timing optimization

Abstract

This invention relates to a method, system, and storage medium for processor clock tree deskewing and timing optimization. The method for processor clock tree deskewing and timing optimization, through joint timing and topology analysis, automatic candidate copy object identification, and topology-aware logical copying and connection reconstruction, can effectively reduce the fan-out delay of critical signals and achieve clock tree load balancing and deskewing without modifying the RTL code during the back-end design process. At the same time, iterative optimization ensures timing convergence and logical equivalence, thereby improving the efficiency of processor physical design.

Description

Technical Field

[0001] This invention relates to the field of processor back-end design technology, and in particular to a method, system and storage medium for processor clock tree deskewing and timing optimization. Background Technology

[0002] As semiconductor processes evolve towards advanced nodes of 7 nanometers and below, processor physical design faces numerous severe challenges. The complexity of backend control logic increases dramatically, with single control signals often needing to drive a large number of functional units. Signal connections across modules and physical regions are increasing, timing margins are continuously shrinking, and path delay sensitivity is significantly enhanced. Among these challenges, the large fan-out signal problem is particularly prominent. When a single logic node drives multiple downstream resistor-capacitor (RC) loads, the output load increases significantly, leading to prolonged signal switching delays. Furthermore, multiple subsequent timing paths share this driving source, making it a common bottleneck across multiple paths. During Clock Tree Synthesis (CTS), high fan-out clock gating signals or enable signals can also cause load imbalances in downstream clock branches, introducing significant clock skew, increasing the difficulty of deskew correction, and severely restricting the increase of processor operating frequency.

[0003] Through long-term technological accumulation, the industry has developed a manually driven logic replication process, which is a mature practice in processor back-end design. Logic replication, as an effective means of distributing downstream load, reducing equivalent load, shortening signal delay, and balancing clock tree load, typically involves the following steps:

[0004] Use static timing analysis tools to generate timing reports. Engineers manually analyze reports to locate paths with large fan-out or negative timing margins; combined with placement and routing results, they determine whether certain logic needs to be replicated. Backtrack and manually modify the register transfer level (RTL) code to achieve logic replication at the source code level; resynthesize, place and route, and perform timing analysis again.

[0005] However, existing artificial drive solutions have significant technical drawbacks: First, it relies heavily on engineers' experience, and the interpretation of timing reports and physical layout depends entirely on manual intervention, resulting in unstable and unreproducible results. Secondly, the optimization iteration speed is slow. Each logic copy requires modification of RTL code and a complete backend process, which takes a long time. Third, it is difficult to perform large-scale optimization. When there are a large number of large fan-out or differential timing paths, manual analysis is difficult to cover them. Fourth, it is not adapted to the design requirements of advanced process nodes. In high-frequency, low-margin designs, manual methods become the main bottleneck for timing convergence, which seriously affects the efficiency and performance of processor design.

[0006] Therefore, it is necessary to propose a new method to solve the above-mentioned technical problems. Summary of the Invention

[0007] This invention provides a method, system, and storage medium for processor clock tree deskewing and timing optimization, aiming to solve the technical problems of existing clock tree optimization methods being reliant on manual labor and inefficient.

[0008] To address the aforementioned technical problems, in a first aspect, the present invention provides a method for processor clock tree deskewing and timing optimization, comprising the following steps: S101. Obtain the timing test report of the timing path in the processor to be optimized and parse it. Determine the timing parameters of the timing path based on the parsing results. Then, determine the large fan-out signal nodes that cause timing degradation and / or clock tree skew in the processor to be optimized based on the timing parameters. Analyze the timing path based on the large fan-out signal nodes and preset identification rules to obtain a set of candidate logic replication paths. S102. Based on each of the time-series paths in the candidate logical replication path set, perform topology analysis and physical region mapping analysis on the logical units associated with the large fan-out signal nodes therein to obtain the influence coefficient of each logical unit. Then, calculate the replication priority score of each logical unit based on the influence coefficient, and mark the logical units whose replication priority scores meet the preset threshold as target replication logical nodes. S103. Generate at least one logical replica that is functionally completely equivalent to the target replication logical node at the current netlist level of the processor to be optimized, and obtain the downstream load of the target replication logical node. According to the preset downstream load allocation rule, allocate the downstream load to the target replication logical node and its corresponding at least one logical replica to obtain the optimized netlist. S104. Perform timing analysis on the optimized netlist, obtain the optimized timing test report, and determine whether all timing paths in the optimized timing test report meet the preset timing convergence target and clock tree deskew target: if not, return to step S101; if yes, output the optimized netlist as the clock tree deskew and timing optimization result of the processor to be optimized.

[0009] Furthermore, in step S101, the timing parameters include at least one of the following: the fan-out number of the logical node, the delay of the timing path, and the timing margin of the timing path.

[0010] Furthermore, the preset identification rule in step S101 is specifically as follows: When the number of fan-outs of the logical node is greater than a first preset threshold and the timing margin of the timing path is less than a second preset threshold, the timing path is marked as a candidate logical replication path. When the timing margin of the timing path in which the logical node is located is negative, and the contribution ratio of the logical node to the delay of the timing path exceeds a preset ratio threshold, the timing path is marked as a candidate logical replication path.

[0011] Furthermore, the influence coefficient in step S102 includes the fan-out number of the logical node, the number of logical levels, and the latency contribution, and the replication priority score is a weighted score based on the influence coefficient; Specifically, the weights corresponding to different influence coefficients are determined based on the order of the number of fan-out nodes (from most to least), the number of logic levels (from front to back), and the delay contribution (from most to least).

[0012] Furthermore, the preset downstream load allocation rule in step S103 is specifically as follows: Based on the distribution of the physical regions where the downstream loads are located and / or the corresponding timing paths, the downstream loads are connected to at least one logical replica corresponding to the logical node in a grouping manner, wherein: The input side of each logical replica is consistent with the logical node, and the output side of each logical replica does not generate a new timing path.

[0013] Furthermore, the high fan-out signal node includes an enable signal node for the clock gating unit and a high fan-out reset signal node.

[0014] Secondly, the present invention also provides a method for processor clock tree deskewing and timing optimization, comprising: The timing analysis module is used to obtain and parse the timing test report of the timing path in the processor to be optimized, determine the timing parameters of the timing path based on the parsing results, and then determine the large fan-out signal nodes that cause timing degradation and / or clock tree skew in the processor to be optimized based on the timing parameters. The timing path is then analyzed based on the large fan-out signal nodes and preset identification rules to obtain a set of candidate logic replication paths. The logical replication module is used to perform topology analysis and physical region mapping analysis on each of the timing paths corresponding to the large fan-out signal nodes in the candidate logical replication path set, to obtain the influence coefficient of each logical unit, and then calculate the replication priority score of each logical unit based on the influence coefficient, and mark the logical units whose replication priority scores meet the preset threshold as target replication logical nodes. The load distribution module is used to generate at least one logical replica that is functionally completely equivalent to the target replication logical node at the current netlist level of the processor to be optimized, and to obtain the downstream load of the target replication logical node, and to distribute the downstream load to the target replication logical node and its corresponding at least one logical replica according to a preset downstream load distribution rule, so as to obtain the optimized netlist. The iteration module is used to perform timing analysis on the optimized netlist, obtain an optimized timing test report, and determine whether all timing paths in the optimized timing test report meet the preset timing convergence target and clock tree deskew target. If not, it returns to the timing analysis module; if so, it outputs the optimized netlist as the clock tree deskew and timing optimization result of the processor to be optimized.

[0015] Furthermore, the preset downstream load allocation rule is specifically as follows: Based on the distribution of the physical regions where the downstream loads are located and / or the corresponding timing paths, the downstream loads are connected to at least one logical replica corresponding to the logical node in a grouping manner, wherein: The input side of each logical replica is consistent with the logical node, and the output side of each logical replica does not generate a new timing path.

[0016] Thirdly, the present invention also provides a computer device, including: a memory, a processor, and a processor clock tree deskewing and timing optimization program stored in the memory and executable on the processor, wherein when the processor executes the processor clock tree deskewing and timing optimization program, it implements the steps of the processor clock tree deskewing and timing optimization method as described in any of the above embodiments.

[0017] Fourthly, the present invention also provides a storage medium storing a processor clock tree deskewing and timing optimization program, wherein when the processor executes the processor clock tree deskewing and timing optimization program, the processor clock tree deskewing and timing optimization program implements the steps of the processor clock tree deskewing and timing optimization method as described in any of the above embodiments.

[0018] The beneficial effects achieved by this invention are that it proposes a method for processor clock tree deskewing and timing optimization. This method, through joint timing and topology analysis, automatic candidate copy object identification, and topology-aware logical copying and connection reconstruction, can effectively reduce the fan-out delay of critical signals and achieve clock tree load balancing and deskewing without modifying the RTL code during the back-end design process. At the same time, iterative optimization ensures timing convergence and logical equivalence, thereby improving the efficiency of processor physical design. Attached Figure Description

[0019] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a flowchart of the steps of the processor clock tree deskipation and timing optimization method provided in the embodiments of the present invention; Figure 2 This is a schematic diagram of the system structure for processor clock tree deskipation and timing optimization provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0020] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0021] The specific embodiments / examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0022] Example 1 Please refer to Figure 1 , Figure 1 This is a flowchart illustrating the steps of a processor clock tree skew removal and timing optimization method provided in this embodiment of the invention. The processor clock tree skew removal and timing optimization method includes the following steps: S101. Obtain the timing test report of the timing path in the processor to be optimized and parse it. Determine the timing parameters of the timing path based on the parsing results. Then, determine the large fan-out signal nodes that cause timing degradation and / or clock tree skew in the processor to be optimized based on the timing parameters. Analyze the timing path based on the large fan-out signal nodes and preset identification rules to obtain a set of candidate logic replication paths.

[0023] Step S101 aims to complete timing data parsing, bottleneck node identification, and high-optimization-benefit path analysis based on the results of Static Timing Analysis (STA), avoiding aimless redundant optimization. In this embodiment of the invention, the timing test report is a report generated after analyzing the design netlist and physical implementation results using a static timing analysis tool during the design process of an existing processor circuit. This report is the core analysis file for processor backend timing convergence, and it fully records the electrical and timing characteristics of all timing paths in the gate-level netlist, providing standardized data input for subsequent quantitative analysis.

[0024] Specifically, the high fan-out signal node includes the enable signal node of the clock gating unit and the high fan-out reset signal node. Among them, the clock gating unit is the core unit of the low-power design of the clock tree. Its enable signal is usually a global control signal, and its fan-out range covers multiple clock branches. High fan-out will degrade the signal conversion delay, causing the effective clock edge of different clock branches to be offset, directly increasing the clock skew and destroying the clock tree balance. The reset signal is a global synchronous or asynchronous control signal for the processor, requiring a large number of trigger reset ports, making it a naturally high fan-out node. A large RC load will cause the reset signal to flip edge to become slower, which may cause reset path timing violations or register reset timing abnormalities.

[0025] In step S101, the timing parameters include at least one of the following: the fan-out number of the logical node, the delay of the timing path, and the timing margin of the timing path.

[0026] The fan-out number of a logic node refers to the total number of input ports of the lower-level logic units electrically connected to the signal node. The fan-out number directly determines the equivalent RC load of the node. The higher the fan-out number, the more significant the degradation of signal switching delay and transition time. It is the core topology parameter for determining large load bottlenecks.

[0027] Timing path delay is composed of the inherent delay of all standard cells on the path and the interconnect RC delay. In advanced processes, the proportion of interconnect delay is significantly increased, making it a key component of the total path delay.

[0028] The timing margin (Slack) of a timing path refers to the difference between the actual delay of the timing path and the target delay of the constraint. A positive value indicates that the path meets the timing constraints, while a negative value indicates that there is a timing violation. The smaller the absolute value of the margin, the higher the timing risk of the path. It is a direct indicator for judging the timing stress of the path.

[0029] The preset recognition rules are as follows: When the fan-out number of the logical node is greater than a first preset threshold and the timing margin of the timing path is less than a second preset threshold, the timing path is marked as a candidate logical replication path. This rule aims to determine the high-load topology risk of nodes and the timing margin of paths, and combined with screening for paths with potential timing degradation risks, to achieve proactive preventative optimization. When the timing margin of the timing path in which the logical node is located is negative, and the contribution ratio of the logical node to the delay of the timing path exceeds a preset threshold, the timing path is marked as a candidate logical replication path. This rule clarifies the objectively defined rigid timing violations, indicating that logical nodes conforming to the rule are the main cause of path violations.

[0030] S102. For each time-series path in the candidate logical replication path set, perform topology analysis and physical region mapping analysis on the logical units associated with the large fan-out signal nodes therein to obtain the influence coefficient of each logical unit. Then, calculate the replication priority score of each logical unit based on the influence coefficient, and mark the logical units whose replication priority scores meet the preset threshold as target replication logical nodes.

[0031] Step S102 aims to conduct multi-dimensional quantitative evaluation of the associated logical units based on the candidate logical replication paths selected in step S101, and lock the target replication object with the highest optimization benefit through weighted scoring and sorting, so as to avoid resource redundancy and timing disturbance problems caused by indiscriminate logical replication.

[0032] Specifically, step S102 first performs topology analysis and physical region mapping analysis on the logic units associated with the large fan-out signal node. The topology analysis is based on the connection relationships in the circuit netlist, and the core analysis content during the implementation process includes, but is not limited to: The hierarchical position of the logic unit in the timing path, and the input / output branch structure; The fan-out topology of the logic unit is used to determine whether it is a global fan-out type, a regional fan-out type, or other topological characteristics. Extract the number of logic levels from the logic unit to the timing endpoint in the path to clarify the link characteristics of signal transmission.

[0033] Physical region mapping analysis combines the physical layout results from the placement and routing phase to associate logic cells, timing paths, and chip physical layout regions. The core analysis content during implementation includes, but is not limited to: Locate the coordinates of the logic unit in the chip layout to determine its physical partition, such as the core computing domain, memory domain, or clock tree distribution domain; Identify the physical distribution characteristics of downstream loads and distinguish between layouts where loads are concentrated in a single physical area and those spanning multiple physical areas. Evaluate the increase in interconnect RC parasitic parameters caused by cross-physical region connections to determine the aggravating effect of physical layout on timing degradation.

[0034] Furthermore, when determining the impact coefficient, the influence of the logic unit on timing degradation and clock tree skew is quantified from three dimensions: topology, path level, and timing hazard. The impact coefficient in step S102 includes the fan-out number, logic level, and latency contribution of the logic node. The replication priority score is a weighted score based on the impact coefficient.

[0035] Specifically, the fan-out number of a logic node refers to the total number of input ports of the lower-level logic units driven by the output node of that logic unit. The higher the fan-out number, the larger the equivalent RC load of the node, and the more significant the degradation of signal inversion delay and transition time. The logic level refers to the number of standard logic units connected in series from the logic unit to the end of the timing path. The earlier the logic level, the more the delay fluctuation of the unit will be transmitted and amplified at each level, affecting the entire downstream timing link and having a wider global impact on timing convergence. The delay contribution refers to the proportion of the sum of the delay of the logic unit itself and the delay of its interconnection in the total delay of the entire timing path. The higher the proportion, the more prominent the timing benefit of optimizing the unit is, indicating that the unit is the core bottleneck point causing insufficient timing margin and negative timing violations in the path.

[0036] In this embodiment of the invention, the weights corresponding to different influence coefficients are determined according to the order of the number of fan-outs of the logical nodes (from most to least), the order of the number of logical levels (from front to back), and the order of the delay contribution (from most to least).

[0037] Subsequently, quantitative screening is achieved by setting a preset threshold for replication priority scores: logic units with scores higher than the preset threshold are marked as target replication logic nodes. The preset threshold is a configurable engineering parameter that can be flexibly adjusted according to process nodes, timing constraints, chip power consumption, and area redundancy to achieve a balance between optimization benefits and design costs. The selected nodes provide precise operation targets for subsequent netlist-level logic replication.

[0038] S103. At least one logical replica that is functionally equivalent to the target replication logical node is generated at the current netlist level of the processor to be optimized, and the downstream load of the target replication logical node is obtained. According to the preset downstream load allocation rules, the downstream load is allocated to the target replication logical node and its corresponding at least one logical replica to obtain the optimized netlist.

[0039] Step S103 is divided into two parts: netlist-level logic reconstruction and load balancing execution. It aims to complete logic replication and downstream load redistribution at the gate-level netlist level without modifying the upstream RTL code, skipping the RTL resynthesis process, and shortening the optimization iteration cycle. Then, load sharing alleviates the high RC load and signal conversion time degradation caused by large fan-out, while strictly constraining the topology change boundary to avoid introducing new logic and timing risks, and outputting an optimized netlist for subsequent layout, routing, and timing analysis.

[0040] Specifically, in this embodiment of the invention, the object of the logic copy operation is the gate-level netlist, that is, the standard cell-level interconnection netlist output after logic synthesis. This operation only modifies the connection and instantiation relationship of the gate-level circuit, without having to backtrack and modify the RTL source code of the design, nor with having to re-execute logic synthesis. This is a lightweight means of implementing the back-end physical design stage in this embodiment of the invention.

[0041] The logical replica and the target replicated logical node must meet the following requirements: consistent Boolean logic function, consistent timing behavior characteristics, consistent standard cell type, and consistent driving capability. They can be determined as equivalent nodes in the Logic Equivalence Check (LEC) to avoid functional errors from the root. The number of replicas is determined based on the fan-out scale of the original node and the physical distribution of downstream loads. It is usually one or more, with the goal of achieving load balancing and distribution.

[0042] Downstream load refers to all the input ports of the lower-level logic units directly driven by the output port of the target replication logic node. Generally, the processor circuit contains various standard units such as flip-flops, combinational logic gates, and clock gating units.

[0043] The key load information to be extracted in this step includes: the physical coordinates of the cell corresponding to the load, the physical partition of the chip to which it belongs, the timing path of the load, the timing constraints, and the input capacitor load value, so as to provide a quantitative basis for subsequent grouping and allocation.

[0044] In this embodiment of the invention, the allocation of downstream loads is based on the core principles of physical proximity and timing consistency, adapting to the characteristics of high line delay and strong timing sensitivity in advanced processes. The preset downstream load allocation rule in step S103 is specifically as follows: Based on the distribution of the physical regions where the downstream loads are located and / or the corresponding timing paths, the downstream loads are connected to at least one logical replica corresponding to the logical node in a grouping manner, wherein: The input side of each logical replica is consistent with the logical node, and the output side of each logical replica does not generate a new timing path.

[0045] The grouping methods described in the embodiments of this invention can be differentiated according to actual needs. The main purpose is to balance the number of driving loads and the equivalent total RC capacitance between the original node and each logical replica. For example: Grouping by physical region: In back-end design, the interconnect length directly determines the RC parasitic parameters and line delay. Grouping downstream loads in the same physical sub-region and clock tree coverage area into a group and connecting them to the same logical replica can shorten the interconnect length from the driver to the load, reduce line delay and crosstalk risk, alleviate local wiring congestion, and balance the physical load distribution of different replicas.

[0046] Grouping by timing path distribution: Grouping downstream loads of the same critical timing path and clock domain into one group to avoid splitting the load of a single critical path and maintain the link integrity of the original timing path; at the same time, it ensures that the timing pressure of each replica-driven timing path is similar, helps to balance the load of clock tree branches and reduce clock skew.

[0047] In this embodiment of the invention, downstream load allocation has constraints on both the input and output sides. The input signal network, driver source, timing constraints, and port interconnections of the logical replica are completely identical to those of the original node, ensuring that the phase and delay characteristics of the replica's input signals are consistent with those of the original node. This does not alter the input-side circuit topology and timing behavior, guaranteeing both logical functional equivalence and preventing the introduction of new timing violations on the input side. Since the timing path is uniquely defined by the start and end points, the connection relationship between the output side and the existing downstream loads is preserved. No new timing path start and end points are added, the start and end units of the original timing path are not changed, the timing path analysis set remains unchanged, no new timing analysis dimensions are added, and the introduction of uncontrollable new timing violations is avoided, while maintaining the stability of the timing constraint system.

[0048] The final optimized netlist retains all the logical functions of the original design. This embodiment of the invention optimizes the circuit topology and load distribution only through logic replication and load redistribution, and can be used in the subsequent design process of placement and routing, timing analysis, and physical verification.

[0049] S104. Perform timing analysis on the optimized netlist, obtain the optimized timing test report, and determine whether all timing paths in the optimized timing test report meet the preset timing convergence target and clock tree deskew target: if not, return to step S101; if yes, output the optimized netlist as the clock tree deskew and timing optimization result of the processor to be optimized.

[0050] Step S104 aims to construct a closed-loop verification and process convergence decision-making mechanism for optimization effects. It quantifies the optimization effect after logic replication and load refactoring in S103 through standardized timing analysis. Using preset design objectives (preset timing convergence objectives and clock tree deskew objectives) as criteria, it determines whether to iterate or terminate the output. During implementation, this step replaces the inefficient traditional manual analysis and iteration model with automated verification and closed-loop iteration. This ensures the objectivity and reproducibility of the optimization effect judgment and adapts to the high-frequency, low-timing-margin design characteristics of advanced processes, thereby improving timing convergence efficiency and design reliability.

[0051] The beneficial effects achieved by this invention are that it proposes a method for processor clock tree deskewing and timing optimization. This method, through joint timing and topology analysis, automatic candidate copy object identification, and topology-aware logical copying and connection reconstruction, can effectively reduce the fan-out delay of critical signals and achieve clock tree load balancing and deskewing without modifying the RTL code during the back-end design process. At the same time, iterative optimization ensures timing convergence and logical equivalence, thereby improving the efficiency of processor physical design.

[0052] Example 2 This invention also provides a system 200 for processor clock tree deskipation and timing optimization. Please refer to [link / reference]. Figure 2 , Figure 2 This is a schematic diagram of the system structure for processor clock tree deskipation and timing optimization provided in an embodiment of the present invention, which includes: The timing analysis module 201 is used to obtain and parse the timing test report of the corresponding timing path in the processor to be optimized, determine the timing parameters of the timing path based on the parsing results, then determine the large fan-out signal nodes that cause timing degradation and / or clock tree skew in the processor to be optimized based on the timing parameters, and analyze the timing path based on the large fan-out signal nodes and preset identification rules to obtain a set of candidate logic replication paths. The logical replication module 202 is used to perform topology analysis and physical region mapping analysis on each of the timing paths in the candidate logical replication path set and the logical units associated with the large fan-out signal nodes therein, to obtain the influence coefficient of each logical unit. Then, based on the influence coefficient, the replication priority score of each logical unit is calculated, and the logical units whose replication priority scores meet the preset threshold are marked as target replication logical nodes. The load distribution module 203 is used to generate at least one logical replica that is functionally completely equivalent to the target replication logical node at the current netlist level of the processor to be optimized, and to obtain the downstream load of the target replication logical node, and to distribute the downstream load to the target replication logical node and its corresponding at least one logical replica according to a preset downstream load distribution rule, so as to obtain an optimized netlist. The iteration module 204 is used to perform timing analysis on the optimized netlist, obtain an optimized timing test report, and determine whether all timing paths in the optimized timing test report meet the preset timing convergence target and clock tree deskew target. If not, it returns to the timing analysis module 201; if yes, it outputs the optimized netlist as the clock tree deskew and timing optimization result of the processor to be optimized.

[0053] Furthermore, the preset downstream load allocation rule is specifically as follows: Based on the distribution of the physical regions where the downstream loads are located and / or the corresponding timing paths, the downstream loads are connected to at least one logical replica corresponding to the logical node in a grouping manner, wherein: The input side of each logical replica is consistent with the logical node, and the output side of each logical replica does not generate a new timing path.

[0054] The system 200 can implement the steps in the processor clock tree deskipation and timing optimization method in the above embodiments, and can achieve the same technical effect. Referring to the description in the above embodiments, it will not be repeated here.

[0055] Example 3 This invention also provides a computer device, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a processor clock tree deskewing and timing optimization program stored in the memory 302 and executable on the processor 301.

[0056] The processor 301 calls the processor clock tree deskewing and timing optimization program stored in the memory 302, and executes the steps in the processor clock tree deskewing and timing optimization method provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps: S101. Obtain the timing test report of the timing path in the processor to be optimized and parse it. Determine the timing parameters of the timing path based on the parsing results. Then, determine the large fan-out signal nodes that cause timing degradation and / or clock tree skew in the processor to be optimized based on the timing parameters. Analyze the timing path based on the large fan-out signal nodes and preset identification rules to obtain a set of candidate logic replication paths.

[0057] The high fan-out signal node includes the enable signal node of the clock gating unit and the high fan-out reset signal node.

[0058] In step S101, the timing parameters include at least one of the following: the number of fan-outs of the logical node, the delay of the timing path, and the timing margin of the timing path.

[0059] The preset recognition rules are as follows: When the number of fan-outs of the logical node is greater than a first preset threshold and the timing margin of the timing path is less than a second preset threshold, the timing path is marked as a candidate logical replication path. When the timing margin of the timing path in which the logical node is located is negative, and the contribution ratio of the logical node to the delay of the timing path exceeds a preset ratio threshold, the timing path is marked as a candidate logical replication path.

[0060] S102. For each time-series path in the candidate logical replication path set, perform topology analysis and physical region mapping analysis on the logical units associated with the large fan-out signal nodes therein to obtain the influence coefficient of each logical unit. Then, calculate the replication priority score of each logical unit based on the influence coefficient, and mark the logical units whose replication priority scores meet the preset threshold as target replication logical nodes.

[0061] The influence coefficient in step S102 includes the fan-out number of the logical node, the number of logical levels, and the latency contribution. The replication priority score is a weighted score based on the influence coefficient. Specifically, the weights corresponding to different influence coefficients are determined based on the order of the number of fan-out nodes (from most to least), the number of logic levels (from front to back), and the delay contribution (from most to least).

[0062] S103. At least one logical replica that is functionally equivalent to the target replication logical node is generated at the current netlist level of the processor to be optimized, and the downstream load of the target replication logical node is obtained. According to the preset downstream load allocation rules, the downstream load is allocated to the target replication logical node and its corresponding at least one logical replica to obtain the optimized netlist.

[0063] The preset downstream load allocation rule in step S103 is specifically as follows: Based on the distribution of the physical regions where the downstream loads are located and / or the corresponding timing paths, the downstream loads are connected to at least one logical replica corresponding to the logical node in a grouping manner, wherein: The input side of each logical replica is consistent with the logical node, and the output side of each logical replica does not generate a new timing path.

[0064] S104. Perform timing analysis on the optimized netlist, obtain the optimized timing test report, and determine whether all timing paths in the optimized timing test report meet the preset timing convergence target and clock tree deskew target: if not, return to step S101; if yes, output the optimized netlist as the clock tree deskew and timing optimization result of the processor to be optimized.

[0065] The computer device 300 provided in this embodiment of the invention can implement the steps in the processor clock tree deskipation and timing optimization method as described in the above embodiments, and can achieve the same technical effect. Referring to the description in the above embodiments, it will not be repeated here.

[0066] Example 4 This invention also provides a storage medium storing a program for processor clock tree deskewing and timing optimization. When the processor executes the program, it implements the various processes and steps of the processor clock tree deskewing and timing optimization method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0067] Those skilled in the art will understand that implementing all or part of the processes in the above embodiments can be accomplished by hardware related to processor clock tree deskipation and timing optimization programs or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0068] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0069] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0070] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A method for processor clock tree deskewing and timing optimization, characterized in that, Includes the following steps: S101. Obtain the timing test report of the timing path in the processor to be optimized and parse it. Determine the timing parameters of the timing path based on the parsing results. Then, determine the large fan-out signal nodes that cause timing degradation and / or clock tree skew in the processor to be optimized based on the timing parameters. Analyze the timing path based on the large fan-out signal nodes and preset identification rules to obtain a set of candidate logic replication paths. S102. Based on each of the time-series paths in the candidate logical replication path set, perform topology analysis and physical region mapping analysis on the logical units associated with the large fan-out signal nodes therein to obtain the influence coefficient of each logical unit. Then, calculate the replication priority score of each logical unit based on the influence coefficient, and mark the logical units whose replication priority scores meet the preset threshold as target replication logical nodes. S103. Generate at least one logical replica that is functionally completely equivalent to the target replication logical node at the current netlist level of the processor to be optimized, and obtain the downstream load of the target replication logical node. According to the preset downstream load allocation rule, allocate the downstream load to the target replication logical node and its corresponding at least one logical replica to obtain the optimized netlist. S104. Perform timing analysis on the optimized netlist, obtain the optimized timing test report, and determine whether all timing paths in the optimized timing test report meet the preset timing convergence target and clock tree deskew target: if not, return to step S101; if yes, output the optimized netlist as the clock tree deskew and timing optimization result of the processor to be optimized.

2. The method for processor clock tree deskewing and timing optimization according to claim 1, characterized in that, In step S101, the timing parameters include at least one of the following: the fan-out number of the logical node, the delay of the timing path, and the timing margin of the timing path.

3. The method for processor clock tree deskewing and timing optimization according to claim 2, characterized in that, The preset identification rule in step S101 is specifically as follows: When the number of fan-outs of the logical node is greater than a first preset threshold and the timing margin of the timing path is less than a second preset threshold, the timing path is marked as a candidate logical replication path. When the timing margin of the timing path in which the logical node is located is negative, and the contribution ratio of the logical node to the delay of the timing path exceeds a preset ratio threshold, the timing path is marked as a candidate logical replication path.

4. The method for processor clock tree deskewing and timing optimization according to claim 1, characterized in that, The influence coefficient in step S102 includes the fan-out number of the logical node, the number of logical levels, and the latency contribution. The replication priority score is a weighted score based on the influence coefficient. Specifically, the weights corresponding to different influence coefficients are determined based on the order of the number of fan-out nodes (from most to least), the number of logic levels (from front to back), and the delay contribution (from most to least).

5. The method for processor clock tree deskewing and timing optimization according to claim 1, characterized in that, The preset downstream load allocation rule in step S103 is specifically as follows: Based on the distribution of the physical regions where the downstream loads are located and / or the corresponding timing paths, the downstream loads are connected to at least one logical replica corresponding to the logical node in a grouping manner, wherein: The input side of each logical replica is consistent with the logical node, and the output side of each logical replica does not generate a new timing path.

6. The method for processor clock tree deskewing and timing optimization according to claim 1, characterized in that, The high fan-out signal node includes the enable signal node of the clock gating unit and the high fan-out reset signal node.

7. A system for processor clock tree deskewing and timing optimization, characterized in that, include: The timing analysis module is used to obtain and parse the timing test report of the timing path in the processor to be optimized, determine the timing parameters of the timing path based on the parsing results, and then determine the large fan-out signal nodes that cause timing degradation and / or clock tree skew in the processor to be optimized based on the timing parameters. The timing path is then analyzed based on the large fan-out signal nodes and preset identification rules to obtain a set of candidate logic replication paths. The logical replication module is used to perform topology analysis and physical region mapping analysis on each of the timing paths corresponding to the large fan-out signal nodes in the candidate logical replication path set, to obtain the influence coefficient of each logical unit, and then calculate the replication priority score of each logical unit based on the influence coefficient, and mark the logical units whose replication priority scores meet the preset threshold as target replication logical nodes. The load distribution module is used to generate at least one logical replica that is functionally completely equivalent to the target replication logical node at the current netlist level of the processor to be optimized, and to obtain the downstream load of the target replication logical node, and to distribute the downstream load to the target replication logical node and its corresponding at least one logical replica according to a preset downstream load distribution rule, so as to obtain the optimized netlist. The iteration module is used to perform timing analysis on the optimized netlist, obtain an optimized timing test report, and determine whether all timing paths in the optimized timing test report meet the preset timing convergence target and clock tree deskew target. If not, it returns to the timing analysis module. If so, output the optimized netlist as the clock tree deskewing and timing optimization result of the processor to be optimized.

8. The processor clock tree deskewing and timing optimization system according to claim 7, characterized in that, The preset downstream load allocation rule is as follows: Based on the distribution of the physical regions where the downstream loads are located and / or the corresponding timing paths, the downstream loads are connected to at least one logical replica corresponding to the logical node in a grouping manner, wherein: The input side of each logical replica is consistent with the logical node, and the output side of each logical replica does not generate a new timing path.

9. A computer device, characterized in that, include: The processor includes a memory, a processor, and a processor clock tree deskewing and timing optimization program stored in the memory and executable on the processor. When the processor executes the processor clock tree deskewing and timing optimization program, it implements the steps of the processor clock tree deskewing and timing optimization method as described in any one of claims 1-6.

10. A storage medium, characterized in that, The storage medium stores a program for processor clock tree deskewing and timing optimization. When the processor executes the program for processor clock tree deskewing and timing optimization, it implements the steps in the method for processor clock tree deskewing and timing optimization as described in any one of claims 1-6.

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