Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a plurality of scan lines and at least one pull-down unit. The plurality of scan lines are arranged at intervals along a first direction; the pull-down circuit is connected with an nth scan line, and is used for pulling down the potential of the nth scan line; the pull-down circuit comprises a forward scan pull-down unit and / or a reverse scan pull-down unit; the forward scan pull-down unit is connected with the nth scan line and is connected with an nth+m level scan signal, a first control signal and a reference low-level signal; the reverse scan pull-down unit is connected with the nth scan line and is connected with an nth-m level scan signal, a second control signal and the reference low-level signal; n and m are both integers greater than zero, n is greater than or equal to 2, and n is greater than m. The application can improve the falling edge uniformity of the scan signal in the display panel, increase the charging time of the pixel and avoid incorrect charging, and meet the requirements of forward scanning and reverse scanning of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Gate Driver On Array (GOA) technology integrates gate driver circuitry onto the display panel's array substrate to achieve progressive scanning. This drive technology eliminates the need for a gate driver, reducing production costs and enabling narrow-bezel panel designs. It is used by a variety of displays.

[0003] As the size of the display panel increases and the resolution improves, the RC loading (resistance-capacitance load) of the scan line continues to increase, and the transmission loss of the scan signal output by the GOA increases, resulting in a serious deterioration of the falling edge of the scan signal, reducing the pixel charging time and increasing the risk of pixel mischarging. Summary of the Invention

[0004] The present application provides a display panel and a display device to solve the technical problems of serious deterioration of the falling edge of a scanning signal, reduced pixel charging time, and increased risk of pixel mischarging due to RC loading.

[0005] The present application provides a display panel, comprising:

[0006] A plurality of scanning lines, wherein the plurality of scanning lines are arranged at intervals along a first direction;

[0007] at least one pull-down circuit connected to the n-th scan line, the pull-down circuit being used to pull down the potential of the n-th scan line;

[0008] In which, the pull-down circuit includes a forward scan pull-down unit and / or a reverse scan pull-down unit; the forward scan pull-down unit is connected to the n+mth level scan signal, the first control signal and the reference low-level signal, and is connected to the nth scan line; the reverse scan pull-down unit is connected to the nmth level scan signal, the second control signal and the reference low-level signal, and is connected to the nth scan line; n and m are both integers greater than zero, and n≥2, n>m.

[0009] Optionally, in some embodiments of the present application, the positive scan pull-down unit includes a first transistor and a second transistor;

[0010] Among them, the gate of the first transistor is connected to one of the n+m-th level scanning signal and the first control signal, the source of the first transistor is connected to the drain of the second transistor, and the drain of the first transistor is connected to the n-th scanning line; the gate of the second transistor is connected to the other of the n+m-th level scanning signal and the first control signal, and the source of the second transistor is connected to the reference low-level signal.

[0011] Optionally, in some embodiments of the present application, the reverse sweep pull-down unit includes a third transistor and a fourth transistor;

[0012] Among them, the gate of the third transistor is connected to one of the nm-th level scanning signal and the second control signal, the source of the third transistor is connected to the drain of the fourth transistor, and the drain of the third transistor is connected to the nth scanning line; the gate of the fourth transistor is connected to the other of the nm-th level scanning signal and the second control signal, and the source of the fourth transistor is connected to the reference low-level signal.

[0013] Optionally, in some embodiments of the present application, the display panel has a display area, and the pull-down circuit is arranged in the display area.

[0014] Optionally, in some embodiments of the present application, the display panel includes a plurality of pull-down circuits, each of the pull-down circuits is connected to one of the scan lines, and each of the scan lines is connected to at least one of the pull-down circuits.

[0015] Optionally, in some embodiments of the present application, the pull-down circuits corresponding to two adjacent scan lines are arranged in an interlaced manner along the first direction.

[0016] Optionally, in some embodiments of the present application, along the direction in which the scan lines extend, the display panel further has a first non-display area and a second non-display area located on both sides of the display area; the display panel further includes a first GOA circuit and a second GOA circuit, the first GOA circuit being disposed in the first non-display area, and the second GOA circuit being disposed in the second non-display area;

[0017] Each of the scan lines is connected to two pull-down circuits. Along the extending direction of the scan lines, the pull-down circuits connected to the odd-numbered scan lines are located between the pull-down circuits connected to the even-numbered scan lines.

[0018] Optionally, in some embodiments of the present application, the display panel further includes at least one first control signal line and at least one second control signal line, the first control signal line is used to transmit the first control signal, and the second control signal line is used to transmit the second control signal; the first control signal line and the second control signal line both extend along the first direction, and each of the pull-down circuits is respectively connected to the first control signal line and the second control signal line.

[0019] Optionally, in some embodiments of the present application, along the direction in which the scan line extends, the display panel has a display area and a first non-display area and a second non-display area located on both sides of the display area; the display panel also includes a first GOA circuit, the first GOA circuit is located in the first non-display area, and the pull-down circuit is located in the second non-display area.

[0020] Correspondingly, the present application also provides a display device, which includes a display panel and a driving device. The display panel is any one of the display panels described above, and the driving device outputs the first control signal and the second control signal to the display panel.

[0021] The present application provides a display panel and a display device. The display panel includes a plurality of scan lines and at least one pull-down unit. The plurality of scan lines are arranged at intervals along a first direction; the pull-down circuit is connected to the nth scan line, and the pull-down circuit is used to pull down the potential of the nth scan line; wherein the pull-down circuit includes a forward scan pull-down unit and / or a reverse scan pull-down unit; the forward scan pull-down unit is connected to the n+mth level scan signal, the first control signal and the reference low-level signal, and is connected to the nth scan line; the reverse scan pull-down unit is connected to the nmth level scan signal, the second control signal and the reference low-level signal, and is connected to the nth scan line; n and m are both integers greater than zero, and n≥2, n>m. The present application can further pull down the potential of the nth scan line by setting a pull-down circuit connected to the nth scan line in the display panel, thereby improving the uniformity of the falling edge of the scan signal in the display panel, increasing the charging time of the pixel and avoiding mischarging. In addition, since the pull-down circuit can include both a forward scanning pull-down unit and a reverse scanning pull-down unit, the display panel can realize forward scanning and reverse scanning, meeting the application scenarios where the same screen is compatible with both face-up and flip-up mounting. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a first structural schematic diagram of a display panel provided in this application;

[0024] Figure 2 It is a structural diagram of the pull-down circuit provided by this application;

[0025] Figure 3 This is a signal timing diagram of the existing display panel provided by this application when it is working;

[0026] Figure 4 This is a signal timing diagram of the display panel provided by this application when it is working;

[0027] Figure 5 is a first circuit diagram of a pull-down circuit provided by the present application;

[0028] Figure 6 yes Figure 5 The signal timing diagram of the pull-down circuit shown in FIG. 1 is when the display panel is scanning in the forward direction;

[0029] Figure 7 yes Figure 5 The signal timing diagram of the pull-down circuit shown in FIG. 1 when the display panel is reversely scanned;

[0030] Figure 8 is a second circuit diagram of the pull-down circuit provided by this application;

[0031] Figure 9 is a second structural schematic diagram of the display panel provided by this application;

[0032] Figure 10 is a third circuit diagram of the pull-down circuit provided by this application;

[0033] Figure 11 yes Figure 10 The signal timing diagram of the pull-down circuit shown in FIG. 1 is when the display panel is scanning in the forward direction;

[0034] Figure 12 yes Figure 10 The signal timing diagram of the pull-down circuit shown in FIG. 1 when the display panel is reversely scanned;

[0035] Figure 13 is a fourth circuit diagram of the pull-down circuit provided by the present application;

[0036] Figure 14 is a third structural schematic diagram of the display panel provided by this application;

[0037] Figure 15 This is a structural schematic diagram of the display device provided in this application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0039] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first" and "second" etc. may explicitly or implicitly include one or more of the said features, and therefore cannot be understood as limitations on the present application. In addition, it should be noted that, unless otherwise clearly specified and defined, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] The present application provides a display panel and a display device, which are described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.

[0041] See also Figure 1 and Figure 2 , Figure 1 is a first structural schematic diagram of a display panel provided in this application; Figure 2 In the embodiment of the present application, the display panel 100 includes a plurality of scan lines 20 and at least one pull-down circuit 10 .

[0042] The plurality of scan lines 20 are arranged at intervals along the first direction Y. For example, along the first direction Y, the plurality of scan lines 20 are respectively the first scan line G1, the second scan line G2, the third scan line G3, the fourth scan line G4, the n-1th scan line Gn-1, the nth scan line Gn, the n+1th scan line Gn+1, the n+2th scan line Gn+2, etc., which are not described in detail here.

[0043] The pull-down circuit 10 is connected to the n-th scan line Gn and is used to pull down the potential of the n-th scan line Gn.

[0044] Specifically, the pull-down circuit 10 includes a forward scan pull-down unit 11 and / or a reverse scan pull-down unit 12. The forward scan pull-down unit 11 receives the n+mth level scan signal G(n+m), the first control signal U2D, and the reference low-level signal VGL, and is connected to the nth scan line Gn. The reverse scan pull-down unit 12 receives the nmth level scan signal G(nm), the second control signal D2U, and the reference low-level signal VGL, and is connected to the nth scan line Gn. Wherein, n and m are both integers greater than zero, and n≥2, n>m.

[0045] By providing a pull-down circuit 10 connected to the nth scan line Gn in the display panel 100, the embodiment of the present application can further pull down the potential of the nth scan line Gn, thereby improving the falling edge uniformity of the scan signal within the display panel 100, increasing the charging time of the pixels, and preventing incorrect charging. Furthermore, because the pull-down circuit 10 can include both a forward-scanning pull-down unit 11 and a reverse-scanning pull-down unit 12, the display panel 100 can implement both forward and reverse scanning, meeting the requirements for both flip-up and face-down mounting applications on the same screen.

[0046] Of course, in some embodiments of the present application, when the display panel 100 performs only forward scanning or only reverse scanning, the pull-down circuit 10 may include only the forward scanning pull-down unit 11 or only the reverse scanning pull-down unit 12 to meet the requirements of the screen being mounted upright or inverted.

[0047] For details, please refer to Figure 3 and Figure 4 , Figure 3 This is a signal timing diagram of the existing display panel provided by this application when it is working; Figure 4 This is a signal timing diagram of the display panel provided by the present application when it is working. The present application embodiment is described by taking m=1 as an example, but this should not be understood as limiting the present application.

[0048] like Figure 3As shown, the scanning signals of each level are turned on line by line. For example, when the (n - 1)-th level scanning signal G(n - 1) changes from the high potential VGH to the low potential VGL, the n-th level scanning signal G(n) changes from the low potential VGL to the high potential VGH; when the n-th level scanning signal G(n) changes from the high potential VGH to the low potential VGL, the (n + 1)-th level scanning signal G(n + 1) changes from the low potential VGL to the high potential VGH. However, as the size of the display panel increases and the resolution improves, the RC Loading of the scanning line 20 continuously increases, and the transmission loss of the scanning signal increases, resulting in serious deterioration of the falling edges of the scanning signals of each level. For example, when the (n - 1)-th level scanning signal G(n - 1) changes from the high potential VGH to the low potential VGL, the (n - 1)-th level scanning signal G(n - 1) has a first falling edge t1; when the n-th level scanning signal G(n) changes from the high potential VGH to the low potential VGL, the n-th level scanning signal G(n) has a second falling edge t2. The slopes of the falling edge t1 and the falling edge t2 are relatively gentle, indicating that the pull-down of the (n - 1)-th level scanning signal G(n - 1) and the n-th level scanning signal G(n) from the high potential VGH to the low potential VGL is relatively slow.

[0049] As Figure 4 shown, in the embodiment of the present application, when the n-th level scanning signal G(n) changes from the high potential VGH to the low potential VGL, under the action of the (n + 1)-th level scanning signal G(n + 1), the first control signal U2D, the (n - 1)-th level scanning signal G(n - 1), and the second control signal D2U, the pull-down circuit 10 further pulls down the n-th level scanning signal G(n); at this time, the (n + 1)-th level scanning signal G(n + 1) has a third falling edge t4. Similarly, when the (n - 1)-th level scanning signal G(n - 1) changes from the high potential VGH to the low potential VGL, the pull-down circuit 10 further pulls down the potential of the (n - 1)-th level scanning signal G(n - 1); at this time, the n-th level scanning signal G(n) has a fourth falling edge t3. The durations of the third falling edge t4 and the fourth falling edge t3 are shorter, and the pull-down is relatively rapid.

[0050] It can be known that t3 = t4 < t1 = t2. That is, in the embodiment of the present application, under the action of the pull-down circuit 10, the potential of the n-th scanning line Gn can be further pulled down, effectively reducing the falling edges of the scanning signals of each level.

[0051] In the embodiment of the present application, the pull-down circuit 10 can be arranged in the display area of the display panel 100 or in the non-display area of the display panel 100, and can be specifically set according to the specification requirements of the display panel 100.

[0052] For example, in some embodiments of the present application, the display panel 100 has a display area AA. Multiple scanning lines 20 are arranged in the display area AA. The pull-down circuit 10 is also arranged in the display area AA.

[0053] In the embodiment of the present application, the pull-down circuit 10 is integrated into the display area AA, so that the frame of the display panel 100 can be effectively reduced, thereby facilitating a narrow frame.

[0054] In the embodiment of the present application, the display panel 100 may include a plurality of pull-down circuits 10. Each pull-down circuit 10 is connected to a scan line 20. Each scan line 20 is connected to at least one pull-down circuit 10 to achieve uniformity in the falling edge of the scan signal on each scan line 20. Figure 1 The number and position of the pull-down circuits 10 shown in the figure are only examples and should not be construed as limiting the present application.

[0055] Specifically, in the embodiment of the present application, the pull-down circuits 10 corresponding to two adjacent scan lines 20 are arranged in an alternating manner along the first direction Y. For example, when each scan line 20 is connected to a pull-down circuit 10, the multiple pull-down circuits 10 connected to the odd-numbered scan lines 20 are arranged in one column along the first direction Y, and the multiple pull-down circuits 10 connected to the even-numbered scan lines 20 are arranged in another column along the first direction Y.

[0056] It is understandable that due to the pixel circuits (not shown) also being disposed within the display area AA of the display panel 100, the wiring space within the display area AA is limited. In the embodiment of the present application, the pull-down circuits 10 corresponding to two adjacent scan lines 20 are staggered to effectively utilize the wiring space within the display area AA, while also improving the uniformity of the distribution of the multiple pull-down circuits 10 within the surface, thereby avoiding affecting the display image of the display panel 100.

[0057] In the embodiment of the present application, the display panel 100 may further include a GOA circuit. Specifically, when the display panel 100 adopts single-sided driving, the display panel 100 may include only the first GOA circuit 31 or the second GOA circuit 32; when the display panel 100 adopts double-sided driving, the display panel 100 may include both the first GOA circuit 31 and the second GOA circuit 32. This application does not specifically limit this.

[0058] The GOA circuit is used to generate scanning signals at each level and output the scanning signals to the corresponding scanning lines 20. For example, the GOA circuit is used to output the n-1th level scanning signal G(n-1) to the n-1th scanning line Gn-1, output the nth level scanning signal G(n) to the nth scanning line Gn, and output the n+1th level scanning signal G(n+1) to the n+1th scanning line Gn+1.

[0059] Specifically, in the embodiment of the present application, when the display panel 100 adopts dual-sided drive, the display panel 100 further includes a first non-display area NA1 and a second non-display area NA2 located on either side of the display area AA along the direction in which the scan lines 20 extend. The first GOA circuit 31 is disposed in the first non-display area NA1, and the second GOA circuit 32 is disposed in the second non-display area NA2.

[0060] In an embodiment of the present application, the pull-down circuit 10 can be connected to the scan signal output end of the GOA circuit (not shown in the figure) to access the n+mth level scan signal G(n+m) and the nmth level scan signal G(nm).

[0061] Of course, the pull-down circuit 10 can also be connected to the corresponding scan line 20 to receive the n+m-th level scan signal G(n+m) and the nm-th level scan signal G(nm). Figure 1 As shown, the pull-down circuit 10 is connected to the n-th scan line Gn, and can be connected to the n-th level scan signal G(n), which will not be described in detail here.

[0062] It should be noted that the display panel 100 typically charges pixels using a row-by-row scanning method. Therefore, when the n-th level scan signal G(n) is a high-level signal, the n-1-th level scan signal G(n-1) needs to be pulled down; when the n+1-th level scan signal G(n+1) is a high-level signal, the n-th level scan signal G(n) needs to be pulled down. Therefore, a pull-down module is provided in both the first GOA circuit 31 and the second GOA circuit 32. The pull-down modules in the first GOA circuit 31 and the second GOA circuit 32 are independent of the pull-down circuit 10 in the present application, but are both used to pull down the corresponding scan signals.

[0063] In the embodiment of the present application, n and m are both integers greater than zero. The value of n can be determined based on the driving architecture of the display panel 100 and the number of scan lines. The value of m can be determined based on the cascade relationship between the GOA units in the GOA circuit (the first GOA circuit 31 / the second GOA circuit 32). For example, m can be 1, 2, 3, 4, etc., which will not be repeated here.

[0064] It should be noted that Figure 1 The embodiment of the present application is described by taking m=1 as an example, but this should not be construed as limiting the present application.

[0065] In the embodiment of the present application, the display panel 100 further includes at least one first control signal line 41 and at least one second control signal line 42. The first control signal line 41 is used to transmit a first control signal U2D. The second control signal line 42 is used to transmit a second control signal D2U. Both the first control signal line 41 and the second control signal line 42 extend along a first direction Y, and each pull-down circuit 10 is connected to the first control signal line 41 and the second control signal line 42, respectively.

[0066] When multiple pull-down circuits 10 are arranged in multiple columns along the extending direction of the scan lines 20, a first control signal line 41 and a second control signal line 42 can be provided for each column of pull-down circuits 10. Alternatively, a first control signal line 41 and a second control signal line 42 can be provided between two adjacent columns of pull-down circuits 10, with the pull-down circuits 10 in the two adjacent columns being connected to the same first control signal line 41 and the same second control signal line 42. This can streamline the wiring in the display panel 100 and prevent signal crosstalk.

[0067] It should be noted that the reference low-level signal VGL is also a signal required within the display panel 100, and the pull-down circuit 10 can be connected to the transmission line of the original reference low-level signal VGL within the display panel 100. Of course, additional signal lines can also be provided to transmit the reference low-level signal VGL required by the pull-down circuit 10.

[0068] In some embodiments of the present application, each scan line 20 may be connected to two pull-down circuits 10. Along the extension direction of the scan lines 20, the pull-down circuits 10 connected to the odd-numbered scan lines 20 are located between the pull-down circuits 10 connected to the even-numbered scan lines 20.

[0069] On the one hand, when the display panel 100 is large, the scan lines 20 extend longer, resulting in greater RC loading. This can lead to different transmission waveforms of the scan signals on the same scan line 20, resulting in uneven falling edges of the scan signals. In the embodiment of the present application, by connecting each scan line 20 to two pull-down circuits 10, the potential of the scan line 20 can be pulled down at different locations on the scan line 20. Combined with the pull-down effects of the first GOA circuit 31 and the second GOA circuit 32, the falling edge uniformity of the scan signals within the display panel 100 can be further improved.

[0070] On the other hand, by placing the pull-down circuits 10 connected to the odd-numbered scan lines 20 between the pull-down circuits 10 connected to the even-numbered scan lines 20 , the wiring within the plane can be regularized, thereby improving the utilization of the wiring space.

[0071] Furthermore, the display panel 100 further includes a first connection line 43 and a second connection line 44. The first connection line 43 and the second connection line 44 extend in the same direction as the scan line 20. The first connection line 43 and the second connection line 44 can be disposed in the display area AA or in the non-display area of ​​the lower frame of the display panel 100.

[0072] It is understood that when the display panel 100 includes multiple first control signal lines 41 and multiple second control signal lines 42, the first connecting lines 43 are connected to the multiple first control signal lines 41, and the second connecting lines 44 are connected to the multiple second control signal lines 42. Thus, the first control signal U2D can be transmitted to the multiple first control signal lines 41 through the first connecting lines 43, and the second control signal D2U can be transmitted to the multiple second control signal lines 42 through the second connecting lines 44.

[0073] See also Figure 2 and Figure 5 , Figure 5 1 is a first circuit diagram of a pull-down circuit provided by the present application. In some embodiments of the present application, the positive scan pull-down unit 11 includes a first transistor T1 and a second transistor T2.

[0074] The gate of the first transistor T1 is connected to the n+mth level scan signal G(n+m). The source of the first transistor T1 is connected to the drain of the second transistor T2. The drain of the first transistor T1 is connected to the nth scan line Gn. The gate of the second transistor T2 is connected to the first control signal U2D. The source of the second transistor T2 is connected to the reference low-level signal VGL.

[0075] When m=1, the gate of the first transistor T1 receives the n+1th level scanning signal G(n+1). The forward scanning pull-down unit 11 is used to pull down the potential of the nth scanning line Gn when the display panel 100 performs forward scanning.

[0076] Furthermore, in the embodiment of the present application, the reverse scan pull-down unit 12 includes a third transistor T3 and a fourth transistor T4.

[0077] The gate of the third transistor T3 is connected to the nm-th level scan signal G(nm). The source of the third transistor T3 is connected to the drain of the fourth transistor T4. The drain of the third transistor T3 is connected to the n-th scan line Gn. The gate of the fourth transistor T4 is connected to the second control signal D2U. The source of the fourth transistor T4 is connected to the reference low-level signal VGL.

[0078] When m=1, the gate of the third transistor T3 receives the n-1th level scanning signal G(n-1). The reverse scan pull-down unit 12 is used to pull down the potential of the nth scan line Gn when the display panel 100 performs reverse scanning.

[0079] It should be noted that the transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other pole is called the drain. According to the form in the accompanying drawings, the middle end of the switching transistor is specified as the gate, the signal input end is the source, and the output end is the drain. In addition, the transistors used in the embodiments of the present application may include P-type transistors and / or N-type transistors, wherein the P-type transistor is turned on when the gate is low and is cut off when the gate is high, and the N-type transistor is turned on when the gate is high and is cut off when the gate is low.

[0080] In addition, the transistors in the following embodiments of the present application are all described using N-type transistors as an example, but this should not be understood as a limitation to the present application.

[0081] See also Figure 5 and Figure 6 . Figure 6 yes Figure 5 The pull-down circuit shown in the figure shows a signal timing diagram during forward scanning of the display panel. During forward scanning, the first control signal U2D remains high, turning on the second transistor T2; the second control signal D2U remains low, turning off the fourth transistor T4. That is, during forward scanning, the forward-scan pull-down unit 11 is in operation, while the reverse-scan pull-down unit 12 is inoperative.

[0082] When the GOA circuit outputs a high-level n-th scan signal G(n) to the n-th scan line Gn, the pixels connected to the n-th scan line Gn begin to charge. Next, when the GOA circuit outputs a high-level n+1-th scan signal G(n+1) to the n+1-th scan line Gn+1, the pixels connected to the n+1-th scan line Gn+1 begin to charge. When the n+1-th scan signal G(n+1) is high, the first transistor T1 turns on, and the reference low-level signal VGL is transmitted to the n-th scan line Gn via the second transistor T2 and the first transistor T1, thereby further pulling down the potential of the n-th scan line Gn, improving the falling edge uniformity of the scan signal on the n-th scan line Gn, increasing the pixel charging time, and avoiding mischarging.

[0083] See also Figure 5 and Figure 7 , Figure 7 yes Figure 5The pull-down circuit shown in the figure shows a signal timing diagram during reverse scanning of the display panel. During reverse scanning, the first control signal U2D remains low, turning off the second transistor T2; the second control signal D2U remains high, turning on the fourth transistor T4. In other words, during reverse scanning, the forward-scanning pull-down unit 11 is inactive, while the reverse-scanning pull-down unit 12 is active.

[0084] When the GOA circuit outputs a high-level n-th scan signal G(n) to the n-th scan line Gn, the pixels connected to the n-th scan line Gn begin to charge. Next, when the GOA circuit outputs a high-level n-1-th scan signal G(n-1) to the n-1-th scan line Gn-1, the pixels connected to the n-1-th scan line Gn-1 begin to charge. When the n-1-th scan signal G(n-1) is high, the third transistor T3 turns on, and the reference low-level signal VGL is transmitted to the n-th scan line Gn via the fourth transistor T4 and the third transistor T3, thereby further pulling down the potential of the n-th scan line Gn, improving the falling edge uniformity of the scan signal on the n-th scan line Gn, increasing the pixel charging time, and avoiding mischarging.

[0085] See also Figure 8 , Figure 8 This is a second circuit diagram of the pull-down circuit provided by this application. Figure 5 The pull-down circuit 10 shown differs in at least one aspect: in the embodiment of the present application, the gate of the first transistor T1 receives the first control signal U2D. The source of the first transistor T1 is connected to the drain of the second transistor T2. The drain of the first transistor T1 is connected to the nth scan line Gn. The gate of the second transistor T2 receives the n+mth level scan signal G(n+m). The source of the second transistor T2 receives the reference low-level signal VGL.

[0086] When m=1, the gate of the second transistor T2 receives the n+1th level scanning signal G(n+1). The forward scanning pull-down unit 11 is used to pull down the potential of the nth scanning line Gn when the display panel 100 performs forward scanning.

[0087] In addition, the gate of the third transistor T3 is connected to the second control signal D2U. The source of the third transistor T3 is connected to the drain of the fourth transistor T4. The drain of the third transistor T3 is connected to the nth scan line Gn. The gate of the fourth transistor T4 is connected to the nmth level scan signal G(nm). The source of the fourth transistor T4 is connected to the reference low-level signal VGL.

[0088] When m=1, the gate of the third transistor T3 receives the n-1th level scanning signal G(n-1). The reverse scan pull-down unit 12 is used to pull down the potential of the nth scan line Gn when the display panel 100 performs reverse scanning.

[0089] It should be noted that Figure 8 The signal timing diagram of the pull-down circuit 10 shown is similar to Figure 5 The signal timing diagram of the pull-down circuit 10 is the same as that shown, and will not be repeated here.

[0090] See also Figure 9 , Figure 9 : is a second structural diagram of the display panel provided by this application. Figure 1 The difference between the display panel 100 shown is that, in the embodiment of the present application, m = 2. For example, when the pull-down circuit 10 is connected to the n+1th scan line Gn+1 to pull down the potential of the n+1th scan line Gn+1, the pull-down circuit 10 is connected to the n-1th scan line Gn-1 to receive the n-1th level scan signal G(n-1); at the same time, the pull-down circuit 10 is connected to the n+3th scan line Gn+3 to receive the n+3th level scan signal G(n+3).

[0091] See also Figure 10 , Figure 10 This is a third circuit diagram of the pull-down circuit provided by the present application. In this embodiment of the present application, the gate of the first transistor T1 is connected to the n+2-th level scan signal G(n+2). The source of the first transistor T1 is connected to the drain of the second transistor T2. The drain of the first transistor T1 is connected to the n-th scan line Gn. The gate of the second transistor T2 is connected to the first control signal U2D. The source of the second transistor T2 is connected to the reference low-level signal VGL.

[0092] The gate of the third transistor T3 is connected to the n-2th level scan signal G(n-2). The source of the third transistor T3 is connected to the drain of the fourth transistor T4. The drain of the third transistor T3 is connected to the nth scan line Gn. The gate of the fourth transistor T4 is connected to the second control signal D2U. The source of the fourth transistor T4 is connected to the reference low-level signal VGL.

[0093] See also Figure 10 and Figure 11 . Figure 11 yes Figure 10 The pull-down circuit shown in the figure shows a signal timing diagram during forward scanning of the display panel. During forward scanning, the first control signal U2D remains high, turning on the second transistor T2; the second control signal D2U remains low, turning off the fourth transistor T4. That is, during forward scanning, the forward-scan pull-down unit 11 is in operation, while the reverse-scan pull-down unit 12 is inoperative.

[0094] When the GOA circuit outputs a high-level n-th scan signal G(n) to the n-th scan line Gn, the pixels connected to the n-th scan line Gn begin to charge. Next, when the GOA circuit outputs a high-level n+2-th scan signal G(n+2) to the n+2-th scan line Gn+2, the pixels connected to the n+2-th scan line Gn+2 begin to charge. When the n+2-th scan signal G(n+2) is high, the first transistor T1 turns on, and the reference low-level signal VGL is transmitted to the n-th scan line Gn via the second transistor T2 and the first transistor T1, thereby further pulling down the potential of the n-th scan line Gn, improving the falling edge uniformity of the scan signal on the n-th scan line Gn, increasing the pixel charging time, and avoiding mischarging.

[0095] See also Figure 10 and Figure 12 . Figure 12 yes Figure 10 The pull-down circuit shown in the figure shows a signal timing diagram during reverse scanning of the display panel. During reverse scanning, the first control signal U2D remains low, turning off the second transistor T2; the second control signal D2U remains high, turning on the fourth transistor T4. In other words, during reverse scanning, the forward-scanning pull-down unit 11 is inactive, while the reverse-scanning pull-down unit 12 is active.

[0096] When the GOA circuit outputs a high-level n-th scan signal G(n) to the n-th scan line Gn, the pixels connected to the n-th scan line Gn begin to charge. Next, when the GOA circuit outputs a high-level n-2-th scan signal G(n-2) to the n-2-th scan line Gn-2, the pixels connected to the n-2-th scan line Gn-2 begin to charge. When the n-2-th scan signal G(n-2) is high, the third transistor T3 turns on, and the reference low-level signal VGL is transmitted to the n-th scan line Gn via the fourth transistor T4 and the third transistor T3, thereby further pulling down the potential of the n-th scan line Gn, improving the falling edge uniformity of the scan signal on the n-th scan line Gn, increasing the pixel charging time, and avoiding mischarging.

[0097] See also Figure 13 , Figure 13 is a fourth circuit diagram of the pull-down circuit provided by this application. Figure 10 The pull-down circuit 10 shown differs in at least one embodiment of the present application, wherein the gate of the first transistor T1 receives the first control signal U2D. The source of the first transistor T1 is connected to the drain of the second transistor T2. The drain of the first transistor T1 is connected to the nth scan line Gn. The gate of the second transistor T2 receives the n+2th level scan signal G(n+2). The source of the second transistor T2 receives the reference low-level signal VGL.

[0098] In addition, the gate of the third transistor T3 is connected to the second control signal D2U. The source of the third transistor T3 is connected to the drain of the fourth transistor T4. The drain of the third transistor T3 is connected to the nth scan line Gn. The gate of the fourth transistor T4 is connected to the nmth level scan signal G(n-2). The source of the fourth transistor T4 is connected to the reference low-level signal VGL.

[0099] It should be noted that Figure 13 The signal timing diagram of the pull-down circuit 10 shown is similar to Figure 10 The signal timing diagram of the pull-down circuit 10 is the same as that shown, and will not be repeated here.

[0100] See also Figure 14 , Figure 14 is a third structural diagram of the display panel provided in this application. Figure 1 The difference between the display panel 100 shown is that, in the embodiment of the present application, the display panel 100 only includes the first GOA circuit 31. The first GOA circuit 31 is located in the first non-display area NA1. The pull-down circuit 10 is located in the second non-display area NA2.

[0101] The display panel 100 in the embodiment of the present application employs unilateral drive. Within a single scan line 20, the scan signal is transmitted from the first GOA circuit 31 in a direction away from the first GOA circuit 31. When the display panel 100 is large, the scan line 20 extends longer, resulting in greater RC loading. Transmission loss of the scan signal gradually increases along the direction of the scan line 20. After the first GOA circuit 31 pulls down the potential of the scan signal, the falling edge of the scan signal at various locations on the corresponding scan line 20 becomes uneven.

[0102] In the embodiment of the present application, a pull-down circuit 10 is provided in the second non-display area NA2. The pull-down circuit 10 and the first GOA circuit 31 can respectively pull down the potential of the scan line 20 at both ends of the scan line 20, thereby further improving the falling edge uniformity of the scan signal in the display panel 100 and avoiding pixel mischarging.

[0103] Accordingly, the present application further provides a display device. The display device includes a display panel. The display panel is the display panel 100 described in any of the above embodiments, which will not be described in detail here.

[0104] In addition, the display device can be a smart phone, a tablet computer, an e-book reader, a smart watch, a camera, a game console, etc., which is not limited in this application.

[0105] For details, please refer to Figure 15 , Figure 151 is a schematic diagram of a structure of a display device provided in the present application, wherein the display device 1000 includes a display panel 100 and a driving device 200. The driving device 200 outputs a first control signal U2D and a second control signal D2U to the display panel 100.

[0106] The driving device 200 may include a source driver chip, a circuit board, etc. The first control signal U2D and the second control signal D2U may be output by the source driver chip. The first control signal U2D and the second control signal D2U may also be output by a power management integrated circuit on the circuit board. This application does not specifically limit this.

[0107] The display device 1000 in the embodiment of the present application includes a display panel 100. A pull-down circuit is provided in the display panel 100 to further pull down the potential of the scan line 20, thereby improving the uniformity of the falling edge of the scan signal within the display panel 100, increasing the charging time of the pixels, and preventing incorrect charging. Furthermore, because the pull-down circuit can include both forward-scanning and reverse-scanning pull-down units, the display panel can implement both forward and reverse scanning, meeting the requirements for both flip-up and flip-up mounting of the same screen.

[0108] The display panel and display device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: A plurality of scanning lines, wherein the plurality of scanning lines are arranged at intervals along a first direction; at least one pull-down circuit connected to the n-th scan line, the pull-down circuit being used to pull down the potential of the n-th scan line; The pull-down circuit includes a forward scan pull-down unit and / or a reverse scan pull-down unit; the forward scan pull-down unit receives an n+mth level scan signal, a first control signal, and a reference low-level signal, and is connected to the nth scan line; the reverse scan pull-down unit receives an nmth level scan signal, a second control signal, and the reference low-level signal, and is connected to the nth scan line; n and m are both integers greater than zero, and n≥2, n>m; The positive scan pull-down unit includes a first transistor and a second transistor; The gate of the first transistor is connected to one of the n+m-th level scan signal and the first control signal, the source of the first transistor is connected to the drain of the second transistor, and the drain of the first transistor is connected to the n-th scan line; the gate of the second transistor is connected to the other of the n+m-th level scan signal and the first control signal, and the source of the second transistor is connected to the reference low-level signal; The reverse sweep pull-down unit includes a third transistor and a fourth transistor; The gate of the third transistor is connected to one of the nm-th level scan signal and the second control signal, the source of the third transistor is connected to the drain of the fourth transistor, and the drain of the third transistor is connected to the n-th scan line; the gate of the fourth transistor is connected to the other of the nm-th level scan signal and the second control signal, and the source of the fourth transistor is connected to the reference low-level signal; The display panel has a display area. The pull-down circuit is arranged in the display area. The display panel includes a plurality of pull-down circuits. Each pull-down circuit is connected to one scan line, and each scan line is connected to at least two pull-down circuits.

2. The display panel according to claim 1, wherein: Along the first direction, the pull-down circuits corresponding to two adjacent scan lines are arranged in an alternating manner.

3. The display panel according to claim 1, wherein: The display panel further comprises a first non-display area and a second non-display area located on both sides of the display area along the direction in which the scan line extends; the display panel further comprises a first GOA circuit and a second GOA circuit, the first GOA circuit being arranged in the first non-display area, and the second GOA circuit being arranged in the second non-display area; Each of the scan lines is connected to two pull-down circuits. Along the extending direction of the scan lines, the pull-down circuits connected to the odd-numbered scan lines are located between the pull-down circuits connected to the even-numbered scan lines.

4. The display panel according to claim 1, wherein: The display panel also includes at least one first control signal line and at least one second control signal line, the first control signal line is used to transmit the first control signal, and the second control signal line is used to transmit the second control signal; the first control signal line and the second control signal line both extend along the first direction, and each of the pull-down circuits is respectively connected to the first control signal line and the second control signal line.

5. A display device comprising a display panel and a driving device, characterized in that: The display panel is the display panel according to any one of claims 1 to 4, and the driving device outputs the first control signal and the second control signal to the display panel.

Images