Three-dimensional stacked memory chip and electronic device

Abstract

The application provides a three-dimensional stacked memory chip and an electronic device. The three-dimensional stacked memory chip comprises: a plurality of memory dies and a logic die connected in layers; the logic die is connected in layers with the plurality of memory dies, and the logic die comprises a first interface in communication with the outside; wherein at least one memory die is provided with a detection circuit, the detection circuit provided in the at least one memory die is connected with the first interface respectively, and the detection circuit is used for detecting the internal working voltage of the memory die to which the detection circuit belongs and outputting through the first interface. The three-dimensional stacked memory chip effectively reduces the area occupied by the first interface on the three-dimensional stacked memory chip, and reduces the manufacturing cost of the three-dimensional stacked memory chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a three-dimensional stacked memory chip and an electronic device. BACKGROUND

[0002] At present, the internal working voltage of a chip usually needs to be detected to verify whether the output of each generator inside the chip is accurate and whether power-on is completed normally.

[0003] To this end, the chip is generally provided with a detection circuit and an interface in communication with the outside world, the detection circuit is used to detect the internal working voltage of the chip, and the detection circuit is in communication with the interface and outputs the detected internal working voltage through the interface. However, the interface and the interlayer interconnection structure on the three-dimensional stacked memory chip occupy a large area on the three-dimensional stacked memory chip and have a high cost. SUMMARY

[0004] The present application provides a three-dimensional stacked memory chip and an electronic device, aiming at solving the problem of large area occupation and high cost of the interface on the three-dimensional stacked memory chip.

[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a three-dimensional stacked memory chip. The three-dimensional stacked memory chip comprises: a plurality of memory dies and logic dies connected in layers; the logic die is connected in layers with the plurality of memory dies, and the logic die comprises a first interface in communication with the outside world; wherein at least one of the memory dies is provided with a detection circuit, and the detection circuit provided in each of the memory dies is connected with the first interface respectively, and the detection circuit is used to detect the internal working voltage of the memory die to which it belongs and output through the first interface.

[0006] The three-dimensional stacked memory chip further comprises a control element, the control element is connected with the first interface and the detection circuit, and is used to output the internal working voltage of the memory die through the first interface respectively.

[0007] The control element is arranged in the memory die; and / or

[0008] The control element is arranged in the logic die.

[0009] Each of the memory dies is provided with a first control element, wherein the detection circuit in each of the memory dies is selectively connected to the first interface through the corresponding first control element, so as to selectively output the internal working voltage of the memory die detected by the corresponding detection circuit through the first interface.

[0010] The detection circuit is arranged in one of the plurality of memory dies, and the other memory dies are connected to the detection circuit through interlayer interconnection structures between the plurality of memory dies, so as to detect internal working voltages of the plurality of memory dies through the detection circuit.

[0011] The memory die where the detection circuit is arranged is further provided with a plurality of second control elements, the detection circuit is connected to any of the memory dies through the second control elements and the interlayer interconnection structures between the plurality of memory dies, so as to selectively detect internal working voltages of the plurality of memory dies through the detection circuit and output through the first interface.

[0012] The memory die where the detection circuit is arranged is further provided with a plurality of second control elements, the detection circuit is connected to any of the memory dies through the second control elements and the interlayer interconnection structures between the plurality of memory dies, so as to selectively detect internal working voltages of the plurality of memory dies through the detection circuit and output through the first interface.

[0013] The memory die where the detection circuit is arranged is adjacent to the logic die.

[0014] The memory die where the detection circuit is arranged is adjacent to the logic die.

[0015] The memory die where the detection circuit is arranged is adjacent to the logic die.

[0016] To solve the above technical problems, another technical solution adopted by the present application is to provide an electronic device, which comprises the three-dimensional stacked memory chip as described above.

[0017] The beneficial effects of the embodiments of the present application are distinguished from the prior art: the three-dimensional stacked memory chip and the electronic device provided by the embodiments of the present application, the three-dimensional stacked memory chip is provided by arranging a plurality of memory dies connected in layers and a logic die connected with the plurality of memory dies, at least one memory die is provided with a detection circuit, and the detection circuit arranged in at least one memory die is connected with the first interface respectively, so as to detect the internal working voltage of the memory die to which the detection circuit belongs respectively, and output through the first interface, so as to verify whether the output of each generator in each memory die is accurate and whether the power-on is completed normally. Among them, since the detection circuit arranged in at least one memory die shares one first interface, the number of first interfaces on the three-dimensional stacked memory chip is greatly reduced, the occupied area of the first interface on the three-dimensional stacked memory chip is effectively reduced, and the manufacturing cost of the three-dimensional stacked memory chip is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The structure diagram of the three-dimensional stacked memory chip provided by the first embodiment of the present application is provided;

[0019] Figure 2a The structure diagram of the three-dimensional stacked memory chip provided by a specific embodiment of the present application is provided;

[0020] Figure 2b The structure diagram of the three-dimensional stacked memory chip provided by another specific embodiment of the present application is provided;

[0021] Figure 2c The structure diagram of the three-dimensional stacked memory chip provided by the second embodiment of the present application is provided;

[0022] Figure 3 The structure diagram of the three-dimensional stacked memory chip provided by the third embodiment of the present application is provided;

[0023] Figure 4 The structure diagram of the three-dimensional stacked memory chip provided by the fourth embodiment of the present application is provided;

[0024] Figure 5 The structure diagram of the three-dimensional stacked memory chip provided by the fifth embodiment of the present application is provided;

[0025] Figure 6 The structure diagram of the three-dimensional stacked memory chip provided by the sixth embodiment of the present application is provided;

[0026] Figure 7 The structure diagram of the three-dimensional stacked memory chip provided by the seventh embodiment of the present application is provided;

[0027] Figure 8 The structure diagram of the electronic device provided by an embodiment of the present application is provided.

[0028] BRIEF DESCRIPTION OF DRAWINGS

[0029] Three-dimensional stacked memory chip 10; memory die 1; detection circuit 11; first control element 12; second control element 13; logic die 2; first interface 21; control element 3. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0031] The terms "first", "second", "third" in the present application are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0032] In this document, the term "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor is it independent or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] The present application will be described in detail below with reference to the drawings and embodiments.

[0034] Please refer to Figure 1 , Figure 1This is a simplified structural diagram of a three-dimensional stacked memory chip provided in the first embodiment of this application. In this embodiment, a three-dimensional stacked memory chip 10 is provided. The three-dimensional stacked memory chip 10 includes at least two memory dies 1 and a logic die 2 (LOGIC) that are stacked and interconnected. The memory die 1 is a Dynamic Random Access Memory (DRAM).

[0035] At least one memory chip 1 is equipped with a detection circuit 11 to detect the internal operating voltage of its respective memory chip 1, thereby verifying whether the output of each generator inside each memory chip 1 is accurate and whether the power-on is completed normally. A logic chip 2 is stacked with at least two memory chips 1. The memory chip 1 adjacent to the logic chip 2 is defined as the first memory chip (DRAM 1). Along the direction away from the logic chip 2, the other memory chips 1 are sequentially referred to as the second memory chip (DRAM 2), the third memory chip (DRAM 3), ..., the nth memory chip (DRAM n), where n is a natural number greater than or equal to 2.

[0036] The logic die 2 includes a first interface 21. At least one detection circuit 11 in each memory die 1 is connected to the first interface 21 to output the detected internal operating voltage of each memory die 1 through the first interface 21. Since the detection circuit 11 in at least one memory die 1 shares a single first interface 21, the number of first interfaces 21 on the three-dimensional stacked memory chip 10 is significantly reduced, effectively reducing the area occupied by the first interfaces 21 on the three-dimensional stacked memory chip 10 and lowering the manufacturing cost of the three-dimensional stacked memory chip 10.

[0037] Specifically, each detection circuit 11 is connected to the first interface 21 via an interlayer interconnect structure between two memory dies 1 and / or an interlayer interconnect structure between memory die 1 and logic die 2. The interlayer interconnect structure between the two memory dies 1 includes stacked interconnect vias or a combination of other memory dies 1 and stacked interconnect vias located between the two memory dies 1. The stacked interconnect vias can be through-silicon vias (TSVs). Dies can also be replaced with wafers.

[0038] In the first embodiment, as Figure 1 As shown, each memory chip 1 is provided with a detection circuit 11 to detect the internal operating voltage of the corresponding memory chip 1 and output it through the first interface 21.

[0039] exist Figure 1In the embodiment shown, the three-dimensional stacked memory chip 10 includes three memory dies 1. The connection between the detection circuit 11 on each memory die 1 and the first interface 21 is as follows: the detection circuit 11 on the third memory die (DRAM3) is connected to the first interface 21 through the stacked interconnection hole between the third memory die (DRAM3) and the second memory die (DRAM2), the stacked interconnection hole between the second memory die (DRAM2) and the first memory die (DRAM1), and the stacked interconnection hole between the first memory die (DRAM1) and the logic die 2. The detection circuit 11 on the second memory die (DRAM2) is connected to the first interface 21 through the stacked interconnection hole between the second memory die (DRAM2) and the first memory die (DRAM1), and the stacked interconnection hole between the first memory die (DRAM1) and the logic die 2. The detection circuit 11 on the first memory die (DRAM1) is connected to the first interface 21 through the stacked interconnection hole between the first memory die (DRAM1) and the logic die 2.

[0040] In combination Figure 1 The above connection method can share the interlayer interconnection structure between the first memory die (DRAM1) and the logic die 2 between each detection circuit 11 and the first interface 21. Further, the connection link between the detection circuit 11 on the third memory die (DRAM3) and the first interface 21 can share the stacked interconnection hole between the second memory die (DRAM2) and the first memory die (DRAM1) and the first memory die (DRAM1) and the logic die 2 with the connection link between the second memory die (DRAM2) and the first interface 21. In this way, compared with the prior art scheme in which each memory die 1 is connected to an interface through a corresponding connection link, the number of channels of the interlayer interconnection structure can be further reduced, and the area occupied by the interlayer interconnection structure on the three-dimensional stacked memory chip 10 can be further reduced, thereby further reducing the manufacturing cost of the three-dimensional stacked memory chip 10.

[0041] In this embodiment, referring to Figure 2a , Figure 2a The structure diagram of the three-dimensional stacked memory chip provided in a specific embodiment of the present application; in order to prevent the internal operating voltages detected by each detection circuit 11 from interfering with each other. The three-dimensional stacked memory chip 10 further includes a control element 3 connected between the first interface 21 and the detection circuit 11, for outputting the internal operating voltage of the memory die 1 through the first interface 21.

[0042] In a specific embodiment, as Figure 2aAs shown, the control element 3 is disposed on the logic die 2. The detection circuit 11 in each memory die 1 is selectively connected to the first interface 21 through the interlayer interconnection structure between the memory dies 1, the interlayer interconnection structure between the logic die 2 and the memory dies 1, and the control element 3, so as to selectively output the internal operating voltage of the memory die 1 detected by the corresponding detection circuit 11 through the first interface 21.

[0043] As shown, three memory dies 1 are taken as an example. The detection circuit 11 on the first memory die (DRAM1) is connected to the first interface 21 through the interlayer interconnection structure between the first memory die (DRAM1) and the logic die 2, and the control element 3. Figure 2a The detection circuit 11 on the second memory die (DRAM2) is connected to the first interface 21 through the interlayer interconnection structure between the second memory die (DRAM2) and the first memory die (DRAM1), the first memory die (DRAM1), the interlayer interconnection structure between the first memory die (DRAM1) and the logic die 2, and the control element 3. The detection circuit 11 on the third memory die (DRAM3) is connected to the first interface 21 through the interlayer interconnection structure between the third memory die (DRAM3) and the second memory die (DRAM2), the second memory die (DRAM2), the interlayer interconnection structure between the second memory die (DRAM2) and the first memory die (DRAM1), the first memory die (DRAM1), the interlayer interconnection structure between the first memory die (DRAM1) and the logic die 2, and the control element 3.

[0044] The control element 3 can be a multiplexer. When the control element 3 receives a first trigger instruction, the control element 3 connects the detection circuit 11 on the first memory die (DRAM1) to the first interface 21 to output the internal operating voltage of the first memory die (DRAM1), so as to verify whether the output of each generator inside the first memory die (DRAM1) is accurate and whether the power-on is completed normally. When the control element 3 receives a second trigger instruction, the control element 3 connects the detection circuit 11 on the second memory die (DRAM2) to the first interface 21 to output the internal operating voltage of the second memory die (DRAM2), so as to verify whether the output of each generator inside the second memory die (DRAM2) is accurate and whether the power-on is completed normally. When the control element 3 receives a third trigger instruction, the control element 3 connects the detection circuit 11 on the third memory die (DRAM3) to the first interface 21 to output the internal operating voltage of the third memory die (DRAM3), so as to verify whether the output of each generator inside the third memory die (DRAM3) is accurate and whether the power-on is completed normally. Similarly, the above process can be repeated.

[0045] Of course, in other embodiments, see Figure 2b , Figure 2b a structural diagram of a three-dimensional stacked memory chip provided for another embodiment of the present application; unlike the embodiment shown in Figure 2a , the number of control elements 3 can be multiple, and the multiple control elements 3 are connected one-to-one with the multiple memory dies 1 to selectively output the internal operating voltage of the memory die 1 detected by the detection circuit 11 through the first interface 21 after receiving the trigger instruction.

[0046] For example, the control element 3 connected with the first memory die (DRAM1) receives the trigger instruction, and the control element 3 communicates the detection circuit 11 on the first memory die (DRAM1) with the first interface 21 to output the internal operating voltage of the first memory die (DRAM1), so as to verify whether the output of each generator inside the first memory die (DRAM1) is accurate and whether the power-on is completed normally. The control element 3 connected with the second memory die (DRAM2) receives the trigger instruction, and the control element 3 communicates the detection circuit 11 on the second memory die (DRAM2) with the first interface 21 to output the internal operating voltage of the second memory die (DRAM2), so as to verify whether the output of each generator inside the second memory die (DRAM2) is accurate and whether the power-on is completed normally. The control element 3 connected with the third memory die (DRAM3) receives the trigger instruction, and the control element 3 communicates the detection circuit 11 on the third memory die (DRAM3) with the first interface 21 to output the internal operating voltage of the third memory die (DRAM3), so as to verify whether the output of each generator inside the third memory die (DRAM3) is accurate and whether the power-on is completed normally.

[0047] In an embodiment, one detection circuit 11 is communicated with the first interface 21 at a time, that is, one control element 3 is controlled to communicate at a time to output the internal operating voltage of a single memory die 1, so as to avoid the problem of mutual interference between the internal operating voltages of the memory dies 1.

[0048] In yet another embodiment, see Figure 2c , Figure 2c a structural diagram of a three-dimensional stacked memory chip provided for the second embodiment of the present application; in order to prevent the internal operating voltages detected by the detection circuits 11 from interfering with each other, the number of control elements 3 is multiple, and the multiple control elements 3 are arranged on the memory dies 1 one-to-one.

[0049] Specifically, as Figure 2cAs shown, a first control element 12 can be correspondingly arranged in each memory die 1. The detection circuit 11 in each memory die 1 is selectively connected to the first interface 21 through the corresponding first control element 12, the interlayer interconnection structure between the memory dies 1, and the interlayer interconnection structure between the logic die 2 and the memory dies 1, so as to selectively output the internal operating voltage of the memory die 1 detected by the corresponding detection circuit 11 through the first interface 21.

[0050] For example, three memory dies 1 are taken as an example. The detection circuit 11 on the first memory die (DRAM1) is connected to the first interface 21 through the first control element 12 on the first memory die (DRAM1) and the interlayer interconnection structure between the first memory die (DRAM1) and the logic die 2. The detection circuit 11 on the second memory die (DRAM2) is connected to the first interface 21 through the first control element 12 on the second memory die (DRAM2), the interlayer interconnection structure between the second memory die (DRAM2) and the first memory die (DRAM1), the first memory die (DRAM1), and the interlayer interconnection structure between the first memory die (DRAM1) and the logic die 2. The detection circuit 11 on the third memory die (DRAM3) is connected to the first interface 21 through the first control element 12 on the third memory die (DRAM3), the interlayer interconnection structure between the third memory die (DRAM3) and the second memory die (DRAM2), the second memory die (DRAM2), the interlayer interconnection structure between the second memory die (DRAM2) and the first memory die (DRAM1), the first memory die (DRAM1), and the interlayer interconnection structure between the first memory die (DRAM1) and the logic die 2.

[0051] In specific embodiments, the detection circuit 11 on the memory die 1 is connected to the first interface 21 through the first control element 12 to output the internal operating voltage on the corresponding memory die 1. For example, the first control element 12 on the first memory die (DRAM1) receives a trigger instruction, and then the first control element 12 connects the detection circuit 11 on the first memory die (DRAM1) to the first interface 21 to output the internal operating voltage of the first memory die (DRAM1), so as to verify whether the output of each generator inside the first memory die (DRAM1) is accurate and whether the power-on is completed normally. The first control element 12 on the second memory die (DRAM2) receives a trigger instruction, and then the first control element 12 connects the detection circuit 11 on the second memory die (DRAM2) to the first interface 21 to output the internal operating voltage of the second memory die (DRAM2), so as to verify whether the output of each generator inside the second memory die (DRAM2) is accurate and whether the power-on is completed normally.

[0052] In a specific embodiment, each time a detection circuit 11 is connected to the first interface 21, that is, each time the first control element 12 in a storage die 1 is connected to output the internal working voltage of a single storage die 1, thereby avoiding the problem of mutual interference between the internal working voltages of each storage die 1.

[0053] Of course, in other specific embodiments, a first control element 12 may be provided in some storage chips 1, while the other storage chips 1 may not be provided with the first control element 12. This application does not limit this.

[0054] Of course, multiple control elements 3 can also be partially disposed on the memory chip 1, with the remainder disposed on the logic chip 2. For example, the control element 3 connected to the detection circuit 11 connected to the first memory chip (DRAM1) can be disposed on the first memory chip (DRAM1); the control element 3 connected to the detection circuit 11 connected to the second memory chip (DRAM2) can be disposed on the second memory chip (DRAM2); and the control element 3 connected to the detection circuit 11 connected to the third memory chip (DRAM3) can be disposed on the logic chip 2.

[0055] In the second embodiment, see Figure 3 , Figure 3 This is a simplified structural diagram of a three-dimensional stacked memory chip provided in the second embodiment of this application. A detection circuit 11 is provided in one of the plurality of memory chips 1. The other memory chips 1 are connected to the detection circuit 11 through interlayer interconnect structures between the plurality of memory chips 1, so that the detection circuit 11 can detect the internal operating voltage of each of the plurality of memory chips 1. That is, the internal operating voltage of each of the plurality of memory chips 1 is detected by the detection circuit 11 in one memory chip 1. Compared to Figure 1 In the corresponding embodiments, other memory chips 1 do not need to be equipped with detection circuits 11, which can reduce the number of detection circuits 11, thereby saving costs and saving the area required for other memory chips 1 to be equipped with detection circuits 11.

[0056] Specifically, the memory die 1 equipped with the detection circuit 11 can be a memory die 1 adjacent to the logic die 2, i.e., the first memory die (DRAM 1). Compared to a second or third memory die 1, the number of interlayer interconnect structures connecting the first memory die (DRAM 1) to the detection circuit 11 can be reduced, thereby further reducing the area occupied by the interlayer interconnect structure on the three-dimensional stacked memory chip 10 and lowering costs. Of course, in other specific embodiments, see... Figure 4 , Figure 4The structure diagram of the three-dimensional stacked memory chip 10 provided by the fourth embodiment of the present application is shown in FIG. 4. The memory die 1 provided with the detection circuit 11 can also be the second memory die (DRAM2) (as shown in FIG. 1) or the third memory die (DRAM3) and the like. Figure 4

[0057] In order to avoid the internal working voltages of the detected memory dies 1 interfering with each other, in a specific embodiment, referring to FIG. 5, the detection circuit 11 is connected to the first interface 21 through the interlayer interconnection structure between the second control element 13 and the memory die 1, and the detection circuit 11 is connected to the first interface 21 through the interlayer interconnection structure between the memory dies 1 and / or the interlayer interconnection structure between the logic die 2 and the memory dies 1. Figure 5 Figure 5 The structure diagram of the three-dimensional stacked memory chip 10 provided by the fifth embodiment of the present application is shown in FIG. 6. The memory die 1 provided with the detection circuit 11 is further provided with a plurality of second control elements 13. The second control element 13 and the first control element 12 can be a control switch.

[0058] In a specific embodiment, the detection circuit 11 is connected to any memory die 1 selectively through the interlayer interconnection structure between the second control element 13 and the memory die 1, and the detection circuit 11 is connected to the first interface 21 through the interlayer interconnection structure between the memory dies 1 and / or the interlayer interconnection structure between the logic die 2 and the memory dies 1, so as to selectively detect the internal working voltage of any memory die 1 by the detection circuit 11 and output through the first interface 21.

[0059] Specifically, the plurality of second control elements 13 are arranged one-to-one corresponding to the plurality of memory dies 1, and one second control element 13 is controlled to be turned on at a time, so as to select the communication between the detection circuit 11 and one memory die 1 at a time, that is, to control the detection circuit 11 to detect the internal working voltage of one memory die 1 at a time, so as to avoid the problem of mutual interference between the internal working voltages of the memory dies 1.

[0060] ​​For example, the three-dimensional stacked memory chip 10 includes a logic die 2, a first memory die (DRAM1), a second memory die (DRAM2) and a third memory die (DRAM3) stacked in sequence with the logic die 2. If the detection circuit 11 is specifically arranged on the first memory die (DRAM1), three second control elements 13 are also arranged on the first memory die (DRAM1) correspondingly, and the detection circuit 11 is connected with the first memory die (DRAM1) through the first second control element 13. The detection circuit 11 is connected with the second memory die (DRAM2) through the second second control element 13 and the interlayer interconnection structure between the first memory die (DRAM1) and the second memory die (DRAM2). The detection circuit 11 is connected with the third memory die (DRAM3) through the third second control element 13, the interlayer interconnection structure between the first memory die (DRAM1) and the second memory die (DRAM2), and the interlayer interconnection structure between the second memory die (DRAM2) and the third memory die (DRAM3).

[0061] Of course, if the detection circuit 11 is arranged on the second memory die (DRAM2), three second control elements 13 are arranged on the second memory die (DRAM2) correspondingly. The detection circuit 11 is connected with the first memory die (DRAM1) through the first second control element 13 and the interlayer interconnection structure between the first memory die (DRAM1) and the second memory die (DRAM2). The detection circuit 11 is connected with the second memory die (DRAM2) through the second second control element 13. The detection circuit 11 is connected with the third memory die (DRAM3) through the third second control element 13 and the interlayer interconnection structure between the second memory die (DRAM2) and the third memory die (DRAM3).

[0062] It can be understood that, in the above specific embodiments, the detection circuit 11 is directly connected with the memory die 1 on which it is arranged through the second control element 13, without the interlayer interconnection structure between the memory dies 1. Of course, in specific embodiments, the detection circuit 11 can also be directly connected with the memory die 1 on which it is arranged, i.e., without the second control element 13, which is not limited in the present application.

[0063] In another specific embodiment, in order to avoid mutual interference of internal working voltages of the detected memory dies 1; see Figure 6 , Figure 6This is a simplified structural diagram of a three-dimensional stacked memory chip provided in the sixth embodiment of this application; each memory die 1 is further provided with a corresponding second control element 13. That is, the first memory die (DRAM1) is provided with a corresponding second control element 13.

[0064] In this specific embodiment, each memory chip 1 is selectively connected to the detection circuit 11 through the second control element 13 and the interlayer interconnection structure between the plurality of memory chips 1. The detection circuit 11 is connected to the first interface 21 through the interlayer interconnection structure between the plurality of memory chips 1 and / or the interlayer interconnection structure between the logic chip 2 and the plurality of memory chips 1, so that the internal operating voltage of any plurality of memory chips 1 can be selectively detected by the detection circuit 11 and output through the first interface 21.

[0065] For example, such as Figure 6 As shown, the three-dimensional stacked memory chip 10 includes a logic die 2, and a first memory die (DRAM1), a second memory die (DRAM2), and a third memory die (DRAM3) stacked sequentially on the logic die 2. A second control element 13 is respectively disposed on the first memory die (DRAM1), the second memory die (DRAM2), and the third memory die (DRAM3). If the detection circuit 11 is specifically disposed on the first memory die (DRAM1), then the first memory die (DRAM1) is connected to the detection circuit 11 through the second control element 13 thereon. The second memory die (DRAM2) is connected to the detection circuit 11 through the second control element 13 thereon and the interlayer interconnection structure between the first memory die (DRAM1) and the second memory die (DRAM2). The third memory die (DRAM3) is connected to the detection circuit 11 via the second control element 13, the interlayer interconnect structure between the second memory die (DRAM2) and the third memory die (DRAM3), and the interlayer interconnect structure between the first memory die (DRAM1) and the second memory die (DRAM2). In this embodiment, the detection circuit 11 is specifically connected to the first interface 21 via the interlayer interconnect structure between the logic die 2 and the first memory die (DRAM1), so that the internal operating voltage output of the first memory die (DRAM1), the second memory die (DRAM2), or the third memory die (DRAM3) selectively detected by the detection circuit 11 can be output via the first interface 21.

[0066] Of course, in other specific embodiments, see Figure 7 , Figure 7The structure diagram of the three-dimensional stacked memory chip provided by the seventh embodiment of the present application is shown in FIG. 7. If the detection circuit 11 is arranged on the second memory die (DRAM2), the first memory die (DRAM1) is connected with the detection circuit 11 through the second control element 13 on the first memory die (DRAM1) and the interlayer interconnection structure between the first memory die (DRAM1) and the second memory die (DRAM2). The second memory die (DRAM2) is connected with the detection circuit 11 through the second control element 13 on the second memory die (DRAM2). The third memory die (DRAM3) is connected with the detection circuit 11 through the second control element 13 on the third memory die (DRAM3) and the interlayer interconnection structure between the second memory die (DRAM2) and the third memory die (DRAM3). In this embodiment, the detection circuit 11 is connected to the first interface 21 through the interlayer interconnection structure between the first memory die (DRAM1) and the second memory die (DRAM2) and the interlayer interconnection structure between the logic die 2 and the first memory die (DRAM1), so as to output the internal operating voltage of the first memory die (DRAM1), or the second memory die (DRAM2) or the third memory die (DRAM3) selectively detected by the detection circuit 11 through the first interface 21.

[0067] Of course, in other embodiments, the detection circuit 11 can also be arranged on each of some of the memory dies 1, and the some of the memory dies 1 share the same detection circuit 11. For example, among the five memory dies 1, three of them each have a detection circuit 11 arranged thereon, and the other two of them share one detection circuit 11. The arrangement of the detection circuit 11 on each of the memory dies 1 is the same as the above-mentioned arrangement of the detection circuit 11 on each of the memory dies 1 in the first embodiment of the present application. The connection of the detection circuit 11 with the first interface 21 is also the same as the above-mentioned connection of the detection circuit 11 with the first interface 21 in the first embodiment of the present application. The specific arrangement of the detection circuit 11 and the connection of the detection circuit 11 with the first interface 21 are the same as the above-mentioned specific arrangement of the detection circuit 11 and the connection of the detection circuit 11 with the first interface 21 in the first embodiment of the present application. For details, please refer to the above description, which will not be repeated here. Figure 1 and Figure 2c The arrangement of the detection circuit 11 and the connection of the detection circuit 11 with the first interface 21 are the same as the above-mentioned arrangement of the detection circuit 11 and the connection of the detection circuit 11 with the first interface 21 in the first embodiment of the present application. For details, please refer to the above description, which will not be repeated here. Figures 3 to 7 The arrangement of the detection circuit 11 and the connection of the detection circuit 11 with the first interface 21 are the same as the above-mentioned arrangement of the detection circuit 11 and the connection of the detection circuit 11 with the first interface 21 in the first embodiment of the present application. For details, please refer to the above description, which will not be repeated here.

[0068] The three-dimensional stacked memory chip 10 provided in the embodiment comprises a plurality of memory dies 1 and a logic die 2 connected with the plurality of memory dies 1. The detection circuit 11 is arranged in at least one of the memory dies 1. The detection circuit 11 arranged in the at least one of the memory dies 1 is connected with the first interface 21 respectively. The internal working voltage of the memory die 1 to which the detection circuit 11 belongs is detected by the detection circuit 11, and the detection result is output through the first interface 21. Whether the output of each generator in the memory die 1 is accurate and whether the power-on is completed normally are verified. Since the detection circuit 11 arranged in the at least one of the memory dies 1 shares the first interface 21, the number of the first interface 21 on the three-dimensional stacked memory chip 10 is greatly reduced, the area occupied by the first interface 21 on the three-dimensional stacked memory chip 10 is effectively reduced, and the manufacturing cost of the three-dimensional stacked memory chip 10 is reduced. Meanwhile, the detection circuit 11 is arranged on one of the memory dies 1, and the internal working voltage of the memory die 1 to which the detection circuit 11 belongs is detected by the detection circuit 11. The number of the detection circuit 11 is reduced, and the area occupied by the detection circuit 11 on the three-dimensional stacked memory chip 10 and the cost of the three-dimensional stacked memory chip 10 are reduced.

[0069] Reference is made to Figure 8 , Figure 8 The structural schematic diagram of an electronic device provided in an embodiment of the present application is shown. In the embodiment, an electronic device is provided, which comprises the three-dimensional stacked memory chip 10 provided in any one of the above embodiments. The specific structure and functions of the three-dimensional stacked memory chip 10 can be referred to the above related description, and the same technical effects can be achieved, which will not be described here.

[0070] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the device embodiment described above is only illustrative. For example, the division of the units is only a logical function division. There can be another division manner in actual implementation. For example, a plurality of units or dies can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0071] In addition, each functional unit in the embodiments of the present application can be integrated in a processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be in the form of hardware or in the form of a software functional unit.

[0072] The above merely describes the embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields, which is made according to the content of the present application specification and drawings, is also included in the patent protection scope of the present application.

Claims

1. A three-dimensional stacked memory chip, characterized in that, include: Several storage grains stacked together; A logic die, which is stacked and connected to the plurality of storage dies, and the logic die includes a first interface communicating with the outside world; At least one of the memory chips is provided with a detection circuit, which is connected to the first interface. The detection circuit is used to detect the internal operating voltage of each memory chip connected to it and output it through the first interface. Different memory chips correspond to different first connection links that are respectively connected to the detection circuits. The detection circuit is connected to the first interface through a second connection link. The second connection link includes an interlayer interconnection structure between the plurality of memory chips and / or an interlayer interconnection structure between the logic chip and the plurality of memory chips. The second connection links corresponding to different memory chips at least share the interlayer interconnection structure between the logic chip and the adjacent memory chip.

2. The three-dimensional stacked memory chip according to claim 1, characterized in that, The three-dimensional stacked memory chip also includes a control element, which is connected to the first interface and the detection circuit, and is used to output the internal operating voltage of the memory chip through the first interface.

3. The three-dimensional stacked memory chip according to claim 2, characterized in that, The control element is disposed on the storage die; and / or The control element is located on the logic die.

4. The three-dimensional stacked memory chip according to claim 3, characterized in that, Each of the memory chips is provided with a first control element, wherein the detection circuit in each memory chip is selectively connected to the first interface through the corresponding first control element, so as to selectively output the internal operating voltage of the memory chip detected by the corresponding detection circuit through the first interface.

5. The three-dimensional stacked memory chip according to claim 1, characterized in that, The detection circuit is provided in one of the plurality of memory chips, and the other memory chips are respectively connected to the detection circuit through the interlayer interconnect structure between the plurality of memory chips, so as to detect the internal operating voltage of the plurality of memory chips respectively through the detection circuit.

6. The three-dimensional stacked memory chip according to claim 5, characterized in that, The memory die equipped with the detection circuit is further provided with a plurality of second control elements. The detection circuit selectively connects to any of the memory dies through the second control elements and the interlayer interconnect structure between the plurality of memory dies. The detection circuit is connected to the first interface through the interlayer interconnect structure between the plurality of memory dies and / or the interlayer interconnect structure between the logic die and the plurality of memory dies, so that the internal operating voltage of any of the plurality of memory dies can be selectively detected by the detection circuit and output through the first interface.

7. The three-dimensional stacked memory chip according to claim 5, characterized in that, Each of the memory chips is further provided with a corresponding second control element, wherein each of the memory chips is selectively connected to the detection circuit through the second control element and the interlayer interconnection structure between the plurality of memory chips, and the detection circuit is connected to the first interface through the interlayer interconnection structure between the plurality of memory chips and / or the interlayer interconnection structure between the logic chip and the plurality of memory chips, so that the detection circuit can selectively detect the internal operating voltage of any of the plurality of memory chips and output it through the first interface.

8. The three-dimensional stacked memory chip according to claim 5, characterized in that, The storage die equipped with the detection circuit is a storage die adjacent to the logic die.

9. The three-dimensional stacked memory chip according to claim 1, characterized in that, Some of the storage chips are provided with the detection circuit in each of them, and some of the storage chips share the same detection circuit.

10. The three-dimensional stacked memory chip according to claim 1, characterized in that, The storage chips are all dynamic random access memories.

11. An electronic device, characterized in that, Includes the three-dimensional stacked memory chip as described in any one of claims 1-10.

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