Air spacer in transistor and method of forming the same

Abstract

Methods include forming a gate stack over a semiconductor region, and forming a first gate spacer on sidewalls of the gate stack. The first gate spacer includes an inner sidewall spacer and a dummy spacer portion located on an outer side of the inner sidewall spacer. The methods also include removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The combination of the air gap and the inner sidewall spacer forms a second gate spacer. A source / drain region is formed to have a portion located on an outer side of the second gate spacer. Embodiments of the invention relate to air spacers in transistors and methods of forming the same.

Description

[0001] This application is a divisional application of the patent application entitled "Air Spacers in Transistors and Methods of Forming the Same" with application number 201811132819.8, filed on September 27, 2018. TECHNICAL FIELD

[0002] Embodiments of the present application relate to air spacers in transistors and methods of forming the same. BACKGROUND

[0003] Technological advances in integrated circuit (IC) materials and design have resulted in generations of ICs, where each generation has a smaller and more complex circuit than the last. As the dimensions of the circuitry on ICs decrease, the number of interconnections that can be made on the chip increases. This increase in interconnectivity has resulted in an increase in the complexity of ICs.

[0004] This scaling increases the complexity of processing and manufacturing ICs, and to achieve these advances, similar developments in IC processing and manufacturing are needed. For example, fin field effect transistors (FinFETs) have been introduced as a replacement for planar transistors. Structures of FinFETs and methods of manufacturing FinFETs are being developed.

[0005] Formation of FinFETs typically involves forming a semiconductor fin, implanting the semiconductor fin to form a well region, forming a dummy gate electrode on the semiconductor fin, etching some portions of the semiconductor fin, and performing epitaxy to regrow source / drain regions. SUMMARY

[0006] According to some embodiments of the present application, a method of forming a semiconductor device is provided, comprising: forming a gate stack over a semiconductor region; forming a first gate spacer on a sidewall of the gate stack, wherein the first gate spacer comprises: an inner sidewall spacer; and a dummy spacer portion on an outer side of the inner sidewall spacer; removing the dummy spacer portion to form a trench; forming a dielectric layer to seal a portion of the trench as an air gap, wherein a combination of the air gap and the inner sidewall spacer forms a second gate spacer; and forming the source / drain regions including a portion on an outer side of the second gate spacer.

[0007] According to further embodiments of the present invention, there is also provided a method of forming a semiconductor device, comprising: forming a dummy gate stack on a semiconductor fin; forming a dummy gate spacer on sidewalls of the dummy gate stack; forming a contact etch stop layer over a source / drain region, wherein the source / drain region is located on a side of the dummy gate spacer; forming an interlayer dielectric over portions of the contact etch stop layer; replacing the dummy gate stack with a replacement gate stack; forming a first contact plug electrically connected to the source / drain region over the source / drain region, wherein the first contact plug penetrates the contact etch stop layer; etching portions of the dummy gate spacer to form a trench; and forming a sealing layer to fill a top portion of the trench, wherein a lower portion of the trench is sealed as an air gap.

[0008] According to yet further embodiments of the present invention, there is also provided a semiconductor device, comprising: a gate stack; a gate spacer located on sidewalls of the gate stack, wherein the gate spacer comprises: an inner sidewall spacer having a vertical portion contacting the gate stack; and an air gap, wherein the gate stack and the air gap are located on an outer side of the vertical portion of the inner sidewall spacer; and a contact etch stop layer having a vertical portion, wherein the vertical portion of the contact etch stop layer and the vertical portion of the inner sidewall spacer are located on opposite sides of the air gap. BRIEF DESCRIPTION OF DRAWINGS

[0009] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that, in accordance with standard practice in the industry, the various elements are not drawn to scale. In fact, the dimensions of the various elements can be arbitrarily increased or decreased for the sake of clarity in the discussion.

[0010] Figures 1-9 is a perspective view of an intermediate stage in the formation of a fin field effect transistor (FinFET) including an air gap in a gate spacer according to some embodiments.

[0011] Figures 10-18A and Figure 18B 、 Figure 19A and Figure 19B is a cross-sectional view of an intermediate stage in the formation of an air gap in a gate spacer prior to source / drain epitaxy according to some embodiments.

[0012] Figures 20-25 、 Figure 26A and Figure 26B is a cross-sectional view of an intermediate stage in the formation of an air gap in a gate spacer after the formation of a replacement gate according to some embodiments.

[0013] Figures 27-34 、 Figure 35A andFigure 35B is a cross-sectional view of an intermediate stage of forming an air gap in a gate spacer after formation of a source / drain contact plug according to some embodiments.

[0014] Figure 36 shows a top view of a transistor having an air gap in a gate spacer according to some embodiments.

[0015] Figure 37 shows various shapes of air gaps in a gate spacer according to some embodiments.

[0016] Figure 38 shows a process flow for forming a transistor and a contact plug according to some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, the following description can refer to the formation of a first component over or on a second component, which can include direct formation of the first component over or on the second component, or can include one or more additional components formed between the first and second components, such that the first component is not formed directly on the second component. As will be understood by those skilled in the art, the specific sequence of steps described is illustrative only and can not be required to practice the application. Also, other devices besides those listed can be used, and the specific devices can be interchangeable between embodiments. The same numbers are used, where possible, to indicate like components. Additionally, some terminology can also be used in the description for the sake of brevity.

[0018] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] Transistors and methods of forming the same are provided according to various exemplary embodiments. Intermediate stages of forming a transistor are shown according to some embodiments. Some variations of some embodiments are discussed. Throughout the various views and exemplary embodiments, the same reference numbers are used to designate the same elements. In the exemplary embodiments shown, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concepts of the present application. Planar transistors can also employ the concepts of the present application.

[0020] Figures 1-9A perspective view showing an intermediate stage of forming an air gap in a gate spacer according to some embodiments of the application. Figures 1-9 The steps shown are also schematically reflected in Figure 38 The process flow 200 shown.

[0021] Figure 1 A perspective view showing an initial structure. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 can be a semiconductor substrate, which can be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 can be doped with p-type or n-type impurities. Isolation regions 22, such as shallow trench isolation (STI) regions, can be formed extending from a top surface of the substrate 20 into the substrate 20. The portions of the substrate 20 located between adjacent STI regions 22 are referred to as semiconductor strips 24. The top surface of the semiconductor strips 24 and the top surface of the STI regions 22 can be substantially flush with each other. According to some embodiments of the application, the semiconductor strips 24 are part of the initial substrate 20, and thus the material of the semiconductor strips 24 is the same as the material of the substrate 20. According to alternative embodiments of the application, the semiconductor strips 24 are replacement strips formed by etching the portions of the substrate 20 located between the STI regions 22 to form recesses and performing epitaxy to regrow another semiconductor material in the recesses. Thus, the semiconductor strips 24 are formed of a different semiconductor material than the substrate 20. According to some exemplary embodiments, the semiconductor strips 24 are formed of silicon germanium, silicon carbon, or a group III-V compound semiconductor material.

[0022] The STI regions 22 can include a pad oxide (not shown), which can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The pad oxide can also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 22 can also include a dielectric material located over the pad oxide, where the dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin-on, etc.

[0023] Referring to Figure 2 The STI regions 22 are recessed such that the top of the semiconductor strips 24 protrude above the top surface 22A of the remaining portions of the STI regions 22 to form protruding fins 24'. The corresponding steps are shown as Figure 38 The step 202 in the process flow 200 shown. The etching can be performed using a dry etching process, where HF3 and NH3 are used as etching gases. During the etching process, a plasma can be generated. Argon can also be included. According to alternative embodiments of the application, the recessing of the STI regions 22 is performed using a wet etching process. For example, the etching chemistry can include HF.

[0024] In the above exemplary embodiments, the fins can be patterned by any suitable method. For example, one or more photolithography processes (including a double patterning or multiple patterning process) can be used to pattern the fins. Generally, a double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns having, for example, smaller pitch than is obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0025] Referring to Figure 3 A dummy gate stack 30 is formed on the top surface and sidewalls of the (protruding) fins 24'. The respective steps are shown as steps 204 in the process flow 200 shown. Figure 38 The dummy gate stack 30 can include a dummy gate dielectric 32 and a dummy gate electrode 34 over the dummy gate dielectric 32. The dummy gate electrode 34 can be formed, for example, using polysilicon, and other materials can also be used. Each dummy gate stack 30 can also include one (or more) hard mask layer(s) 36 over the respective dummy gate electrode 34. The hard mask layer 36 can be formed of silicon nitride, silicon oxide, silicon carbon nitride, or a multilayer thereof. The dummy gate stack 30 can span over a single or multiple protruding fins 24' and / or STI regions 22. The dummy gate stack 30 can also have a longitudinal direction that is perpendicular to the longitudinal direction of the protruding fins 24'.

[0026] Next, a gate spacer 38 is formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present application, the gate spacer 38 is formed of a dielectric material such as silicon nitride, silicon carbon nitride (SiCN), silicon carbon oxygen nitride (SiOCN), etc., and can have a single layer structure or a multilayer structure including multiple dielectric layers.

[0027] According to some embodiments of the present application, an air gap 39 is formed in the gate spacer 38. The air gap 39 can be filled with air, or can be a vacuum or substantially vacuum to have a pressure lower than one atmosphere. The process for forming the corresponding air gap 39 is shown in detail in Figures 10-18A and Figure 18B , Figure 19A and Figure 19B and is discussed accordingly. According to alternative embodiments of the present application, the air gap 39 is not formed in the gate spacer 38 at this time. Instead, the air gap 39 is formed in a subsequent process. Thus, the air gap 39 is shown as a dashed line to indicate that they can or can not be present at this stage.

[0028] According to some embodiments of the present application, an etching step (hereinafter referred to as recessing the source / drain) is performed to etch portions of the protruding fin 24' not covered by the dummy gate stack 30 and the gate spacers 38, thereby creating a structure as shown in Figure 4 The recessing can be anisotropic, and thus portions of the fin 24' directly underneath the dummy gate stack 30 and the gate spacers 38 are protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 can be lower than the top surface 22A of the STI regions 22. Thus, a recess 40 is formed between the STI regions 22. The recess 40 is located on opposite sides of the dummy gate stack 30.

[0029] In the next step, an epitaxial region 42 (source / drain region) is formed by selectively growing a semiconductor material in the recess 40, thereby creating a structure as shown in Figure 5A The corresponding step is shown as step 206 in the process flow 200 shown in Figure 38 According to some exemplary embodiments, the epitaxial region 42 comprises silicon germanium or silicon. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or n-type impurity can be doped in situ as the epitaxial is performed. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorous (SiP) or silicon carbon phosphorous (SiCP) can be grown. According to alternative embodiments of the present application, the epitaxial region 42 is formed of a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the epitaxial region 42 completely fills the recess 40, the epitaxial region 42 starts to laterally expand, and facets can be formed.

[0030] After the epitaxial step, the epitaxial region 42 can be further implanted with a p-type or n-type impurity to form source and drain regions, which are also denoted using the reference numeral "42". According to alternative embodiments of the present application, when the epitaxial region 42 is doped in situ with a p-type or n-type impurity during the epitaxial to form the source / drain region, the implantation step is skipped. The epitaxial region 42 (source / drain region) comprises a lower portion formed in the STI regions 22 and an upper portion formed above the top surface of the STI regions 22.

[0031] Figure 5B The formation of the epitaxial region 42 (source / drain region) according to alternative embodiments of the present application is shown. According to these embodiments, the epitaxial region 42 is not formed by selectively growing a semiconductor material in the recess 40, but rather by selectively growing a semiconductor material in the protruding fin 24' and then etching the protruding fin 24' to form the epitaxial region 42. Figure 3The protruding fin 24' shown is recessed, and an epitaxial region 41 is grown on the protruding fin 24'. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, the material of the epitaxial region 41 can be as follows: Figure 5A The semiconductor material of the epitaxial region 42 shown is similar. Therefore, the epitaxial region 42 (source / drain region) includes protruding fins 24' and epitaxial region 41. Implantation can be performed to implant n-type or p-type impurities.

[0032] Figure 6 A perspective view of the structure after the formation of the contact etch stop layer (CESL) 46 and the interlayer dielectric (ILD) 48 is shown. The corresponding steps are illustrated as follows. Figure 38 Step 208 in the process flow 200 shown. CESL 46 can be formed from silicon nitride, silicon carbonitride, etc. According to some embodiments of the invention, CESL 46 is formed, for example, using a conformal deposition method such as ALD or CVD. ILD 48 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. ILD 48 can also be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based material, such as tetraethyl orthosilicate (TEOS) oxide, plasma-enhanced CVD (PECVD) oxide (SiO2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, can be performed to make the top surfaces of ILD 48, dummy gate stack 30, and gate spacer 38 flush with each other.

[0033] Next step, such as Figure 7 As shown, the dummy gate stack 30 is replaced with a replacement gate stack, wherein the dummy gate stack 30 includes a hard mask layer 36, a dummy gate electrode 34, and a dummy gate dielectric 32, and the replacement gate stack includes a metal gate and a replacement gate dielectric. The corresponding steps are shown as follows. Figure 38 Step 210 in the process flow 200 shown. When forming the replacement gate stack, it is first removed in multiple etching steps. Figure 6 The hard mask layer 36, dummy gate electrode 34, and dummy gate dielectric 32 shown create trenches / openings formed between the gate spacers 38. The top surface and sidewalls of the protruding semiconductor fins 24' are exposed to the trenches. The next step, as... Figure 7 As shown, a gate dielectric layer 52 is formed (replaced). A gate electrode 58 is formed above the gate dielectric layer 52. According to some embodiments of the present invention, the gate dielectric layer 52 (gate dielectric) includes an interface layer (IL) 54 as its lower portion. Figure 20). IL 54 is formed on the exposed surface of protruding fin 24'. IL 54 can include an oxide layer such as a silicon oxide layer formed by a thermal oxidation, a chemical oxidation process, or a deposition process of protruding fin 24'. Gate dielectric layer 52 can also include high-k dielectric layer 56 formed over IL 54 Figure 20 ). High-k dielectric layer 56 includes a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, etc. The high-k dielectric material has a dielectric constant (k value) higher than 3.9, and can be higher than about 7.0. High-k dielectric layer 56 is formed as a conformal layer, and extends over the sidewalls of protruding fin 24' and the sidewalls of gate spacers 38. According to some embodiments of the application, high-k dielectric layer 56 is formed using ALD or CVD.

[0034] Gate electrode 58 can include a plurality of stacked conductive sub-layers. The sub-layers in gate electrode 58 are not shown separately, but in a real structure, the sub-layers are distinguishable from each other. The formation of gate electrode 58 can be implemented using a conformal deposition method such as ALD or CVD, such that the thickness of the vertical portion and the thickness of the horizontal portion of a lower sub-layer of gate electrode 58 are substantially equal to each other.

[0035] Gate electrode 58 can include a diffusion barrier layer and one (or more) work function layer(s) (not shown separately) located over the diffusion barrier layer. The diffusion barrier layer can be formed of titanium nitride (TiN) which can or can not be doped with silicon. The work function layer determines the work function of the gate, and includes at least one layer or a plurality of layers formed of different materials. The material of the work function layer is selected according to whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer can include a TaN layer and a titanium aluminum (TiAl) layer located over the TaN layer. When the FinFET is a p-type FinFET, the work function layer can include a TaN layer, a TiN layer located over the TaN layer, and a TiAl layer located over the TiN layer. After the deposition of the work function layer, a barrier layer is formed, which can be another TiN layer.

[0036] Gate electrode 58 can also include a fill metal that fills all remaining trenches (not filled by the underlying sub-layers). For example, the fill metal can be formed of tungsten or cobalt. After the formation of the fill material, a planarization process such as a CMP process or a mechanical polishing process is implemented, thereby removing the portions of gate dielectric layer 52 and gate electrode 58 located over ILD 48. The remaining portions of gate dielectric layer 52 and gate electrode 58 are referred to hereinafter as replacement gate 62. As shown in FIG. 2B, at this point, the top surfaces of gate electrode 58, gate spacers 38, CESL 46, and ILD 48 can be substantially coplanar. Figure 7

[0037] Figure 8 ​The formation of self-aligned hard mask 64 is shown. Self-aligned hard mask 64 is self-aligned to the underlying replacement gate 62 and is formed of a dielectric material such as Zr02, AI2O3, SiN, SiON, SiCN, Si02, etc. The formation process can include etching replacement gate 62 to form a recess, filling the recess with the dielectric material, and performing a planarization process to remove excess portions of the dielectric material.

[0038] According to some embodiments of the present application, if air gaps 39 have not already been formed in previous process steps, air gaps 39 can be formed after the formation of replacement gate 62 and hard mask 64. The process for forming the corresponding air gaps 39 is shown in detail and discussed accordingly in Figures 20-25 According to optional embodiments of the present application, at this stage, air gaps 39 are not formed in gate spacers 38. Rather, air gaps 39 are formed in a subsequent process. Accordingly, air gaps 39 are shown as dashed lines to indicate that they can or can not be present at this stage.

[0039] Figure 9 The formation of source / drain contact plugs 66A and source / drain silicide regions 69 is shown. The corresponding steps are shown as step 212 in process flow 200 shown in Figure 38 The formation of source / drain contact plugs 66A can include etching portions of ILD 48 and the underlying CESL 46 to form contact openings, exposed portions of silicided epitaxial regions 42 (source / drain regions) to form silicide regions 69, filling the contact openings with a conductive layer and performing planarization. The resulting contact plugs 66A can include a conductive barrier layer formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. and a metal such as tungsten or cobalt located above the conductive barrier layer. Source / drain contact plugs 66A can also be formed after the formation of a dielectric layer (not shown) over the structure in Figure 9 and can include portions that extend into the overlying dielectric layer.

[0040] According to some embodiments of the present application, if air gaps 39 have not already been formed in previous process steps, air gaps 39 can be formed after the formation of source / drain contact plugs 66A. The process for forming the corresponding air gaps 39 is shown in detail and discussed accordingly in Figures 29-34

[0041] Figure 36 The formation of source / drain contact plugs 66A and source / drain silicide regions 69 is shown. The corresponding steps are shown as step 212 in process flow 200 shown in Figure 9 ​A top view of some portions of the FinFET shown. According to some embodiments of the application, the plurality of semiconductor fins 24' are laid out as parallel strips. The plurality of replacement gates 62 are formed as parallel strips across the semiconductor fins 24'. The inner sidewall spacers 37A, which are part of the gate spacers 38, form rings that surround and contact the sidewalls of the replacement gates 62. The air gaps 39 also form rings that surround the inner sidewall spacers 37A. The sidewall portions of the CESL 46 form rings that surround the air gaps 39. According to some embodiments of the application, the air gaps 39 are completely enclosed in another dielectric layer (e.g., the dielectric seal layer 76 as shown Figure 19A and Figure 19B the dielectric seal layer 76) that is also part of the gate spacers 38. Thus, the inner sidewall spacers 37A and the sidewall portions of the CESL 46 are spaced apart from the air gaps 39 by a dielectric layer such as the dielectric seal layer 76. According to alternative embodiments of the application, the air gaps 39 are exposed to either or both of the inner sidewall spacers 37A and the sidewall portions of the CESL 46.

[0042] Figure 36 Two planes are shown, one containing line A-A and the other containing line B-B. The plane containing line A-A is taken between two adjacent fins 24' and thus the fins 24' (and the source / drain epitaxial regions 41 / epitaxial regions 42) are not in the plane. The plane containing line B-B is taken through a fin 24' and thus the fin 24' (and the source / drain epitaxial regions 41 / epitaxial regions 42) is in the plane. In the following figures, all of the cross-sectional views shown with the STI regions 22 are taken from a plane containing line A-A in Figure 36 and all of the cross-sectional views shown without the STI regions 22 are taken from a plane containing line B-B in Figure 36 .

[0043] Figures 10-18A and Figure 18B , Figure 19A and Figure 19B are cross-sectional views of intermediate stages in the formation of air gaps prior to source / drain epitaxy according to some embodiments. The line 24A shown throughout the cross-sectional views represents the top location of the semiconductor fins 24'. Figures 10-17 the steps shown in Figure 3 . Figure 18A and Figure 18B the steps shown in Figure 4 , Figure 5A and Figure 5B the steps shown in Figure 19A and Figure 19B the steps shown in Figure 6 .

[0044] Figure 10A dummy gate stack 30 is shown, which includes a dummy gate dielectric 32, a dummy gate electrode 34, and a hard mask layer 36. A gate spacer 37 is formed on the sidewalls of the dummy gate stack 30. The gate spacer 37 is optionally referred to as a dummy gate spacer since a portion 37B of the gate spacer 37 will be removed. Figure 10 The cross-section shown is taken from the same plane as the plane containing Figure 36 line A-A. Since the semiconductor fin 24' is not in the plane, the semiconductor fin 24' is at a level between the top surface of 24A and the top surface of the STI region 22 in Figure 10 The cross-section is taken at a level between the top surface of 24A and the top surface of the STI region 22. The gate spacer 37 includes an inner sidewall spacer 37A and a dummy spacer portion 37B. The inner sidewall spacer 37A and the dummy spacer portion 37B are formed of different materials, which can be selected from Si02, SiN, SiCN, SiON, SiOCN, SiC, etc. When formed of SiOCN, the inner sidewall spacer 37A can have a carbon atomic percentage greater than about 10%, and the dummy spacer portion 37B can have a carbon atomic percentage lower than about 10%. The dummy spacer portion 37B can also be formed of TiN or a composite layer of Si02 and SiOCN. The dummy spacer portion 37B can overlap with the horizontal leg of the inner sidewall spacer 37A. The thickness of the inner sidewall spacer 37A can be in a range between about 2 nm and about 5 nm. The thickness of the dummy spacer portion 37B can be in a range between about 2 nm and about 6 nm.

[0045] Figure 11 The formation of a buffer dielectric layer 70 and a sacrificial fill material 72 is shown. According to some embodiments, the buffer dielectric layer 70 is formed of a material different from the materials of the inner sidewall spacer 37A and the dummy spacer portion 37B. A conformal deposition method such as atomic layer deposition (ALD) or CVD can be used to deposit either of the buffer dielectric layer 70 and the sacrificial fill material 72. The buffer dielectric layer 70 and the sacrificial fill material 72 can also be formed of Si02, SiN, SiCN, SiON, SiOCN, SiC, etc. A planarization process such as a CMP process or a mechanical polishing process is implemented, and the buffer dielectric layer 70 can serve as a CMP stop layer. In addition, the sacrificial fill material 72 is formed of a material different from the materials of the hard mask layer 36, the gate spacer 37, and the buffer dielectric layer 70.

[0046] In the next step, referring to Figure 12 , the sacrificial fill material 72 is etched back. The level of the top surface of the sacrificial fill material 72 determines in part the height of the air gap 39 (Fig. 4) formed subsequently. Figure 15 Some portions of the buffer dielectric layer 70 are exposed. Thereafter, as Figure 13As shown, exposed portions of the etch buffer dielectric layer 70 are etched, exposing the top edges of the inner sidewall spacers 37A and the dummy spacer portions 37B. In the etch, the etch selectivity, i.e., the ratio of the etch rate of the sacrificial fill material 72 to the etch rate of the materials of the hard mask layer 36, gate spacers 37, and buffer dielectric layer 70, is high, e.g., greater than about 60, and can be greater than about 100. As a result, the hard mask layer 36, gate spacers 37, and buffer dielectric layer 70 are not etched.

[0047] Thereafter, the dummy spacer portions 37B of the gate spacers 37 are removed in an etch step. The etch can be performed using dry etching or wet etching. The etchant is selected to not attack the exposed components of the inner sidewall spacers 37A, buffer dielectric layer 70, sacrificial fill material 72, hard mask layer 36, and possibly the dummy gate electrodes 34. As a result, the trenches 74 are formed as shown. Figure 14 As viewed from a top view, the trenches 74 will be rings that encircle the dummy gate stacks 30 and the inner sidewall spacers 37A. According to some embodiments, the dummy spacer portions comprise silicon oxide, and the etch uses a combination of NF3, HF, and water (H2O). Other etchants such as SiCONi (NF3and NH3), Certas (HF and NH3), and HF can also be used. In the formation of the trenches 74, the etchant is selected so that the hard mask layer 36, inner sidewall spacers 37A, buffer dielectric layer 70, and sacrificial fill material 72 are not damaged.

[0048] Figure 15 The formation of the dielectric seal layer 76 is shown. For example, the dielectric seal layer 76 can be formed of SiOC or silicon nitride, and other dielectric materials different from the materials of the buffer dielectric layer 70 and sacrificial fill material 72 can also be used. According to some embodiments, the formation of the dielectric seal layer 76 includes a conformal deposition process such as ALD or CVD, and a subsequent non-conformal deposition process such as PECVD. The conformal process results in a conformal layer deposited on the sidewalls of the inner sidewall spacers 37A and the sidewalls of the buffer dielectric layer 70, with air gaps 39 between the conformal layers. The non-conformal deposition process seals the top of the trenches 74 Figure 14 . As a result, the air gaps 39 are formed that are encircled by the dielectric seal layer 76. According to some embodiments of the invention, the air gaps 39 have a height H1 greater than about 75 nm, and can be in a range between about 75 nm and 500 nm, depending on the height of the dummy gate electrodes 34. The width W1 of the air gaps 39 can be in a range between about 2 nm and about 5 nm.

[0049] In Figure 15 and subsequent Figure 19A , Figure 19B , Figure 26A , Figure 26B , Figure 35A andFigure 35B In the figures, the shape of the air gap 39 is schematically shown as a rectangular cross-sectional view. It should be understood that the air gap 39, as shown in these figures, can have different shapes when different materials and / or methods are used to form the surrounding dielectric material, such as the dielectric sealing layer 76. Figure 37 Possible shapes of the air gap 39 according to some embodiments are shown. For example, the air gap 39 may have a teardrop shape, an elliptical shape, a rectangular shape with rounded corners, etc.

[0050] According to some embodiments, the sidewall portions of the dielectric sealing layer 76 have thicknesses T1 and T1', which can be in the range of about 1 nm and about 3 nm. The ratios T1 / W2 and T1' / W2 can be in the range of about 0.3 and about 0.5, where W2 is the trench 74 ( Figure 14 The width of ).

[0051] Subsequently, anisotropic etching was performed on the dielectric sealing layer 76, and the resulting structure is as follows: Figure 16 As shown. According to some embodiments of the invention, etching includes a dry etching process performed using process gases such as CF4 / O2 / N2 (a mixture of CF4, O2, and N2), NF3 / O2, SF6, SF6 / O2, etc. Therefore, the horizontal portions of the dielectric sealing layer 76 are removed. Some vertical portions of the dielectric sealing layer 76 retain the sealing gas gap 39. Throughout this specification, the combination of the inner sidewall spacer 37A, the dielectric sealing layer 76, and the gas gap 39 is referred to as the gate spacer 38.

[0052] Next, the remaining portion of the buffer dielectric layer 70 and sacrificial filler material 72 is removed during the etching step. The resulting structure is as follows. Figure 17 As shown, the sidewalls of the dielectric sealing layer 76 are exposed. Furthermore, the semiconductor fin 24' is exposed again. Figure 17 It also shows Figure 3 A cross-sectional view of the structure is shown. During etching, due to the differences between the dielectric sealing layer 76, the buffer dielectric layer 70, and the sacrificial filler 72, and the selection of appropriate etching chemicals, the etching selectivity is high, preventing damage to the dielectric sealing layer 76. Etching can be wet etching or dry etching. The etching selectivity is the ratio of the etching rate of the buffer dielectric layer 70 and the sacrificial filler 72 to the etching rate of the dielectric sealing layer 76. For example, according to some embodiments of the invention, the etching ratio is greater than about 100.

[0053] In subsequent steps, epitaxial region 42 (source / drain region) is formed, and Figure 18A A cross-sectional view of the epitaxial region 42 (source / drain region) is shown. Figure 18A The cross-sectional view shown is from and includes Figure 36 The line BB in the diagram is obtained from the same plane as the plane in the diagram. Also refer to...Figure 4 , Figure 5A and Figure 5B The formation of epitaxial region 42 (source / drain region) was discussed.

[0054] Figure 18B This illustrates the process following the formation of the epitaxial region 42 (source / drain region), from the region containing... Figure 36 A cross-sectional view obtained from the plane of line AA. Since the epitaxial regions 42 (source / drain regions) are not in the plane, they are not shown. Conversely, the STI region 22 is in the plane, and... Figure 18B As shown in the image.

[0055] Figure 19A and Figure 19B The formation of CESL 46 and ILD 48 and the subsequent planarization process are shown to make the top surfaces of CESL 46 and ILD 48 flush with the top surface of the gate spacer 38. Figure 19A and Figure 19B Different cross-sectional views of the same step are shown. Figure 19A It shows the contents Figure 36 The cross-sectional view obtained from the plane of line AA in the diagram. Figure 19B It shows the contents Figure 36 A cross-sectional view obtained from the plane of line BB in the diagram. A three-dimensional view of the structure is shown in... Figure 6 As shown in the image.

[0056] Figures 20-25 An air gap 39 is shown, formed after the replacement gate is formed and before the source / drain contact plug is formed, according to some embodiments. Figure 25 The intermediate stage of ). According to these embodiments, implementation Figures 1-7 The process shown, in which, skipping Figures 10-19A / Figure 19B The steps are shown. Therefore, in Figure 7 In the middle, air gap 39 has not yet formed, and will be discussed below. Figures 20-25 It is formed in the process shown.

[0057] Also there Figure 20 It shows Figure 7 The cross-sectional view of the structure shown. Figure 20 A gate dielectric layer 52 is shown, which includes an interface layer 54 and a high-k dielectric layer 56. The combination of the gate electrode 58 and the gate dielectric layer 52 forms a replacement gate 62. A hard mask 64 overlaps with the replacement gate 62.

[0058] Next step, refer to Figure 21 In the etching step, ILD 48 is recessed to form groove 78. Next, a protective layer 77 is formed, such as... Figure 22The protective layer 77 is formed of a material different from that of the dummy spacer portion 37B and a material different from that of the ILD 48. According to some embodiments of the present application, the protective layer 77 is formed of SiOC or other types of dielectric materials such as SiN, SiCN or SiC. Thereafter, a planarization process is implemented to form Figure 23 the structure shown, and exposes the top edge of the dummy spacer portion 37B. According to some embodiments of the present application, the resulting protective layer 77 can have a thickness T2 in a range between about 5 nm and about 10 nm. Further, according to some embodiments, the ratio T2 / H2 can be in a range between about 0.05 and about 0.1.

[0059] In the next step, the dummy spacer portion 37B is etched, forming a trench 74 as shown in Figure 24 . The etching process can be similar to that discussed with reference to Figure 14 , and thus is not repeated here. The trench 74 also forms a ring that surrounds the corresponding replacement gate 62. As shown in Figure 25 , in a subsequent process, a dielectric sealing layer 76 is formed. According to some embodiments of the present application, the dielectric sealing layer 76 is formed using a non-conformal deposition method such as PECVD, such that the air gap 39 is sealed in the dielectric sealing layer 76. It should be appreciated that the air gap 39 can have a shape different from that shown. For example, the air gap 39 can have a shape as shown in Figure 37 or other shapes.

[0060] According to some embodiments of the present application, the inner sidewall spacer 37A and the top and sidewall surfaces of the CESL 46 have at least some portions exposed to the air gap 39. The dielectric sealing layer 76 can also partially or completely cover the top and sidewall surfaces of the inner sidewall spacer 37A and the CESL 46, such that the air gap 39 is completely enclosed in the dielectric sealing layer 76, similar to those shown in Figure 19A and Figure 19B . The respective deposition of the dielectric sealing layer 76 can include a conformal deposition process such as ALD or CVD, and a subsequent non-conformal deposition process such as PECVD. Alternatively, the dielectric sealing layer 76 is formed with a non-conformal deposition process. Thereafter, a planarization process is implemented. The top surface of the remaining dielectric sealing layer 76 can be higher than or level with the top surface of the inner sidewall spacer 37A. Figure 25 The structure shown also corresponds to the structure shown in Figure 8 . Throughout the specification, the combination of the inner sidewall spacer 37A, the dielectric sealing layer 76 and the air gap 39 forms the gate spacer 38.

[0061] Figure 26A and Figure 26BFormation of ILD 80, source / drain contact plug 66A and gate contact plug 66B and subsequent planarization process are shown. Figure 26A and Figure 26B Different cross-sectional views of the same steps are shown. Figure 26A A cross-sectional view taken from a plane containing line A-A in Figure 36 is shown. Figure 26B A cross-sectional view taken from a plane containing line B-B in Figure 36 is shown. A perspective view of this structure is shown in Figure 9 except that gate contact plug 66B is shown in Figure 26A and Figure 26B As shown in Figure 26B , source / drain contact plug 66A is in contact with a source / drain silicide region 69 formed on the surface of epitaxial region 42 (source / drain region). According to some embodiments of the present application, contact plugs 66A and 66B include a metal nitride layer (such as a TiN layer) and a metal region (formed of tungsten or cobalt) above the metal nitride layer.

[0062] Figures 27-34 An intermediate stage in the formation of air gap 39 (shown in Figure 25 ) after the formation of replacement gate and source / drain contact plugs is shown according to some embodiments. According to these embodiments, the process shown in Figures 1-9 is implemented and the steps shown in Figures 10-18B and the process steps in Figures 20-25 are skipped. Thus, in Figure 9 , air gap 39 has not yet been formed and the process shown in Figures 27-34 is implemented later to form air gap 39.

[0063] Figure 27 A cross-sectional view of the structure shown in Figure 9 is shown, where replacement gates 62, hard mask 64 and source / drain contact plugs 66A are shown. Gate contact plugs have not yet been formed. According to these embodiments, as shown in Figure 27 , source / drain contact plugs 66A are shown as extending laterally to contact opposite vertical portions of CESL 46. Thus, in the plane shown, the portion of ILD 48 located between two adjacent replacement gates 62 is all replaced with source / drain contact plugs 66A. According to other embodiments of the present application, there can be remaining ILD 48 on opposite sides of contact plugs 66A, similar to that shown in Figure 26A . Hard mask 64 covers replacement gates 62. Hard mask 64 can be formed of Zr02, AI203, SiN, SiON, SiCN, Si02, etc.

[0064] According to some embodiments of the application, the contact plug 66A includes cobalt. As Figure 28 illustrated, a protective layer 86 can be formed to protect the underlying cobalt-containing contact plug 66A. According to some embodiments of the application, the protective layer 86 is an electrically conductive layer, which can further be a metal layer formed of a different metal than the metal in the contact plug 66A. For example, the protective layer 86 can be a tungsten layer. The protective layer 86 can also be formed of a dielectric material such as SiN, Si02, SiCN, etc. As Figure 28 illustrated, the formation of the protective layer 86 can include recessing the contact plug 66A to form a recess 85, depositing the protective layer 86 to a level above the top surface of the hard mask 64, planarizing the top surface of the protective layer 86, and performing an etch process to recess the protective layer 86. The corresponding steps are shown as steps 212 and 214 in the process flow 200, as Figure 38 illustrated. The level of the top surface of the protective layer 86 determines in part the height of the air gap to be subsequently formed. For example, the top surface of the protective layer 86 can be flush with or below the top surface of the replacement gate 62. The recess 85 has a depth Dl, which can be in a range between about 5 nm and about 10 nm. The ratio Dl / H3 can be in a range between about 0.08 and about 0.16, where H3 is the height of the contact plug 66A before the protective layer 86 is formed and recessed, as Figure 27 illustrated.

[0065] Next, as Figure 29 illustrated, the CESL 46 and the dummy spacer portion 37B are etched such that their top surfaces are lowered. The corresponding steps are shown as steps 216 and 218 in the process flow 200, as Figure 38 illustrated. The hard mask 64 and the protective layer 86 protect the underlying components from the etching. Thereafter, the dummy spacer portion 37B is removed in an etching step, forming the trench 74, as Figure 30 illustrated. The corresponding steps are shown as steps 216 and 218 in the process flow 200, as Figure 38 illustrated. The etching process can be an isotropic etching process, which can be a dry etching process or a wet etching process.

[0066] During the etching of the CESL 46 and the dummy spacer portion 37B, some portions of the ILD 48 (not shown in Figure 30 , refer to Figure 9 ) can be exposed. Therefore, an additional protective layer (not shown) can be formed to protect the exposed portions of the ILD 48 prior to the etching of the dummy spacer portion 37B. The formation process and material of the additional protective layer can be similar to those of the protective layer 77 shown in Figure 22 and Figure 23 . The additional protective layer protects the ILD 48 from etching when the trench 74 is formed.

[0067] In a subsequent step, as shown in Figure 31 , a dielectric layer is formed to seal the air gap 39. The corresponding step is shown as step 220 in the process flow 200 shown in Figure 38 . According to some embodiments of the application, the dielectric liner 87 is deposited as a conformal layer extending into the trench 74 ( Figure 30 ). According to some embodiments, the sidewall portions of the dielectric liner 87 have thicknesses T1 and T1', which can be in a range between about 0.5 nm and about 2 nm. The ratios T1 / W2 and T1' / W2 can be in a range between about 0.2 and about 0.4, where W2 is the width of the trench 74 ( Figure 30 ). According to alternative embodiments, the formation of the dielectric liner 87 is skipped. Thereafter, the dielectric sealing layer 76 is formed to seal the air gap 39. It should be appreciated that the air gap 39 can have a shape different from the shape shown. For example, the air gap 39 can have a shape shown in Figure 37 or other shapes. The dielectric sealing layer 76 can be formed using a non-conformal deposition method, such as PECVD, such that the height of the dielectric sealing layer 76 is as large as possible, e.g., greater than about 2 nm, and can be in a range between about 1 nm and about 3 nm. Thereafter, the protective layer 88 can be formed. According to some embodiments of the application, the protective layer 88 is formed using a material that provides high etch selectivity to the protective layer 88 and the ILD 48 ( Figure 35B , not shown in Figure 32 ). According to alternative embodiments, the protective layer 88 can not be formed depending on the materials in the wafer.

[0068] In a subsequent step, an anisotropic etch process (or multiple anisotropic etch processes) is implemented, and the horizontal portions of the dielectric liner 87, the dielectric sealing layer 76, and the protective layer 88 are removed. The resulting structure is shown in Figure 32 . As a result, the protective layer 86 is exposed. The corresponding step is shown as step 222 in the process flow 200 shown in Figure 38 . Throughout the specification, the combined area of the dielectric liner 87, the dielectric sealing layer 76, the protective layer 88, the inner sidewall spacer 37A, and the air gap 39 is referred to as the gate spacer 38.

[0069] Figure 33 The formation of the self-aligned dielectric region 90 is shown. The corresponding step is shown as step 224 in the process flow 200 shown in Figure 38 . According to some embodiments, the formation of the dielectric region 90 includes depositing a dielectric material, and implementing planarization to remove excess portions of the dielectric material above the top surface of the hard mask 64.

[0070] Figure 34 The formation of the etch stop layer 92 and the ILD 94 is shown. Figure 35A andFigure 35B Different cross-sectional views in the formation of the source / drain contact plug 96A and gate contact plug 66B and subsequent planarization process are shown. Figure 35A A cross-sectional view taken from a plane containing line A-A in Figure 36 Figure 35B A cross-sectional view taken from a plane containing line B-B in Figure 36 Figure 35B As shown, the source / drain contact plug 96 contacts the underlying protective layer 86 when the protective layer 86 is conductive, or the source / drain contact plug 96 passes through the protective layer 86 to contact the contact plug 66A when the protective layer 86 is formed of a dielectric material.

[0071] Embodiments of the present application have some advantageous features. Since the air gap has a k value equal to 1.0, which is lower than the k values of other dielectric materials, the k value of the gate spacer is reduced when the air gap is included. The reduction in the k value of the gate spacer results in a reduction in the parasitic capacitance between the gate electrode and nearby regions such as the source / drain regions and source / drain contacts. As a result, the speed of the resulting FinFET is improved.

[0072] ​​According to some embodiments of the application, a method includes forming a gate stack over a semiconductor region; and forming a first gate spacer on sidewalls of the gate stack. The first gate spacer includes an inner sidewall spacer and a dummy spacer portion located on an outer side of the inner sidewall spacer. The method also includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. A combination of the air gap and the inner sidewall spacer forms a second gate spacer. A source / drain region is formed to have a portion located on an outer side of the second gate spacer. In an embodiment, the method also includes forming a buffer dielectric layer contacting sidewalls of the first gate spacer; forming a sacrificial layer over a bottom of the buffer dielectric layer; recessing the buffer dielectric layer and the sacrificial layer to expose the dummy spacer portion, wherein the dummy spacer portion is removed after recessing the buffer dielectric layer and the sacrificial layer; and removing the buffer dielectric layer and the sacrificial layer. In an embodiment, the method also includes forming a contact etch stop layer contacting sidewalls of the first gate spacer; and forming an interlayer dielectric over a bottom of the contact etch stop layer, wherein the dummy spacer portion is removed after forming the interlayer dielectric, and the contact etch stop layer has sidewalls exposed to the air gap. In an embodiment, the method also includes forming a first source / drain contact plug electrically connected to the source / drain region over the source / drain region; recessing the first source / drain contact plug to form a recess; and forming a protective layer in the recess, wherein the dummy spacer portion is removed while the protective layer protects the first source / drain contact plug. In an embodiment, the protective layer is formed of a conductive material, and forming the protective layer includes forming a second source / drain contact plug located over and contacting the protective layer. In an embodiment, the method also includes forming a dielectric liner to fill a portion of the trench, wherein the air gap is spaced apart from the inner sidewall spacer by a portion of the dielectric liner. In an embodiment, the air gap has a portion extending below a top surface of the source / drain region.

[0073] According to some embodiments of the application, a method includes: forming a dummy gate stack on a semiconductor fin; forming a dummy gate spacer on a sidewall of the dummy gate stack; forming a contact etch stop layer over a source / drain region, wherein the source / drain region is located on a side of the dummy gate spacer; forming an interlayer dielectric over a portion of the contact etch stop layer; replacing the dummy gate stack with a replacement gate stack; forming a first contact plug electrically connected to the source / drain region over the source / drain region, wherein the first contact plug passes through the contact etch stop layer; etching a portion of the dummy gate spacer to form a trench; and forming a sealing layer to fill a top portion of the trench, wherein a lower portion of the trench is sealed as an air gap. In an embodiment, the dummy gate spacer includes: an inner sidewall portion; and a dummy spacer portion located on an outer side of the inner sidewall portion, wherein the dummy spacer portion is etched to form the trench, and the inner sidewall portion is left after the etching. In an embodiment, the inner sidewall portion includes: a vertical leg located on the dummy gate stack; and a horizontal leg, wherein the dummy spacer portion overlaps and contacts the horizontal leg, and wherein the trench extends to a top surface of the horizontal leg. In an embodiment, the method further includes forming a dielectric liner to fill an outer portion of the trench, wherein an inner portion of the trench is left as an air gap. In an embodiment, the method further includes forming a second contact plug contacting the first contact plug over the first contact plug, wherein the air gap is left after forming the second contact plug. In an embodiment, the method further includes, prior to etching the portion of the dummy gate spacer to form the trench, recessing the first contact plug to form a recess; and forming a protective layer in the recess, wherein the protective layer protects the first contact plug when the portion of the dummy gate spacer is etched. In an embodiment, the first contact plug includes cobalt, and the protective layer includes tungsten.

[0074] According to some embodiments of the application, a device includes: a gate stack; a gate spacer located on a sidewall of the gate stack, wherein the gate spacer includes: an inner sidewall spacer having a vertical portion contacting the gate stack; and an air gap, wherein the gate stack and the air gap are located on opposite sides of the vertical portion of the inner sidewall spacer; and a contact etch stop layer having a vertical portion, wherein the vertical portion of the contact etch stop layer and the vertical portion of the inner sidewall spacer are located on opposite sides of the air gap. In an embodiment, the air gap forms a ring surrounding the gate stack. In an embodiment, the device further includes a semiconductor fin, wherein the gate stack is located on a sidewall and a top surface of the semiconductor fin, and the air gap extends below the top surface of the semiconductor fin. In an embodiment, the inner sidewall spacer further includes a horizontal portion, and the air gap overlaps the horizontal portion. In an embodiment, the contact etch stop layer is exposed to the air gap. The device further includes a dielectric layer having a portion spacing the contact etch stop layer from the air gap.

[0075] According to some embodiments of the application, a method of forming a semiconductor device is provided, comprising: forming a gate stack over a semiconductor region; forming a first gate spacer on sidewalls of the gate stack, wherein the first gate spacer comprises: an inner sidewall spacer; and a dummy spacer portion on an outer side of the inner sidewall spacer; removing the dummy spacer portion to form a trench; forming a dielectric layer to seal a portion of the trench as an air gap, wherein a combination of the air gap and the inner sidewall spacer forms a second gate spacer; and forming the source / drain region including a portion on an outer side of the second gate spacer.

[0076] In the above method, further comprising: forming a buffer dielectric layer contacting sidewalls of the first gate spacer; forming a sacrificial layer over a bottom of the buffer dielectric layer; recessing the buffer dielectric layer and the sacrificial layer to expose the dummy spacer portion, wherein the dummy spacer portion is removed after recessing the buffer dielectric layer and the sacrificial layer; and removing the buffer dielectric layer and the sacrificial layer.

[0077] In the above method, further comprising: forming a contact etch stop layer contacting sidewalls of the first gate spacer; and forming an interlayer dielectric over a bottom of the contact etch stop layer, wherein the dummy spacer portion is removed after forming the interlayer dielectric, and the contact etch stop layer has sidewalls exposed to the air gap.

[0078] In the above method, further comprising: forming a first source / drain contact plug electrically connected to the source / drain region over the source / drain region; recessing the first source / drain contact plug to form a recess; and forming a protective layer in the recess, wherein the dummy spacer portion is removed when the protective layer protects the first source / drain contact plug.

[0079] In the above method, the protective layer is formed of a conductive material, and forming the protective layer comprises forming a second source / drain contact plug over the protective layer and contacting the protective layer.

[0080] In the above method, further comprising forming a dielectric liner to fill a portion of the trench, wherein the air gap is spaced apart from the inner sidewall spacer by a portion of the dielectric liner.

[0081] In the above method, the air gap has a portion extending below a top surface of the source / drain region.

[0082] According to other embodiments of the present invention, there is also provided a method of forming a semiconductor device, comprising: forming a dummy gate stack on a semiconductor fin; forming a dummy gate spacer on sidewalls of the dummy gate stack; forming a contact etch stop layer over a source / drain region, wherein the source / drain region is located on a side of the dummy gate spacer; forming an interlayer dielectric over portions of the contact etch stop layer; replacing the dummy gate stack with a replacement gate stack; forming a first contact plug electrically connected to the source / drain region over the source / drain region, wherein the first contact plug penetrates the contact etch stop layer; etching portions of the dummy gate spacer to form a trench; and forming a seal layer to fill a top portion of the trench, wherein a lower portion of the trench is sealed as an air gap.

[0083] In the above method, the dummy gate spacer comprises: an inner sidewall portion; and a dummy spacer portion located on an outer side of the inner sidewall portion, wherein the dummy spacer portion is etched to form the trench, and the inner sidewall portion is preserved after the etching.

[0084] In the above method, the inner sidewall portion comprises: a vertical leg located on the dummy gate stack; and a horizontal leg, wherein the dummy spacer portion overlaps and contacts the horizontal leg, and wherein the trench extends to a top surface of the horizontal leg.

[0085] In the above method, further comprising forming a dielectric liner to fill an outer portion of the trench, wherein an inner portion of the trench is left as the air gap.

[0086] In the above method, further comprising forming a second contact plug over the first contact plug, the second contact plug contacting the first contact plug, wherein the air gap is preserved after forming the second contact plug.

[0087] In the above method, further comprising: prior to etching portions of the dummy gate spacer to form the trench, recessing the first contact plug to form a recess; and forming a protective layer in the recess, wherein the protective layer protects the first contact plug when portions of the dummy gate spacer are etched.

[0088] In the above method, the first contact plug comprises cobalt, and the protective layer comprises tungsten.

[0089] According to yet other embodiments of the present invention, there is also provided a semiconductor device, comprising: a gate stack; a gate spacer on a sidewall of the gate stack, wherein the gate spacer comprises: an inner sidewall spacer having a vertical portion contacting the gate stack; and an air gap, wherein the gate stack and the air gap are on an outer side of the vertical portion of the inner sidewall spacer; and a contact etch stop layer having a vertical portion, wherein the vertical portion of the contact etch stop layer and the vertical portion of the inner sidewall spacer are on opposite sides of the air gap.

[0090] In the above semiconductor device, the air gap forms a ring surrounding the gate stack.

[0091] In the above semiconductor device, further comprising a semiconductor fin, wherein the gate stack is on a sidewall and a top surface of the semiconductor fin, and the air gap extends below the top surface of the semiconductor fin.

[0092] In the above semiconductor device, the inner sidewall spacer further comprises a horizontal portion, and the air gap overlaps the horizontal portion.

[0093] In the above semiconductor device, the contact etch stop layer is exposed to the air gap.

[0094] In the above semiconductor device, further comprising a dielectric layer having a portion spacing the contact etch stop layer from the air gap.

[0095] The features outlined herein summarize several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will appreciate that they can readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: A gate stack is formed above the semiconductor region; A first gate spacer is formed on the sidewall of the gate stack, wherein the first gate spacer includes: an inner sidewall spacer; and a pseudo spacer portion located on the outer side of the inner sidewall spacer; Remove the pseudo spacer portion to form a groove; A dielectric layer is formed to seal a portion of the trench as an air gap, wherein the combination of the air gap and the inner sidewall spacer forms a second gate spacer; and Forming a source / drain region including a portion located on the outside of the second gate spacer. The method for forming a semiconductor device further includes: Forming a contact etch stop layer that contacts the sidewall of the first gate spacer; and An interlayer dielectric is formed above the bottom of the contact etch stop layer, wherein the dummy spacer portion is removed after the interlayer dielectric is formed, and the contact etch stop layer has sidewalls exposed to the air gap. The air gap has a first portion extending below the top surface of the source / drain region, and a second portion of the source / drain region is exposed to the first portion of the air gap.

2. The method of claim 1, further comprising forming a source / drain contact plug extending into the interlayer dielectric.

3. The method of claim 2, further comprising forming a protective layer covering the interlayer dielectric, wherein the protective layer protects the interlayer dielectric when the pseudo spacer portion is removed.

4. The method of claim 3, wherein forming the protective layer comprises: The interlayer dielectric is recessed to form a groove; The protective layer is deposited and extends into the groove; as well as The protective layer is planarized to have a first top surface that is coplanar with the second top surface of the pseudo spacer portion.

5. The method of claim 4, wherein the source / drain plug further penetrates the protective layer.

6. The method according to claim 1, wherein, The inner wall spacer includes a horizontal leg and a vertical leg connected to the horizontal leg, the pseudo spacer portion overlapping the horizontal leg, wherein a first edge of the horizontal leg is perpendicularly aligned with a second edge of the pseudo spacer portion.

7. The method according to claim 1, wherein, The thickness of the inner wall spacer is in the range of 2nm to 5nm.

8. The method according to claim 1, wherein, The thickness of the pseudo spacer portion is in the range of 2 nm to 6 nm.

9. A semiconductor device, comprising: Gate stack ； A gate spacer is located on a sidewall of the gate stack, wherein the gate spacer includes: an inner sidewall spacer having a vertical portion contacting the gate stack; and an air gap, wherein the gate stack and the air gap are located on the outer side of the vertical portion of the inner sidewall spacer; and A contact etch stop layer has a vertical portion, wherein the vertical portion of the contact etch stop layer and the vertical portion of the inner sidewall spacer are located on opposite sides of the air gap. The semiconductor device further includes a source / drain region, which is adjacent to the gate stack. The air gap has a first portion extending below the top surface of the source / drain region, the first portion being located between the source / drain region and the inner sidewall spacer, and the source / drain region has a second portion exposed to the first portion of the air gap.

10. The semiconductor device according to claim 9, wherein, The air gap forms a ring surrounding the gate stack.

11. The semiconductor device of claim 9, further comprising semiconductor fins, wherein, The gate stack is located on the sidewalls and top surface of the semiconductor fin, and the air gap extends below the top surface of the semiconductor fin.

12. The semiconductor device according to claim 9, wherein, The inner wall spacer also includes a horizontal portion, and the air gap overlaps with the horizontal portion.

13. The semiconductor device according to claim 9, wherein, The contact etch stop layer is exposed in the air gap.

14. The semiconductor device of claim 9, further comprising an interlayer dielectric, the interlayer dielectric being above the bottom of the contact etch stop layer.

15. The semiconductor device of claim 14, further comprising a source / drain contact plug extending into the interlayer dielectric and contacting the source / drain region.

16. A semiconductor device, comprising: Gate stack, and source / drain regions adjacent to each other. An inner sidewall spacer, the inner sidewall spacer comprising: a vertical portion on the sidewall of the gate stack; and a horizontal portion extending from the bottom end of the vertical portion; The air gap is located on the outer side of the vertical portion of the inner wall spacer. A contact etch stop layer is located on opposite sides of the gate stack and covers the source / drain regions. The contact etch stop layer has a first vertical portion located above the source / drain regions and opposite the vertical portion. The air gap has a first portion located between the source / drain region and the vertical portion, wherein the vertical portion, the first vertical portion, the side of the source / drain region opposite to the vertical portion, the horizontal portion, and the dielectric sealing layer located between the first vertical portion and the vertical portion together surround and form the first portion.

17. The semiconductor device of claim 16, wherein at the first portion of the air gap, the interface between the source / drain region and the contact etch stop layer is located between the bottom surface of the dielectric sealing layer and the horizontal portion.

18. The semiconductor device of claim 16, wherein at the first portion of the air gap, the side of the source / drain region opposite to the vertical portion is aligned vertically with the side of the first vertical portion.

19. The semiconductor device according to claim 16, wherein, The air gap forms a ring surrounding the gate stack.

20. The semiconductor device of claim 16, further comprising an interlayer dielectric, the interlayer dielectric being located above the bottom of the contact etch stop layer.

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