A semiconductor structure and a method of fabrication

Abstract

The present application provides a semiconductor structure and a preparation method. The semiconductor structure comprises a semiconductor substrate, a shallow trench formed in the semiconductor substrate, and an isolation oxide layer filled in the shallow trench. The upper surface of the isolation oxide layer in a low voltage area is higher than the upper surface of the isolation oxide layer in a high voltage area. After forming a first gate oxide layer and a second gate oxide layer, the upper surface of the first gate oxide layer on the high voltage area isolation oxide layer is slightly higher than the upper surface of the low voltage area isolation oxide layer, thereby improving the flatness of the entire structure surface. The preparation method uses a first photomask in the existing process, combines with a method of coating a negative photoresist layer, exposes the high voltage area isolation oxide layer, and forms protection for the low voltage area. Then, the high voltage area isolation oxide layer is consumed and thinned, and then the first gate oxide layer is formed, thereby reducing the surface height of the first gate oxide layer on the high voltage area isolation oxide layer, and finally improving the flatness of the entire structure surface.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] With the increasing integration of semiconductor devices, a variety of circuits and devices operating at different voltages are often integrated on a chip. For devices in the high-voltage region and devices in the low-voltage region, gate oxide layers of different thicknesses are used to achieve different voltage withstand performances.

[0003] Referring to Figures 1-8 , in the prior art, the method for forming gate oxide layers of different thicknesses in the high-voltage region and the low-voltage region is as follows: first, a semiconductor intermediate structure is provided, as shown in Figure 1 , including a semiconductor substrate 101, a sacrificial oxide layer 102, a passivation layer 103, and an anti-reflective layer 104 stacked in sequence, the semiconductor substrate 101 has a shallow trench 11 formed therein, the inner wall of the shallow trench 11 has a line oxide layer 21 formed thereon, and an isolation oxide layer 105 is filled in the shallow trench 11 and protrudes from the anti-reflective layer 104; then, as shown in Figures 2-3 , the isolation oxide layer 105 above the active region is removed by etching, and then the anti-reflective layer 104 and the residual isolation oxide layer 105 protruding from the upper surface of the passivation layer 103 are removed by chemical mechanical polishing; then, as shown in Figure 4 , the sacrificial oxide layer 102 and the passivation layer 103 are removed by acid washing, and a first gate oxide layer 201 (thick gate oxide layer) is formed by thermal oxidation; then, as shown in Figures 5-7 , a positive photoresist is coated on the surface of the first gate oxide layer 201, the photoresist in the low-voltage region 100 is removed by exposure, and the first gate oxide layer 201 in the low-voltage region 100 is removed by wet etching; then, as shown in Figure 8 , the residual photoresist is removed, and a second gate oxide layer 210 (thin gate oxide layer) is formed on the active region of the low-voltage region by thermal oxidation. Finally, the low-voltage region 100 retains the relatively thin second gate oxide layer 210, and the high-voltage region 200 retains the relatively thick first gate oxide layer 201.

[0004] However, the above-mentioned process method has a problem, because the thicknesses of the first gate oxide layer 201 and the second gate oxide layer 210 are different, resulting in different height differences d1 between the upper surface of the isolation structure and the upper surface of the active region in the low-voltage region 100 and different height differences d2 between the upper surface of the isolation structure and the upper surface of the active region in the high-voltage region 200, that is, the first gate oxide layer 201 in the high-voltage region is more protruding, and d2 is usually greater than d1 The above is not conducive to the growth and etching of subsequent polysilicon, which further affects the regulation of device performance.

[0005] Therefore, it is necessary to propose a method to eliminate the protrusion of the first gate oxide layer 201 in the high-voltage area, make the surface of the whole structure as flat as possible, thereby facilitating the growth and etching of the subsequent polysilicon, and eliminating the adverse effects on the performance regulation of the device.

[0006] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art just because they are described in the background section of the present application. SUMMARY

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a semiconductor structure and a preparation method, which are used to solve the problem of the relatively protruding gate oxide layer in the high-voltage area in the prior art.

[0008] To achieve the above-mentioned purposes and other related purposes, the present application provides a preparation method of a semiconductor structure, which comprises the following steps:

[0009] S1: providing a semiconductor intermediate structure, comprising a semiconductor substrate, a sacrificial oxide layer, a passivation layer and an anti-reflection layer which are sequentially stacked, the semiconductor substrate is formed with a shallow trench, the shallow trench isolates an active area, an isolation oxide layer is filled in the shallow trench and protrudes from the anti-reflection layer, and the semiconductor substrate comprises a low-voltage area and a high-voltage area;

[0010] S2: removing the isolation oxide layer above the active area by etching process, and then removing the anti-reflection layer and part of the isolation oxide layer by chemical mechanical grinding, so that the upper surface of the isolation oxide layer is lower than the upper surface of the passivation layer;

[0011] S3: forming a negative photoresist layer on the upper surfaces of the isolation oxide layer and the passivation layer;

[0012] S4: shielding the high-voltage area with a first photoetching plate, then exposing and removing the negative photoresist layer of the high-voltage area;

[0013] S5: thinning the isolation oxide layer of the high-voltage area by dry etching;

[0014] S6: removing the negative photoresist layer, the sacrificial oxide layer and the passivation layer, and forming a first gate oxide layer on the semiconductor substrate and the isolation oxide layer.

[0015] Preferably, the preparation method further comprises the following steps:

[0016] S7: coating a positive photoresist layer on the surface of the first gate oxide layer, using the first photoetching plate to shield the high-voltage area, then performing exposure, removing the positive photoresist layer in the low-voltage area, and removing the first gate oxide layer in the low-voltage area;

[0017] S8: removing the positive photoresist layer, and forming a second gate oxide layer on the active area in the low-voltage area, thereby forming the semiconductor structure.

[0018] Preferably, in the semiconductor structure, the height difference d1 between the upper surface of the isolation oxide layer in the low-voltage area and the upper surface of the active area has the following relationship with the height difference d2 between the upper surface of the first gate oxide layer on the isolation oxide layer in the high-voltage area and the upper surface of the active area:

[0019] Preferably, in the semiconductor structure, the upper surface of the first gate oxide layer on the isolation oxide layer in the high-voltage area is higher than the upper surface of the isolation oxide layer in the low-voltage area.

[0020] Preferably, the first gate oxide layer and the second gate oxide layer are formed by a thermal oxidation process.

[0021] Preferably, the first gate oxide layer and the second gate oxide layer are both silicon oxide.

[0022] Preferably, the formation of the semiconductor intermediate structure in step S1 comprises the following steps:

[0023] S1-1: sequentially forming the sacrificial oxide layer, the passivation layer, and the anti-reflection layer on the semiconductor substrate;

[0024] S1-2: forming a photoresist on the anti-reflection layer and patterning the photoresist, using the patterned photoresist as a mask to etch the semiconductor substrate, the sacrificial oxide layer, the passivation layer, and the anti-reflection layer, thereby forming the shallow trench in the substrate, and the shallow trench isolates the active area;

[0025] S1-3: growing a line oxide layer on the inner wall of the shallow trench, and the isolation oxide layer is formed on the surface of the line oxide layer.

[0026] Preferably, the isolation oxide layer is obtained by high-density plasma deposition.

[0027] Preferably, after the isolation oxide layer in the high-voltage area is thinned in step S5, the upper surface of the isolation oxide layer is lower than the upper surface of the isolation oxide layer in the low-voltage area.

[0028] The present application also provides a semiconductor structure, which comprises:

[0029] A semiconductor substrate comprising a low-voltage area and a high-voltage area, and a shallow trench formed in the semiconductor substrate, and the shallow trench isolates an active area.

[0030] an isolation oxide layer filled in the shallow trench, the upper surface of the isolation oxide layer in the low voltage area being higher than the upper surface of the isolation oxide layer in the high voltage area;

[0031] a first gate oxide layer formed on the upper surface of the isolation oxide layer and the active region in the high voltage area;

[0032] a second gate oxide layer formed on the upper surface of the active region in the low voltage area.

[0033] Preferably, in the semiconductor structure, the height difference d1 between the upper surface of the isolation oxide layer in the low voltage area and the upper surface of the active region and the height difference d2 between the upper surface of the first gate oxide layer on the isolation oxide layer in the high voltage area and the upper surface of the active region have the following relationship:

[0034] Preferably, in the semiconductor structure, the upper surface of the first gate oxide layer on the isolation oxide layer in the high voltage area is higher than the upper surface of the isolation oxide layer in the low voltage area.

[0035] Preferably, a line oxide layer is formed on the inner wall of the shallow trench, and the isolation oxide layer is formed on the surface of the line oxide layer.

[0036] Preferably, the first gate oxide layer and the second gate oxide layer are both silicon oxide.

[0037] As described above, the present application provides a semiconductor structure and a preparation method. The semiconductor structure comprises a semiconductor substrate, a shallow trench formed in the semiconductor substrate, and an isolation oxide layer filled in the shallow trench. The upper surface of the isolation oxide layer in the low voltage area is higher than the upper surface of the isolation oxide layer in the high voltage area. After the formation of the first gate oxide layer and the second gate oxide layer, the upper surface of the first gate oxide layer on the isolation oxide layer in the high voltage area is slightly higher than the upper surface of the isolation oxide layer in the low voltage area, thereby improving the flatness of the entire structure surface, facilitating the growth and etching of the polysilicon, and eliminating the adverse effects on the performance of the device. The preparation method uses the first photolithography plate in the existing process, combines the method of coating a negative photoresist layer, exposes the isolation oxide layer in the high voltage area, and protects the low voltage area at the same time. Then, the isolation oxide layer in the high voltage area is consumed and thinned, and then the first gate oxide layer is formed, thereby reducing the surface height of the first gate oxide layer on the isolation oxide layer in the high voltage area, and finally improving the flatness of the entire structure surface. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figures 1-8 A process flow diagram for forming different thickness gate oxide layers in the prior art is shown.

[0039] Figures 9-19 A process flow diagram for forming a semiconductor structure in the present application is shown.

[0040] Element No.

[0041] 11 Shallow trench

[0042] 12 Active region

[0043] 101 Semiconductor substrate

[0044] 102 Sacrificial oxide layer

[0045] 103 Passivation layer

[0046] 104 Anti-reflective layer

[0047] 105 Isolation oxide layer

[0048] 201 First gate oxide layer

[0049] 202 Positive photoresist layer

[0050] 203 Negative photoresist layer

[0051] 301 First photo mask

[0052] 210 Second gate oxide layer

[0053] 100 Low voltage region

[0054] 200 High voltage region DETAILED DESCRIPTION

[0055] The present application is herein described, by way of example only, with the assistance of specific details to facilitate a comprehensive understanding of the application by those skilled in the art. The application can be practiced without recourse to these specific details. The description herein is intended to be illustrative only and is not intended to limit the scope of the present application, which is defined by the appended claims.

[0056] In the detailed description of embodiments of the application, only the preferred embodiments are shown and described, and it is to be understood that modifications and variations can be affected without departing from the scope of the application. For the purposes of clarity and the understanding of the general principles of the application, reference is made to the accompanying drawings that illustrate and explain the application.

[0057] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may be present. As used herein, "between" is inclusive of both endpoints.

[0058] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0059] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0060] This embodiment provides a method for preparing a semiconductor structure, comprising the following steps:

[0061] S1: Providing a semiconductor intermediate structure, including a semiconductor substrate 101, a sacrificial oxide layer 102, a passivation layer 103, and an anti-reflection layer 104 stacked in sequence, wherein a shallow trench 11 is formed in the semiconductor substrate, wherein the shallow trench 11 isolates an active area 12, a line oxide layer 21 is formed on the inner wall of the shallow trench 11, an isolation oxide layer 105 is filled in the shallow trench 11 and protrudes from the anti-reflection layer 104, and the semiconductor substrate 101 includes a low-voltage region 100 and a high-voltage region 200;

[0062] S2: Next, the isolation oxide layer 105 above the active area is removed by an etching process, and then the anti-reflection layer 104 and a portion of the isolation oxide layer 10 are removed by chemical mechanical polishing, so that the upper surface of the isolation oxide layer 105 is lower than the upper surface of the passivation layer 103;

[0063] S3: forming a negative photoresist layer 203 on the upper surfaces of the isolation oxide layer 105 and the passivation layer 103;

[0064] S4: using the first photoresist 301 to shield the high-voltage area 200, and then performing exposure to remove the negative photoresist layer 203 in the high-voltage area 200;

[0065] S5: using dry etching to thin the isolation oxide layer 105 of the high voltage region 200.

[0066] S6: removing the negative photoresist layer 203, the sacrificial oxide layer 102, and the passivation layer 103, and forming a first gate oxide layer 201 (thick gate oxide layer) on the semiconductor substrate 101 and the isolation oxide layer 105;

[0067] S7: Coating a positive photoresist layer 202 on the surface of the first gate oxide layer 201, using the first photomask 301 to shield the high-voltage area 200, and then performing exposure, removing the positive photoresist layer 202 in the low-voltage area 100, and removing the first gate oxide layer 201 in the low-voltage area 100;

[0068] S8: Remove the positive photoresist layer 202 and form a second gate oxide layer 210 (thin gate oxide layer) on the active area 12 of the low voltage region 100. Finally, the low voltage region 100 retains the thinner second gate oxide layer 210, while the high voltage region 200 retains the thicker first gate oxide layer 201.

[0069] The preparation process of the semiconductor structure of the present invention will be described in detail below with reference to the accompanying drawings.

[0070] As an embodiment, the formation of the semiconductor intermediate structure in step S1 specifically includes the following steps:

[0071] S1-1: forming a sacrificial oxide layer 102, a passivation layer 103, and an anti-reflection layer 104 in sequence on a semiconductor substrate 101;

[0072] Specifically, if Figure 1 As shown, the material of the semiconductor substrate 101 can be silicon, germanium, silicon-on-insulator (SOI), or silicon carbide substrate, etc., or a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, etc., and is preferably silicon in this embodiment. The sacrificial oxide layer 102 can be formed by an oxidation growth process, which can provide a buffer for the subsequent passivation layer 103, avoiding the disadvantage of dislocations generated when the passivation layer 103 such as silicon nitride is directly grown on the semiconductor substrate 101, thereby protecting the semiconductor substrate 101. In this embodiment, the sacrificial oxide layer 102 and the anti-reflection layer 104 are preferably silicon oxide layers, and the passivation layer 103 is preferably a silicon nitride layer.

[0073] Next, step S1-2 is performed: a photoresist is formed on the anti-reflection layer 104 and patterned, and the patterned photoresist layer is used as a mask to etch the semiconductor substrate 101, the sacrificial oxide layer 102, the passivation layer 103 and the anti-reflection layer 104 to form a shallow trench 11 in the substrate 101, and the shallow trench 11 isolates the active area 12.

[0074] Next, step S1-3 is performed: a linear oxide layer 21 is grown on the inner wall (including the bottom and sidewalls) of the shallow trench 11, and then an isolation oxide layer 105 is formed in the shallow trench 11. Specifically, the linear oxide layer 21 is preferably a silicon oxide layer, and the isolation oxide layer 105 is also silicon oxide. The isolation oxide layer 105 is preferably deposited using a high-density plasma (HDP) method. HDP can achieve excellent step coverage and is particularly suitable for filling high-aspect-ratio gaps. It has good hole-filling effect. The deposited insulating dielectric film has advantages such as high density and low impurity defects, and has excellent adhesion to silicon wafers.

[0075] Further, if Figures 2-3 As shown, as an embodiment, in step S2, the isolation oxide layer 105 above the active area is partially removed by an etching process, and then the anti-reflection layer 104 and the upper isolation oxide layer 10 are removed by chemical mechanical polishing, so that the upper surface of the isolation oxide layer 105 is lower than the upper surface of the passivation layer 103;

[0076] Specifically, step 2 is similar to the process in the above-mentioned background technology. The isolation oxide layer 105 above the active area is partially removed by the active area inversion. The active area inversion is used to protect the isolation oxide layer 105 in the shallow trench, and only the isolation oxide layer 105 above the active area 105 is removed. This process cannot completely remove the isolation oxide layer 105 above the active area 105, but can only remove most of it. Then, the anti-reflective layer 104 and the upper isolation oxide layer 10 are removed by chemical mechanical polishing, so that the upper surface of the isolation oxide layer 105 is lower than the upper surface of the passivation layer 103. It should be understood that in the process of planarization by chemical mechanical polishing, different materials have different removal rates, so it cannot be guaranteed that the upper surface of the isolation oxide layer 105 after planarization is completely flush with the upper surface of the passivation layer 103.

[0077] Further, if Figure 9 As shown, as an embodiment, in step S3, a negative photoresist layer 203 is formed on the upper surfaces of the isolation oxide layer 105 and the passivation layer 103;

[0078] Specifically, the negative photoresist layer, also known as photoresist, is a mixture of light-sensitive liquid composed of three main components: photosensitive resin, sensitizer (photosensitive dye) and solvent. After light exposure, the photosensitive resin can quickly undergo a photocuring reaction in the exposed area, causing the physical properties of the material, particularly solubility, affinity, etc. to change significantly. After proper solvent treatment, the soluble part is dissolved, and the desired image is obtained, that is, the exposed area is the final reserved pattern. On the contrary, the positive photoresist layer is exposed to ultraviolet light and other light sources. The exposed area can quickly decompose the photosensitive part, which is soluble in the developer. The unexposed part is insoluble in the developer and remains on the substrate. The pattern of the photoetching plate is the final reserved pattern of the positive photoresist layer.

[0079] Further, as shown in Figures 10-11 , as an embodiment, in step S4, the high-voltage area 200 is shielded by the first photoetching plate 301, and then exposed to light to remove the negative photoresist layer 203 of the high-voltage area 200.

[0080] The part of the negative photoresist layer 203 shielded by the first photoetching plate 301 is removed, that is, the negative photoresist layer 203 of the high-voltage area 200 is removed. The reason for using negative photoresist here is that the first photoetching plate 301 is needed in the later step S7 to form the low-voltage area second gate oxide layer 210. Therefore, in order to utilize the first photoetching plate 301 to save costs, negative photoresist is selected without the need to make additional photoetching plates.

[0081] Further, as shown in Figure 12 , as an embodiment, in step S5, dry etching is used to thin the isolation oxide layer 105 of the high-voltage area 200.

[0082] Specifically, in this step, the isolation oxide layer 105 of the high-voltage area is first thinned so that its upper surface is lower than the upper surface of the isolation oxide layer 105 of the low-voltage area. Therefore, after forming the first gate oxide layer 201, the upper surface of the first gate oxide layer 201 can be slightly higher than the upper surface of the isolation oxide layer 105 of the low-voltage area.

[0083] Further, as shown in Figure 13 , as an embodiment, in step S6, the negative photoresist layer 203, the sacrificial oxide layer 102, and the passivation layer 103 are removed, and the first gate oxide layer 201 (thick gate oxide layer) is formed on the semiconductor substrate 101 and the isolation oxide layer 105.

[0084] Specifically, the sacrificial oxide layer 102 and the passivation layer 103 can be removed by acid washing, and then the first gate oxide layer 201 is formed by a thermal oxidation process. The material of the first gate oxide layer 201 is preferably silicon oxide, and the thickness of the first gate oxide layer 201 can be adjusted according to actual needs, which is not limited here.

[0085] Further, as shown in the figure, as an embodiment, in step S7, a positive photoresist layer 202 is coated on the surface of the first gate oxide layer 201, the high-voltage area 200 is shielded by using the first photoetching plate 301, and then exposure is performed, the positive photoresist layer 202 of the low-voltage area 100 is removed, and the first gate oxide layer 201 of the low-voltage area 100 is removed. Figures 14-18

[0086] Specifically, in step S7, the positive photoresist layer is selected, and the purpose is to expose the surface of the low-voltage area 100 when the first photoetching plate 301 is used, so as to remove the first gate oxide layer 201 of the low-voltage area. Here, wet etching is preferably used to remove the first gate oxide layer 201 of the low-voltage area 100.

[0087] Further, as shown in the figure, as an embodiment, in step S8, the positive photoresist layer 202 is removed, and the second gate oxide layer 210 is formed on the active area 12 of the low-voltage area 100. Figure 19

[0088] Specifically, similar to the first gate oxide layer 201, the second gate oxide layer 210 is also formed by a thermal oxidation process, and the material of the second gate oxide layer 210 is also preferably silicon oxide. The thickness of the second gate oxide layer 201 can be adjusted according to actual needs. After step S8 is completed, the height difference d1 between the upper surface of the isolation oxide layer 105 of the low-voltage area 100 and the upper surface of the active area 12 has the following relationship with the height difference d2 between the upper surface of the first gate oxide layer 201 of the isolation oxide layer 105 of the high-voltage area 200 and the upper surface of the active area: That is, the upper surface of the first gate oxide layer 201 of the isolation oxide layer 105 of the high-voltage area 200 is slightly higher than the upper surface of the isolation oxide layer 105 of the low-voltage area 100. Thus, the flatness of the entire structure surface is improved, which is beneficial to the growth and etching of the subsequent polysilicon and eliminates the adverse effects on the performance control of the device. It should be noted that the second gate oxide layer 201 is also formed on the high-voltage area 200 at the same time, but its thickness is very thin, so it can be ignored.

[0089] ​​The embodiment provides a preparation method of a semiconductor structure. A first photoetching plate in an existing process is combined with a method of coating a negative photoresist layer to expose an isolation oxide layer in a high-voltage area and form protection for a low-voltage area. Then, the isolation oxide layer in the high-voltage area is consumed and thinned, and then a first gate oxide layer is formed, so as to reduce the surface height of the first gate oxide layer on the isolation oxide layer in the high-voltage area. Finally, the upper surface of the first gate oxide layer in the high-voltage area is slightly higher than the upper surface of the isolation oxide layer in the low-voltage area, so as to improve the flatness of the surface of the whole structure, thereby facilitating the growth and etching of polysilicon in the subsequent process and eliminating the adverse effect on the performance of the device.

[0090] Embodiment two

[0091] The embodiment provides a semiconductor structure which can be formed by the preparation method in the above embodiment one, but is not limited to the preparation method in the above embodiment one, such as shown in the following figure. Figure 18 The semiconductor structure specifically comprises:

[0092] A semiconductor substrate 101 comprises a low-voltage area 100 and a high-voltage area 200. A shallow trench 11 is formed in the semiconductor substrate 101, and the shallow trench 11 isolates an active area.

[0093] An isolation oxide layer 105 is filled in the shallow trench. The upper surface of the isolation oxide layer 105 in the low-voltage area 100 is higher than the upper surface of the isolation oxide layer 105 in the high-voltage area 200.

[0094] A first gate oxide layer 201 is formed on the upper surface of the isolation oxide layer 105 and the active area 12 in the high-voltage area 200.

[0095] A second gate oxide layer 210 is formed on the upper surface of the active area 12 in the low-voltage area 100.

[0096] The height difference d1 between the upper surface of the isolation oxide layer 105 in the low-voltage area 100 and the upper surface of the active area 12 and the height difference d2 between the upper surface of the first gate oxide layer 201 on the isolation oxide layer 105 in the high-voltage area 200 and the upper surface of the active area have the following relationship: That is, the upper surface of the first gate oxide layer 201 on the isolation oxide layer 105 in the high-voltage area 200 is slightly higher than the upper surface of the isolation oxide layer 105 in the low-voltage area 100. Therefore, the flatness of the surface of the whole structure is improved, the growth and etching of polysilicon in the subsequent process are facilitated, and the adverse effect on the performance of the device is eliminated.

[0097] Further, a line oxide layer 21 is formed on the inner wall of the shallow trench 11, and the isolation oxide layer 105 is formed on the surface of the line oxide layer 21.

[0098] Specifically, the semiconductor substrate 101 can be silicon, germanium, silicon-on-insulator (SOI), or silicon carbide substrate, etc., the shallow trench 11 can be formed by etching, after the shallow trench 11 is formed by etching, a line oxide layer 21 is formed on the inner wall (including the bottom and the sidewall) of the shallow trench 11, and then the isolation oxide layer 105 is filled in the shallow trench 11. Specifically, the line oxide layer 21 is preferably a silicon oxide layer, and the isolation oxide layer 105 is also silicon oxide, and the isolation oxide layer 105 is preferably obtained by high-density plasma (HDP) deposition, HDP can achieve very good step coverage, is particularly suitable for filling high-aspect-ratio gaps, has good hole-filling effect, and the deposited insulating medium film has the advantages of high density, low impurity defects, and excellent adhesion to silicon wafers.

[0099] The first gate oxide layer 201 and the second gate oxide layer 210 can be formed by a thermal oxidation process, and are preferably silicon oxide materials, and the thickness can be adjusted according to actual needs.

[0100] In summary, the present application provides a semiconductor structure and a preparation method, the semiconductor structure includes a semiconductor substrate, a shallow trench is formed in the semiconductor substrate, and an isolation oxide layer is filled in the shallow trench, the upper surface of the isolation oxide layer in the low-voltage region is higher than the upper surface of the isolation oxide layer in the high-voltage region, so that after the first gate oxide layer and the second gate oxide layer are formed, the upper surface of the first gate oxide layer on the high-voltage region isolation oxide layer is slightly higher than the upper surface of the low-voltage region isolation oxide layer, thereby improving the flatness of the entire structure surface, facilitating the growth and etching of the subsequent polysilicon, and eliminating the adverse effects on the performance control of the device. The preparation method uses the first photolithography plate in the existing process, combines the method of coating a negative photoresist layer, exposes the isolation oxide layer in the high-voltage region, and at the same time protects the low-voltage region. Then the isolation oxide layer in the high-voltage region is consumed and thinned, and then the first gate oxide layer is formed, thereby reducing the surface height of the first gate oxide layer on the high-voltage region isolation oxide layer, and finally improving the flatness of the entire structure surface.

[0101] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises the following steps: S1: Providing a semiconductor intermediate structure, including a semiconductor substrate, a sacrificial oxide layer, a passivation layer, and an anti-reflection layer stacked in sequence, wherein a shallow trench is formed in the semiconductor substrate, the shallow trench isolating an active area, an isolation oxide layer is filled in the shallow trench and protrudes from the anti-reflection layer, and the semiconductor substrate includes a low-voltage area and a high-voltage area; S2: removing the isolation oxide layer above the active area by an etching process, and then removing the anti-reflection layer and a portion of the isolation oxide layer by chemical mechanical polishing, so that the upper surface of the isolation oxide layer is lower than the upper surface of the passivation layer; S3: forming a negative photoresist layer on the upper surfaces of the isolation oxide layer and the passivation layer; S4: using a first photomask to shield the high-voltage area, then performing exposure, and removing the negative photoresist layer in the high-voltage area; S5: thinning the isolation oxide layer in the high voltage area by dry etching; S6: removing the negative photoresist layer, the sacrificial oxide layer, and the passivation layer, and forming a first gate oxide layer on the semiconductor substrate and the isolation oxide layer; S7: coating a positive photoresist layer on the surface of the first gate oxide layer, shielding the high-voltage area with the first photomask, and then exposing the layer to light, removing the positive photoresist layer in the low-voltage area, and removing the first gate oxide layer in the low-voltage area; S8: removing the positive photoresist layer and forming a second gate oxide layer on the active area of ​​the low voltage region, thereby forming the semiconductor structure; the height difference d1 between the upper surface of the isolation oxide layer in the low voltage region and the upper surface of the active area and the height difference d2 between the upper surface of the first gate oxide layer on the isolation oxide layer in the high voltage region and the upper surface of the active area have the following relationship: 0≤d2-d1≤ In step S5 , after the isolation oxide layer in the high-voltage region is thinned, its upper surface is lower than the upper surface of the isolation oxide layer in the low-voltage region, thereby improving the surface flatness of the entire semiconductor structure.

2. The preparation method according to claim 1, characterized in that In the semiconductor structure, an upper surface of the first gate oxide layer on the high-voltage region isolation oxide layer is higher than an upper surface of the low-voltage region isolation oxide layer.

3. The preparation method according to claim 1, characterized in that The first gate oxide layer and the second gate oxide layer are formed by a thermal oxidation process.

4. The preparation method according to claim 1, characterized in that The first gate oxide layer and the second gate oxide layer are both made of silicon oxide.

5. The preparation method according to claim 1, characterized in that The formation of the semiconductor intermediate structure in step S1 includes the following steps: S1-1: forming the sacrificial oxide layer, the passivation layer, and the anti-reflection layer in sequence on the semiconductor substrate; S1-2: forming a photoresist on the anti-reflection layer and patterning the photoresist, etching the semiconductor substrate, the sacrificial oxide layer, the passivation layer and the anti-reflection layer using the patterned photoresist as a mask to form the shallow trench in the substrate, wherein the shallow trench isolates the active area; S1-3: growing a linear oxide layer on the inner wall of the shallow trench, and forming the isolation oxide layer on the surface of the linear oxide layer.

6. The preparation method according to claim 1, characterized in that The isolation oxide layer is deposited by a high-density plasma method.

7. A semiconductor structure, characterized in that The semiconductor structure comprises: A semiconductor substrate comprising a low-voltage region and a high-voltage region, wherein a shallow trench is formed in the semiconductor substrate, and the shallow trench isolates an active region; an isolation oxide layer, filling the shallow trench; a first gate oxide layer formed on the isolation oxide layer of the high voltage region and the upper surface of the active region; A second gate oxide layer is formed on the upper surface of the active area of ​​the low voltage area. The upper surface of the isolation oxide layer in the low-voltage region is higher than the upper surface of the isolation oxide layer in the high-voltage region, thereby improving the surface flatness of the entire semiconductor structure; the height difference d1 between the upper surface of the isolation oxide layer in the low-voltage region and the upper surface of the active region and the height difference d2 between the upper surface of the first gate oxide layer on the isolation oxide layer in the high-voltage region and the upper surface of the active region have the following relationship:

8. The semiconductor structure according to claim 7, wherein: In the semiconductor structure, an upper surface of the first gate oxide layer on the high-voltage region isolation oxide layer is higher than an upper surface of the low-voltage region isolation oxide layer.

9. The semiconductor structure according to claim 7, wherein: A linear oxide layer is formed on the inner wall of the shallow trench, and the isolation oxide layer is formed on the surface of the linear oxide layer.

10. The semiconductor structure according to claim 7, wherein: The first gate oxide layer and the second gate oxide layer are both made of silicon oxide.

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