A semiconductor device test structure and a test method thereof

Abstract

The present application provides a semiconductor device test structure and a test method therefor. The test structure includes a dielectric layer and a plurality of metal layers arranged at intervals in the dielectric layer. The metal layers include a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer arranged from bottom to top, and wires and switches are arranged between different metal layers to associate the metal layers in different regions. By applying test voltages at different positions of the same test structure to test the electrical properties of the dielectric layer between different metal layers, it is determined whether there is leakage in the dielectric layer between different metal layers, and further whether there is leakage in the dielectric layer in the semiconductor device structure, which can effectively improve the flexibility and efficiency of the test structure while reducing the occupied area of the chip layout.

Description

Technical Field

[0001] This application relates to the field of semiconductor-related technologies, and in particular, to a semiconductor device test structure and a test method thereof. Background Art

[0002] In integrated circuit manufacturing, in the BEOL (Back End Of Line) stage, materials with lower capacitance values are usually filled between metal layers as dielectric layers, such as the dielectric layer between interconnect lines, the dielectric layer between an interconnect line and a via, the dielectric layer between vias, etc., to reduce the breakdown voltage. Silicon dioxide is usually selected as the dielectric layer material.

[0003] Currently, for the test of IMD (Inter Metal Dielectric) performance, it mainly focuses on testing the IMD properties corresponding to the metal line layer to metal line layer structure, via to via structure, and the upper metal line layer to the lower metal line layer structure. However, various types of defects that may exist in the IMD, or aging caused by the use environment or service time, may all cause the risk of leakage failure of the IMD at different positions. Designing a separate test structure for the IMD properties at different positions will greatly occupy the area of the chip layout, and there are problems of poor test flexibility and low test efficiency.

[0004] Therefore, how to provide a new semiconductor device test structure and a test method thereof, which can effectively improve the flexibility and efficiency of IMD property testing and reduce the occupied area of the chip layout, has become an urgent problem to be solved in this field. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor device test structure and a test method thereof, which can effectively improve the flexibility and efficiency of IMD property testing and reduce the occupied area of the chip layout.

[0006] In a first aspect, an embodiment of this application provides a semiconductor device test structure, including a dielectric layer and a plurality of metal layers arranged at intervals in the dielectric layer. The plurality of metal layers include a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer arranged from bottom to top. The dielectric layer is separated by the metal layers into a first dielectric layer, a second dielectric layer, and a third dielectric layer sandwiched between adjacent metal layers from bottom to top.

[0007] The dielectric layer includes three partitions arranged transversely, including a first partition, a second partition, and a third partition. The same metal layer located in different partitions is isolated from each other by the dielectric layer. Adjacent metal layers in the second partition are electrically connected by metal pillars. The second metal layer and the third metal layer in the first partition are electrically connected by the metal pillars. The first metal layer and the second metal layer, and the third metal layer and the fourth metal layer in the third partition are respectively electrically connected by the metal pillars. The second metal layer and the third metal layer in the third partition are connected by a first wire; the fourth metal layer in the third partition and the third metal layer in the first partition are connected by a second wire. Switches are respectively provided on the first wire and the second wire.

[0008] In a possible implementation manner, a first switch is provided on the first wire, a second switch and a third switch are provided on the second wire, and the first switch, the second switch, and the third switch include diodes with unidirectional conductivity.

[0009] In a possible implementation manner, the positive electrode of the first switch is connected to the second metal layer in the third partition, the positive electrode of the second switch is connected to the fourth metal layer in the third partition, the positive electrode of the third switch is connected to the third metal layer in the first partition, and the negative electrode of the second switch is connected to the negative electrode of the third switch.

[0010] In a possible implementation manner, it further includes a first test terminal, a second test terminal, a third test terminal, a fourth test terminal, and a fifth test terminal. The first test terminal is connected in series between the second switch and the third switch and is respectively connected to the negative electrodes of the second switch and the third switch; the second test terminal is connected to the fourth metal layer in the second partition; the third test terminal is connected in series between the second switch and the fourth metal layer in the third partition; the fourth test terminal is connected to the first metal layer in the third partition, and the fifth test terminal is connected to the third metal layer in the first partition.

[0011] In a possible implementation manner, the first test terminal, the second test terminal, the third test terminal, the fourth test terminal, and the fifth test terminal are all exposed on the surface of the dielectric layer.

[0012] In a possible implementation manner, the material of the metal layer includes copper or aluminum, and the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are different, including low-K or ultra-low-K materials.

[0013] In a second aspect, an embodiment of the present application further provides a test method for a semiconductor device test structure, including the above semiconductor device test structure, and steps for confirming whether there is leakage in the first dielectric layer, the second dielectric layer, and the third dielectric layer, specifically including:

[0014] Apply a positive voltage to the second test terminal and a negative voltage to the first test terminal;

[0015] When there is a current between the first test terminal and the second test terminal, then there is a leakage in one or more of the first dielectric layer, the second dielectric layer, and the third dielectric layer.

[0016] In a possible implementation manner, it includes the step of confirming the position where there is a leakage between the first dielectric layer, the second dielectric layer, and the third dielectric layer, specifically including;

[0017] Apply a positive voltage to the fourth test terminal and a negative voltage to the second test terminal;

[0018] When there is no current between the fourth test terminal and the second test terminal, then the second dielectric layer has a leakage, and the first dielectric layer and the third dielectric layer are normal;

[0019] When there is a first current value between the fourth test terminal and the second test terminal, then there is a leakage in the first dielectric layer and / or the third dielectric layer.

[0020] In a possible implementation manner, when there is a leakage in the first dielectric layer and / or the third dielectric layer, it further includes the step of confirming whether there is a leakage in the second dielectric layer, specifically including:

[0021] Apply a positive voltage to the fifth test terminal and a negative voltage to the second test terminal;

[0022] When there is a current between the fifth test terminal and the second test terminal, then the second dielectric layer has a leakage.

[0023] In a possible implementation manner, it includes the step of confirming the position where there is a leakage in the first dielectric layer and / or the third dielectric layer, specifically including:

[0024] Apply a positive voltage to the third test terminal and a negative voltage to the second test terminal;

[0025] When there is no current between the third test terminal and the second test terminal, then the first dielectric layer has a leakage and the third dielectric layer is normal;

[0026] When there is a second current value between the third test terminal and the second test terminal, then when the first current value = the second current value, the third dielectric layer has a leakage and the first dielectric layer is normal; when the first current value > the second current value, the first dielectric layer and the third dielectric layer have a leakage at the same time.

[0027] Compared with the prior art, the beneficial effects of the present application are at least as follows:

[0028] The present application provides a semiconductor device test structure and a test method therefor. The test structure includes a dielectric layer and a plurality of metal layers arranged at intervals in the dielectric layer. The metal layers include a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer arranged from bottom to top, and wires and switches are arranged between different metal layers to associate the metal layers in different regions. By applying test voltages at different positions of the same test structure, the electrical properties of the dielectric layer between different metal layers are tested to determine whether there is leakage in the dielectric layer between different metal layers, and further to determine whether there is leakage in the dielectric layer in the semiconductor device structure, effectively improving the flexibility and efficiency of the test structure, and at the same time reducing the occupied area of the chip layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0030] Figures 1a to 1c FIG. 9 is a schematic diagram of a semiconductor device test structure shown according to the prior art;

[0031] Figure 2 FIG. 13 is a schematic diagram of a semiconductor device test structure shown according to an embodiment of the present application.

[0032] ILLUSTRATION:

[0033] 100 Metal layer; 101 First metal layer; 102 Second metal layer; 103 Third metal layer; 104 Fourth metal layer; 200 Dielectric layer; 201 First dielectric layer; 202 Second dielectric layer; 203 Third dielectric layer; 300 Switch; 301 First switch; 302 Second switch; 303 Third switch; 401 First test terminal; 402 Second test terminal; 403 Third test terminal; 404 Fourth test terminal; 405 Fifth test terminal. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] The following specific embodiments illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or operated through other different specific implementation manners, and various details in the present application can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0035] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the term "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances. In addition, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0036] In semiconductor processes, in order to improve the yield of semiconductor devices, before manufacturing actual semiconductor devices, some test structures are additionally manufactured to facilitate the testing of the IMD properties corresponding to different metal layers.

[0037] Figures 1a to 1c is a schematic diagram of a semiconductor device test structure commonly used in the current industry. This test structure includes a dielectric layer and multiple metal layers arranged at intervals in the dielectric layer. By electrically testing the IMD properties corresponding to different metal layers one by one, it can be determined whether the IMD has breakdown. See Figure 1a , after applying voltages to the first test terminal (PAD1) and the second test terminal (PAD2), the breakdown property of IMD1 can be measured. Similarly, see Figure 1b and Figure 1c , after applying voltages to the first test terminal and the second test terminal, the breakdown properties of IMD2 and IMD3 can also be measured respectively.

[0038] However, in the design of actual chips, due to the complexity of wiring, the layout of the metal layers formed by BEOL becomes complex. For the testing of the IMD properties in complex structures, it is necessary to separately test various structures that appear in the entire metal layer formed by BEOL. That is, a large number of metal layers need to be arranged in different regions to cope with the testing of the IMD properties of different layers. The testing of the IMD properties corresponding to the entire metal layer can be completed only through multiple tests. Therefore, the entire testing process is complicated and inefficient, and the effective utilization rate of the chip layout is low.

[0039] Based on the above problems, the present application provides a semiconductor device test structure and its test method to simplify the process of testing the performance of IMD in the prior art and improve the test efficiency and the utilization rate of the chip layout. The following will be described with specific embodiments.

[0040] According to one aspect of the present application, a semiconductor device test structure is provided. See Figure 2, including a dielectric layer 200 and a plurality of metal layers 100 arranged at intervals in the dielectric layer 200. The plurality of metal layers 100 include a first metal layer 101, a second metal layer 102, a third metal layer 103, and a fourth metal layer 104 arranged from bottom to top. The dielectric layer 200 is separated by the metal layers 100 into a first dielectric layer 201, a second dielectric layer 202, and a third dielectric layer 203 sandwiched between adjacent metal layers 100 from bottom to top.

[0041] The dielectric layer 200 includes three partitions arranged horizontally, including a first partition, a second partition, and a third partition. The same metal layer 100 located in different partitions is isolated from each other through the dielectric layer 200. The adjacent metal layers 100 in the second partition are electrically connected through metal posts. The second metal layer 102 and the third metal layer 103 in the first partition are electrically connected through metal posts. The first metal layer 101 and the second metal layer 102, and the third metal layer 103 and the fourth metal layer 104 in the third partition are respectively electrically connected through metal posts. The second metal layer 102 and the third metal layer 103 in the third partition are connected through a first wire; the fourth metal layer 104 in the third partition and the third metal layer 103 in the first partition are connected through a second wire. Switches 300 are respectively provided on the first wire and the second wire.

[0042] The first wire and the second wire connect the metal layers 100 in the first partition and the third partition in series with each other. By providing switches 300 on the first wire and the second wire, the current in the first wire and the second wire can be controlled to conduct according to a preset path when powered on. Furthermore, when a voltage is applied to the first metal layer 101 in the second partition, the electrical characteristics of the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 can be quickly confirmed, that is, whether there is leakage in the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203.

[0043] In an embodiment, a first switch 301 is provided on the first wire, and a second switch 302 and a third switch 303 are provided on the second wire. The first switch 301, the second switch 302, and the third switch 303 include diodes with unidirectional conductivity. Selecting diodes with unidirectional conductivity as the switches 300 can enable the current to conduct along a preset path when an electrode is connected to a specific node.

[0044] Preferably, the positive electrode of the first switch 301 is connected to the second metal layer 102 of the third partition, the positive electrode of the second switch 302 is connected to the fourth metal layer 104 of the third partition, the positive electrode of the third switch 303 is connected to the third metal layer 103 of the first partition, and the negative electrode of the second switch 302 is connected to the negative electrode of the third switch 303. That is to say, when the above-mentioned specific node is set between the second switch 302 and the third switch 303 on the second wire and the access electrode is the negative electrode, the current can flow through the second metal layer 102 and the third metal layer 103 in the first partition to the negative electrode of the specific node. At the same time, the current can also sequentially pass through the first metal layer 101, the second metal layer 102, the third metal layer 103, and the fourth metal layer 104 in the third partition to the negative electrode of the specific node.

[0045] In one embodiment, the semiconductor device test structure further includes a first test terminal 401 (PAD1), a second test terminal 402 (PAD2), a third test terminal 403 (PAD3), a fourth test terminal 404 (PAD4), and a fifth test terminal 405 (PAD5). The first test terminal 401 is connected in series between the second switch 302 and the third switch 303. At the position of the above-mentioned specific node, it is respectively connected to the negative electrodes of the second switch 302 and the third switch 303. The second test terminal 402 is connected to the fourth metal layer 104 of the second partition for providing electrode connections for the metal layers 100 in the second partition; the third test terminal 403 is connected in series between the second switch 302 and the fourth metal layer 104 of the third partition for providing electrode connections for the third metal layer 103 and the fourth metal layer 104 in the third partition; the fourth test terminal 404 is connected to the first metal layer 101 of the third partition for providing electrode connections for the metal layers 100 in the third partition; the fifth test terminal 405 is connected to the third metal layer 103 of the first partition for providing electrode connections for the third metal layer 103 and the second metal layer 102 in the first partition.

[0046] Preferably, the first test terminal 401, the second test terminal 402, the third test terminal 403, the fourth test terminal 404, and the fifth test terminal 405 are jointly arranged and exposed on the surface of the dielectric layer 200, so as to facilitate electrode connection of the test structure in the same plane and improve the convenience of testing.

[0047] During the test, a voltage is applied between the second test terminal 402 and the first test terminal 401, the third test terminal 403, the fourth test terminal 404, and the fifth test terminal 405 respectively. According to whether there is a conduction current in the circuit with a voltage difference, the electrical characteristics of the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 are judged, that is, whether there is leakage.

[0048] In one embodiment, the material of the metal layer 100 includes copper or aluminum, and the materials of the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 are different, including low-K or ultra-low-K materials.

[0049] On the other hand, a test method for a semiconductor device test structure is provided, including the step of confirming whether there is leakage in the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203, specifically including: applying a positive voltage to the second test terminal 402 and a negative voltage to the first test terminal 401.

[0050] Due to the unidirectional conductivity of the first switch 301, the second switch 302, and the third switch 303, when there is a current between the first test terminal 401 and the second test terminal 402, it indicates that one or more of the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 have leakage. When there is no current between the first test terminal 401 and the second test terminal 402, none of the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 have leakage. That is to say, by applying a voltage between the first test terminal 401 and the second test terminal 402 only once, it is possible to determine whether there is leakage in the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203, that is, whether there is leakage in the semiconductor device structure. The efficiency of abnormal detection of semiconductor devices is effectively improved.

[0051] In one embodiment, when there is a current between the first test terminal 401 and the second test terminal 402, it further includes the step of confirming the position where leakage occurs between the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203, specifically including: applying a positive voltage to the fourth test terminal 404 and a negative voltage to the second test terminal 402.

[0052] The positive voltage applied to the fourth test terminal 404 enables the current to sequentially pass through the first metal layer 101, the second metal layer 102, the third metal layer 103, and the fourth metal layer 104 in the third partition. When there is no current in the circuit between the fourth test terminal 404 and the second test terminal 402, it indicates that the first dielectric layer 201 and the third dielectric layer 203 are normal, and the leakage only occurs in the second dielectric layer 202. When there is a current in the circuit between the fourth test terminal 404 and the second test terminal 402, it indicates that the current can flow to the second partition and form a path between the fourth test terminal 404 and the second test terminal 402, that is, at least one of the first dielectric layer 201 and the third dielectric layer 203 has leakage, and there is also a first current value.

[0053] Preferably, when there is current in the circuit between the fourth test terminal 404 and the second test terminal 402, it should also include the step of confirming whether there is leakage in the second dielectric layer 202, specifically including applying a positive voltage to the fifth test terminal 405 and a negative voltage to the second test terminal 402. When there is current in the circuit between the fifth test terminal 405 and the second test terminal 402, it indicates that there is also leakage in the second dielectric layer 202.

[0054] In one embodiment, when there is current in the circuit between the fourth test terminal 404 and the second test terminal 402, it also includes the step of confirming the position where there is leakage in the first dielectric layer 201 and / or the third dielectric layer 203, specifically including: applying a positive voltage to the third test terminal 403 and connecting the second test terminal 402 to a negative voltage. Due to the unidirectional conductivity of the first switch 301 and the third switch 303, the current generated by the positive voltage applied to the third test terminal 403 can only flow from the fourth metal layer 104 in the third partition to the third metal layer 103, and cannot continue to flow to the second metal layer 102 in the third partition and the third metal layer 103 in the first partition.

[0055] When there is no current between the third test terminal 403 and the second test terminal 402, it indicates that there is leakage in the first dielectric layer 201 and the third dielectric layer 203 is normal. When there is current between the third test terminal 403 and the second test terminal 402 and the current magnitude is the second current value, it is necessary to judge the specific leakage positions of the first dielectric layer 201 and the third dielectric layer 203 according to the magnitudes of the first current value and the second current value. When the first current value is equal to the second current value, there is leakage in the third dielectric layer 203 and the first dielectric layer 201 is normal. When the first current value is significantly greater than the second current value, it indicates that there is leakage in both the first dielectric layer 201 and the third dielectric layer 203.

[0056] It should be noted that during the above test process, the voltage magnitudes applied between the second test terminal 402 and the first test terminal 401, the third test terminal 403, the fourth test terminal 404, and the fifth test terminal 405 need to be kept consistent to ensure the accuracy of the leakage judgment of the first dielectric layer 201 and the third dielectric layer 203. In an actual semiconductor device structure, multiple numbers of the above test structures can be set at different positions. Using the above test structures to test the properties of the dielectric layers in the semiconductor device structure can save more than 50% of the layout area compared with the prior art, and the test time can also be reduced by two-thirds, effectively reducing the layout cost of the chip and improving the test efficiency.

[0057] The present application provides a semiconductor device test structure and a test method thereof. The test structure includes a dielectric layer 200 and a plurality of metal layers 100 spaced apart and located in the dielectric layer 200. The metal layer 100 includes a first metal layer 101, a second metal layer 102, a third metal layer 103, and a fourth metal layer 104 arranged from bottom to top, and wires and switches 300 are arranged between different metal layers 100 to associate the metal layers 100 in different regions. By applying test voltages at different positions of the same test structure, the electrical properties of the dielectric layer 200 between different metal layers 100 are tested to determine whether there is leakage in the dielectric layer 200 between different metal layers 100, and further determine whether there is leakage in the dielectric layer 200 in the semiconductor device structure, effectively improving the flexibility and efficiency of the test structure and reducing the occupied area of the chip layout at the same time.

[0058] The foregoing is only the preferred embodiment of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the technical principle of the present application, several improvements and replacements can still be made, and these improvements and replacements should also be regarded as the protection scope of the present application.

Claims

1. A semiconductor device test structure, characterized in that, It includes a dielectric layer and a plurality of metal layers located in the dielectric layer and arranged at intervals. The plurality of metal layers include a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer arranged from bottom to top. The dielectric layer is separated by the metal layers into a first dielectric layer, a second dielectric layer, and a third dielectric layer sandwiched between adjacent metal layers from bottom to top. The dielectric layer includes three partitions arranged horizontally, including a first partition, a second partition, and a third partition. The same metal layer located in different partitions is isolated from each other through the dielectric layer. The adjacent metal layers in the second partition are electrically connected through metal columns. The second metal layer and the third metal layer in the first partition are electrically connected through the metal columns. The first metal layer and the second metal layer, and the third metal layer and the fourth metal layer in the third partition are respectively electrically connected through the metal columns. The second metal layer and the third metal layer in the third partition are connected through a first wire. The fourth metal layer in the third partition and the third metal layer in the first partition are connected through a second wire. Switches are respectively provided on the first wire and the second wire. A first switch is provided on the first wire, and a second switch and a third switch are provided on the second wire. The first switch, the second switch, and the third switch include diodes with unidirectional conductivity. The positive electrode of the first switch is connected to the second metal layer in the third partition. The positive electrode of the second switch is connected to the fourth metal layer in the third partition. The positive electrode of the third switch is connected to the third metal layer in the first partition. The negative electrodes of the second switch and the third switch are connected to each other. The semiconductor device test structure further includes a first test terminal, a second test terminal, a third test terminal, a fourth test terminal, and a fifth test terminal. The first test terminal is connected in series between the second switch and the third switch and is respectively connected to the negative electrodes of the second switch and the third switch. The second test terminal is connected to the fourth metal layer in the second partition. The third test terminal is connected in series between the second switch and the fourth metal layer in the third partition. The fourth test terminal is connected to the first metal layer in the third partition. The fifth test terminal is connected to the third metal layer in the first partition. The first test terminal, the second test terminal, the third test terminal, the fourth test terminal, and the fifth test terminal are all exposed on the surface of the dielectric layer.

2. The test structure according to claim 1, wherein The material of the metal layer includes copper or aluminum. The materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are different and include low-K or ultra-low-K materials.

3. A testing method for a testing structure of a semiconductor device, comprising the testing structure described in claim 2, characterized in that, It includes the step of confirming whether there is leakage in the first dielectric layer, the second dielectric layer, and the third dielectric layer, specifically including; Applying a positive voltage to the second test terminal and a negative voltage to the first test terminal. When there is a current between the first test terminal and the second test terminal, then one or more of the first dielectric layer, the second dielectric layer, and the third dielectric layer have leakage.

4. The test method according to claim 3, wherein It includes the step of confirming the position where there is leakage between the first dielectric layer, the second dielectric layer, and the third dielectric layer, specifically including; Applying a positive voltage to the fourth test terminal and a negative voltage to the second test terminal. When there is no current between the fourth test terminal and the second test terminal, there is a leakage in the second dielectric layer, and the first dielectric layer and the third dielectric layer are normal; When there is a first current value between the fourth test terminal and the second test terminal, there is a leakage in the first dielectric layer and / or the third dielectric layer.

5. The test method according to claim 4, wherein When there is a leakage in the first dielectric layer and / or the third dielectric layer, it further includes a step of confirming whether there is a leakage in the second dielectric layer, specifically including: Applying a positive voltage to the fifth test terminal and a negative voltage to the second test terminal; When there is a current between the fifth test terminal and the second test terminal, there is a leakage in the second dielectric layer.

6. The test method according to claim 4, wherein It includes a step of confirming the position where there is a leakage in the first dielectric layer and / or the third dielectric layer, specifically including; Applying a positive voltage to the third test terminal and a negative voltage to the second test terminal; When there is no current between the third test terminal and the second test terminal, there is a leakage in the first dielectric layer and the third dielectric layer is normal; When there is a second current value between the third test terminal and the second test terminal, then when the first current value = the second current value, there is a leakage in the third dielectric layer and the first dielectric layer is normal; when the first current value > the second current value, there is a leakage in both the first dielectric layer and the third dielectric layer.

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