A unidirectional thyristor and its manufacturing method

Abstract

The present application provides a unidirectional thyristor and a manufacturing method thereof, relating to the technical field of unidirectional thyristors. The unidirectional thyristor includes: a first semiconductor layer of a first doping type, a second semiconductor layer and a third semiconductor layer located on both sides of the first semiconductor layer; wherein, both the second semiconductor layer and the third semiconductor layer are of a second doping type, an anode region located on the side of the second semiconductor layer away from the first semiconductor layer, a conduction region and a control electrode region located on the side of the third semiconductor layer away from the first semiconductor layer, wherein the conduction region is of the first doping type, the conduction region includes a main conduction region, an auxiliary conduction region and a damping region, and the junction depth and doping concentration of the main conduction region are both less than the junction depth and doping concentration of the auxiliary conduction region, and a cathode region located on the side of the main conduction region and the damping region away from the first semiconductor layer. The unidirectional thyristor and the manufacturing method thereof provided by the present application have the advantage of having a higher dv / dt.

Description

Technical Field

[0001] The present application relates to the technical field of silicon controlled rectifiers, and more particularly, to a silicon controlled rectifier and a manufacturing method thereof. Background Art

[0002] A silicon controlled rectifier (SCR) is short for a silicon controlled rectifier. There are several types of silicon controlled rectifiers, including unidirectional, bidirectional, turn-off, and light-controlled types. It has the advantages of small size, light weight, high efficiency, long life, and convenient control, and is widely used in various automatic control and high-power power conversion applications such as controlled rectification, voltage regulation, inversion, and contactless switches.

[0003] A unidirectional silicon controlled rectifier is a controllable rectifier electronic component that can be turned from off to on under the action of an external control signal. However, once it is turned on, the external signal cannot turn it off, and it can only be turned off by removing the load or reducing the voltage across it. A unidirectional silicon controlled rectifier is a four-layer three-terminal semiconductor device composed of three PN junctions. Compared with a diode with one PN junction, the forward conduction of a unidirectional silicon controlled rectifier is controlled by the control electrode current; compared with a triode with two PN junctions, the difference is that the silicon controlled rectifier has no amplification effect on the control electrode current.

[0004] For a conventional gate-sensitive trigger unidirectional silicon controlled rectifier, due to its relatively deep PN junction and high impurity concentration, dv / dt (the rising slope of the voltage in the off state) has always been at a relatively low level, resulting in limited applications of existing unidirectional silicon controlled rectifiers.

[0005] In summary, in the prior art, there is a problem that the level of dv / dt of the silicon controlled rectifier is relatively low, which limits the application of the unidirectional silicon controlled rectifier. Summary of the Invention

[0006] The purpose of the present application is to provide a unidirectional silicon controlled rectifier and a manufacturing method thereof to solve the problem in the prior art that the level of dv / dt of the silicon controlled rectifier is relatively low, which limits the application of the unidirectional silicon controlled rectifier.

[0007] To achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

[0008] In a first aspect, an embodiment of the present application provides a unidirectional silicon controlled rectifier, which includes:

[0009] A first semiconductor layer of a first doping type;

[0010] A second semiconductor layer and a third semiconductor layer located on both sides of the first semiconductor layer; wherein, both the second semiconductor layer and the third semiconductor layer are of a second doping type;

[0011] The anode region located on the side of the second semiconductor layer away from the first semiconductor layer;

[0012] The conduction region and the control electrode region located on the side of the third semiconductor layer away from the first semiconductor layer, wherein the conduction region is of the first doping type, the conduction region includes a main conduction region, an auxiliary conduction region, and a damping region, the damping region is located between the main conduction region and the auxiliary conduction region, and the junction depth and doping concentration of the main conduction region are both smaller than the junction depth and doping concentration of the auxiliary conduction region;

[0013] The cathode region located on the side of the main conduction region and the damping region away from the first semiconductor layer.

[0014] Optionally, a protruding region is provided in the second semiconductor layer, the protruding region has the same projection area as the auxiliary conduction region in the vertical direction, and the junction depth of the protruding region is greater than the junction depth of other regions in the second semiconductor.

[0015] Optionally, the junction depth of the protruding region is 50 - 70 um, and the junction depth of other regions in the second semiconductor is 35 ± 3 um.

[0016] Optionally, the junction depth of the main conduction region is 20 ± 2 um, and the junction depth of the auxiliary conduction region is 28 ± 2 um; and / or

[0017] The sheet resistance of the main conduction region is 5.6 ± 0.4 Ω / sq; the sheet resistance of the auxiliary conduction region is 1.0 ± 0.1 Ω / sq.

[0018] Optionally, the width of the damping region is 20 ± 2 um.

[0019] Optionally, the first doping type is N-type doping, and the second doping type is P-type doping; or

[0020] The first doping type is P-type doping, and the second doping type is N-type doping.

[0021] On the other hand, an embodiment of the present application also provides a method for manufacturing a thyristor, the method includes:

[0022] Providing a first semiconductor layer of the first doping type;

[0023] Manufacturing a second semiconductor layer and a third semiconductor layer on both sides of the first semiconductor layer respectively; wherein, both the second semiconductor layer and the third semiconductor layer are of the second doping type;

[0024] A conduction region is fabricated on the side of the third semiconductor layer away from the first semiconductor layer. Herein, the conduction region is of a first doping type and includes a main conduction region, an auxiliary conduction region, and a damping region. The damping region is located between the main conduction region and the auxiliary conduction region, and the junction depth and doping concentration of the main conduction region are both smaller than those of the auxiliary conduction region.

[0025] A control region is fabricated on the side of the third semiconductor layer away from the first semiconductor layer, a cathode region is fabricated on the side of the main conduction region and the damping region away from the first semiconductor layer, and an anode region is fabricated on the side of the second semiconductor layer away from the first semiconductor layer.

[0026] Optionally, before the steps of fabricating the second semiconductor layer and the third semiconductor layer on both sides of the first semiconductor layer respectively, the method further includes:

[0027] A protruding window is fabricated on the back surface of the first semiconductor layer; herein, the back surface of the first semiconductor layer is the side where the second semiconductor layer is located.

[0028] Diffusion of a second doping type is performed along the protruding window, and a doped region is formed at the protruding window.

[0029] After the steps of fabricating the second semiconductor layer and the third semiconductor layer on both sides of the first semiconductor layer respectively, the method further includes:

[0030] A protruding region is formed in the second semiconductor layer, wherein the protruding region has the same projection area as the auxiliary conduction region in the vertical direction, and the junction depth of the protruding region is greater than that of other regions in the second semiconductor.

[0031] Optionally, the steps of fabricating the second semiconductor layer and the third semiconductor layer on both sides of the first semiconductor layer respectively include:

[0032] Thermal diffusion of a second doping type is performed on both sides of the first semiconductor layer, and the second semiconductor layer and the third semiconductor layer are formed.

[0033] Optionally, the steps of fabricating the conduction region on the side of the third semiconductor layer away from the first semiconductor layer include:

[0034] An auxiliary conduction region window is fabricated on the side of the third semiconductor layer away from the first semiconductor layer;

[0035] Diffusion of a first doping type is performed along the auxiliary conduction region window, and the auxiliary conduction region is formed at the auxiliary conduction region window.

[0036] A main conduction region window is fabricated on the side of the third semiconductor layer away from the first semiconductor layer; wherein, the main conduction region window and the auxiliary conduction region window are arranged at intervals.

[0037] First-doping-type diffusion is carried out along the main conduction region window, and a main conduction region is formed at the main conduction region window.

[0038] Compared with the prior art, the present application has the following beneficial effects:

[0039] The embodiment of the present application provides a unidirectional thyristor and a manufacturing method thereof. The unidirectional thyristor includes: a first semiconductor layer of a first doping type, a second semiconductor layer and a third semiconductor layer located on both sides of the first semiconductor layer; wherein, both the second semiconductor layer and the third semiconductor layer are of a second doping type, an anode region located on the side of the second semiconductor layer away from the first semiconductor layer, a conduction region and a control electrode region located on the side of the third semiconductor layer away from the first semiconductor layer, wherein the conduction region is of the first doping type, the conduction region includes a main conduction region, an auxiliary conduction region and a damping region, and the junction depth and doping concentration of the main conduction region are both smaller than the junction depth and doping concentration of the auxiliary conduction region, and a cathode region located on the side of the main conduction region and the damping region away from the first semiconductor layer. Since the present application is provided with an auxiliary conduction region and a main conduction region, and the junction depth and doping concentration of the main conduction region are both smaller than the junction depth and doping concentration of the auxiliary conduction region, the auxiliary conduction region can be preferentially conducted, thereby extending to drive the entire main region to conduct. Moreover, when there is no conduction signal of the control electrode, since there is a damping region between the main conduction region and the auxiliary region, the transient electrical signal will not be completely and quickly conducted to the auxiliary region. At this time, the dv / dt carrier is mainly borne by the main conduction region, and the main conduction region is designed with a shallow junction and a lower impurity concentration, so as to achieve the effect of having a higher dv / dt.

[0040] In order to make the above-mentioned objects, features and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0042] Figure 1 It is a top view of a conventional gate-sensitive-triggered unidirectional thyristor.

[0043] Figure 2 It is a schematic cross-sectional view of a conventional gate-sensitive-triggered unidirectional thyristor.

[0044] Figure 3 This is a schematic cross-sectional view of the thyristor provided by the embodiment of the present application.

[0045] Figure 4 This is a top view of the thyristor provided by the embodiment of the present application.

[0046] Figure 5 This is a schematic flow chart of the manufacturing method of the thyristor provided by the embodiment of the present application.

[0047] Figure 6 This is a schematic cross-sectional view corresponding to S1031 provided by the embodiment of the present application.

[0048] Figure 7 This is a schematic cross-sectional view corresponding to S1032 provided by the embodiment of the present application.

[0049] Figure 8 This is a schematic cross-sectional view after forming the shielding layer provided by the embodiment of the present application.

[0050] Figure 9 This is a schematic cross-sectional view corresponding to S1061 provided by the embodiment of the present application.

[0051] Figure 10 This is a schematic cross-sectional view corresponding to S1062 provided by the embodiment of the present application.

[0052] Figure 11 This is a schematic cross-sectional view corresponding to S1063 provided by the embodiment of the present application.

[0053] Figure 12 This is a schematic cross-sectional view corresponding to S1064 provided by the embodiment of the present application. Detailed implementation manners

[0054] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.

[0055] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0056] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Also, in the description of the present application, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0057] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0058] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is customarily placed during use. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation on the present application.

[0059] In the description of the present application, it should also be noted that unless otherwise clearly specified and limited, the terms "set", "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0060] The following will, with reference to the drawings, elaborate on some embodiments of the present application. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0061] As Figure 1 with Figure 2 described, Figure 1 with Figure 2The top view and cross-sectional view of a conventional gate turn-off thyristor are respectively shown. Among them, the G region shown in the figure represents the control electrode region, K represents the cathode region, and the A region represents the anode region. As described in the background art, for a conventional gate turn-off thyristor, due to its relatively deep PN junction and high impurity concentration, dv / dt (the rising slope of voltage in the off state) has always been at a relatively low level, resulting in limited application scenarios.

[0062] To solve the above problems, the present application provides a thyristor, which improves the dv / dt of the thyristor by setting a main conduction region and an auxiliary conduction region.

[0063] The thyristor provided by the present application will be exemplarily described below:

[0064] As an optional implementation manner, please refer to Figure 3 and Figure 4 . The thyristor includes: a first semiconductor layer of a first doping type, a second semiconductor layer and a third semiconductor layer located on both sides of the first semiconductor layer; wherein, both the second semiconductor layer and the third semiconductor layer are of a second doping type, an anode region located on the side of the second semiconductor layer away from the first semiconductor layer, a conduction region and a control electrode region located on the side of the third semiconductor layer away from the first semiconductor layer, wherein the conduction region is of the first doping type, the conduction region includes a main conduction region, an auxiliary conduction region and a damping region, the damping region is located between the main conduction region and the auxiliary conduction region, and the junction depth and doping concentration of the main conduction region are both smaller than the junction depth and doping concentration of the auxiliary conduction region, and a cathode region located on the side of the main conduction region and the damping region away from the first semiconductor layer.

[0065] Compared with the prior art, the conduction region of the present application is provided with a main conduction region and an auxiliary conduction region, and the auxiliary conduction region is connected to the main conduction region through a damping region. Since the auxiliary conduction region has a deeper PN junction than the main conduction region, it can be preferentially conducted, thereby driving the entire main conduction region to conduct; when there is no control electrode conduction signal, there is a damping region from the main conduction region to the auxiliary region, and the damping region is relatively thin, and the transient electrical signal will not be completely and quickly conducted to the auxiliary conduction region. At this time, the dv / dt carrier is mainly borne by the main conduction region, and the shallow junction designed for the main conduction region can also have a lighter impurity concentration, so that the dv / dt becomes higher and is applicable to more scenarios.

[0066] It should be noted that the doping types described in the present application include N-type doping and P-type doping. Among them, when the first doping type is N-type doping, the second doping type is P-type doping; when the first doping type is P-type doping, the second doping type is N-type doping.

[0067] It should also be noted that, in order to ensure that the auxiliary conduction region can conduct preferentially and quickly, as an implementation method, a protruding region is provided in the second semiconductor layer. The protruding region has the same projection area as the auxiliary conduction region in the vertical direction, and the junction depth of the protruding region is greater than the junction depth of other regions in the second semiconductor.

[0068] On this basis, the PN junction of the auxiliary conduction region added on the front is deeper than that of the main conduction region, and with the help of the protruding PN structure on the back of the chip at the corresponding position, this region can be preferentially conducted, so as to ensure that when the thyristor conducts, the auxiliary conduction region can be preferentially conducted, and then the entire cathode region is driven to conduct by the extension of the auxiliary conduction region.

[0069] Among them, the difference in junction depth between the auxiliary conduction region and the main conduction region, the position distance between the auxiliary conduction region and the main conduction region, and the junction depth of the protruding region on the back of the chip. The change of these values will affect the static parameters and dv / dt of the entire thyristor, and a balance needs to be achieved among these values.

[0070] As an implementation method, the junction depth of the protruding region is 50 - 70um, and the junction depth of other regions in the second semiconductor except the protruding region is 35 ± 3um. The junction depth of the main conduction region is 20 ± 2um, the junction depth of the auxiliary conduction region is 28 ± 2um, the sheet resistance of the main conduction region is 5.6 ± 0.4Ω / □; the sheet resistance of the auxiliary conduction region is 1.0 ± 0.1Ω / □, and moreover, the width of the damping region is 20 ± 2um.

[0071] Based on the above implementation method, please refer to Figure 5 , the embodiment of the present application also provides a method for manufacturing a thyristor, which includes:

[0072] S102, providing a first semiconductor layer of a first doping type;

[0073] S104, respectively manufacturing a second semiconductor layer and a third semiconductor layer on both sides of the first semiconductor layer; wherein, both the second semiconductor layer and the third semiconductor layer are of a second doping type;

[0074] S106, manufacturing a conduction region on the side of the third semiconductor layer away from the first semiconductor layer, wherein the conduction region is of the first doping type, and the conduction region includes a main conduction region, an auxiliary conduction region, and a damping region. The damping region is located between the main conduction region and the auxiliary conduction region, and the junction depth and doping concentration of the main conduction region are both less than the junction depth and doping concentration of the auxiliary conduction region;

[0075] S108, manufacturing a control region on the side of the third semiconductor layer away from the first semiconductor layer, manufacturing a cathode region on the side of the main conduction region and the damping region away from the first semiconductor layer, and manufacturing an anode region on the side of the second semiconductor layer away from the first semiconductor layer.

[0076] As an alternative implementation, before S104, the method further includes:

[0077] S1031, fabricating a protruding window on the back surface of the first semiconductor layer; wherein, the back surface of the first semiconductor layer is the side where the second semiconductor layer is located;

[0078] S1032, performing diffusion of the second doping type along the protruding window and forming a doped region at the protruding window;

[0079] After S106, the method further includes:

[0080] Forming a protruding region in the second semiconductor layer, wherein the protruding region has the same projection area as the auxiliary conduction region in the vertical direction, and the junction depth of the protruding region is greater than the junction depth of other regions in the second semiconductor.

[0081] Wherein, referring to Figure 6 , this application takes the first doping type as N-type doping and the second doping type as P-type doping as an example for illustration. First, an N-type semiconductor is provided. And, for the convenience of subsequent doping operations, masking layers are fabricated on both the front and back surfaces of the first semiconductor layer. For example, a SiO2 masking layer is formed by an oxidation method. Then, a protruding window is fabricated on the back surface of the first semiconductor layer. It can be understood that the position of the protruding window corresponds to the position of the subsequent auxiliary conduction region.

[0082] After fabricating the window, diffusion of the second doping type is performed along the protruding window and a doped region is formed at the protruding window. By fabricating the doped region, it can prepare for the subsequent protruding region. When thermal diffusion is performed on both sides of the first semiconductor layer, a second semiconductor layer and a third semiconductor layer can be respectively formed on both sides of the first semiconductor layer. Among them, due to the existence of the doped region, after the thermal diffusion is completed, the second semiconductor layer includes a protruding region, and the junction depth of the protruding region is greater than the junction depth of other regions in the second semiconductor. For example, the junction depth of the protruding region is 50 - 70 um, and the junction depth of other regions in the second semiconductor is 35 ± 3 um.

[0083] Then, the masking layers on both sides of the first semiconductor layer are removed, and P-type thermal diffusion is performed on both sides of the first semiconductor layer. As Figure 7 shown, after the thermal diffusion is completed, masking layers are continuously formed on the second semiconductor layer and the third semiconductor layer, as Figure 8 shown.

[0084] Wherein, as an implementation manner, S106 includes:

[0085] S1061, fabricating an auxiliary conduction region window on the side of the third semiconductor layer away from the first semiconductor layer;

[0086] S1062, perform diffusion of the first doping type along the auxiliary conduction region window, and form an auxiliary conduction region at the auxiliary conduction region window;

[0087] S1063, fabricate a main conduction region window on the side of the third semiconductor layer away from the first semiconductor layer; wherein, the main conduction region window and the auxiliary conduction region window are arranged at intervals;

[0088] S1064, perform diffusion of the first doping type along the main conduction region window, and form a main conduction region at the main conduction region window.

[0089] Among them, please refer to Figure 9 , when an auxiliary conduction region needs to be fabricated, first fabricate an auxiliary conduction region window on the side of the triple semiconductor layer away from the first semiconductor layer, then perform diffusion of the first doping type along the auxiliary conduction region window, and form an auxiliary conduction region at the auxiliary conduction region window. Of course, since the junction depth and doping concentration of the auxiliary conduction region are greater than those of the main conduction region, relevant parameters in the actual diffusion process need to be ensured during the actual diffusion process.

[0090] After the fabrication of the auxiliary conduction region is completed, as Figure 10 shown, fabricate another masking layer. In addition, in order to be able to bear a higher dv / dt, a main conduction region with a shallower junction depth and lower concentration needs to be fabricated.

[0091] Please refer to Figure 11 , first fabricate a main conduction region window, then perform diffusion of the first doping type along the main conduction region window, and form a main conduction region at the main conduction region window. After the fabrication of the main conduction region is completed, a damping region is formed through the lateral diffusion of the auxiliary conduction region and the main conduction region, and the thickness of the damping region is relatively thin, and its structure is as Figure 12 shown.

[0092] As an implementation method, the junction depth of the main conduction region is 20 ± 2 um, the junction depth of the auxiliary conduction region is 28 ± 2 um, the sheet resistance of the main conduction region is 5.6 ± 0.4 Ω / □; the sheet resistance of the auxiliary conduction region is 1.0 ± 0.1 Ω / □, and the width of the damping region is 20 ± 2 um.

[0093] Of course, the above fabrication process is only a simplification of the actual fabrication process of the unilateral thyristor, and its complete process includes:

[0094] Primary oxidation → Double-sided etching of the through-ring → Double-sided aluminum implantation → IMP-DEP → Punch-through diffusion → Back-side window etching → Back-side aluminum implantation → Back-side boron compensation → Front-side boron implantation → Double-sided aluminum 2 implantation → IMP-DEP2 → Aluminum re-diffusion → Front-side K region 1 etching → Phosphorus pre-diffusion 1 → Oxidation → Front-side K region 2 etching → Phosphorus pre-diffusion 2 → Phosphorus re-diffusion → Front-side grooving → Mesa etching → Glass passivation → Front-side lead etching → Double-sided aluminum evaporation → Front-side reverse etching → Vacuum alloying → Back-side silver evaporation → Testing → Dicing.

[0095] In summary, the embodiment of the present application provides a thyristor and a manufacturing method thereof. The thyristor includes: a first semiconductor layer of a first doping type, a second semiconductor layer and a third semiconductor layer located on both sides of the first semiconductor layer; wherein, both the second semiconductor layer and the third semiconductor layer are of a second doping type, an anode region located on the side of the second semiconductor layer away from the first semiconductor layer, a conduction region and a control electrode region located on the side of the third semiconductor layer away from the first semiconductor layer, wherein the conduction region is of the first doping type, the conduction region includes a main conduction region, an auxiliary conduction region and a damping region, and the junction depth and doping concentration of the main conduction region are both smaller than the junction depth and doping concentration of the auxiliary conduction region, and a cathode region located on the side of the main conduction region and the damping region away from the first semiconductor layer. Since the present application provides an auxiliary conduction region and a main conduction region, and the junction depth and doping concentration of the main conduction region are both smaller than the junction depth and doping concentration of the auxiliary conduction region, the auxiliary conduction region can be preferentially conducted, thereby extending and driving the entire main region to conduct. Moreover, when there is no conduction signal of the control electrode, due to the damping region provided between the main conduction region and the auxiliary region, the transient electrical signal will not be completely and quickly conducted to the auxiliary region. At this time, the dv / dt carrier is mainly borne by the main conduction region, and the main conduction region is designed with a shallow junction and a relatively low impurity concentration, so as to achieve the effect of having a higher dv / dt.

[0096] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0097] For those skilled in the art, it is obvious that the present application is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, it is intended to include all changes falling within the meaning and scope of the equivalent elements of the claims in the present application. Any reference signs in the claims should not be regarded as limiting the claimed rights.

Claims

1. A silicon controlled rectifier, characterized in that The silicon-controlled rectifier includes: A first semiconductor layer of a first doping type; A second semiconductor layer and a third semiconductor layer located on both sides of the first semiconductor layer; wherein, both the second semiconductor layer and the third semiconductor layer are of a second doping type; An anode region located on the side of the second semiconductor layer away from the first semiconductor layer; A conduction region and a control electrode region located on the side of the third semiconductor layer away from the first semiconductor layer, wherein the conduction region is of a first doping type, the conduction region includes a main conduction region, an auxiliary conduction region, and a damping region, the damping region is located between the main conduction region and the auxiliary conduction region, and the junction depth and doping concentration of the main conduction region are both smaller than the junction depth and doping concentration of the auxiliary conduction region; A cathode region located on the side of the main conduction region and the damping region away from the first semiconductor layer.

2. The silicon controlled rectifier as claimed in claim 1, wherein A protruding region is provided in the second semiconductor layer, the protruding region has the same projection area as the auxiliary conduction region in the vertical direction, and the junction depth of the protruding region is greater than the junction depth of other regions in the second semiconductor.

3. The silicon controlled rectifier as claimed in claim 2, wherein The junction depth of the protruding region is 50-70 um, and the junction depth of other regions in the second semiconductor is 35±3 um.

4. The silicon controlled rectifier as claimed in claim 1, wherein, The junction depth of the main conduction region is 20±2 um, and the junction depth of the auxiliary conduction region is 28±2 um; and / or The sheet resistance of the main conduction region is 5.6±0.4 Ω / square; the sheet resistance of the auxiliary conduction region is 1.0±0.1 Ω / square.

5. The silicon controlled rectifier as claimed in claim 1, wherein, The width of the damping region is 20±2 um.

6. The silicon controlled rectifier as claimed in claim 1, wherein, The first doping type is N-type doping, and the second doping type is P-type doping; or The first doping type is P-type doping, and the second doping type is N-type doping.

7. A method for manufacturing a unidirectional thyristor, characterized in that The method includes: Providing a first semiconductor layer of a first doping type; Fabricating a second semiconductor layer and a third semiconductor layer on both sides of the first semiconductor layer respectively; wherein, both the second semiconductor layer and the third semiconductor layer are of a second doping type; Fabricating a conduction region on the side of the third semiconductor layer away from the first semiconductor layer, wherein the conduction region is of a first doping type, the conduction region includes a main conduction region, an auxiliary conduction region, and a damping region, the damping region is located between the main conduction region and the auxiliary conduction region, and the junction depth and doping concentration of the main conduction region are both smaller than the junction depth and doping concentration of the auxiliary conduction region; Fabricating a control region on the side of the third semiconductor layer away from the first semiconductor layer, fabricating a cathode region on the side of the main conduction region and the damping region away from the first semiconductor layer, and fabricating an anode region on the side of the second semiconductor layer away from the first semiconductor layer.

8. The method for manufacturing a unidirectional thyristor according to claim 7, characterized in that, Before the step of fabricating a second semiconductor layer and a third semiconductor layer on both sides of the first semiconductor layer respectively, the method further includes: Fabricating a protruding window on the back surface of the first semiconductor layer; wherein, the back surface of the first semiconductor layer is the surface where the second semiconductor layer is located; Performing second doping type diffusion along the protruding window and forming a doped region at the protruding window; After the step of fabricating a second semiconductor layer and a third semiconductor layer on both sides of the first semiconductor layer respectively, the method further includes: A protruding region is formed in the second semiconductor layer, where the projection region of the protruding region in the vertical direction is the same as that of the auxiliary conduction region, and the junction depth of the protruding region is greater than the junction depth of other regions in the second semiconductor.

9. The method for manufacturing a unidirectional thyristor according to claim 7, characterized in that, The steps of fabricating the second semiconductor layer and the third semiconductor layer on both sides of the first semiconductor layer respectively include: Performing thermal diffusion of a second doping type on both sides of the first semiconductor layer, and forming the second semiconductor layer and the third semiconductor layer.

10. The method for manufacturing a unidirectional thyristor according to claim 7, characterized in that, The steps of fabricating a conduction region on the side of the third semiconductor layer away from the first semiconductor layer include: Fabricating an auxiliary conduction region window on the side of the third semiconductor layer away from the first semiconductor layer; Performing diffusion of a first doping type along the auxiliary conduction region window, and forming an auxiliary conduction region at the auxiliary conduction region window; Fabricating a main conduction region window on the side of the third semiconductor layer away from the first semiconductor layer; wherein, the main conduction region window and the auxiliary conduction region window are arranged at intervals; Performing diffusion of a first doping type along the main conduction region window, and forming a main conduction region at the main conduction region window.

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