Method for improving the reliability of trench gate mos devices

Abstract

The application provides a method for improving the reliability of a trench gate MOS device, comprising: providing a substrate, wherein a trench gate structure, a well region, a source and a drain are formed in the substrate; forming an interlayer insulating medium layer; applying a preset voltage to the drain and a ground voltage to the trench gate structure and the source to perform a high-temperature reverse bias test on the trench gate MOS device; wherein the step of forming the interlayer insulating medium layer comprises: forming a first oxide layer; forming a second oxide layer, and the second oxide layer is formed without using a plasma enhanced CVD process. The film layer structure of the interlayer insulating medium layer is improved, the second oxide layer is formed without using a plasma enhanced CVD process, that is, the second oxide layer is formed without plasma, and thus the electrons or impurities can be effectively prevented from entering the product channel in the process, the influence of the electrons or impurities on the channel when the device is turned on can be effectively avoided, and the reliability of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of MOS device manufacturing, in particular to a method for improving the reliability of a trench gate MOS device. BACKGROUND

[0002] In a conventional planar MOS (Metal Oxide Semiconductor) device, the source, gate and drain of the MOS transistor are all located on the horizontal plane of the silicon wafer, which not only occupies a large area, but also has a large on-resistance and power consumption, and cannot meet the requirements of power device miniaturization and low power consumption. The trench MOS device cleverly forms the gate of the transistor in the trench perpendicular to the surface of the silicon wafer, so that the on-resistance is transferred to the longitudinal direction of the silicon wafer, which has three advantages: (1) reducing the device area, further improving the device integration density, (2) effectively reducing the on-resistance and power consumption, (3) basically eliminating the lateral flow of holes in the P well, effectively suppressing the pnpn latch-up effect (pnpn latch-up effect refers to when the working current of the device is greater than the latch-up critical current, the parasitic pnpn tube will be turned on, and at this time the actual control MOS tube may not be turned on, so the device cannot be controlled by the MOS tube through the external circuit to turn off the device), so the trench MOS device is widely used in power devices.

[0003] As a power device, the reliability of the trench MOS device is particularly important, and the reliability HTRB (High Temperature Reverse Bias) test of the power device manufacturing process is closely related to product design, process conditions, etc.

[0004] REFERENCE Figure 1 , Figure 1 is a recorded schematic diagram of using an existing trench gate MOS device to perform HTRB test, BSL product and product 2 are designed different products of the same platform, wherein, from Figure 1 it can be seen that when product 2 is tested under the condition of 48V examination voltage, 80pcs examination number and 150℃ examination temperature, 2pcs fail at 500h (hour) examination time, and 3pcs fail at 1000h examination time, it can be seen that product 2 fails in the reliability HTRB examination, which shows that the existing part of the trench gate MOS device cannot pass the HTRB test under high voltage condition, that is, the reliability of the existing trench gate MOS device has a problem. SUMMARY

[0005] The present application provides a method for improving the reliability of a trench gate MOS device, which can solve the problem that the existing trench gate MOS device cannot pass the HTRB test under high voltage condition.

[0006] In one aspect, the embodiments of the present application provide a method for improving the reliability of a trench gate MOS device, comprising:

[0007] providing a substrate, wherein a trench gate structure, a well region on the side of the trench gate structure, and a source and a drain on the two sides of the trench gate structure on the well region are formed in the substrate;

[0008] forming an interlayer dielectric layer covering the surface of the substrate and the surface of the trench gate structure;

[0009] applying a preset voltage to the drain and a ground voltage to the trench gate structure and the source to perform a high-temperature reverse bias test on the trench gate MOS device;

[0010] wherein the step of forming the interlayer dielectric layer comprises:

[0011] forming a first oxide layer covering the surface of the substrate and the surface of the trench gate structure;

[0012] forming a second oxide layer covering the first oxide layer, wherein the second oxide layer is formed without using a plasma enhanced CVD process.

[0013] Optionally, in the method for improving the reliability of the trench gate MOS device, the second oxide layer is formed using an O3TEOS CVD process.

[0014] Optionally, in the method for improving the reliability of the trench gate MOS device, the second oxide layer is formed using an HARP process.

[0015] Optionally, in the method for improving the reliability of the trench gate MOS device, the preset voltage applied to the drain is 48V-60V.

[0016] Optionally, in the method for improving the reliability of the trench gate MOS device, the test temperature of the high-temperature reverse bias test is 120℃-180℃, and the test time is 168h-1000h.

[0017] Optionally, in the method for improving the reliability of the trench gate MOS device, the thickness of the second oxide layer is 0.5-2nm.

[0018] Optionally, in the method for improving the reliability of the trench gate MOS device, the first oxide layer is a silicon-rich oxide layer.

[0019] Optionally, in the method for improving the reliability of the trench gate MOS device, the first oxide layer is formed using a CVD process.

[0020] Optionally, in the method for improving the reliability of the trench gate type MOS device, the thickness of the first oxide layer is

[0021] Optionally, in the method for improving the reliability of the trench gate type MOS device, the doping ion conductivity type of the substrate is N type; the doping ion conductivity type of the well region is P type; and the doping ion conductivity types of the source and the drain are both N type.

[0022] The technical scheme of the present application has at least the following advantages:

[0023] The present application improves the film layer structure of the interlayer insulating medium layer, forms the second oxide layer without using the plasma enhanced CVD process, i.e., forms the second oxide layer without plasma, avoids the situation that the formation of the second oxide layer by the plasma enhanced CVD process causes some electrons or impurities to gather at the channel position, i.e., effectively avoids the electrons or impurities from entering the product channel during the process, thereby effectively avoids the influence of the electrons or impurities on the channel when the device is turned on, and thus significantly improves the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical scheme in the specific embodiments or prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0025] Figure 1 is a record schematic diagram of the HTRB test using the existing trench gate type MOS device;

[0026] Figure 2 is a flowchart of the method for improving the reliability of the trench gate type MOS device according to the embodiment of the present application;

[0027] Figure 3 is a schematic diagram of the semiconductor structure after the execution of step S10 according to the embodiment of the present application;

[0028] Figure 4 is a schematic diagram of the semiconductor structure after the formation of the first oxide layer according to the embodiment of the present application;

[0029] Figure 5 is a schematic diagram of the semiconductor structure after the formation of the second oxide layer according to the embodiment of the present application;

[0030] Figure 6 is a record schematic diagram of the HTRB test using the existing trench gate type MOS device and the trench gate type MOS device according to the embodiment of the present application;

[0031] In the drawings:

[0032] 100 - substrate, 101 - well region, 102 - source, 103 - drain, 120 - trench gate structure, 121 - gate oxide layer, 122 - trench gate, 130 - interlayer dielectric layer, 131 - first oxide layer, 132 - second oxide layer. DETAILED DESCRIPTION

[0033] The technical solutions in the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of them. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of the present application.

[0034] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0035] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements; it can be wireless connection, or it can be wired connection. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0036] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0037] The inventor found that the existing trench gate MOS device will have electrons or impurities gathered at the channel position during the reliability HTRB test, which will affect the channel when the device is turned on, resulting in device failure, especially under the condition of increasing test voltage and increasing test time, the device failure problem is more serious.

[0038] Therefore, the embodiment of the present application provides a method for improving the reliability of the trench gate type MOS device, referring to Figure 2 , Figure 2 is a flow chart of the method for improving the reliability of the trench gate type MOS device of the embodiment of the present application, and the method for improving the reliability of the trench gate type MOS device comprises the following steps:

[0039] Step S10: referring to Figure 3 , Figure 3 is a schematic diagram of the semiconductor structure after step S10 of the embodiment of the present application, and a substrate 100 is provided, wherein a trench gate structure 120, a well region 101 located at the side of the trench gate structure 120, and a source 102 and a drain 103 respectively located at the two sides of the trench gate structure 120 on the well region 101 are formed in the substrate 100. Specifically, the substrate 100 can be one of single crystal silicon, polycrystalline silicon, and amorphous silicon, and the substrate 100 can also be gallium arsenide, silicon germanium compound, etc., and the substrate 100 can also have a structure of silicon on insulator or epitaxial layer on silicon; the substrate 100 can also be other semiconductor materials, which are not listed one by one here.

[0040] Further, the doping ion conductivity type of the substrate 100 is N type, which can be N+ heavily doped substrate; the doping ion conductivity type of the well region 101 is P type; and the doping ion conductivity types of the source 102 and the drain 103 are both N type.

[0041] Preferably, the trench gate structure 120 comprises a gate oxide layer 121 covering the bottom wall and the sidewall of the trench and a trench gate 122 filling the remaining trench.

[0042] Step S20: referring to Figure 4 and Figure 5 , Figure 4 is a schematic diagram of the semiconductor structure after forming the first oxide layer of the embodiment of the present application, Figure 5 is a schematic diagram of the semiconductor structure after forming the second oxide layer of the embodiment of the present application. An interlayer dielectric layer 130 is formed, which covers the surfaces of the gate oxide layer 121 and the trench gate 122.

[0043] Specifically, in the embodiment, the step of forming the interlayer dielectric layer 130 comprises:

[0044] First, as shown in Figure 4 , a first oxide layer 131 is formed, which covers the surfaces of the gate oxide layer 121 and the trench gate 122. The first oxide layer 131 includes but is not limited to a silicon-rich oxide layer (SRO). The first oxide layer 131 can be formed by CVD process in the embodiment. The thickness of the first oxide layer 131 can be 1-10 nm.

[0045] Next, as shown in Figure 5 Fig. 2, a second oxide layer 132 is formed covering the first oxide layer 131, wherein the second oxide layer 132 is formed without using a plasma enhanced CVD process.

[0046] In one embodiment, the second oxide layer 132 is formed using an O3TEOS CVD process.

[0047] In another embodiment, the second oxide layer 132 is formed using a HARP process.

[0048] Further, the thickness of the second oxide layer 132 can be 10-1000A, for example, 10A, 20A, 30A, 40A, 50A, 60A, 70A, 80A, 90A, 100A, 200A, 300A, 400A, 500A, 600A, 700A, 800A, 900A, 1000A, etc.

[0049] Step S30: A preset voltage is applied to the drain 102, and a ground voltage is applied to the trench gate structure 120 (trench gate 122) and the source 103 (i.e., the trench gate structure 120 (trench gate 122) and the source 103 are grounded) to perform a high-temperature reverse bias test on the trench gate type MOS device. During the high-temperature reverse bias test, the source 102, the trench gate 122, and the drain 103 can each be led out to the surface of the interlayer dielectric layer 130 (not shown) through a contact hole (filled with a metal material in the hole).

[0050] Specifically, the preset voltage applied to the drain is 48V-60V, for example, 50V, 55V, 58V, 60V, etc. The test temperature of the high-temperature reverse bias test is 120°C-180°C, for example, 140°C, 145°C, 150°C, 155°C, 160°C, 165°C, 170°C, 175°C, etc. The test time is 168h-1000h, for example, 168h, 400h, 500h, 600h, 700h, 800h, 900h, 968h, 1000h, etc.

[0051] Reference Figure 6 , Figure 6 is a record schematic diagram of HTRB tests using existing trench gate type MOS devices and trench gate type MOS devices of embodiments of the present application, which can be used to compare the performance of the existing trench gate type MOS devices and the trench gate type MOS devices of embodiments of the present application. Figure 6As can be seen, under the conditions of test temperature 150°C and test voltage 48V, when the interlayer dielectric layer (ILD) is a combination of silicon-rich oxide layer + plasma-enhanced oxide layer, 2pcs test failures occur at 500h of test time, and 3pcs test failures occur at 1000h of test time. However, when the interlayer dielectric layer (ILD) is a combination of the first oxide layer 131 and the second oxide layer 132 in the present application, under the conditions of test temperature 150°C and test voltage 48V, 60V, all of the trench gate MOS devices of the embodiments of the present application pass the HTRB test at 168h, 500h, and 1000h of test time.

[0052] As can be seen, by improving the film layer structure of the interlayer dielectric layer 130, the second oxide layer 132 is not formed by using the plasma-enhanced CVD process, i.e., the second oxide layer 132 is formed without plasma, which avoids the situation that some electrons or impurities are gathered at the channel position due to the plasma-enhanced CVD process for forming the second oxide layer 132, i.e., the electrons or impurities can be effectively prevented from entering the product channel during the process, thereby effectively avoiding the influence of the electrons or impurities on the channel when the device is turned on, and thus the device reliability is significantly improved.

[0053] Obviously, the above embodiments are merely examples for clearly illustrating but not limiting the embodiments. Based on the above description, other different forms of changes or modifications can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or modifications derived therefrom are still within the protection scope of the present application.

Claims

1. A method for improving the reliability of trench gate MOS devices, characterized in that, include: A substrate is provided in which a trench gate structure, a well region located on the side of the trench gate structure, and a source and a drain located on both sides of the trench gate structure on the well region are formed; An interlayer insulating dielectric layer is formed, which covers the substrate surface and the trench gate structure surface; A preset voltage is applied to the drain, and a ground voltage is applied to the trench gate structure and the source to perform a high-temperature reverse bias test on the trench gate MOS device. The step of forming the interlayer insulating dielectric layer includes: A first oxide layer is formed using a CVD process, and the first oxide layer covers the surface of the substrate and the surface of the trench gate structure. A second oxide layer is formed, which covers the first oxide layer, wherein the second oxide layer is formed without using a plasma-enhanced CVD process.

2. The method for improving the reliability of trench gate MOS devices according to claim 1, characterized in that, The second oxide layer is formed using the O3TEOS CVD process.

3. The method for improving the reliability of trench gate MOS devices according to claim 1, characterized in that, The second oxide layer is formed using the HARP process.

4. The method for improving the reliability of trench gate MOS devices according to claim 1, characterized in that, The preset voltage applied to the drain is 48V to 60V.

5. The method for improving the reliability of trench gate MOS devices according to claim 1, characterized in that, The high-temperature reverse bias test is conducted at a temperature of 120℃ to 180℃ for a duration of 168h to 1000h.

6. The method for improving the reliability of trench gate MOS devices according to claim 1, characterized in that, The thickness of the second oxide layer is 7. The method for improving the reliability of trench gate MOS devices according to claim 1, characterized in that, The first oxide layer is a silicon-rich oxide layer.

8. The method for improving the reliability of trench gate MOS devices according to claim 1, characterized in that, The thickness of the first oxide layer is 9. The method for improving the reliability of trench gate MOS devices according to claim 1, characterized in that, The substrate is N-type doped with ions; the well region is P-type doped with ions; and both the source and drain are N-type doped with ions.

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