Three-primary-color light-emitting diode chip preparation method and three-primary-color light-emitting diode chip

Abstract

The present disclosure provides a method for fabricating a three-primary-color light-emitting diode chip and a three-primary-color light-emitting diode chip, belonging to the field of optoelectronic manufacturing technology. The fabrication method comprises: fabricating a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer on three substrates, respectively; fabricating a first intermediate layer on the surfaces of the first epitaxial layer and the second epitaxial layer, and connecting the first epitaxial layer and the second epitaxial layer via the first intermediate layer; removing the substrate of the second epitaxial layer; roughening the surface of the second epitaxial layer exposed after removing the substrate; fabricating a second intermediate layer on the surfaces of the second epitaxial layer and the third epitaxial layer, and connecting the second epitaxial layer and the third epitaxial layer via the second intermediate layer; removing the substrate of the third epitaxial layer; and fabricating electrodes connected to the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a method for preparing a three-primary-color light-emitting diode chip and a three-primary-color light-emitting diode chip. Background Art

[0002] A tri-color LED is an electronic component that uses the principle of three primary colors to emit light of different colors. Tri-color LEDs have the characteristics of self-luminescence, high brightness, high contrast, high responsiveness and energy saving.

[0003] In the related art, a three-primary-color light-emitting diode generally includes an epitaxial structure, which includes three stacked blue epitaxial layers, green epitaxial layers, and red epitaxial layers, with two adjacent epitaxial layers connected via an intermediate layer. Summary of the Invention

[0004] The present disclosure provides a method for manufacturing a three-primary-color light-emitting diode chip and a three-primary-color light-emitting diode chip, which can enhance the bonding strength between two epitaxial layers of the three-primary-color light-emitting diode chip and improve light extraction efficiency. The technical solution is as follows:

[0005] The present disclosure provides a method for preparing a three-primary-color light-emitting diode chip, the method comprising:

[0006] forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on three substrates respectively;

[0007] forming a first intermediate layer on the surfaces of the first epitaxial layer and the second epitaxial layer, and connecting the first epitaxial layer and the second epitaxial layer through the first intermediate layer;

[0008] removing the substrate of the second epitaxial layer;

[0009] roughening a surface of the second epitaxial layer exposed after removing the substrate;

[0010] forming a second intermediate layer on the surfaces of the second epitaxial layer and the third epitaxial layer, and connecting the second epitaxial layer and the third epitaxial layer through the second intermediate layer;

[0011] removing the substrate of the third epitaxial layer;

[0012] Electrodes connected to the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are fabricated.

[0013] Optionally, the first intermediate layer includes: a first transparent conductive layer, a first adhesion layer and a second transparent conductive layer;

[0014] The step of forming a first intermediate layer on the surfaces of the first epitaxial layer and the second epitaxial layer, and connecting the first epitaxial layer and the second epitaxial layer through the first intermediate layer comprises:

[0015] forming the first transparent conductive layer on the surface of the first epitaxial layer, and forming the second transparent conductive layer on the surface of the second epitaxial layer;

[0016] The first adhesive layer is formed on the first transparent conductive layer and adhered to the second transparent conductive layer.

[0017] Optionally, the second intermediate layer includes: a third transparent conductive layer and a second adhesion layer;

[0018] The step of forming a second intermediate layer on the surfaces of the second epitaxial layer and the third epitaxial layer, and connecting the second epitaxial layer and the third epitaxial layer via the second intermediate layer, comprises:

[0019] forming the third transparent conductive layer on the surface of the third epitaxial layer;

[0020] The second adhesion layer is formed on the roughened surface of the second epitaxial layer and is bonded to the third transparent conductive layer.

[0021] Optionally, the step of fabricating electrodes connected to the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer includes:

[0022] Etching using an etching process to expose the N-type layer in the first epitaxial layer and the second epitaxial layer respectively;

[0023] Etching the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer using an etching process to expose the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer respectively;

[0024] Making P electrodes respectively connected to the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer;

[0025] A first N-electrode connected to the N-type layer in the first epitaxial layer is fabricated, a second N-electrode connected to the N-type layer in the second epitaxial layer is fabricated, and a third N-electrode connected to the N-type layer in the third epitaxial layer is fabricated.

[0026] Optionally, the surface of the second epitaxial layer exposed after the substrate is removed is an N-type layer, and the roughening of the surface of the second epitaxial layer exposed after the substrate is removed includes:

[0027] The surface of the N-type layer of the second epitaxial layer is etched using an etching solution to roughen the surface of the second epitaxial layer exposed after the substrate is removed.

[0028] Optionally, the etching the surface of the N-type layer of the second epitaxial layer using a corrosive solution includes:

[0029] The surface of the N-type layer of the second epitaxial layer is immersed in a KOH solution at a temperature range of 60-70 degrees for 5-20 minutes.

[0030] Optionally, before manufacturing the P electrode, the first N electrode, the second N electrode, and the third N electrode, the preparation method further includes:

[0031] forming a protective layer covering the first epitaxial layer, the second epitaxial layer and the third epitaxial layer;

[0032] A via hole for connecting the P electrode, the first N electrode, the second N electrode, and the third N electrode is opened on the protection layer.

[0033] The present disclosure provides a three-primary-color light-emitting diode chip, comprising a substrate, a first epitaxial layer, a first intermediate layer, a second epitaxial layer, a second intermediate layer, and a third epitaxial layer stacked in sequence, and further comprising electrodes connected to the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer;

[0034] A surface of the second epitaxial layer in contact with the second intermediate layer is roughened.

[0035] Optionally, the first intermediate layer includes: a first transparent conductive layer, a first adhesion layer and a second transparent conductive layer;

[0036] The first transparent conductive layer is located on the surface of the first epitaxial layer, the second transparent conductive layer is located on the surface of the second epitaxial layer, and the first adhesive layer is bonded to the first transparent conductive layer and the second transparent conductive layer respectively.

[0037] Optionally, the second intermediate layer includes: a third transparent conductive layer and a second adhesion layer;

[0038] The third transparent conductive layer is located on the surface of the third epitaxial layer, the second adhesion layer is located on the roughened surface of the second epitaxial layer, and the second adhesion layer is bonded to the third transparent conductive layer.

[0039] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0040] The disclosed embodiment roughens the surface exposed after the substrate is removed from the second epitaxial layer, thereby making the bonding force between the second epitaxial layer and the second intermediate layer stronger, thereby increasing the bonding force between the second epitaxial layer and the third epitaxial layer, and improving the physical properties of the three-primary-color light-emitting diode chip. In addition, the roughened second epitaxial layer can improve the light extraction efficiency of the light passing through the first epitaxial layer and the second epitaxial layer, which is beneficial to the light extraction efficiency of the entire three-primary-color light-emitting diode chip. Finally, since the surface exposed after the substrate is removed from the second epitaxial layer is actually the N-type layer of the epitaxial layer, and the N-type layer is relatively thick, the surface exposed after the substrate is removed from the second epitaxial layer can be roughened to achieve the purpose of roughening, increase the bonding force between the second epitaxial layer and the third epitaxial layer, and improve the light extraction efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] Figure 1 This is a flow chart of a method for preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0043] Figure 2 This is a flow chart of a method for preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0044] Figure 3 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0045] Figure 4 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0046] Figure 5 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0047] Figure 6 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0048] Figure 7 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0049] Figure 8 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0050] Figure 9 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0051] Figure 10 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0052] Figure 11 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0053] Figure 12 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0054] Figure 13 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0055] Figure 14 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0056] Figure 15 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0057] Figure 16 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0058] Figure 17 This is a structural diagram of the process of preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure;

[0059] Figure 18 It is a structural schematic diagram of the preparation process of the three-primary-color light-emitting diode chip provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0061] Figure 1 This is a flow chart of a method for preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure. Figure 1 , the preparation method comprises:

[0062] S101: forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on three substrates respectively.

[0063] For example, the substrate may be a sapphire substrate or other substrates.

[0064] For example, the first epitaxial layer may be a blue epitaxial layer, the second epitaxial layer may be a green epitaxial layer, and the third epitaxial layer may be a red epitaxial layer.

[0065] Illustratively, the first epitaxial layer includes a first N-type layer, a first light-emitting layer, and a first P-type layer sequentially stacked on a substrate. The second epitaxial layer includes a second N-type layer, a second light-emitting layer, and a second P-type layer sequentially stacked on the substrate. The third epitaxial layer includes a third N-type layer, a third light-emitting layer, and a third P-type layer sequentially stacked on the substrate.

[0066] S102: forming a first intermediate layer on surfaces of the first epitaxial layer and the second epitaxial layer, and connecting the first epitaxial layer and the second epitaxial layer through the first intermediate layer.

[0067] Here, the first intermediate layer is formed on the surfaces of the first epitaxial layer and the second epitaxial layer away from the substrate.

[0068] S103: removing the substrate of the second epitaxial layer.

[0069] S104: Roughening the surface of the second epitaxial layer exposed after removing the substrate.

[0070] That is, the surface of the second epitaxial layer that is originally in contact with the substrate is roughened.

[0071] S105: forming a second intermediate layer on the surfaces of the second epitaxial layer and the third epitaxial layer, and connecting the second epitaxial layer and the third epitaxial layer through the second intermediate layer.

[0072] Here, the second intermediate layer is formed on the roughened surface of the first epitaxial layer and the surface of the third epitaxial layer away from the substrate.

[0073] S106: removing the substrate of the third epitaxial layer.

[0074] S107: Fabricating electrodes connected to the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer.

[0075] Here, the electrode is made on the surface of the third epitaxial layer that was originally in contact with the substrate.

[0076] The disclosed embodiment roughens the surface exposed after the substrate is removed from the second epitaxial layer, thereby making the bonding force between the second epitaxial layer and the second intermediate layer stronger, thereby increasing the bonding force between the second epitaxial layer and the third epitaxial layer, and improving the physical properties of the three-primary-color light-emitting diode chip. In addition, the roughened second epitaxial layer can improve the light extraction efficiency of the light passing through the first epitaxial layer and the second epitaxial layer, which is beneficial to the light extraction efficiency of the entire three-primary-color light-emitting diode chip. Finally, since the surface exposed after the substrate is removed from the second epitaxial layer is actually the N-type layer of the epitaxial layer, and the N-type layer is relatively thick, the surface exposed after the substrate is removed from the second epitaxial layer can be roughened to achieve the purpose of roughening, increase the bonding force between the second epitaxial layer and the third epitaxial layer, and improve the light extraction efficiency.

[0077] Figure 2 This is a flow chart of a method for preparing a three-primary-color light-emitting diode chip provided by an embodiment of the present disclosure. Figure 2 , the preparation method comprises:

[0078] S201: forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on three substrates respectively.

[0079] For example, the substrate may be a sapphire substrate or other substrates.

[0080] For example, the first epitaxial layer may be a blue epitaxial layer, the second epitaxial layer may be a green epitaxial layer, and the third epitaxial layer may be a red epitaxial layer.

[0081] Figure 3 This is a schematic diagram of the structure after step S201 is completed. Figure 3 The first epitaxial layer 21 includes a first N-type layer 211, a first light-emitting layer 212, and a first P-type layer 213, which are sequentially stacked on the substrate 10. The second epitaxial layer 22 includes a second N-type layer 221, a second light-emitting layer 222, and a second P-type layer 223, which are sequentially stacked on the substrate 10. The third epitaxial layer 23 includes a third N-type layer 231, a third light-emitting layer 232, and a third P-type layer 233, which are sequentially stacked on the substrate 10.

[0082] The first N-type layer and the second N-type layer may both be N-type GaN layers, the first P-type layer and the second P-type layer may both be P-type GaN layers, the third N-type layer may be an N-type AlGaInP current spreading layer, and the third P-type layer may be a P-type AlInP layer.

[0083] Optionally, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer each include alternately grown InGaN quantum well layers and GaN quantum barrier layers. The first light-emitting layer, the second light-emitting layer, and the third light-emitting layer each include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0084] As an example, in the embodiment of the present disclosure, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer each include five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0085] Optionally, the thickness of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer may all be 150 nm to 200 nm.

[0086] Exemplarily, the thickness of the first epitaxial layer and the second epitaxial layer may both be 2 μm to 4 μm. For example, the thickness of the first epitaxial layer and the second epitaxial layer may both be 3 μm. Exemplarily, the thickness of the third epitaxial layer may be 3 μm to 5 μm. For example, the thickness of the third epitaxial layer may be 4 μm.

[0087] It is worth mentioning that Figure 3 The provided example is only the basic structure of the epitaxial layer. In other implementations, the epitaxial layer may also include other structures. For example, the first epitaxial layer 21 may include a GaN low-temperature layer, a GaN intrinsic layer, a first N-type layer, a first light-emitting layer, a first P-type layer, and a window layer stacked in sequence. The second epitaxial layer 22 may include a GaN low-temperature layer, a GaN intrinsic layer, a second N-type layer, a second light-emitting layer, a second P-type layer, and a window layer stacked in sequence. The third epitaxial layer 23 may include a GaAs layer, an etching stop layer, a third N-type layer, an AlInP carrier confinement layer, a third light-emitting layer, a third P-type layer, and a window layer stacked in sequence.

[0088] S202: forming a first transparent conductive layer on the surface of the first epitaxial layer, and forming a second transparent conductive layer on the surface of the second epitaxial layer.

[0089] Figure 4 This is a schematic diagram of the structure after step S202 is completed. Figure 4 A first transparent conductive layer 31 is formed on the surface of the first P-type layer 213 of the first epitaxial layer, and a second transparent conductive layer 32 is formed on the surface of the second P-type layer 223 of the first epitaxial layer.

[0090] In one possible implementation, the first transparent conductive layer 31 and the second transparent conductive layer 32 may both be indium tin oxide (ITO) film layers, and the thickness of the first transparent conductive layer 31 and the second transparent conductive layer 32 may both be 50 angstroms to 5000 angstroms. In another possible implementation, the first transparent conductive layer 31 and the second transparent conductive layer 32 may both be NiAu film layers, and the thickness of the first transparent conductive layer 31 and the second transparent conductive layer 32 may both be less than 20 angstroms.

[0091] The transparent conductive layer made of the above-mentioned material and thickness can achieve both ohmic contact and light transmittance of the transparent conductive layer.

[0092] In addition, the method may further include: performing annealing treatment on the first transparent conductive layer 31 and the second transparent conductive layer 32 .

[0093] S203: forming a first adhesive layer on the first transparent conductive layer and bonding the first adhesive layer to the second transparent conductive layer.

[0094] Figure 5 This is a schematic diagram of the structure after step S203 is completed. Figure 5 , forming a first adhesive layer 71 on the surface of the first transparent conductive layer 31, and then attaching the second transparent conductive layer 32 thereto, and bonding them by pressure.

[0095] The first adhesion layer 71 may be made by spin coating, and the material of the first adhesion layer 71 may be an organic adhesion material. The thickness of the first adhesion layer 71 may be in the range of 0.5 to 3 μm.

[0096] During bonding, the pressure range used may be 2000-8000 kg, and the temperature range may be 200-300° C.

[0097] In the embodiment of the present disclosure, the first transparent conductive layer 31 , the first adhesive layer 71 and the second transparent conductive layer 32 constitute a first intermediate layer 50 , and the first epitaxial layer and the second epitaxial layer are connected via the first intermediate layer.

[0098] S204: removing the substrate of the second epitaxial layer.

[0099] Figure 6 This is a schematic diagram of the structure after step S204 is completed. Figure 6 , the substrate 10 of the second epitaxial layer is removed, thereby exposing the second N-type layer 221 in the second epitaxial layer.

[0100] The substrate of the second epitaxial layer can be removed by chemical lift-off or laser lift-off.

[0101] S205: Roughening the surface of the second epitaxial layer exposed after removing the substrate.

[0102] In this step, the surface of the second epitaxial layer exposed after removing the substrate is an N-type layer. Step S205 may include:

[0103] The surface of the N-type layer of the second epitaxial layer is etched using an etching solution to roughen the surface of the second epitaxial layer exposed after the substrate is removed.

[0104] In this implementation, the N-type layer, due to its greater thickness, can withstand the etching process to achieve roughening, thereby increasing the bonding strength between the second and third epitaxial layers and improving light extraction efficiency. However, the surface where the first and second epitaxial layers meet is a transparent conductive layer, which is thinner and more difficult to roughen, and thus cannot be treated in the same way.

[0105] Exemplarily, etching the surface of the N-type layer of the second epitaxial layer using a corrosive solution includes:

[0106] The surface of the N-type layer of the second epitaxial layer is immersed in a KOH solution at a temperature range of 60-70 degrees for 5-20 minutes.

[0107] For example, a KOH solution is used to soak the surface of the N-type layer of the second epitaxial layer at a temperature of 65 degrees for 10 minutes to roughen the surface of the N-type layer.

[0108] Figure 7 This is a schematic diagram of the structure after step S205 is completed. Figure 7 The surface of the second N-type layer 221 in the second epitaxial layer is roughened.

[0109] S206: forming a third transparent conductive layer on the surface of the third epitaxial layer.

[0110] Figure 8 This is a schematic diagram of the structure after step S206 is completed. Figure 8 A third transparent conductive layer 33 is formed on the surface of the third P-type layer 233 of the third epitaxial layer.

[0111] In one possible implementation, the third transparent conductive layer 33 may be an ITO film layer, and the thickness of the third transparent conductive layer 33 may be 50 angstroms to 5000 angstroms. In another possible implementation, the third transparent conductive layer 33 may be a NiAu film layer, and the thickness of the third transparent conductive layer 33 may be less than 20 angstroms.

[0112] The transparent conductive layer made of the above-mentioned material and thickness can achieve both ohmic contact and light transmittance of the transparent conductive layer.

[0113] In addition, the method may further include: performing annealing treatment on the third transparent conductive layer 33 .

[0114] S207: forming a second adhesion layer on the roughened surface of the second epitaxial layer and bonding it to the third transparent conductive layer.

[0115] Figure 9 This is a schematic diagram of the structure after step S207 is completed. Figure 9A second adhesion layer 72 is formed on the surface of the second N-type layer 221 in the second epitaxial layer, and then the third transparent conductive layer 33 is attached to the second adhesion layer 72 and bonded by pressure.

[0116] The second adhesive layer 72 may be formed by spin coating, and the material of the second adhesive layer 72 may be an organic adhesive material. The thickness of the second adhesive layer 72 may be in the range of 0.5 to 3 μm.

[0117] During bonding, the pressure range used may be 2000-8000 kg, and the temperature range may be 200-300° C.

[0118] In the embodiment of the present disclosure, the third transparent conductive layer 33 and the second adhesive layer 72 constitute the second intermediate layer 60 , and the second epitaxial layer and the third epitaxial layer are connected via the second intermediate layer.

[0119] S208: removing the substrate of the third epitaxial layer.

[0120] Figure 10 This is a schematic diagram of the structure after step S208 is completed. Figure 10 , the substrate 10 of the third epitaxial layer is removed, so that the third N-type layer 231 of the third epitaxial layer is exposed.

[0121] The substrate of the third epitaxial layer can be removed by chemical lift-off or laser lift-off.

[0122] S209: performing etching using an etching process to expose the N-type layer in the first epitaxial layer and the second epitaxial layer respectively.

[0123] Figure 11 This is a schematic diagram of the structure after step S209 is completed. Figure 11 , etching one side of the third, second and first epitaxial structures to form a step-shaped groove structure, so that the first N-type layer 211 of the first epitaxial layer is exposed.

[0124] Figure 12 This is a schematic diagram of the structure after step S209 is completed. Figure 12 , etching the other side of the third and second epitaxial structures to form a step-shaped groove structure, so that the second N-type layer 221 of the second epitaxial layer is exposed.

[0125] Here, etching may be performed on different sides of the epitaxial wafer to expose the first N-type layer 211 and the second N-type layer 221 respectively.

[0126] The etching process may be dry etching.

[0127] S210: performing etching using an etching process to expose the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer respectively.

[0128] Figure 13 is a schematic diagram of the structure after step S210 is completed, see Figure 13 , another side edge of the third, second and first epitaxial structures is etched to form a step-shaped groove structure, so that the first transparent conductive layer 31, the second transparent conductive layer 32 and the third transparent conductive layer 33 are all exposed.

[0129] The etching process may be dry etching.

[0130] S211: making P electrodes respectively connected to the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer.

[0131] Figure 14 This is a schematic diagram of the structure after step S211 is completed. Figure 14 A P-electrode connection structure 41 is made on another side of the third, second and first epitaxial structures. The P-electrode connection structure 41 connects the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer in sequence. A P-electrode 42 is made on the third N-type layer 231. The P-electrode connection structure 41 and the P-electrode 42 are connected.

[0132] Exemplarily, the P-electrode connection structure is manufactured by evaporation (sputtering).

[0133] S212: fabricating a first N-electrode connected to the N-type layer in the first epitaxial layer, fabricating a second N-electrode connected to the N-type layer in the second epitaxial layer, and fabricating a third N-electrode connected to the N-type layer in the third epitaxial layer.

[0134] Figure 15 This is a schematic diagram of the structure after step S212 is completed. Figure 15 A first N-electrode connection structure 43 is fabricated on one side of the third, second, and first epitaxial structures. The first N-electrode connection structure 43 is connected to the first N-type layer 211 . A first N-electrode 44 is fabricated on the third N-type layer 231 . The first N-electrode connection structure 43 is connected to the first N-electrode 44 .

[0135] Figure 16 This is a schematic diagram of the structure after step S212 is completed. Figure 16 A second N-electrode connection structure 45 is fabricated on the other side of the third and second epitaxial structures. The second N-electrode connection structure 45 is connected to the second N-type layer 221 . A second N-electrode 46 is fabricated on the third N-type layer 231 . The second N-electrode connection structure 45 is connected to the second N-electrode 46 .

[0136] Exemplarily, the first N-electrode connection structure and the second N-electrode connection structure are manufactured by evaporation (sputtering).

[0137] Figure 17This is a schematic diagram of the structure after step S212 is completed. Figure 17 , a third N-electrode 47 is fabricated on the third N-type layer 231 , and the third N-electrode 47 is connected to the third N-type layer 231 .

[0138] Exemplarily, the P electrode 42 , the first N electrode 44 , the second N electrode 46 and the third N electrode 47 may all be columnar metal electrodes, and the surface metal of the columnar metal electrodes may be an alloyable metal such as Au or Ni.

[0139] Figure 18 This is a top view after step S212 is completed, see Figure 18 , Figures 15 to 17 Only the individual electrode structures are shown. Figure 18 The distribution of the P electrode and three N electrodes is shown, and the four electrodes are located at the four corners.

[0140] like Figure 18 As shown, three reference numerals 80 in the figure represent three stepped groove structures etched in steps S209 and S210.

[0141] Figure 18 The cross-sectional view of AA is the aforementioned Figure 14 , the cross-sectional view of BB is the aforementioned Figure 15 , the cross-sectional view of CC is the aforementioned Figure 16 , the cross-sectional view of DD is the aforementioned Figure 17 .

[0142] Optionally, before fabricating the P electrode, the first N electrode, the second N electrode, and the third N electrode, the preparation method further includes:

[0143] forming a protective layer covering the first epitaxial layer, the second epitaxial layer and the third epitaxial layer;

[0144] A via hole for connecting the P electrode, the first N electrode, the second N electrode and the third N electrode is opened on the protection layer.

[0145] Exemplarily, the P-electrode connection structure, the first N-electrode connection structure, and the second N-electrode connection structure are also manufactured after the protective layer.

[0146] For example, a group of via holes is opened for the P-electrode connection structure to connect to the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer respectively.

[0147] For another example, a via hole is opened for the first N-electrode connection structure to connect to the first N-type layer.

[0148] For another example, a via hole is opened for the second N-electrode connection structure to connect to the second N-type layer.

[0149] For another example, a via hole is opened for the third N-electrode to connect to the third N-type layer.

[0150] By providing a protective layer and opening vias in the protective layer, it is ensured that each electrode and connection structure is electrically connected only to the layer that needs to be connected, and avoids electrical connection with other layers.

[0151] For the sake of simplicity, the protective layer is not shown in the above figures.

[0152] Exemplarily, the protective layer can be implemented by using a SiO2 / SiN / Al2O3 stack.

[0153] The via holes are opened on the protective layer by wet etching.

[0154] Optionally, after the electrode is manufactured, the method may further include: using spin coating to cover the entire surface with an organic material to form an organic protective layer, such as polyimide.

[0155] In addition, conventional thinning and cutting can be performed after the electrode is produced to complete the chip unit production.

[0156] The disclosed embodiments also provide a schematic structural diagram of a three-primary-color LED chip. The three-primary-color LED chip includes a substrate, a first epitaxial layer, a first intermediate layer, a second epitaxial layer, a second intermediate layer, and a third epitaxial layer stacked in sequence. The three-primary-color LED chip also includes electrodes connected to the first, second, and third epitaxial layers. The surface of the second epitaxial layer in contact with the second intermediate layer is roughened.

[0157] The three-primary-color light-emitting diode chip can be used Figure 1 or Figure 2 The structure of the three-primary-color light-emitting diode chip can be seen in Figures 14 to 18 .

[0158] The disclosed embodiment roughens the surface exposed after the substrate is removed from the second epitaxial layer, thereby making the bonding force between the second epitaxial layer and the second intermediate layer stronger, thereby increasing the bonding force between the second epitaxial layer and the third epitaxial layer, and improving the physical properties of the three-primary-color light-emitting diode chip. In addition, the roughened second epitaxial layer can improve the light extraction efficiency of the light passing through the first epitaxial layer and the second epitaxial layer, which is beneficial to the light extraction efficiency of the entire three-primary-color light-emitting diode chip. Finally, since the surface exposed after the substrate is removed from the second epitaxial layer is actually the N-type layer of the epitaxial layer, and the N-type layer is relatively thick, the surface exposed after the substrate is removed from the second epitaxial layer can be roughened to achieve the purpose of roughening, increase the bonding force between the second epitaxial layer and the third epitaxial layer, and improve the light extraction efficiency.

[0159] Exemplarily, the first intermediate layer includes: a first transparent conductive layer, a first adhesion layer, and a second transparent conductive layer;

[0160] The first transparent conductive layer is located on the surface of the first epitaxial layer, the second transparent conductive layer is located on the surface of the second epitaxial layer, and the first adhesive layer is bonded to the first transparent conductive layer and the second transparent conductive layer respectively.

[0161] Exemplarily, the second intermediate layer includes: a third transparent conductive layer and a second adhesive layer;

[0162] The third transparent conductive layer is located on the surface of the third epitaxial layer, the second adhesive layer is located on the roughened surface of the second epitaxial layer, and the second adhesive layer is bonded to the third transparent conductive layer.

[0163] Exemplarily, the electrodes may include a P electrode, a first N electrode, a second N electrode, and a third N electrode.

[0164] The above does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not intended to limit the present disclosure. Any technician familiar with the profession can make slight changes or modifications to equivalent embodiments with equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A method for preparing a three-primary-color light-emitting diode chip, characterized in that: The preparation method comprises: forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on three substrates respectively; forming a first intermediate layer on the surfaces of the first epitaxial layer and the second epitaxial layer, and connecting the first epitaxial layer and the second epitaxial layer through the first intermediate layer; removing the substrate of the second epitaxial layer; roughening a surface of the second epitaxial layer exposed after removing the substrate; forming a second intermediate layer on the surfaces of the second epitaxial layer and the third epitaxial layer, and connecting the second epitaxial layer and the third epitaxial layer through the second intermediate layer; removing the substrate of the third epitaxial layer; Electrodes connected to the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are fabricated.

2. The preparation method according to claim 1, characterized in that The first intermediate layer includes: a first transparent conductive layer, a first adhesion layer and a second transparent conductive layer; The step of forming a first intermediate layer on the surfaces of the first epitaxial layer and the second epitaxial layer, and connecting the first epitaxial layer and the second epitaxial layer through the first intermediate layer comprises: forming the first transparent conductive layer on the surface of the first epitaxial layer, and forming the second transparent conductive layer on the surface of the second epitaxial layer; The first adhesive layer is formed on the first transparent conductive layer and adhered to the second transparent conductive layer.

3. The preparation method according to claim 2, characterized in that The second intermediate layer includes: a third transparent conductive layer and a second adhesive layer; The step of forming a second intermediate layer on the surfaces of the second epitaxial layer and the third epitaxial layer, and connecting the second epitaxial layer and the third epitaxial layer via the second intermediate layer, comprises: forming the third transparent conductive layer on the surface of the third epitaxial layer; The second adhesion layer is formed on the roughened surface of the second epitaxial layer and adhered to the third transparent conductive layer.

4. The preparation method according to claim 3, characterized in that The step of fabricating electrodes connected to the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer includes: Etching using an etching process to expose the N-type layer in the first epitaxial layer and the second epitaxial layer respectively; Etching the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer using an etching process to expose the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer respectively; Making P electrodes respectively connected to the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer; A first N-electrode connected to the N-type layer in the first epitaxial layer is fabricated, a second N-electrode connected to the N-type layer in the second epitaxial layer is fabricated, and a third N-electrode connected to the N-type layer in the third epitaxial layer is fabricated.

5. The preparation method according to any one of claims 1 to 4, characterized in that The surface of the second epitaxial layer exposed after the substrate is removed is an N-type layer, and the roughening of the surface of the second epitaxial layer exposed after the substrate is removed includes: The surface of the N-type layer of the second epitaxial layer is etched using an etching solution to roughen the surface of the second epitaxial layer exposed after the substrate is removed.

6. The preparation method according to claim 5, characterized in that The etching of the surface of the N-type layer of the second epitaxial layer using a corrosive solution comprises: The surface of the N-type layer of the second epitaxial layer is immersed in a KOH solution at a temperature range of 60-70 degrees Celsius for 5-20 minutes.

7. The preparation method according to claim 4, characterized in that Before manufacturing the P electrode, the first N electrode, the second N electrode, and the third N electrode, the manufacturing method further includes: forming a protective layer covering the first epitaxial layer, the second epitaxial layer and the third epitaxial layer; A via hole for connecting the P electrode, the first N electrode, the second N electrode, and the third N electrode is opened on the protection layer.

8. A three-primary-color light-emitting diode chip, characterized in that: The three-primary-color light-emitting diode chip includes a substrate, a first epitaxial layer, a first intermediate layer, a second epitaxial layer, a second intermediate layer, and a third epitaxial layer stacked in sequence, and further includes electrodes connected to the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer; The surface of the second epitaxial layer in contact with the second intermediate layer is roughened; The second intermediate layer includes: a third transparent conductive layer and a second adhesive layer; The third transparent conductive layer is located on the surface of the third epitaxial layer, the second adhesion layer is located on the roughened surface of the second epitaxial layer, and the second adhesion layer is bonded to the third transparent conductive layer; The material of the second adhesion layer is an organic adhesion material.

9. The three-primary-color light-emitting diode chip according to claim 8, characterized in that: The first intermediate layer includes: a first transparent conductive layer, a first adhesion layer and a second transparent conductive layer; The first transparent conductive layer is located on the surface of the first epitaxial layer, the second transparent conductive layer is located on the surface of the second epitaxial layer, and the first adhesive layer is bonded to the first transparent conductive layer and the second transparent conductive layer respectively.

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