Direct-current-direct-current power conversion system and power conversion method thereof

Abstract

The DC-DC power conversion system includes a resonant switching capacitor converter and a controller. The resonant switching capacitor converter receives an input voltage and switches between a first state and a second state to generate an output voltage. The resonant switching capacitor converter includes an input terminal, a resonant slot, an output capacitor, a first set of switches, and a second set of switches. The input terminal receives the input voltage. The output capacitor generates the output voltage. The first set of switches is coupled to the resonant slot and the output capacitor, receiving a first control signal to conduct in the first state and to cut off in the second state. The second set of switches is coupled to the resonant slot and the output capacitor, receiving a second control signal to conduct in the second state and to cut off in the first state. The controller adjusts the first and second control signals according to the output voltage.

Description

Technical Field

[0001] This invention relates to electronic circuits, and in particular to a DC-DC power conversion system and its power conversion method. Background Technology

[0002] A DC-DC converter is a device that converts DC voltage to different DC voltages, commonly used in mobile electronic devices such as cell phones and laptops to provide power. A resonant switched-capacitor converter (RSCC) is a type of DC-DC converter that generates little or no power consumption when transmitting power.

[0003] A resonant switching capacitor converter converts the input voltage to the output voltage at a fixed conversion ratio. When the input voltage is too high, the resonant switching capacitor converter will still produce an excessively high output voltage at the fixed conversion ratio, causing damage to electronic devices.

[0004] Related technologies utilize an additional bulk converter to control the input voltage of the resonant switching capacitor converter, thereby controlling the output voltage of the resonant switching capacitor converter. However, the bulk converter occupies a large circuit area, increasing manufacturing costs. Summary of the Invention

[0005] This invention provides a DC-DC power conversion system, including a resonant switching capacitor converter and a controller. The resonant switching capacitor converter receives an input voltage and switches between a first state and a second state to generate an output voltage. The resonant switching capacitor converter includes an input terminal, a resonant slot, an output capacitor, a first set of switches, and a second set of switches. The input terminal receives the input voltage. The output capacitor has a first terminal for generating the output voltage and a second terminal coupled to a ground terminal. The first set of switches is coupled to the resonant slot and the output capacitor, and receives a first control signal to conduct in the first state and to cut off in the second state. The second set of switches is coupled to the resonant slot and the output capacitor, and receives a second control signal to conduct in the second state and to cut off in the first state. The output terminal is coupled to the output capacitor to output the output voltage. The controller is coupled to the first set of switches and the second set of switches, and adjusts the first control signal according to the output voltage to control a first on-time of the first set of switches, and adjusts the second control signal according to the output voltage to control a second on-time of the second set of switches.

[0006] This invention provides another power conversion method applicable to DC-DC power conversion systems. The DC-DC power conversion system includes a resonant switching capacitor converter and a controller. The resonant switching capacitor converter includes a resonant slot, an output capacitor, a first set of switches coupled to the resonant slot and the output capacitor, and a second set of switches coupled to the resonant slot and the output capacitor. The power conversion method includes the resonant switching capacitor converter switching between a first state and a second state to generate an output voltage. The controller adjusts a first control signal and a second control signal according to the output voltage. The first set of switches receives the first control signal to conduct for a first conduction time in the first state, and the second set of switches receives the second control signal to conduct for a second conduction time in the second state. Attached Figure Description

[0007] Figure 1 This is a block diagram of a DC-DC power conversion system in an embodiment of the present invention.

[0008] Figure 2 yes Figure 1 A circuit diagram of a DC-DC power conversion system.

[0009] Figure 3 yes Figure 1 A flowchart of the power conversion method of a DC-DC power conversion system.

[0010] Figure 4 yes Figure 1 The circuit diagram of the controller.

[0011] Figure 5 yes Figure 4 The waveform diagram of the controller.

[0012] Figure 6 yes Figure 1 The first control signal Sc1 and the second control signal Sc2 of the DC-DC power conversion system are essentially analog waveforms at 50% duty cycle.

[0013] Figure 7 yes Figure 1 The first control signal Sc1 and the second control signal Sc2 of the DC-DC power conversion system are essentially analog waveforms at 25% duty cycle.

[0014] Figure 8 yes Figure 1 A circuit diagram of another resonant switching capacitor converter.

[0015] Figure 9 yes Figure 1 A circuit diagram of another resonant switching capacitor converter.

[0016] Figure 10 yes Figure 1 A circuit diagram of another resonant switching capacitor converter. Detailed Implementation

[0017] Figure 1 This is a block diagram of a DC-DC power conversion system 1 according to an embodiment of the present invention. The DC-DC power conversion system 1 uses a resonant switched-capacitor converter (RSCC) to convert the input voltage Vin to the output voltage Vout, and can adjust the output voltage Vout to maintain a fixed value without the need for a bulk converter, thereby providing overvoltage protection without significantly increasing the circuit area. The input voltage Vin and the output voltage Vout are DC voltages, and the output voltage Vout can be greater than or less than the input voltage Vin. In some embodiments, the DC-DC power conversion system 1 can down-convert the input voltage Vin to generate the output voltage Vout, and the ratio of the input voltage Vin to the output voltage Vout can be greater than 2:1. For example, the ratio of the input voltage Vin to the output voltage Vout can be 4:1, and when the input voltage Vin exceeds 60V, the output voltage Vout can still be maintained below 13V.

[0018] The DC-DC power conversion system 1 includes a resonant switching capacitor converter (RSCC) 10, a controller 12, an input terminal 14, and an output terminal 16. The controller 12 can repeatedly and alternately switch the RSCC 10 between a first state and a second state. The RSCC 10 can receive an input voltage Vin and switch between the first state and the second state to generate an output voltage Vout.

[0019] RSCC 10 may include a first resonant tank 103, an output capacitor Co, a first set of switches 101, and a second set of switches 102. Input terminal 14 may receive an input voltage Vin from a front-end capacitor or front-end circuit. The first resonant tank 103 may receive the input voltage Vin from input terminal 14 and generate a sinusoidal voltage and current, achieving zero current switching of RSCC 10 and reducing power loss of RSCC 10. The first set of switches 101 may be coupled to the first resonant tank 103 and the output capacitor Co, and may receive a first control signal Sc1 to conduct in a first state and cut off in a second state. The second set of switches 102 may be coupled to the first resonant tank 103 and the output capacitor Co, and may receive a second control signal Sc2 to conduct in a second state and cut off in a first state. The first set of switches 101 and the second set of switches 102 can control the coupling relationship between the first resonant slot 103 and the output capacitor Co in the first and second states, respectively, according to the first control signal Sc1 and the second control signal Sc2, so as to generate an output voltage Vout at the output capacitor Co. In some embodiments, in the first state, the first set of switches 101 can connect the first resonant slot 103 in series between the input terminal 14 and the output capacitor Co; in the second state, the second set of switches 102 can connect the first resonant slot 103 and the output capacitor Co in parallel. The output terminal 16 can be coupled to the output capacitor Co, and can output the output voltage Vout to subsequent circuits, such as a central processing unit.

[0020] The controller 12 is coupled to the first set of switches 101 and the second set of switches 102. In steady state, it can adjust the first control signal Sc1 according to the output voltage Vout to control the first conduction time of the first set of switches 101, and adjust the second control signal Sc2 according to the output voltage Vout to control the second conduction time of the second set of switches 102, thereby generating the output voltage Vout.

[0021] Although Figure 1 This illustrates a specific connection method for RSCC 10. In some embodiments, the internal circuitry of RSCC 10 can also be connected in other ways. For example, the first resonant slot 103 can be separately coupled to the output capacitor Co, and the first set of switches 101 and the second set of switches 102 may not be directly coupled to the output capacitor Co. The coupling methods of other circuits are similar. Figure 1 same.

[0022] Figure 2 yes Figure 1 A circuit diagram of a DC-DC power conversion system 1. Figure 2The RSCC 10 provides a 4:1 voltage conversion ratio, with a rated input voltage range of 48V to 60V and an output voltage Vout maintained below 13V. The RSCC 10 includes a storage capacitor C3, a first resonant tank 103, a second resonant tank 104, an output capacitor Co, and transistors Q1 to Q10. Transistors Q1 to Q10 can be N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but are not limited to these.

[0023] The first resonant slot 103 includes a first resonant capacitor C1 and a first resonant inductor L1. The first resonant capacitor C1 has a first terminal and a second terminal. The first resonant inductor L1 has a first terminal and a second terminal, coupled to the first terminal of the output capacitor Co. The second resonant slot 104 includes a second resonant capacitor C2 and a second resonant inductor L2. The second resonant capacitor C2 has a first terminal and a second terminal. The second resonant inductor L2 has a first terminal and a second terminal, coupled to the first terminal of the output capacitor Co. The output capacitor Co has a first terminal that generates an output voltage Vout, and a second terminal that is coupled to a ground terminal. The ground terminal can provide a ground voltage Vss, for example, 0V.

[0024] Transistors Q1 through Q3, Q7, and Q8 form a first group of switches 101. Transistor Q1 has a first terminal coupled to input terminal 14; a second terminal; and a control terminal for receiving a first control signal Sc1. Transistor Q2 has a first terminal; a second terminal coupled to the first terminal of the first resonant capacitor C1; and a control terminal for receiving the first control signal Sc1. Transistor Q3 has a first terminal coupled to the second terminal of the first resonant capacitor C1; a second terminal coupled to the first terminal of the first resonant inductor L1; and a control terminal for receiving the first control signal Sc1. Transistor Q7 has a first terminal coupled to the first terminal of the second resonant inductor L2; a second terminal coupled to the first terminal of the second resonant capacitor C2; and a control terminal for receiving the first control signal Sc1. Transistor Q8 has a first terminal coupled to the second terminal of the second resonant capacitor C2; a second terminal coupled to ground; and a control terminal for receiving the first control signal Sc1.

[0025] Transistors Q4 to Q6, Q9, and Q10 can form a second set of switches 102. Transistor Q4 has a first terminal coupled to the first terminal of the second resonant capacitor C2; a second terminal coupled to the first terminal of the storage capacitor C3; and a control terminal for receiving a second control signal Sc2. Transistor Q5 has a first terminal coupled to the second terminal of the storage capacitor C3; a second terminal coupled to ground; and a control terminal for receiving the second control signal Sc2. Transistor Q6 has a first terminal coupled to the second terminal of the second resonant capacitor C2; a second terminal coupled to the first terminal of the second resonant inductor L2; and a control terminal for receiving the second control signal Sc2. Transistor Q9 has a first terminal coupled to the first terminal of the first resonant inductor L1; a second terminal coupled to the first terminal of the first resonant capacitor C1; and a control terminal for receiving the second control signal Sc2. Transistor Q10 has a first terminal coupled to the second terminal of the first resonant capacitor C1; a second terminal coupled to ground; and a control terminal for receiving the second control signal Sc2.

[0026] During operation, the first resonant slot 103 and the second resonant slot 104 provide a voltage conversion ratio of 2 to 1, the input voltage Vin can be 4 times the output voltage Vout, the voltage across the storage capacitor C2 can be 2 times the output voltage Vout, and the voltage across the first resonant capacitor C1, the second resonant capacitor C2, and the output capacitor Co can each be 1 times the output voltage Vout, so that RSCC 10 provides a voltage conversion ratio of 4 to 1.

[0027] In the first state, the first set of switches 101 and the second set of switches 102 can be configured such that the first end of the storage capacitor C3 is coupled to the input terminal 14, the first end of the first resonant capacitor C1 is coupled to the second end of the storage capacitor C3, the second end of the first resonant capacitor C1 is coupled to the first end of the second resonant capacitor C2 and the first end of the output capacitor Co, the second end of the second resonant capacitor C2 and the second end of the output capacitor Co are coupled to the ground terminal, the first resonant capacitor C1 can charge the output capacitor Co, and the second resonant capacitor C2 can discharge the output capacitor Co.

[0028] In the second state, the first set of switches 101 and the second set of switches 102 can be configured such that the first terminal of the output capacitor Co is coupled to the first terminal of the first resonant capacitor C1 and the second terminal of the second resonant capacitor C2, the first terminal of the storage capacitor C3 is coupled to the first terminal of the second resonant capacitor C2, and the second terminal of the storage capacitor C3 is coupled to the ground terminal. The first resonant capacitor C1 can discharge the output capacitor Co, and the second resonant capacitor C2 can charge the output capacitor Co.

[0029] RSCC 10 can alternate between a first state and a second state to continuously charge and discharge all capacitors within RSCC 10 to maintain charge balance, while simultaneously transferring power from input terminal 14 to output terminal 16 to generate output voltage Vout. To achieve charge balance among all capacitors within RSCC 10, controller 12 can adjust the first control signal Sc1 and the second control signal Sc2 to have equal operating cycles, so that the first resonant slot 103 and the second resonant slot 104 generate sinusoidal currents Io1 and Io2 with opposite phases and the same average magnitude, respectively. In both the first and second states, currents Io1 and Io2 are half (Io / 2) of the output current Io of RSCC 10.

[0030] The controller 12 can adjust the first control signal Sc1 according to the output voltage Vout to control the first on-time and first off-time of the first group of switches 101, and adjust the second control signal Sc2 according to the output voltage Vout to control the second on-time and second off-time of the second group of switches 102. For example, when the output voltage Vout is less than the upper limit of the output voltage (e.g., 13V), the controller 12 can adjust the first control signal Sc1 to be close to 50% of the duty cycle, so that the first on-time of the first group of switches 101 is substantially equal to the first off-time of the first group of switches 101, and adjust the second control signal Sc2 to be close to 50% of the duty cycle, so that the second on-time of the second group of switches 102 is substantially equal to the second off-time of the second group of switches 102, thereby generating 1 / 4 of the input voltage Vin as the output voltage Vout. When the output voltage Vout exceeds the upper limit of the output voltage, the controller 12 can adjust the first control signal Sc1 to less than 50% of the duty cycle to make the first on-time of the first group of switches 101 less than the first off-time of the first group of switches 101, and adjust the second control signal Sc2 to less than 50% of the duty cycle to make the second on-time of the second group of switches 102 less than the second off-time of the second group of switches 102, thereby regulating the output voltage Vout within the upper limit of the output voltage to provide overvoltage protection. When the output voltage Vout is much higher than 13V, the controller 12 can adjust the first control signal Sc1 and the second control signal Sc2 to close to 0% of the duty cycle to turn off RSCC10 and provide overvoltage protection. The first on-time and the second on-time are non-overlapping, and the length of the first on-time can be equal to the length of the second on-time, and the length of the first off-time can be equal to the length of the second off-time.

[0031] In some embodiments, during power-on, the first conduction time and the second conduction time may be equal to a preset conduction time, and gradually increased from the preset conduction time to the conduction time in steady state. The preset conduction time may be much less than 50% of the duty cycle of the first control signal Sc1 and the second control signal Sc2. For example, the preset conduction time may be equal to 0% of the duty cycle of the first control signal Sc1 and the second control signal Sc2. During power-on, the input voltage Vin may experience a surge due to the switching of the power switch. The controller 12 may gradually adjust the first control signal Sc1 and the second control signal Sc2 from 0% duty cycle (preset conduction time) to 48% duty cycle (conduction time in steady state) to stabilize the DC-DC power conversion system 1 and prevent it from being affected by the input voltage Vin during power-on.

[0032] The DC-DC power conversion system 1 adjusts the first control signal Sc1 and the second control signal Sc2 according to the output voltage Vout to regulate the output voltage Vout, providing overvoltage protection without significantly increasing the circuit area.

[0033] Figure 3 This is a flowchart of a power conversion method 300 in a DC-DC power conversion system 1. The power conversion method 300 includes steps S302 to S308 for adjusting the output voltage Vout. Any reasonable technical modifications or adjustments to the steps are within the scope of this invention. Steps S302 to S308 are described below:

[0034] Step S302: RSCC 10 switches between the first state and the second state to generate the output voltage Vout;

[0035] Step S304: The controller 12 adjusts the first control signal Sc1 and the second control signal Sc2 according to the output voltage Vout;

[0036] Step S306: The first group of switches 101 receives the first control signal Sc1 to conduct for a first conduction time in the first state;

[0037] Step S308: The second group of switches 102 receives the second control signal Sc2 and conducts the second conduction time in the second state.

[0038] A detailed description of the power conversion method 300 can be found in the preceding paragraphs and will not be repeated here.

[0039] Figure 4This is a circuit diagram of a controller 12. The controller 12 includes a voltage divider 120, a first comparator circuit 121, a second comparator circuit 122, a first AND gate 123, a flip-flop 124, a second AND gate 125, and a third AND gate 126. The voltage divider 120 is coupled to the first terminal of the output capacitor Co. The first comparator circuit 121 is coupled to the voltage divider 120. The second comparator circuit 122 is coupled to the first comparator circuit 121. The first AND gate 123 is coupled to the second comparator circuit 122. The flip-flop 124 is coupled to the first AND gate 123. The second AND gate 125 and the third AND gate 126 are coupled to the flip-flop 124.

[0040] Voltage divider 120 receives the output voltage Vout from the first terminal of the output capacitor Co to generate a divided voltage Vd of the output voltage Vout. Voltage divider 120 may include resistors Rd1 and Rd2. Resistor Rd1 includes a first terminal coupled to the first terminal of the output capacitor Co; and a second terminal. Resistor Rd2 includes a first terminal coupled to the second terminal of resistor Rd1 to provide the divided voltage Vd; and a second terminal coupled to ground.

[0041] A first comparator circuit 121 compares a voltage divider Vd with a reference voltage Vref to generate a first comparator voltage Va. The reference voltage Vref may correspond to the upper limit of the output voltage Vout. The reference voltage Vref may be a fixed voltage level. Increasing the reference voltage Vref increases the upper limit of the output voltage. The first comparator circuit 121 may include a comparator 1210 and a capacitor Cc. The comparator 1210 includes a positive input for receiving the reference voltage Vref; an inverting input, coupled to the second end of a resistor Rd1, for receiving the voltage divider Vd; and an output for outputting a comparison current based on the difference between the reference voltage Vref and the voltage divider Vd. The comparator 1210 may have a gain gm. The comparison current may be positively correlated with the difference between the reference voltage Vref and the voltage divider Vd. The capacitor Cc includes a first end, coupled to the output of the comparator 1210; and a second end, coupled to ground. The comparison current charges the capacitor Cc to generate the first comparator voltage Va. When the voltage divider Vd is less than the reference voltage Vref, the difference between the reference voltage Vref and the voltage divider Vd is positive, and the first comparison voltage Va is larger; when the voltage divider Vd exceeds the reference voltage Vref, the difference between the reference voltage Vref and the voltage divider Vd is negative, and the first comparison voltage Va is smaller.

[0042] The second comparator circuit 122 compares the first comparison voltage Va and the ramp voltage Vramp to generate a second comparison voltage Vc. The ramp voltage Vramp can be a sawtooth wave, generated by an external signal generator based on a clock signal CLK. The period of the sawtooth wave and the period of the clock signal CLK can be the same. The second comparator circuit 122 includes a positive input terminal coupled to the first end of capacitor Cc for receiving the first comparison voltage Va; an inverting input terminal for receiving the ramp voltage Vramp; and an output terminal for outputting the second comparison voltage Vc based on the difference between the first comparison voltage Va and the ramp voltage Vramp. When the ramp voltage Vramp is less than the first comparison voltage Va, the second comparison voltage Vc can be at a logic high level; when the ramp voltage Vramp exceeds the first comparison voltage Va, the second comparison voltage Vc can be at a logic low level.

[0043] The first AND gate 123 performs an AND operation on the second comparison voltage Vc and the clock signal CLK to generate a control signal Vb. The first AND gate 123 may include a first input terminal coupled to the output terminal of the second comparison circuit 122 for receiving the second comparison voltage Vc; a second input terminal for receiving the clock signal CLK; and an output terminal for outputting the control signal Vb. The frequency of the clock signal CLK may be positively correlated with the switching frequencies of the first group of switches 101 and the second group of switches 102. For example, half the frequency of the clock signal CLK may be the switching frequency of the first group of switches 101 and the second group of switches 102. If the output voltage Vout exceeds the upper limit of the output voltage, the waveforms of the control signal Vb and the second comparison voltage Vc may be the same. If the output voltage Vout is less than the upper limit of the output voltage, the waveforms of the control signal Vb and the clock signal CLK may be the same.

[0044] Flip-flop 124 generates an output signal Sq and an inverted output signal Sqb based on the control signal Vb. The output signal Sq and the inverted output signal Sqb are inverses of each other. Flip-flop 124 can be a JK flip-flop, including a J input for receiving a logic high level SH; a K input for receiving a logic high level SH; a clock input ck, coupled to the output of the first AND gate 123, for receiving the control signal Vb; an output Q for outputting the output signal Sq; and an inverted output ˉQ for outputting the inverted signal Sqb. Flip-flop 124 can toggle the output signal Sq and the inverted output signal Sqb in reverse at each rising edge of the control signal Vb.

[0045] The second AND gate 125 performs an AND operation on the control signal Vb and the output signal Sq to generate the first control signal Sc1. The third AND gate 126 performs an AND operation on the control signal Vb and the inverted output signal Sqb to generate the second control signal Sc2.

[0046] The following combinations Figure 5 To explain Figure 4 The operation of controller 12. Figure 5 yes Figure 4 The waveform of controller 12 when the voltage divider Vd exceeds the reference voltage Vref is shown, where the horizontal axis represents time and the vertical axis represents the signal magnitude.

[0047] Between times t1 and t2, the ramp voltage Vramp is less than the first comparison voltage Va, and the control signal Vb is at a logic high level. Flip-flop 124 can output a logic high level as the control signal Vb and a logic low level as the inverted output signal Sqb. Therefore, the second AND gate 125 performs an AND operation on the control signal Vb and the output signal Sqb to generate a logic high level as the first control signal Sc1, and the third AND gate 126 performs an AND operation on the control signal Vb and the inverted output signal Sqb to generate a logic low level as the second control signal Sc2. Time t1 to t2 can be the first on-time of the first group of switches 101, denoted by time period Td1. When the output voltage Vout exceeds the upper limit of the output voltage, the length of time period Td1 can be shortened as the output voltage Vout exceeds the upper limit of the output voltage.

[0048] Between times t2 and t4, the ramp voltage Vramp exceeds the first comparison voltage Va, and the control signal Vb is at a logic low level. Flip-flop 124 maintains the control signal Vb at a logic high level and the inverted output signal Sqb at a logic low level. Therefore, the second AND gate 125 performs an AND operation on the control signal Vb and the output signal Sqb to generate a logic low level as the first control signal Sc1, and the third AND gate 126 performs an AND operation on the control signal Vb and the inverted output signal Sqb to generate a logic low level as the second control signal Sc2.

[0049] Between times t4 and t5, the ramp voltage Vramp is less than the first comparison voltage Va, and the control signal Vb is at a logic high level. Flip-flop 124 switches the control signal Vb to a logic low level and the inverted output signal Sqb to a logic high level at the rising edge of Vb. Therefore, the second AND gate 125 performs an AND operation on the control signal Vb and the output signal Sqb to generate a logic low level as the first control signal Sc1, and the third AND gate 126 performs an AND operation on the control signal Vb and the inverted output signal Sqb to generate a logic high level as the second control signal Sc2. Time t4 to t5 can be the second on-time of the second set of switches 102, denoted as time period Td3. When the output voltage Vout exceeds the upper limit of the output voltage, the length of time period Td3 can be shortened as the output voltage Vout exceeds the upper limit of the output voltage. The lengths of time period Td3 and time period Td1 can be equal.

[0050] Between times t5 and t7, the ramp voltage Vramp exceeds the first comparison voltage Va, and the control signal Vb is at a logic low level. Flip-flop 124 maintains the control signal Vb at a logic low level and the inverted output signal Sqb at a logic high level. Therefore, the second AND gate 125 performs an AND operation on the control signal Vb and the output signal Sqb to generate a logic low level as the first control signal Sc1, and the third AND gate 126 performs an AND operation on the control signal Vb and the inverted output signal Sqb to generate a logic low level as the second control signal Sc2. Time t2 to t7 can be the first cutoff time of the first group of switches 101.

[0051] Controller 12 can switch the second control signal Sc2 to logic high again at time t8 in the same manner. Time t5 to t8 can be the second cutoff time of the second group of switches 102.

[0052] If the output voltage Vout is less than the upper limit of the output voltage, the voltage divider Vd will be less than the reference voltage Vref, the first comparison voltage Va will be greater than the maximum value of the ramp voltage Vramp, the control signal Vc will remain at a logic high level, the second comparison voltage Vc will remain at a logic high level, and the waveform of the control signal Vb will be the same as the waveform of the clock signal CLK. The first control signal Sc1 is at a logic high level between times t1 and t3, and at a logic low level between times t3 and t4. The second control signal Sc2 is at a logic high level between times t4 and t6, and at a logic low level between times t6 and t7. Between times t3 and t4 and between times t6 and t7, the first control signal Sc1 and the second control signal Sc2 are forced to a logic low level to ensure that the first set of switches 101 and the second set of switches 102 will not be turned on simultaneously. Time t3 to t4 is represented by the time period Td2.

[0053] Figure 6 yes Figure 1 The first control signal Sc1 and the second control signal Sc2 of the DC-DC power conversion system are essentially analog waveforms at 50% duty cycle. Figure 7 yes Figure 1 The first control signal Sc1 and the second control signal Sc2 of the DC-DC power conversion system are essentially simulated waveforms at 25% duty cycle. The simulation environment in Figures 6 and 7 is... Figure 2 The DC-DC power conversion system 1 has an input voltage Vin of 48V, a capacitance of 4uF for the first resonant capacitor C1 and the second resonant capacitor C2, a capacitance of 100uF for the storage capacitor C3, an inductance of 25nH for the first resonant inductor L1 and the second resonant inductor L2, and a switching frequency of 500kHz for the first set of switches 101 and the second set of switches 102.

[0054] When both the first control signal Sc1 and the second control signal Sc2 are essentially at 50% of their operating cycle, Figure 6 The waveform diagram shows that the output voltage Vout oscillates around 12V, approximately equal to 1 / 4 of the input voltage Vin, with a ripple of about 0.02V (peak-to-peak). The output current Io is a sinusoidal current. The voltages across the first resonant capacitor C1 (VC1) and the second resonant capacitor C2 (VC2) are complete sinusoidal voltages and are opposite in direction to each other. Currents Io1 and Io2 are also complete sinusoidal currents and are opposite in direction to each other. Between times t1 and t2, current Io1 charges the output capacitor Co and current Io2 discharges the output capacitor Co to generate the output voltage Vout. Between times t2 and t3, current Io1 discharges the output capacitor Co and current Io2 charges the output capacitor Co to generate the output voltage Vout.

[0055] When both the first control signal Sc1 and the second control signal Sc2 are essentially at 25% of their duty cycle, Figure 7 The waveform diagram shows that the output voltage Vout oscillates around 11.7V, and is less than 1 / 4 of the input voltage Vin. The voltage across the first resonant capacitor C1 (VC1) and the voltage across the second resonant capacitor C2 (VC2) are both partially sinusoidal and partially square wave voltages, respectively, and are in opposite directions. The currents Io1 and Io2 are partially sinusoidal currents and are also in opposite directions. Between times t1 and t2, current Io1 charges the output capacitor Co and current Io2 discharges the output capacitor Co to generate the output voltage Vout. Between times t2 and t3, currents Io1 and Io2 are both 0A. Between times t3 and t4, current Io1 discharges the output capacitor Co and current Io2 charges the output capacitor Co to generate the output voltage Vout. Between times t4 and t5, currents Io1 and Io2 are both 0A. Since currents Io1 and Io2 are partially sinusoidal currents, they only partially charge and discharge the output capacitor Co, thus generating an output voltage Vout that is less than 1 / 4 of the input voltage Vin.

[0056] Figure 8 This is a circuit diagram of another type of resonant switching capacitor converter 10. Figure 8 and Figure 2 The difference between the resonant switching capacitor converter 10 and the other is that... Figure 8 The first resonant capacitor C1 and the first resonant inductor L1 are directly coupled to each other, and the second resonant capacitor C2 and the second resonant inductor L2 are directly coupled to each other. The first resonant inductor L1 and the second resonant inductor L2 are not directly coupled to the output capacitor Co. Figure 8 The resonant switching capacitor converter 10 can be replaced Figure 2 The resonant switching capacitor converter 10.

[0057] The first resonant slot 103 includes a first resonant capacitor C1 and a first resonant inductor L1. The first resonant capacitor C1 has a first terminal and a second terminal. The first resonant inductor L1 is coupled to the second terminal of the first resonant capacitor C1. The second resonant slot 104 includes a second resonant capacitor C2 and a second resonant inductor L2. The second resonant capacitor C2 has a first terminal and is coupled to the second terminal of the second resonant capacitor C2. The output capacitor Co has a first terminal that generates an output voltage Vout and a second terminal that is coupled to ground.

[0058] Transistors Q1 through Q3, Q7, and Q8 form a first group of switches 101. Transistor Q1 has a first terminal coupled to input terminal 14; a second terminal coupled to the first terminal of storage capacitor C3; and a control terminal for receiving a first control signal Sc1. Transistor Q2 has a first terminal coupled to the second terminal of storage capacitor C3; a second terminal coupled to the first terminal of first resonant capacitor C1; and a control terminal for receiving the first control signal Sc1. Transistor Q3 has a first terminal coupled to the second terminal of first resonant inductor L1; a second terminal coupled to the first terminal of output capacitor Co; and a control terminal for receiving the first control signal Sc1. Transistor Q7 has a first terminal coupled to the first terminal of output capacitor Co; a second terminal coupled to the first terminal of second resonant capacitor C2; and a control terminal for receiving the first control signal Sc1. Transistor Q8 has a first terminal coupled to the second terminal of second resonant inductor L2; a second terminal coupled to ground; and a control terminal for receiving the first control signal Sc1.

[0059] Transistors Q4 to Q6, Q9, and Q10 can form a second set of switches 102. Transistor Q4 has a first terminal coupled to the first terminal of the second resonant capacitor C2; a second terminal coupled to the first terminal of the storage capacitor C3; and a control terminal for receiving a second control signal Sc2. Transistor Q5 has a first terminal coupled to the second terminal of the storage capacitor C3; a second terminal coupled to ground; and a control terminal for receiving the second control signal Sc2. Transistor Q6 has a first terminal coupled to the second terminal of the second resonant inductor L2; a second terminal coupled to the first terminal of the output capacitor Co; and a control terminal for receiving the second control signal Sc2. Transistor Q9 has a first terminal coupled to the first terminal of the output capacitor Co; a second terminal coupled to the first terminal of the first resonant capacitor C1; and a control terminal for receiving the second control signal Sc2. Transistor Q10 has a first terminal coupled to the second terminal of the first resonant inductor L1; a second terminal coupled to ground; and a control terminal for receiving the second control signal Sc2.

[0060] Figure 8 and Figure 2The operation of the resonant switching capacitor converter 10 is similar, and its description can be found in the previous paragraphs, so it will not be repeated here.

[0061] Figure 9 This is a circuit diagram of another resonant switching capacitor converter 10, which can be replaced. Figure 2 The resonant switching capacitor converter 10. Figure 9 The RSCC 10 may include a first resonant trench 103, a second resonant trench 104, a storage capacitor C92, an output capacitor Co, and transistors Q91 to Q910. Transistors Q91 to Q910 may be N-type MOSFETs, but are not limited thereto.

[0062] The first resonant slot 103 includes a first resonant capacitor C91 and a first resonant inductor L91. The first resonant capacitor C91 has a first terminal and a second terminal. The first resonant inductor L91 has a first terminal coupled to the second terminal of the first resonant capacitor C91; and a second terminal coupled to ground. The storage capacitor C92 has a first terminal and a second terminal. The second resonant slot 104 includes a second resonant capacitor C93 and a second resonant inductor L92. The second resonant capacitor C92 has a first terminal and a second terminal. The second resonant inductor L92 has a first terminal coupled to the second terminal of the second resonant capacitor C92; and a second terminal. The output capacitor Co has a first terminal that generates an output voltage Vout; and a second terminal.

[0063] Transistors Q91, Q93, Q95, Q98, and Q99 form a first set of switches 101. Transistor Q91 has a first terminal coupled to input terminal 14; a second terminal coupled to the first terminal of the second resonant capacitor C93; and a control terminal for receiving a first control signal Sc1. Transistor Q93 has a first terminal coupled to the first terminal of storage capacitor C92; a second terminal coupled to the first terminal of the first resonant capacitor C91; and a control terminal for receiving the first control signal Sc1. Transistor Q95 has a first terminal coupled to the second terminal of the second resonant inductor L92; a second terminal coupled to the first terminal of output capacitor Co; and a control terminal for receiving the first control signal Sc1. Transistor Q98 has a first terminal coupled to the second terminal of storage capacitor C92; a second terminal coupled to ground; and a control terminal for receiving the first control signal Sc1. Transistor Q99 has a first terminal coupled to the second terminal of the first resonant inductor L91; a second terminal coupled to the first terminal of the output capacitor Co; and a control terminal for receiving the first control signal Sc1.

[0064] Transistors Q92, Q94, Q96, Q97, and Q910 can form a second set of switches 102. Transistor Q92 has a first terminal coupled to the first terminal of the second resonant capacitor C93; a second terminal coupled to the first terminal of the storage capacitor C92; and a control terminal for receiving a second control signal Sc2. Transistor Q94 has a first terminal coupled to the first terminal of the first resonant capacitor C91; a second terminal coupled to the first terminal of the output capacitor Co; and a control terminal for receiving the second control signal Sc2. Transistor Q96 has a first terminal coupled to the second terminal of the second resonant inductor L92; a second terminal coupled to ground; and a control terminal for receiving the second control signal Sc2. Transistor Q97 has a first terminal coupled to the second terminal of the storage capacitor C92; a second terminal coupled to the first terminal of the output capacitor Co; and a control terminal for receiving the second control signal Sc2. Transistor Q910 has a first terminal coupled to the second terminal of the first resonant inductor L91; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal Sc2.

[0065] During operation, the first resonant tank 103 and the second resonant tank 104 each provide a voltage conversion ratio of 2:1, and the storage capacitor C92 provides a voltage conversion ratio of 1:1, resulting in RSCC 10 providing a voltage conversion ratio of 4:1. The voltage across the second resonant capacitor C93 can be 3 times the output voltage Vout, the voltage across the storage capacitor C can be 2 times the output voltage Vout, and the voltage across the first resonant capacitor C91 and the output capacitor C0 can each be 1 times the output voltage Vout. In some embodiments, the storage capacitor C92 can also be connected in series with an inductor to form another resonant tank.

[0066] In the first state, the first set of switches 101 and the second set of switches 102 can be configured such that the first end of the second resonant capacitor C93 is coupled to the input terminal 14, the first end of the second resonant inductor L92 is coupled to the second end of the second resonant capacitor C93, the second end of the first resonant inductor L91 is coupled to the second end of the second resonant inductor L92, the second end of the first resonant capacitor C91 is coupled to the first end of the first resonant inductor L91, the first end of the storage capacitor C92 is coupled to the first end of the first resonant capacitor C91, the second end of the storage capacitor C92 is coupled to the ground terminal, the first end of the output capacitor Co is coupled to the second ends of the first resonant inductor L91 and the second end of the second resonant inductor L92, and the second end of the output capacitor Co is coupled to the ground terminal. The second resonant capacitor C93 and the output capacitor Co can be charged, and the storage capacitor C92 can discharge the first resonant capacitor C91 and the output capacitor Co.

[0067] In the second state, the first set of switches 101 and the second set of switches 102 can be configured such that the first terminal of the output capacitor Co is coupled to the first terminal of the first resonant capacitor C91 and the second terminal of the storage capacitor C92, the second terminal of the output capacitor Co is coupled to the ground terminal, the first terminal of the first resonant inductor L91 is coupled to the second terminal of the first resonant capacitor C91, the second terminal of the first resonant inductor L91 is coupled to the ground terminal, the first terminal of the second resonant capacitor C93 is coupled to the first terminal of the storage capacitor C92, the first terminal of the second resonant inductor L92 is coupled to the second terminal of the second resonant capacitor C93, and the second terminal of the first resonant inductor L91 is coupled to the ground terminal. The first resonant capacitor C91 can discharge the output capacitor Co, and the second resonant capacitor C93 can discharge both the storage capacitor C92 and the output capacitor Co.

[0068] RSCC 10 can switch between a first state and a second state to continuously charge and discharge all capacitors within RSCC 10 to maintain charge balance, while transferring power from input 14 to output 16 to generate output voltage Vout.

[0069] Figure 10 yes Figure 1 A circuit diagram of another resonant switching capacitor converter. Figure 10 The resonant switching capacitor converter 10 can be replaced Figure 2 The resonant switching capacitor converter 10. Figure 10 The RSCC 10 may include a first resonant slot 103, a second resonant capacitor C102, a third resonant capacitor C103, an output capacitor Co, and transistors Q101 to Q1010. Transistors Q101 to Q1010 may be N-type MOSFETs, but are not limited thereto.

[0070] The second resonant capacitor C102 has a first terminal and a second terminal. The third resonant capacitor C103 has a first terminal and a second terminal. The first resonant slot 103 includes a first resonant capacitor C101 and a first resonant inductor L101. The first resonant capacitor C101 has a first terminal and a second terminal. The first resonant inductor L101 has a first terminal and a second terminal, coupled to the first terminal of the output capacitor Co. The output capacitor Co has a first terminal, which can generate an output voltage Vout, and a second terminal, coupled to a ground terminal. The third resonant capacitor C103 has a first terminal and a second terminal. The second resonant capacitor C102 has a first terminal and a second terminal.

[0071] Transistors Q101 to Q104 form a first group of switches 101. Transistor Q101 has a first terminal coupled to input terminal 14; a second terminal coupled to the first terminal of the third resonant capacitor C103; and a control terminal for receiving a first control signal Sc1. Transistor Q102 has a first terminal coupled to the second terminal of the third resonant capacitor C103; a second terminal coupled to the first terminal of the second resonant capacitor C102; and a control terminal for receiving the first control signal Sc1. Transistor Q103 has a first terminal coupled to the second terminal of the second resonant capacitor C102; a second terminal coupled to the first terminal of the first resonant capacitor C101; and a control terminal for receiving the first control signal Sc1. Transistor Q104 has a first terminal coupled to the second terminal of the first resonant capacitor C101; a second terminal coupled to the first terminal of the first resonant inductor L101; and a control terminal for receiving the first control signal Sc1.

[0072] Transistors Q105 to Q1010 can form a second set of switches 102. Transistor Q105 has a first terminal coupled to a first terminal of a second resonant inductor L102; a second terminal coupled to a first terminal of a third resonant capacitor C103; and a control terminal for receiving a second control signal Sc2. Transistor Q106 has a first terminal coupled to a first terminal of a second resonant inductor L102; a second terminal coupled to a first terminal of a second resonant capacitor C102; and a control terminal for receiving the second control signal Sc2. Transistor Q107 has a first terminal coupled to a first terminal of a second resonant inductor L102; a second terminal coupled to a first terminal of a first resonant capacitor C101; and a control terminal for receiving the second control signal Sc2. Transistor Q108 has a first terminal coupled to a second terminal of a third resonant capacitor C103; a second terminal coupled to a ground terminal; and a control terminal for receiving the second control signal Sc2. Transistor Q109 has a first terminal coupled to the second terminal of the second resonant capacitor C102; a second terminal coupled to ground; and a control terminal for receiving a second control signal Sc2. Transistor Q1010 has a first terminal coupled to the second terminal of the first resonant capacitor C101; a second terminal coupled to ground; and a control terminal for receiving a second control signal Sc2.

[0073] During operation, the input voltage Vin can be 4 times the output voltage Vout, and the voltage across the third resonant capacitor C103, the second resonant capacitor C102, the first resonant capacitor C101 and the output capacitor Co can each be 1 times the output voltage Vout, so that RSCC 10 provides a 4:1 voltage conversion ratio.

[0074] In the first state, the first set of switches 101 and the second set of switches 102 can be connected in series between the input terminal 14 and the ground terminal, consisting of the third resonant capacitor C103, the second resonant capacitor C102, the first resonant capacitor C101, the first resonant inductor L101, and the output capacitor Co. The first resonant capacitor C101 can charge the output capacitor Co.

[0075] In the second state, the first set of switches 101 and the second set of switches 102 can be connected in parallel with the output capacitor Co, and in series with the first resonant inductor L101 and in parallel with the first resonant capacitor C101, the second resonant capacitor C102, and the third resonant capacitor C103 between the output terminal 16 and the ground terminal. The first resonant capacitor C101, the second resonant capacitor C102, and the third resonant capacitor C103 can discharge the output capacitor Co. The RSCC 10 can alternate between the first state and the second state to continuously charge and discharge all the capacitors in the RSCC 10 to maintain charge balance, while transferring power from the input terminal 14 to the output terminal 16 to generate the output voltage Vout.

[0076] This invention is not limited to RSCC with a 4:1 conversion voltage ratio. Those skilled in the art can also replace the RSCC in the embodiments of this invention with RSCCs with other conversion voltage ratios or other forms of switched-capacitor converters (SCCs) in accordance with the spirit of this invention.

[0077] Figure 1 , 2 The embodiments of 4, 8-10 adjust the first control signal Sc1 and the second control signal Sc2 according to the output voltage Vout to regulate the output voltage Vout, providing overvoltage protection without significantly increasing the circuit area.

[0078] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

[0079] [Symbol Explanation]

[0080] 1: DC-DC power conversion system

[0081] 10. RSCC: Resonant Switching Capacitor Converter

[0082] 101: First set of switches

[0083] 102: Second set of switches

[0084] 103: First Resonance Groove

[0085] 104: Second Resonance Groove

[0086] 12: Controller

[0087] 120: Voltage divider

[0088] 121: First Comparator Circuit

[0089] 1210: Comparator

[0090] 122: Second Comparator Circuit

[0091] 123: The First and the Door

[0092] 124: Trigger

[0093] 125: The Second Gate

[0094] 126: The Third and the Gate

[0095] 14: Input end

[0096] 16: Output terminal

[0097] 300: Power Conversion Method

[0098] S302 to S308: Steps

[0099] A: Ampere

[0100] Cc: Capacitor

[0101] CLK: Clock signal

[0102] ck: Clock input terminal

[0103] Co: Output capacitor

[0104] C1 to C3, C91 to C93, C101 to C103: Capacitors

[0105] gm: gain

[0106] Io: Output current

[0107] Io1, Io2: Current

[0108] J, K: Input terminals

[0109] L1, L2, L91, L92, L101, L102: Inductors

[0110] Q,ˉQ: Output terminal

[0111] Q1 to Q10, Q91 to Q910, Q101 to Q1010: Transistors

[0112] Rd1, Rd2: Resistors

[0113] Sc1: First control signal

[0114] Sc2: Second control signal

[0115] SH: High level of logic

[0116] Sq: Output signal

[0117] Sqb: Inverted output signal

[0118] t1 to t8: Time

[0119] Td1 to Td3: Time period

[0120] V: Volt

[0121] Va: First comparison voltage

[0122] Vb: Control signal

[0123] Vc is the second comparison voltage.

[0124] VC1, VC2: Transvoltage

[0125] Vd: Voltage divider

[0126] Vin: Input voltage

[0127] Vramp: Ramp voltage

[0128] Vref: Reference voltage

[0129] Vss: Grounding voltage

[0130] Vout: Output voltage

Claims

1. A DC-DC power conversion system, comprising: The input terminal is used to receive the input voltage. A resonant switching capacitor converter is used to receive the input voltage and switch between a first state and a second state to generate an output voltage. The resonant switching capacitor converter includes: First resonance groove; An output capacitor, having a first terminal, is used to generate the output voltage; The second end is coupled to the grounding end; A first set of switches, coupled to the first resonant slot and the output capacitor, is used to receive a first control signal to turn on in the first state and turn off in the second state; and The second set of switches is coupled to the first resonant slot and the output capacitor to receive a second control signal to turn on in the second state and turn off in the first state. The output terminal is coupled to the output capacitor and is used to output the output voltage; and A controller, coupled to the first group of switches and the second group of switches, is used to adjust the first control signal according to the output voltage to control the first on-time of the first group of switches, and to adjust the second control signal according to the output voltage to control the second on-time of the second group of switches; The controller includes: A voltage divider, coupled to the first terminal of the output capacitor, is used to generate a voltage divider of the output voltage. A first comparator circuit, coupled to the voltage divider, is used to compare the divided voltage with a reference voltage to generate a first comparison voltage; The second comparator circuit is coupled to the first comparator circuit and is used to compare the first comparison voltage and the ramp voltage to generate the second comparison voltage. The first AND gate is coupled to the second comparator circuit and is used to perform an AND operation on the second comparison voltage and the clock signal to generate a control signal. A trigger, coupled to the first AND gate, is used to generate an output signal and an inverted output signal according to the control signal; A second AND gate, coupled to the flip-flop, is used to perform an AND operation on the control signal and the output signal to generate the first control signal; and The third AND gate, coupled to the flip-flop, is used to perform an AND operation on the control signal and the inverted output signal to generate the second control signal.

2. The DC-DC power conversion system according to claim 1, wherein in the first state, the first set of switches is used to connect the first resonant slot in series between the input terminal and the output capacitor.

3. The DC-DC power conversion system according to claim 1, wherein in the second state, the second set of switches is used to connect the first resonant slot and the output capacitor in parallel.

4. The DC-DC power conversion system according to claim 1, wherein the controller is configured to alternately switch the resonant switching capacitor converter between the first state and the second state.

5. The DC-DC power conversion system according to claim 1, wherein the first turn-on time is less than the first cut-off time of the first set of switches, and the second turn-on time is less than the second cut-off time of the second set of switches.

6. The DC-DC power conversion system of claim 1, wherein the length of the first conduction time is equal to the length of the second conduction time.

7. The DC-DC power conversion system according to claim 1, wherein... The first resonant groove includes: A first resonant capacitor has a first terminal and a second terminal; and A first resonant inductor has a first terminal and a second terminal coupled to the first terminal of the output capacitor; The resonant switching capacitor converter also includes a second resonant slot, which contains: The second resonant capacitor has a first terminal and a second terminal; and The second resonant inductor has a first terminal and a second terminal coupled to the first terminal of the output capacitor; The first set of switches includes: A first transistor has a first terminal; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the first control signal. The second transistor has a first terminal coupled to the second terminal of the first resonant capacitor; a second terminal coupled to the first terminal of the first resonant inductor; and a control terminal for receiving the first control signal. The third transistor has a first terminal coupled to the first terminal of the second resonant inductor; a second terminal coupled to the first terminal of the second resonant capacitor; and a control terminal for receiving the first control signal. and A fourth transistor has a first terminal coupled to the second terminal of the second resonant capacitor; a second terminal coupled to the ground terminal; and a control terminal for receiving the first control signal; and The second set of switches includes: The fifth transistor has a first terminal coupled to the first terminal of the first resonant inductor; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the second control signal. The sixth transistor has a first terminal coupled to the second terminal of the first resonant capacitor; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal. The seventh transistor has a first terminal coupled to the first terminal of the second resonant capacitor; a second terminal; and a control terminal for receiving the second control signal. and The eighth transistor has a first terminal coupled to the second terminal of the second resonant capacitor; a second terminal coupled to the first terminal of the second resonant inductor; and a control terminal for receiving the second control signal.

8. The DC-DC power conversion system according to claim 1, wherein... The first resonant groove includes: A first resonant capacitor has a first terminal and a second terminal; and A first resonant inductor has a first terminal coupled to the second terminal of the first resonant capacitor; and a second terminal; The resonant switching capacitor converter also includes a second resonant slot, which contains: The second resonant capacitor has a first terminal and a second terminal; and The second resonant inductor has a first terminal coupled to the second terminal of the second resonant capacitor; and a second terminal; The first set of switches includes: A first transistor has a first terminal; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the first control signal. The second transistor has a first terminal coupled to the second terminal of the first resonant inductor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the first control signal. The third transistor has a first terminal coupled to the first terminal of the output capacitor; a second terminal coupled to the first terminal of the second resonant capacitor; and a control terminal for receiving the first control signal. and A fourth transistor has a first terminal coupled to the second terminal of the second resonant inductor; a second terminal coupled to the ground terminal; and a control terminal for receiving the first control signal; and The second set of switches includes: The fifth transistor has a first terminal coupled to the first terminal of the output capacitor; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the second control signal. The sixth transistor has a first terminal coupled to the second terminal of the first resonant inductor; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal. The seventh transistor has a first terminal coupled to the first terminal of the second resonant capacitor; a second terminal; and a control terminal for receiving the second control signal. and The eighth transistor has a first terminal coupled to the second terminal of the second resonant inductor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the second control signal.

9. The DC-DC power conversion system according to claim 1, wherein... The first resonant groove includes: A first resonant capacitor has a first terminal and a second terminal; and A first resonant inductor has a first terminal coupled to the second terminal of the first resonant capacitor; and a second terminal; The resonant switching capacitor converter also includes a storage capacitor, having a first terminal and a second terminal; The first set of switches includes: A first transistor has a first terminal coupled to the first terminal of the storage capacitor; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the first control signal. The second transistor has a first terminal coupled to the second terminal of the first resonant inductor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the first control signal. and The third transistor has a first terminal coupled to the second terminal of the storage capacitor; a second terminal coupled to the ground terminal; and a control terminal for receiving the first control signal. and The second set of switches includes: The fifth transistor has a first terminal coupled to the first terminal of the first resonant capacitor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the second control signal. The sixth transistor has a first terminal coupled to the second terminal of the first resonant inductor; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal. The seventh transistor has a first terminal; a second terminal coupled to the first terminal of the storage capacitor; and a control terminal for receiving the second control signal. and The eighth transistor has a first terminal coupled to the second terminal of the storage capacitor; a second terminal coupled to the first terminal of the output capacitor; and a control terminal for receiving the second control signal.

10. The DC-DC power conversion system according to claim 1, wherein... The first resonant groove includes: A first resonant capacitor has a first terminal and a second terminal; and A first resonant inductor has a first terminal and a second terminal coupled to the first terminal of the output capacitor; This resonant switching capacitor converter also includes: The second resonant capacitor has a first terminal and a second terminal; and The second resonant inductor has a first terminal and a second terminal coupled to the first terminal of the output capacitor; The first set of switches includes: The second transistor has a first terminal coupled to the second terminal of the second resonant capacitor; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the first control signal. The third transistor has a first terminal coupled to the second terminal of the first resonant capacitor; a second terminal coupled to the first terminal of the first resonant inductor; and a control terminal for receiving the first control signal. and A fourth transistor has a first terminal; a second terminal coupled to the first terminal of the second resonant capacitor; and a control terminal for receiving the first control signal; and The second set of switches includes: The fifth transistor has a first terminal coupled to the first terminal of the second resonant inductor; a second terminal coupled to the first terminal of the first resonant capacitor; and a control terminal for receiving the second control signal. The sixth transistor has a first terminal coupled to the second terminal of the first resonant capacitor; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal. The seventh transistor has a first terminal coupled to the first terminal of the second resonant inductor; a second terminal coupled to the first terminal of the second resonant capacitor; and a control terminal for receiving the second control signal. and The eighth transistor has a first terminal coupled to the second terminal of the second resonant capacitor; a second terminal coupled to the ground terminal; and a control terminal for receiving the second control signal.

11. The DC-DC power conversion system according to claim 1, wherein the ratio of the input voltage to the output voltage is greater than 2 to 1.

12. The DC-DC power conversion system according to claim 1, wherein at startup, the first conduction time and the second conduction time are equal to a preset conduction time much less than 50% of the duty cycle.

13. A power conversion method applicable to a DC-DC power conversion system, the DC-DC power conversion system comprising a resonant switching capacitor converter and a controller, the resonant switching capacitor converter comprising an input terminal, a first resonant slot, an output capacitor, a first set of switches coupled to the first resonant slot and the output capacitor, and a second set of switches coupled to the first resonant slot and the output capacitor, the method comprising: The resonant switching capacitor converter switches between a first state and a second state to generate an output voltage; The controller adjusts the first control signal and the second control signal based on the output voltage. The first set of switches receives the first control signal to conduct a first conduction time in the first state; and The second set of switches receives the second control signal and conducts a second conduction time in the second state; in, The controller contains: A voltage divider, coupled to the first terminal of the output capacitor, is used to generate a voltage divider of the output voltage. A first comparator circuit, coupled to the voltage divider, is used to compare the divided voltage with a reference voltage to generate a first comparison voltage; The second comparator circuit is coupled to the first comparator circuit and is used to compare the first comparison voltage and the ramp voltage to generate the second comparison voltage. The first AND gate is coupled to the second comparator circuit and is used to perform an AND operation on the second comparison voltage and the clock signal to generate a control signal. A trigger, coupled to the first AND gate, is used to generate an output signal and an inverted output signal according to the control signal; The second AND gate, coupled to the flip-flop, is used to perform an AND operation on the control signal and the output signal to generate the first control signal; and The third AND gate, coupled to the flip-flop, is used to perform an AND operation on the control signal and the inverted output signal to generate the second control signal.

14. The method of claim 13, wherein in the first state, the first set of switches connects the first resonant slot in series between the input terminal and the output capacitor.

15. The method of claim 13, wherein in the second state, the second set of switches is connected in parallel with the first resonant slot and the output capacitor.

16. The method of claim 13, wherein the controller alternately switches the resonant switching capacitor converter between the first state and the second state.

17. The method of claim 13, wherein: The first set of switches receives the first control signal to cut off the first cutoff time; The second set of switches receives the second control signal to cut off the second cutoff time; and The first conduction time is less than the first cutoff time, and the second conduction time is less than the second cutoff time.

18. The method of claim 13, wherein the length of the first conduction time is equal to the length of the second conduction time.

19. The method according to claim 13, wherein at power-on, the first conduction time and the second conduction time are equal to a preset conduction time much less than 50% of the working cycle.

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