Three-phase interleaved boost converter based on coupled inductors and control method thereof

Abstract

The application discloses a three-phase interleaved boost converter based on coupled inductance, which comprises a three-phase boost circuit and a three-winding coupled inductance; the three-phase boost circuit comprises three parallel boost sub-circuits; the three-winding coupled inductance comprises three mutually coupled regulating inductances, which are electrically connected with the boost sub-circuits in correspondence. The application combines the coupled inductance with the three-phase DC / DC boost circuit, fully utilizes the parasitic parameters of the coupled inductance, and realizes the ZVS (Zero Voltage Switching) of the main switch and passive current sharing. Compared with the traditional three-phase interleaved converter, the application realizes the ZVS of the switch with the least number of components, greatly reduces the problems such as EMI (Electromagnetic Interference), saves the cost, solves the problem of uneven current distribution of the three-phase parallel converter, effectively reduces the current stress of the device, and is very suitable for high-power LED driving occasions.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of boost DC / DC converters, in particular to a three-phase interleaved boost converter based on coupled inductors and a control method thereof. BACKGROUND

[0002] Silicon power devices often have the following characteristics: under the same process technology, the larger the rated current, the larger the semiconductor crystal area, the larger the parasitic capacitance, the lower the withstand voltage, and the slower the switching speed. It is the physical characteristics that determine that the models in the switching tube that have high withstand voltage, large current value and high switching speed often need to be produced using extremely advanced semiconductor technology and process, and the yield is also not high. Therefore, the price of these devices on the market is also very expensive, and it is difficult to promote.

[0003] In the face of high-power application scenarios, especially when the converter is required to handle larger power flow, even if expensive silicon carbide switching tubes are used, single-tube converters are difficult to meet the requirements. Therefore, through the parallel connection of converters to disperse the power flow and combine soft switching technology to further reduce single-switch loss, it has become a research hotspot in the field of high-power converters.

[0004] The first problem faced by parallel converters is current sharing, which is determined by the characteristics of most power supplies being voltage sources, i.e. two voltage sources with different voltages cannot be directly connected in parallel. In order to solve the current sharing problem between converters, the simplest way is to introduce a current loop in the converter, so that it has the characteristics of a current source to some extent, i.e. a current source can be connected in parallel. This method of achieving current sharing by adding a current loop is called active current sharing. Active current sharing has the advantages of good current sharing effect, no limitation on the type of topology, and wide applicability. The disadvantage is that this method requires the introduction of a current sensor and the design of an additional controller, which is costly. Another way to achieve current sharing is called passive current sharing, which relies on the working characteristics of the converter to achieve uniform distribution of current or power flow between phases. In passive current sharing, converters with interleaved parallel structure can achieve good current sharing effect by combining interleaved control.

[0005] Soft switching technology refers to the technology of applying active or passive snubber circuits to reduce voltage and current overlap at the turn-on and turn-off moments of the converter; or through the resonance characteristics to produce a phase difference between the voltage and current of the switching tube, eliminating the overlap of voltage and current. It not only solves the problem of switching loss caused by hard switching, the problem of reverse recovery of diodes, but also solves the EMI problem caused by hard switching, which is an important technology for high-frequency conversion.

[0006] In the field of non-isolated interleaved boost converter, Professor He Xiangning's team of Zhejiang University proposes a new active interleaved Boost soft switching circuit structure, which realizes ZCS (zero current switching) turn-on and ZVS (zero voltage switching) turn-off of the main switch through adding auxiliary absorption branch. Although the two-phase interleaved Buck-Boost converter structure proposed by Yao-Ching Hsieh in Taiwan, China has some differences compared with the above-mentioned structure, the design idea belongs to the application of same direction coupled inductor in the basic converter topology. The difference is that Yao-Ching Hsieh improves the control strategy on the basis of similar structure and realizes ZVS turn-on of the main switch. Compared with ZCS, which is suitable for IGBT and other devices with large current tail loss, ZVS technology is more suitable for MOSFET devices. The turn-off loss of MOSFET is much smaller than the turn-on loss, so the realization of ZVS is more significant for MOSFET type converter.

[0007] However, at present, various existing technologies similar to the above two technologies still have the problems of complex structure and low overall efficiency of the converter. SUMMARY

[0008] In order to solve the problems in the prior art, the application provides a coupled inductor three-phase interleaved boost converter and a control method thereof.

[0009] In order to achieve the above-mentioned purpose, the specific scheme adopted by the application is as follows: the three-phase interleaved boost converter based on coupled inductor includes a three-phase boost circuit and a three-winding coupled inductor, the three-phase boost circuit includes three parallel boost sub-circuits, the three-winding coupled inductor includes three mutually coupled regulating inductors, and the regulating inductors are electrically connected with the boost sub-circuits in correspondence.

[0010] Preferably, the boost sub-circuit is a Boost circuit.

[0011] Preferably, the boost sub-circuit includes a main switch and a rectifier diode electrically connected, one end of the regulating inductor is connected between the main switch and the rectifier diode, and the other end of the regulating inductor is grounded.

[0012] Preferably, the main switch is a MOSFET switch tube, the drain electrode of the main switch is used to connect the positive electrode of the input power supply, the source electrode of the main switch is electrically connected with the cathode electrode of the rectifier diode, and the anode electrode of the rectifier diode is electrically connected with the output filter capacitor.

[0013] Preferably, the converter further includes an output filter capacitor.

[0014] Preferably, the three regulating inductors are coupled in the same direction.

[0015] Preferably, the self-inductances of the three regulating inductors are equal.

[0016] A control method of a three-phase interleaved boost converter based on coupling inductors,

[0017] determining a first preset duty ratio and a second preset duty ratio;

[0018] setting an actual duty ratio of the converter to the first preset duty ratio when the converter operates at a rated load, and controlling the boost-buck sub-circuit based on the first preset duty ratio;

[0019] setting an actual duty ratio of the converter to the second preset duty ratio when the converter operates at half of the rated load, and controlling the boost-buck sub-circuit based on the second preset duty ratio.

[0020] Preferably, the method comprises the following steps:

[0021] S1, setting a minimum operating frequency of the converter;

[0022] S2, setting an actual duty ratio of the converter to the first preset duty ratio, and monitoring an output voltage of the converter in real time;

[0023] S3, when the stability of the output voltage reaches a set threshold, continuing to operate the converter, otherwise adjusting an actual operating frequency of the converter;

[0024] S4, when the actual operating frequency of the converter is less than the minimum operating frequency, continuing to operate the converter, otherwise setting the actual duty ratio of the converter to the second preset duty ratio, and continuing to operate the converter.

[0025] The application combines coupling inductors with a three-phase DC / DC boost circuit, fully utilizes the parasitic parameters of the coupling inductors, and realizes ZVS of the main switch and passive current sharing; compared with the traditional three-phase interleaved converter, the application realizes ZVS of the switch with the least number of components, greatly reduces electromagnetic interference (EMI) and other problems, saves cost, solves the problem of uneven current distribution of the three-phase parallel converter, effectively reduces the current stress of the device, and is very suitable for high-power LED driving occasions; compared with the existing two-phase interleaved parallel structure based on coupling inductors, the three-phase parallel not only expands the minimum soft switching duty cycle limit of the working mode from >50% to only >33%, but also further disperses the current stress from 1 / 2 to 1 / 3, improves the output current ripple frequency by 3 / 2, expands the duty cycle as an additional control variable, proposes a control method suitable for the application, and improves the overall efficiency of the converter. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a soft-switching three-phase interleaved parallel boost converter topology based on coupled inductors.

[0028] Figure 2 This is the decoupling equivalent circuit for a soft-switching three-phase interleaved parallel boost converter based on coupled inductors.

[0029] Figure 3 This diagram illustrates the decoupling equivalent process of a three-winding coupled inductor.

[0030] Figure 4 The waveform in time domain of the soft-switching three-phase interleaved parallel boost converter based on coupled inductors in operating mode 1 (D = 0.33) without considering Coss is shown.

[0031] Figure 5 The diagram shows the operating mode 1 (D=0.33) of the soft-switching three-phase interleaved parallel boost converter based on coupled inductors, without considering Coss.

[0032] Figure 6 The waveform in time domain of the soft-switching three-phase interleaved parallel boost converter based on coupled inductors in operating mode 2 (D=0.66) without considering Coss is shown.

[0033] Figure 7 The diagram shows the operating mode 2 (D=0.66) of the soft-switching three-phase interleaved parallel boost converter based on coupled inductors, without considering Coss.

[0034] Figure 8 The time-domain waveform of a soft-switching three-phase interleaved parallel boost converter based on coupled inductors in operating mode D=0.33 considering Coss is given.

[0035] Figure 9 The diagram shows the operating mode of a soft-switching three-phase interleaved parallel boost converter based on coupled inductors, with a Coss value of D=0.33.

[0036] Figure 10The AC equivalent small signal circuit diagram of the T2 mode parasitic oscillation when the working mode of the soft switching three-phase interleaved parallel boost converter based on coupled inductance is D=0.33 under the consideration of Coss.

[0037] Figure 11 The Laplace transform solution related diagram of the T2 mode parasitic oscillation when the working mode of the soft switching three-phase interleaved parallel boost converter based on coupled inductance is D=0.33 under the consideration of Coss.

[0038] Figure 12 The time domain waveform when the working mode of the soft switching three-phase interleaved parallel boost converter based on coupled inductance is D=0.66 under the consideration of Coss.

[0039] Figure 13 The working mode diagram when the working mode of the soft switching three-phase interleaved parallel boost converter based on coupled inductance is D=0.66 under the consideration of Coss.

[0040] Figure 14 The soft switching three-phase interleaved parallel boost converter based on coupled inductance.

[0041] Figure 15 The driving signal (D>0.33) of the soft switching three-phase interleaved parallel boost converter based on coupled inductance.

[0042] Figure 16 The hybrid control strategy of the soft switching three-phase interleaved parallel boost converter based on coupled inductance. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0044] The three-phase interleaved parallel boost converter based on coupled inductance comprises a three-phase boost circuit and a three-winding coupled inductance, the three-phase boost circuit comprises three parallel boost sub-circuits, and the three-winding coupled inductance comprises three mutually coupled regulating inductances, and the regulating inductances are electrically connected with the boost sub-circuits in correspondence.

[0045] In this invention, the parasitic leakage inductance of the coupled inductor is used to turn on the three-phase boost circuit, which greatly reduces switching losses and hard-switching electromagnetic interference (EMI) problems. At the same time, the mutual inductance of the coupled inductor is used to make the current of each phase of the three-phase boost circuit equal, effectively dispersing the current stress of the main switch of the converter. By utilizing the frequency multiplication characteristic of the three-phase interleaved parallel structure, the output current ripple frequency is three times the operating frequency of a single switch, thereby reducing the output current ripple of the converter at the same switching frequency.

[0046] To avoid interference with the load, the converter also includes an output filter capacitor C. o .

[0047] In this embodiment, the boost circuit is configured as a boost circuit. The boost circuit includes a main switch and a rectifier diode electrically connected. One end of an adjusting inductor is connected between the main switch and the rectifier diode, and the other end of the adjusting inductor is grounded. A boost circuit is essentially a bridge arm, consisting of a first bridge arm formed by the main switch S1 and the rectifier diode D1, a second bridge arm formed by the main switch S2 and the rectifier diode D2, and a third bridge arm formed by the main switch S3 and the rectifier diode D3. More specifically, the main switch is configured as a MOSFET switch. The drain of the main switch is connected to the positive terminal of the input power supply, the source of the main switch is electrically connected to the cathode of the rectifier diode, and the anode of the rectifier diode is electrically connected to the output filter capacitor. That is, the sources of S1, S2, and S3 are connected to the input power supply V. i The negative terminals of S1, S2, and S3 are connected to the negative terminals of diodes D1, D2, and D3, respectively. Their connection points are called exchange nodes M1, M2, and M3. The cathodes of diodes D1, D2, and D3 are connected to the output filter capacitor C. o With the positive terminals connected, one tap from each winding of the three-winding coupled inductor is connected to exchange nodes M1, M2, and M3 respectively. The remaining taps are connected together and then connected to the input power supply V. i The positive terminal. The three regulating inductors are coupled in the same direction, and the self-inductance of the three regulating inductors is equal, that is, the self-inductance of each winding is equal, L m1 =L m2 =L m3 =L m The coupling coefficients are also equal, k1 = k2 = k3 = k.

[0048] The equivalent circuit model of the coupled inductor is as follows: Figure 3 As shown in (a). Figure 3 In (a), L1=L2=L3=L, where L is the leakage inductance of the three-winding coupled inductor, and L=L m *(1-k), L cm It is the decoupled magnetizing inductance, L cm =k*L mLet T be an ideal transformer with winding turns n1 = n2 = n3 = n. According to the characteristics of an ideal transformer, when the turns ratio between windings is the same, the potentials at points A, B, and C are the same, i.e., a "virtual short circuit". Short-circuiting points A, B, and C results in... Figure 3 As shown in (b). At this time, n1, n2, n3 and L cm They are connected in parallel, that is, the ideal transformer T and the magnetizing inductor L cm Parallel connection, such as Figure 3 As shown in (c), the coupling inductance M of an ideal transformer tends to infinity, M>>L. cm i cm >>i T ≈0, the ideal transformer T is equivalent to an open circuit, i.e., a "virtual open circuit". Figure 3 (c) The ideal transformer T is disconnected, resulting in the equivalent circuit. Figure 2 .

[0049] The above analysis shows that the three-winding coupled inductor plays a magnetic integration role in this converter, simplifying the original topology that required four inductors to one coupled inductor, greatly reducing the number of passive components and lowering costs.

[0050] The following is a theoretical analysis of the performance converter of the present invention.

[0051] For ease of explanation, we will first ignore the parasitic capacitance of the main switch and perform modal analysis, and then analyze the ZVS implementation of the converter.

[0052] The converter's time-domain waveform when the duty cycle D = 0.33 is as follows: Figure 4 As shown, its operating modes are as follows Figure 5 As shown. Figure 5 (a) T1 mode: S1 is turned off at time t0, D1 continues flowing, v cm It can be obtained by the superposition theorem, as shown in equation (2). According to the premise in the simplified analysis: the self-inductance of the windings is equal and the coupling coefficient is equal, as shown in equation (1). Equation (2) can be further simplified to equation (3);

[0053]

[0054]

[0055]

[0056] At a constant voltage V o -v cm Under the action of the inductor current i l1 It begins to decrease linearly; at a constant voltage v cm Under the influence of i l2 It begins to rise linearly. The magnetizing inductance L in this mode... cm Voltage v at both endsLcm <0, inductor current i cm The inductance decreases, flowing from the magnetizing inductance to the output capacitor C. o Charge.

[0057] When the inductor current i l1 When the current drops to 0, the current reverses, rectifier diode D1 is cut off, and the converter enters mode T2 as shown in Figure 5(b). In this mode, v cm As shown in equation (4);

[0058]

[0059] At a constant voltage v cm Under the action of the inductor current i l2 i cm It increases linearly, as shown in equation (5);

[0060]

[0061] Due to inductance L cm The inductance value is relatively large, and the current change of inductor L2 is not significant in this mode. The magnetizing inductance L... cm Voltage v across the terminals Lcm >0, the inductor current increases, and energy is transferred from the input power supply to the magnetizing inductor. C o It provides energy to the load and stabilizes the output voltage.

[0062] At time t2, switch S3ZVS is turned on, and the converter enters mode T3. Figure 5 As shown in (c), in this mode, according to the voltage divider principle, compared to Figure 5 (b) Inductors L3 and L2 are connected in parallel, v cm The voltages distributed are shown in equation (6);

[0063]

[0064] At time t3, switch S2 is hard-turned off, and the converter switches from second-phase operation to third-phase operation. Since the phase-to-phase operating modes are similar, this step is omitted.

[0065] When the duty cycle D = 0.66: the time-domain waveform of the converter is as follows Figure 6 As shown, its operating modes are as follows Figure 7 As shown.

[0066] T1 mode such as Figure 7 As shown in (a), different from Figure 5 (a) In this mode, S3 also turns on while S2 is conducting, compared to equation (3)v cm The voltage received will be greater. The voltage received in this mode is shown in equation (7), and after further simplification, it is shown in equation (8).

[0067]

[0068]

[0069] T2 mode such as Figure 7 As shown in (b). Figure 7 (b) and Figure 5 (c) is the same, this mode is the same as Figure 4 The inductor current slopes in the T3 mode are the same, so the analysis is omitted.

[0070] T3 mode such as Figure 7 As shown in (c), L1 / / L2 / / L3 and L cm This forms a voltage divider branch, at which point v cm The voltage is closer to 0V, and the v in this mode is... cm As shown in equation (9).

[0071]

[0072] The above analysis shows that under different duty cycles, as the duty cycle increases, more parallel phases participate in energy transfer at the same time, the input impedance of the converter decreases, and more energy can be processed per unit time. Under constant load, this is reflected in an increase in output voltage.

[0073] The above analysis does not include C. oss Ideally, but in reality due to C oss The existence of C means that even when the switch is off, its C oss It will also participate in resonance, V on the main switch. DS Parasitic oscillations are exhibited. At certain D values, these parasitic oscillations will affect the realization of ZVS. The following analysis will address this issue when C... oss The converter's operating modes under certain conditions are analyzed, and the ZVS implementation of its main switch is also analyzed.

[0074] Consider C oss The converter time-domain waveform when the duty cycle is D = 0.33 is as follows: Figure 8 As shown, its operating modes are as follows Figure 9 As shown. Comparison Figure 4 and Figure 9 Obviously C oss The introduction of this has a certain impact on the waveform of the entire converter. In the interval [t1, t4], the inductor current still maintains a linear change, but is superimposed with sinusoidal oscillation.

[0075] Figure 8 At time t0, v G1 Shutdown, time t6 v G2The "turn-off" statement describes the process of the converter switching from the first phase to the second phase, and includes the value of v at time t5. G3 ZVS activation process.

[0076] T1 mode such as Figure 9 As shown in (a), due to i l3 The initial current at time t0 is negative, so the body diode of S3 is turned on. This mode is similar to... Figure 7 (a) Modal consistency. v during time T1 cm The voltage is a constant value and can be obtained from equation (8).

[0077] Inductor current i l3 In V i -v cm Under the action of a constant voltage, i increases linearly, and at time t1 l3 If the value crosses 0, enter the T2 mode.

[0078] T2 mode, body diode D S3 Reverse cutoff, originally flowing through D S3 Inductor current i l3 By changing to C oss3 Flow, such as Figure 11 As shown in (b). The AC equivalent small-signal circuit in this mode is as follows. Figure 10 As shown, by Figure 10 It can be known that the frequency f of the parasitic oscillation is... osc1 As shown in equation (10).

[0079]

[0080] v in T2 mode cm The waveform can be solved using the Laplace transform. Figure 11 (a), (b), and (c) are the circuit diagrams, initial conditions, and Laplace transform operation circuits for this mode, respectively. Figure 11 The initial conditions in (b) are shown in equation (11), i cm correspond Figure 8 Medium inductance L cm Current i cm The maximum value I cm .right Figure 11 Equation (12) is obtained for node A in (c) using the nodal current method;

[0081]

[0082]

[0083]

[0084]

[0085]

[0086]

[0087] Substituting equation (1) into equation (12) and simplifying, we obtain equation (13). Performing an inverse Laplace transform on equation (13) yields equation (14). Equation (14) represents v in mode T2. cm Voltage change, where ω osc1 The angular velocity representing the parasitic oscillation, after being converted into frequency, is consistent with the result obtained from equation (10), v cm_avg Then it means v cm The DC component of the voltage. In mode T2, the inductor current i cm In V i -v cm Under the influence of the action, it shows a downward trend, and at time t2, i D1 It drops to 0 and enters T3 mode.

[0088] The circuit diagram for T3 mode is as follows: Figure 9 As shown in (c), at time t2, diode D1 is turned off, and the capacitance C of switch S1 is... oss1 Discharge begins, C oss1 Because the capacitance is small, the discharge process in this mode is very short. Since the mode duration is short, its impact on energy transfer is limited. Solving for an analytical solution would require additional initial conditions at time t2, making the analytical solution extremely complex; therefore, this step is omitted.

[0089] At time t3, C oss1 Complete discharge, v DS1 Drops to 0, body diode D S1 When the circuit is turned on, it enters the T4 mode, such as... Figure 9 As shown in (d), the capacitance C in mode T4. oss3 Discharge begins and ends at time t4. During the discharge process, C... oss3 The energy was transferred to i l3 In the middle, leading to i l3 The current appears in the negative direction. Similar to mode T3, mode T4 has a very short duration, so the relevant analytical solution expression is omitted.

[0090] T5 mode, such as Figure 9 As shown in (e), C oss3 After the discharge ends, i l3 The negative current will freewheel through the body diode of S3. Ignoring the voltage drop across the body diode, this mode is similar to... Figure 7 (c) has the same mode, v cm As shown in equation (9).

[0091] At time t5, v G3 ZVS is turned on and enters Mode T6. Ignoring the conduction voltage drop of the body diode, the v in Mode T6 cm is the same as that in Mode T5. At time t6, v G2 is turned off, and the circuit switches from the second phase to the third phase.

[0092] Comparison Figure 4 and Figure 8 It can be seen from the above analysis that the influence of the parasitic capacitance C oss on the operating mode cannot be ignored.

[0093] In addition, from the v Figure 8 waveform, v DS3 satisfies that the ZVS turn-on time t5 should be within the interval t4 < t5 < t6. If the turn-on time t5 is between [t1, t3], the parasitic oscillation will be interrupted and soft switching may be lost. G3 Therefore, in the mode with a duty cycle D > 0.33, the dead time T6 should not be set too large. It can be set according to experience as the dead time, and it is appropriate that T6 < 200 nS.

[0094] Another duty cycle region where soft switching is relatively easy to achieve is D = 0.66. Its time-domain waveform is as

[0095] shown, and the operating mode is as Figure 12 shown. The characteristic of this mode is that the switches of the three phases are alternately turned off. As in the v Figure 13 in Figure 12 , v G1 , v G2 , v G3 waveform, taking [t0, t'4] as an example, when S1 is turned off, S2 and S3 are both in the on state. Since C oss 2 and C oss3 are both short-circuited, there is no parasitic oscillation in this mode. ]

[0096] Mode T1: At time t0, S1 is turned off and D1 conducts. This mode is as Figure 13 (a) shown and is the same as Figure 9 (a) and Figure 7 (a). Therefore, the v cm voltage in this mode is as shown in Equation (8). [[ID=..]]

[0097] Mode T2: At time t1, the diode current i D1 drops to 0, and C oss1 starts to discharge. The mode diagram is as Figure 13 (b) shown.

[0098] Mode T3: At time t2, the voltage of C oss1 is 0, the discharge is completed, and the body diode is turned on. The mode diagram is asFigure 13 As shown in (c).

[0099] In mode T4, S1ZVS is activated at time t3, as shown in the modal diagram. Figure 13 As shown in (d), when S2 is turned off at time t4, the converter begins to switch from the first phase to the second phase.

[0100] Ignoring the diode forward voltage drop Figure 13 (c) and Figure 13 (d) and Figure 7 (c) Same, v in modes T3 and T4 cm The voltage can be obtained using equation (9). The voltage of the T2 mode is... cm The waveform can be obtained using Laplace transform, but its duration is relatively short and its impact on the overall converter operation is limited, so the analysis is omitted.

[0101] Based on the above modal analysis, the switching of the main switch mode occurs at the moment the main switch is turned off, regardless of whether it is in the D=0.33 mode or the D=0.66 mode. Once the main switch of a certain phase is turned off, the rectifier diode of that phase conducts and begins to transfer energy to the output capacitor and the load. During the energy transfer process, the voltage across the leakage inductor is clamped by the input and output voltages, and the leakage inductor current decreases linearly until it changes direction; after changing direction, due to C... oss With the presence of [something], the current in the leakage inductance will become negative. The negative current will turn on the body diode of the MOSFET, ultimately achieving ZVS for the main switch.

[0102] Based on the above analysis, considering parasitic capacitance, the duty cycle D has only two suitable operating points: D slightly greater than 0.33 or D slightly greater than 0.66 can achieve ZVS mode.

[0103] If we only consider the main modes of energy transmission, the difference between the two modes is: when D=0.66, only one phase switch is off and the other two phase switches are on, while when D=0.33, only one phase switch is on and the other two phase switches are off. Therefore, the input impedance during charging is only half that of D=0.66 compared to D=0.33, which can provide higher output gain, i.e., higher output voltage under constant load.

[0104] The gain of the converter of this invention will be analyzed below.

[0105] First, we solve for the voltage gain formula in the D=0.33 mode. When solving for the gain, we ignore the effect of the MOSFET's parasitic capacitance. This is because parasitic capacitance is typically very small, and its impact on the converter gain is also relatively small. Furthermore, considering the effect of parasitic capacitance does not yield a straightforward analytical solution. Taking both factors into account, we only provide a solution ignoring C here. oss The process of calculating the gain over time.

[0106] In the D=0.33 mode, still based on Figure 4 For example, observe. Figure 4 v cm The voltage waveform has two main modes: T1 and T2. The voltage (v) in mode T1 is known. cm V cm_T1 As shown in equation (3). v in mode T2 cm V cm_T2 As shown in equation (4). Based on equations (3) and (4), the mutual inductance L can be given. cm The rising and falling slopes of the current are k r and k f As shown in equations (17) and (18);

[0107]

[0108]

[0109] Then, based on the steady-state inductor current i cm The increase value equals the decrease value, resulting in formula (19), T r and T f They represent Figure 4 in i cm The rising phase time and the falling phase time, T 3phase This represents the period of the switching current ripple after three phases are interleaved in parallel. Since it is a three-phase parallel connection, it is one-third of the period of a single switch. s_3phase Similarly, the single switching frequency f s Three times;

[0110]

[0111] Solving equation (19) yields equation (20);

[0112]

[0113] To solve for the average output current I D_avg The peak output current I of the diode must be calculated first. Dmax Value, i.e., inductor current i l2 The value of i at time t3 l2 (t3). Assume i l2 (t0)=0, i l2 The solution to (t3) is shown in equation (21), I D_avg The solution is shown in equation (22).

[0114]

[0115]

[0116] The output power of the converter can be expressed by equations (23) and (24), respectively.

[0117] P o =I Davg ·V o (twenty three);

[0118]

[0119]

[0120] Let V o and V i The ratio is g, as shown in equation (25). Combining equations (22), (23), (24), and (25), we can obtain equation (26).

[0121] 2f s_3phase (n+1)L·g 2 -2f s_3phase L·g-(2n+1)R o =0(26);

[0122] Solving for g in equation (26) yields the expression for g (27);

[0123]

[0124]

[0125] Voltage gain derivation in D=0.66 mode. The gain derivation in D=0.66 mode begins with... Figure 6 For example, the main modes are T1 and T2. v in mode T1 cm_T1 Equation (8) gives the v of mode T2. cm_T2 The current i in this mode is given by equation (6). cm The rising and falling slopes k r k f As shown in equation (28).

[0126]

[0127] Substituting equation (28) into equation (19) and solving, we obtain equation (29).

[0128]

[0129] To solve for the average output current I D_avg The peak output current I of the diode must be calculated first. Dmax Value, i.e., inductor current i l2 The value of i at time t3 l2 (t3). ByFigure 6 It can be seen that i l2 It started rising in the cycle before t0, i l2 (t0)=0.5(I Dmax ), so i l2 The solution to (t3) is shown in equation (30). Simplifying equation (30) yields equation (31). Furthermore, I D_avg The solution is shown in equation (32).

[0130]

[0131]

[0132]

[0133] Substituting equation (32) into the equation composed of equations (23), (24), and (25), we obtain the expression for g, equation (33).

[0134]

[0135] Equation (33) allows us to determine R. o In the case of L, make f s The image relating to g is adjusted using a transformer.

[0136] The present invention also provides a control method for a three-phase interleaved parallel boost converter based on coupled inductors, comprising: determining a first preset duty cycle and a second preset duty cycle; setting the actual duty cycle of the converter to the first preset duty cycle when the converter is operating at rated load, and controlling the boost / buck sub-circuit based on the first preset duty cycle; setting the actual duty cycle of the converter to the second preset duty cycle when the converter is operating at half the rated load, and controlling the boost / buck sub-circuit based on the second preset duty cycle.

[0137] The methods include S1 to S4.

[0138] S1. Set the minimum operating frequency of the converter.

[0139] S2. Set the actual duty cycle of the converter to the first preset duty cycle and monitor the output voltage of the converter in real time.

[0140] S3. When the stability of the output voltage reaches the set threshold, the converter continues to run; otherwise, the actual operating frequency of the converter is adjusted.

[0141] S4. When the actual operating frequency of the converter is less than the minimum operating frequency, the converter continues to run; otherwise, the actual duty cycle of the converter is set to the second preset duty cycle, and the converter continues to run.

[0142] This control method employs a hybrid control approach, adjusting both the operating frequency and duty cycle, thereby expanding the load range and gain range of the converter under constant voltage conditions. Specifically, when the actual load of the converter is less than the rated load, the converter's operating frequency increases, and the actual duty cycle gradually changes from the first preset duty cycle to the second preset duty cycle. Furthermore, the overall gain of the converter decreases. When the actual load drops to half of the rated load, the converter's operating frequency further increases. At this point, switching the actual duty cycle to the second preset duty cycle avoids oscillations caused by gain jumps and reduces the magnitude of gain reduction as the actual load continues to decrease.

[0143] To implement the above control method, the converter needs to be equipped with a voltage acquisition module and a PWM generation module. The voltage acquisition module is used to determine the actual load of the converter. This module can include a voltage divider resistor connected in series with the load. The actual load of the converter is determined by acquiring the voltage value of the voltage divider resistor. The PWM generation module is used to generate three staggered-phase PWM waves with variable duty cycles. This can be implemented using a DSP processor, with the DSP processor's ECAP1, ECAP2, and ECAP3 modules configured in PWM output mode. The period comparison value CAP1 for all three channels is set to the count value, and the CTRPHS register is set to 0, 0.33*count, and 0.66*count respectively, outputting three staggered-phase PWM waves. The CAP2 register is responsible for setting the duty cycle. In D=0.33 mode, all three CAP2 registers are set to 0.33*count; in D=0.66 mode, all three CAP2 registers are set to 0.66*count. The frequency of PWM is controlled in real time by a PI controller. According to the gain expressions (26) and (32), the magnitude of the converter output voltage is controlled. If the output voltage exceeds the reference voltage, the switching frequency is increased. If the output voltage is less than the reference voltage, the switching frequency is decreased to increase the output voltage.

[0144] The default operating mode of the converter after power-on is M=0.66 mode, which uses a PI algorithm to stabilize the output voltage. When the operating frequency drifts above 18.1kHz, the mode switching counter M_Count increments by one. When the operating frequency is less than (18.1 - Num_HIS)kHz, the mode switching counter decrements by one. When the counter value is greater than Num_M0.33, mode switching is performed to enter mode M=0.33. When the counter value returns to 0, it switches back to M=0.66. By modifying the values ​​of NUM_M0.33 and Num_HIS, oscillations caused by frequent mode switching at the zero point can be avoided.

[0145] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0146] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control method for a three-phase interleaved parallel boost converter based on coupled inductors, characterized in that: The three-phase interleaved parallel boost converter includes a three-phase boost circuit and a three-winding coupled inductor. The three-phase boost circuit includes three boost sub-circuits connected in parallel. The three-winding coupled inductor includes three mutually coupled regulating inductors. The regulating inductors are electrically connected to the boost sub-circuits. The control method for a three-phase interleaved parallel boost converter based on coupled inductors includes the following steps: Determine the first preset duty cycle and the second preset duty cycle; When the converter is running under rated load, the actual duty cycle of the converter is set to the first preset duty cycle, and the boost sub-circuit is controlled based on the first preset duty cycle; When the converter operates at half the rated load, the actual duty cycle of the converter is set to the second preset duty cycle, and the boost sub-circuit is controlled based on the second preset duty cycle; Specifically, the control method for the three-phase interleaved parallel boost converter based on coupled inductors includes the following steps: S1. Set the minimum operating frequency of the converter; S2. Set the actual duty cycle of the converter to the first preset duty cycle, and monitor the output voltage of the converter in real time; S3. When the stability of the output voltage reaches a set threshold, the converter continues to operate; otherwise, the actual operating frequency of the converter is adjusted. S4. When the actual operating frequency of the converter is less than the minimum operating frequency, the converter continues to operate; otherwise, the actual duty cycle of the converter is set to the second preset duty cycle, and the converter continues to operate.

2. The control method for a three-phase interleaved parallel boost converter based on coupled inductors as described in claim 1, characterized in that: The boost sub-circuit is configured as a Boost circuit.

3. The control method for a three-phase interleaved parallel boost converter based on coupled inductors as described in claim 1, characterized in that: The converter also includes an output filter capacitor. The main switch is a MOSFET switch. Each boost sub-circuit is a bridge arm, consisting of the first bridge arm formed by the main switch S1 and rectifier diode D1, the second bridge arm formed by the main switch S2 and rectifier diode D2, and the third bridge arm formed by the main switch S3 and rectifier diode D3. The sources of S1, S2, and S3 are connected to the negative terminal of the input power supply Vi, and the drains of S1, S2, and S3 are connected to the anodes of rectifier diodes D1, D2, and D3, respectively. Their connection points are called switching nodes M1, M2, and M3. The cathodes of rectifier diodes D1, D2, and D3 are connected to the positive terminal of the output filter capacitor Co. One tap of each winding of the three-winding coupled inductor is connected to the switching nodes M1, M2, and M3, respectively, and the remaining taps are connected together and connected to the positive terminal of the input power supply Vi.

4. The control method for a three-phase interleaved parallel boost converter based on coupled inductors as described in claim 2, characterized in that: The three regulating inductors are coupled in the same direction.

5. The control method for a three-phase interleaved parallel boost converter based on coupled inductors as described in claim 1, characterized in that: The self-inductance of the three regulating inductors is equal.

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