A radio frequency communication circuit layout design method and system

Abstract

The application discloses a radio frequency communication circuit layout design method and system, and relates to integrated circuits: a design constraint parameter library is constructed; a circuit topology structure is analyzed, circuit node types are identified, and node attribute information is extracted; a corresponding relationship between nodes and grid cells is established through a space mapping function, and a grid attribute matrix reflecting current distribution characteristics is generated; electromagnetic interference intensity received by each grid cell is calculated, grid cells with electromagnetic interference intensity exceeding a preset threshold are marked as areas needing isolation, and an area marking matrix is generated; a parameterized distributed circuit model is constructed for a wiring allowed area, process parameters in the design constraint parameter library are used to establish a mapping relationship of the distributed circuit model; a frequency domain node voltage equation set is constructed and solved, and voltage distribution data of each grid cell is obtained; and a multi-objective evaluation function is constructed according to the voltage distribution data; and the application balances power supply network performance and parasitic effects.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to a method and system for designing radio frequency communication circuit layouts. Background Technology

[0002] As a core component of wireless communication systems, the layout design quality of radio frequency (RF) communication circuits directly impacts the overall system performance. With the rapid development of next-generation communication technologies such as 5G and 6G, the operating frequency of RF circuits is constantly increasing, placing more stringent demands on the precision, electromagnetic compatibility, and signal integrity of the layout design. RF circuit layout design requires comprehensive consideration of factors such as circuit performance, process compatibility, electromagnetic interference suppression, and parasitic effect control. Any design flaw can lead to a severe degradation in system performance or even functional failure.

[0003] Existing RF communication circuit layout design methods typically follow this technical process: First, clarify design requirements and specifications, confirming process parameters and key parameters such as operating frequency, power level, bandwidth, noise figure, and linearity; then analyze the circuit schematic, extract core signals and main signal transmission paths, and simplify the circuit topology; next, perform global layout planning, dividing areas according to functional modules and signal flow rules; employ isolation or shielding techniques for power devices, low-noise components, and sensitive modules; when designing the power and ground grids, ensure sufficient power supply while considering the impact of the power network on internal circuits, paying attention to low impedance handling and decoupling design, and not ignoring the effects of mutual inductance, parasitic capacitance, and substrate noise; finally, perform adjustments and optimizations through post-simulation verification.

[0004] However, existing design methods have significant shortcomings in power network design: they lack a quantitative model of the relationship between metal fill density and circuit performance, making it impossible for designers to accurately predict the specific impact of different metal densities on power integrity and parasitic effects. To ensure power integrity, designers often adopt a conservative design strategy, uniformly and densely filling the entire power network area with metal. While this empirical approach of erring on the side of too much rather than too little may meet voltage drop requirements, it inevitably introduces excessive parasitic inductance and capacitance, severely impacting the high-frequency performance of RF circuits. Especially at high frequencies, excessive parasitic effects can lead to a series of problems such as signal distortion, increased power consumption, and bandwidth limitations, becoming a key bottleneck restricting the improvement of RF circuit performance. Therefore, there is an urgent need for a layout design method that can quantitatively analyze the relationship between metal density and electrical performance, achieving a precise balance between power network performance and parasitic effects. Summary of the Invention

[0005] In response to the problem that excessive use of metal materials in RF circuit layout design to ensure power integrity can lead to excessive parasitic effects, this application provides an RF communication circuit layout design method that balances power network performance and parasitic effects.

[0006] One aspect of this application provides a method for designing a radio frequency (RF) communication circuit layout, comprising: S1, acquiring a dataset of process parameters and performance indicators for the RF communication circuit, and constructing a design constraint parameter library; S2, analyzing the circuit topology, identifying the circuit node types and extracting node attribute information, and generating a node feature dataset containing node types, current characteristics, and spatial locations; S3, discretizing the layout design area into a grid cell array, establishing a correspondence between nodes and grid cells through a spatial mapping function based on the node feature dataset, and generating a grid attribute matrix reflecting current distribution characteristics based on the node current characteristics mapped to each grid cell; S4, calculating the electromagnetic interference intensity experienced by each grid cell based on the power consumption and noise sensitivity values ​​of each node in the node feature dataset, marking grid cells with electromagnetic interference intensity exceeding a preset threshold as areas requiring isolation, and generating an area marking matrix; S5, determining grid cells not marked as requiring isolation as wiring allowable areas based on the area marking matrix, and constructing a parameterized distributed circuit model for the wiring allowable areas. S6. Using process parameters from the design constraint parameter library, establish a mapping relationship between the resistance, inductance, and capacitance parameters of the distributed circuit model and the metal density distribution parameters to be optimized; S7. Use the current distribution data in the grid attribute matrix as the input excitation of the distributed circuit model, calculate the circuit parameter values ​​of the distributed circuit model based on the mapping relationship and the metal density distribution parameters, construct and solve the frequency domain node voltage equations to obtain the voltage distribution data of each grid cell; S8. Based on the voltage distribution data, construct a multi-objective evaluation function including voltage stability, metal usage, and density smoothness, update the metal density distribution parameters using the gradient descent method, substitute the updated metal density distribution parameters into step S5 to recalculate the circuit parameters of the distributed circuit model, and repeat steps S6 and S7 until the change in the evaluation function is less than the preset convergence threshold; S9. Binarize the optimized converged metal density distribution parameters, set the grid cells with density values ​​greater than the preset threshold as metal regions, and set the rest as blank regions, and generate a layout data file based on the binarization results.

[0007] Further, in step S2, a node feature dataset containing node type, current characteristics, and spatial location is generated, including: reading the circuit netlist file, extracting circuit component connection information, and constructing a circuit topology graph containing a node set V and an edge set E; performing a path search algorithm on the circuit topology graph to identify the signal transmission path from the input to the output; dividing the node set V into a power node subset, a sensitive node subset, and a power supply node subset based on the power consumption characteristic value and noise margin value of each node on the signal transmission path, wherein the power node subset contains nodes with power consumption greater than a preset power consumption threshold, and the sensitive node subset contains nodes with noise margin less than a preset noise threshold; constructing a multi-dimensional attribute vector for each node in the node set V, the attribute vector containing node type identifier, DC current value, AC current spectrum data, and node spatial coordinate information; and constructing a node feature dataset based on the attribute vector of each node.

[0008] Furthermore, S3 generates a grid attribute matrix reflecting the current distribution characteristics, including: discretizing the layout design area into a grid cell array based on the size parameters and preset resolution parameters of the layout design area; mapping each node to the corresponding grid cell using a spatial mapping function based on the node spatial coordinate information in the node feature dataset; performing data aggregation processing on the current feature data of the nodes mapped to the corresponding grid cell to generate the current density value of the corresponding grid cell; and constructing a grid attribute matrix based on the current density values ​​of each grid cell.

[0009] In particular, traditional layout design treats the power network as a continuous, monolithic structure, making it impossible to perform differentiated analysis of metal requirements in local areas, thus forcing the adoption of a uniform, conservative design strategy. This solution, however, uses mesh discretization to transform the continuous layout space into a finite number of independently optimizable mesh cells, each with its own independent metal density parameters. This discretization method makes it possible to establish a quantitative mapping relationship between metal density and electrical performance.

[0010] More importantly, the current characteristics of the circuit nodes are accurately allocated to each grid cell through the spatial mapping function, generating a grid attribute matrix that reflects the real current distribution. High current density regions require more metal to ensure that the voltage drop is within the allowable range, while low current density regions can reduce metal filling to reduce parasitic effects.

[0011] Further, in S4, a region labeling matrix is ​​generated, including: extracting the power consumption value of each power node based on a subset of power nodes. And spatial coordinates; for each grid cell (i, j) in the grid cell array, calculate the Euclidean distance between the corresponding grid cell and each power node. According to Euclidean distance Calculate the electromagnetic interference weight of each grid cell. The calculated electromagnetic interference weights With the preset isolation threshold When comparing, When the condition is met, the corresponding grid cell is marked as 1; otherwise, it is marked as 0, generating a binary region labeling matrix. .

[0012] In particular, traditional layout design, in pursuit of power integrity, often overlooks the electromagnetic compatibility (EMC) issues that metal fill may introduce. Designers tend to uniformly fill the entire layout area, including areas near high-power devices. However, filling these areas with metal not only fails to effectively improve power network performance but also makes the metal structure a coupling path for EMC, exacerbating signal crosstalk and noise propagation, while introducing additional parasitic effects.

[0013] This application establishes an electromagnetic interference weighting model based on power consumption and spatial distance. This quantitatively assesses the electromagnetic interference intensity experienced by each grid cell. This is based on physical principles. The attenuation model accurately reflects the spatial distribution characteristics of the electromagnetic field. This is achieved by setting an isolation threshold. The system can automatically identify high-interference areas that are unsuitable for metal placement and generate an area marking matrix. These regions will be excluded from the subsequent metal density optimization process.

[0014] Furthermore, in S5, the mapping relationship between the resistance, inductance, and capacitance parameters of the distributed circuit model and the metal density distribution parameters to be optimized is established, including: based on the region labeling matrix. Mesh cells with a flag value of 0 are defined as allowed wiring regions; a distributed RLC mesh model is constructed for the allowed wiring regions, where adjacent mesh cells (i, j) and The connection parameters between them are determined by the following mapping relationship:

[0015] Resistance parameters: ;

[0016] Inductance parameters: ;

[0017] Capacitor parameters: ;

[0018] in, Let (i,j) be the metal density distribution parameters to be optimized for the grid cell (i,j). The unit length sheet resistance is provided by the design constraint parameter library; Permeability of free space; Capacitance per unit area; Effective line width; and These are the grid cell size parameters;

[0019] The mapping relationship is used as a parameterized distributed circuit model.

[0020] Specifically, the resistance mapping relationship This reflects the relationship between metal density and conductive cross-sectional area; the product of the metal densities of two grid cells determines the effective conductive path between them; inductance mapping relationship. This demonstrates the influence of metal density on magnetic field distribution; higher metal density results in more concentrated current paths and lower self-inductance. (Capacitance mapping relationship) It directly reflects the linear relationship between the metal area and the parasitic capacitance.

[0021] Using these analytical expressions, the system can accurately calculate the density distribution of any metal. The corresponding circuit performance includes voltage drop, power consumption, and parasitic effects. More importantly, these mappings are continuously differentiable, making it possible to subsequently employ gradient optimization algorithms.

[0022] Further, in S6, a set of frequency domain node voltage equations is constructed and solved to obtain the voltage distribution data of each grid cell, including: extracting the current density value of each grid cell from the grid attribute matrix as the current source excitation for the distributed circuit model; and based on the mapping relationship and the current metal density distribution parameters... The circuit parameter values ​​within the allowable wiring area are calculated; for each grid node within the allowable wiring area, a frequency domain node voltage equation is established; through node number mapping and admittance matrix assembly, all node voltage equations are integrated into a system-level sparse linear equation set; the sparse linear equation set is solved to obtain the voltage distribution data of each grid cell.

[0023] Furthermore, the frequency domain nodal voltage equation is expressed as follows: ;in, Let (i, j) be the voltage phasor to be determined for grid node (i, j); For the grid nodes adjacent to node (i, j) Voltage phasors; For node (i, j) and its neighboring nodes Admittance between;

[0024] In particular, the frequency domain node voltage equation established in this scheme fully encodes the influence of metal density in the admittance. In the parameters of capacitance C(i,j), firstly, it employs a frequency domain analysis method, which can simultaneously consider resistive voltage drop and dynamic effects caused by inductance and capacitance, which is particularly important for RF circuits; secondly, it uses admittance... In this form, the equation naturally expresses the effect of metal density on resistance and inductance in a unified way. The higher the metal density, the lower the resistance but the larger the parasitic capacitance. This trade-off is accurately reflected in the calculation results of voltage distribution.

[0025] More importantly, the voltage distribution obtained by solving this system of equations This directly reflects the power integrity level under the current metal density distribution ρ(i,j). Voltage amplitude The spatial distribution reveals which regions have excessive voltage drops, requiring increased metal density; while the voltage phase... The change reflects the degree of influence of parasitic inductance.

[0026] Further, in step S7, based on the voltage distribution data, a multi-objective evaluation function is constructed, encompassing voltage stability, metal usage, and density smoothness. The metal density distribution parameters are updated using the gradient descent method. The updated metal density distribution parameters are then substituted into step S5 to recalculate the circuit parameters of the distributed circuit model. Steps S6 and S7 are repeated until the change in the evaluation function is less than a preset convergence threshold, including:

[0027] The expression for the multi-objective evaluation function is: ;in, This is the weighting coefficient, with a value ranging from 0 to 1.

[0028] In particular, the reason why traditional design methods lead to excessive use of metal is fundamentally due to a lack of quantitative understanding of the balance between power integrity requirements and parasitic cost. When faced with a single metric like voltage drop, designers see only one optimization direction: increasing metal, because they cannot quantify the parasitic loss caused by the added metal.

[0029] This application introduces a second item. This makes the cost of using metals explicit, for every additional unit of metal density... It will be in accordance with The relationship between voltage drop and parasitic capacitance increases, directly affecting the frequency response and power consumption of RF circuits. This explicit cost function forces optimization algorithms to balance the increase in parasitic effects when improving voltage drop. Meanwhile, the third term... The introduction of this technology improves the optimization objectives from a manufacturing feasibility perspective, preventing drastic changes in metal density.

[0030] Further, in step S8, the optimized and converged metal density distribution parameters are binarized. Mesh cells with density values ​​greater than a preset threshold are set as metal regions, and the rest are set as blank regions. A layout data file is generated based on the binarization result, including: the optimized and converged metal density distribution parameters from step S7. By comparing with a preset binarization threshold By comparing the data, each grid cell within the allowable wiring area is divided into a metallic area or a blank area, generating a binary layout data file.

[0031] Another aspect of this application provides a radio frequency communication circuit layout design system, comprising: a parameter library construction module, which acquires a dataset of process parameters and performance indicators of the radio frequency communication circuit, and constructs a design constraint parameter library; a node feature extraction module, which parses the circuit topology, identifies the circuit node type and extracts node attribute information, and generates a node feature dataset containing node type, current characteristics and spatial location; a mesh mapping module, which discretizes the layout design area into a mesh cell array, establishes the correspondence between nodes and mesh cells through a spatial mapping function based on the node feature dataset, and generates a mesh attribute matrix reflecting the current distribution characteristics based on the node current characteristics mapped to each mesh cell; an electromagnetic interference analysis module, which calculates the electromagnetic interference intensity of each mesh cell based on the power consumption value and noise sensitivity value of each node in the node feature dataset, marks mesh cells with electromagnetic interference intensity exceeding a preset threshold as areas that need to be isolated, and generates an area marking matrix; and a circuit model construction module, which, based on the area marking matrix, determines the mesh cells not marked as areas that need to be isolated as allowed wiring areas, and constructs a parameterized distributed circuit for the allowed wiring areas. The model uses process parameters from the design constraint parameter library to establish a mapping relationship between the resistance, inductance, and capacitance parameters of the distributed circuit model and the metal density distribution parameters to be optimized. The voltage solution module uses the current distribution data in the grid attribute matrix as input excitation for the distributed circuit model. Based on the mapping relationship and the metal density distribution parameters, it calculates the circuit parameter values ​​of the distributed circuit model, constructs and solves a set of frequency domain node voltage equations to obtain the voltage distribution data of each grid cell. The optimization iteration module constructs a multi-objective evaluation function including voltage stability, metal usage, and density smoothness based on the voltage distribution data. It updates the metal density distribution parameters using the gradient descent method and passes the updated metal density distribution parameters to the circuit model construction module to recalculate the circuit parameters of the distributed circuit model. The voltage solution module and the optimization iteration module are repeatedly executed until the change in the evaluation function is less than a preset convergence threshold. The layout generation module binarizes the optimized and converged metal density distribution parameters, sets grid cells with density values ​​greater than a preset threshold as metal regions, and the rest as blank regions. It generates a layout data file based on the binarization results.

[0032] Compared to existing technologies, the advantages of this application are:

[0033] This application establishes a quantitative mapping model between metal density and electrical performance, fundamentally solving the problem of excessive parasitic effects introduced by the overuse of metal materials in RF circuit layout design. Traditional design methods lack a quantitative relationship between metal fill amount and circuit performance, and designers often adopt conservative design strategies to ensure power integrity, leading to the overuse of metal materials. This application establishes an analytical mapping relationship between metal density distribution parameters and resistance, inductance, and capacitance, quantitatively linking the physical structure of the layout with electrical performance; it uses a distributed RLC mesh model to accurately calculate voltage distribution and parasitic effects under different metal density distributions; it constructs a multi-objective evaluation function that includes voltage stability, metal usage, and density smoothness, and automatically searches for the optimal metal density distribution through a gradient optimization algorithm. Based on the actual current distribution and performance requirements, it quantitatively determines the minimum metal density required for each region, minimizing parasitic inductance and capacitance while meeting power integrity requirements, thus achieving a precise balance between power network performance and parasitic effects. Attached Figure Description

[0034] This application will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting; in these embodiments, the same reference numerals denote the same structures, wherein:

[0035] Figure 1 This is an exemplary flowchart illustrating a radio frequency communication circuit layout design method according to some embodiments of this application;

[0036] Figure 2 This is an exemplary flowchart illustrating the generation of a node feature dataset according to some embodiments of this application;

[0037] Figure 3 This is an exemplary flowchart illustrating the construction of a region marker matrix according to some embodiments of this application. Detailed Implementation

[0038] The methods and systems provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0039] like Figure 1As shown, the process involves acquiring data sets of process parameters and performance indicators for the RF communication circuit, and constructing a design constraint parameter library. The circuit topology is analyzed, circuit node types are identified, and node attribute information is extracted to generate a node feature dataset containing node type, current characteristics, and spatial location. The layout design area is discretized into a grid cell array. Based on the node feature dataset, a spatial mapping function is used to establish the correspondence between nodes and grid cells. Based on the node current characteristics mapped to each grid cell, a grid attribute matrix reflecting the current distribution characteristics is generated. Based on the power consumption and noise sensitivity values ​​of each node in the node feature dataset, the electromagnetic interference intensity experienced by each grid cell is calculated. Grid cells with electromagnetic interference intensity exceeding a preset threshold are marked as areas requiring isolation, generating an area marking matrix. Based on the area marking matrix, grid cells not marked as requiring isolation are identified as allowable wiring areas. A parameterized distributed circuit model is constructed for the allowable wiring areas, and design constraint parameters are used to... The process parameters in the database are used to establish a mapping relationship between the resistance, inductance, and capacitance parameters of the distributed circuit model and the metal density distribution parameters to be optimized. Current distribution data from the grid attribute matrix is ​​used as input excitation for the distributed circuit model. Based on the mapping relationship and the metal density distribution parameters, the circuit parameter values ​​of the distributed circuit model are calculated. A set of frequency domain node voltage equations is constructed and solved to obtain the voltage distribution data of each grid cell. Based on the voltage distribution data, a multi-objective evaluation function including voltage stability, metal usage, and density smoothness is constructed. The gradient descent method is used to update the metal density distribution parameters. The updated metal density distribution parameters are then used to recalculate the circuit parameters of the distributed circuit model. This process is repeated until the change in the evaluation function is less than a preset convergence threshold. The optimized and converged metal density distribution parameters are binarized. Grid cells with density values ​​greater than the preset threshold are set as metal regions, and the rest are set as blank regions. A layout data file is generated based on the binarization results.

[0040] S1: Design Parameter Acquisition and Data Preprocessing

[0041] Obtain the process parameter dataset of the radio frequency communication circuit. ,in, The number of metal layers. For the k-th layer of metal sheet resistance, Let the capacitance per unit area be the capacitance of the k-th layer. The thickness of the interlayer medium. The dielectric constant is used to obtain the circuit performance index dataset. ,in, Where P is the operating frequency, BW is the power, and NF is the bandwidth. Representing the third-order intersection point, establish a parameter priority weight vector. ,in, ;

[0042] S2: Circuit Topology Analysis and Node Extraction

[0043] Retrieve the circuit netlist file and construct the circuit topology. Where V is the set of nodes and E is the set of edges; the critical path algorithm is executed to identify the main path of signal transmission. Extract the power node set Sensitive Node Set and power / ground port collection Assign an attribute vector to each node. Record node type, DC current, AC current spectrum and preset coordinates;

[0044] S3: Mapping and Function Mapping of Regions

[0045] like Figure 2 As shown, the layout area is quantized into an M×N grid matrix, with a grid size of... , ,in, and Represent the length and width of the map area respectively; establish a functional module mapping matrix. Each grid cell is identified as belonging to a functional module; based on the spatial coordinate information of the nodes in the generated node feature dataset, a spatial mapping function is constructed to map the spatial coordinates of each node. Mapped to the corresponding grid cell index (i, j), where, , Based on the mapping result of the spatial mapping function, the set of nodes mapped to each grid cell (i, j) is extracted. The DC current values ​​and AC current spectrum data of each node in the set are superimposed to generate a current density distribution matrix. Where δ is the Dirac function; arrange the current density values ​​of all grid cells according to the grid index to construct a grid attribute matrix, and the elements of the grid attribute matrix are... This represents the current density value of the grid cell (i, j).

[0046] S4: Sensitive Module Identification and Isolation Area Setting:

[0047] like Figure 3 As shown, based on the partitioned subset of power nodes, the power consumption value of each power node is extracted. and spatial coordinates;

[0048] For each grid cell (i, j) in the grid cell array generated in step S3, calculate the Euclidean distance between the grid cell and each power node. ;

[0049] Based on the inverse square relationship between power consumption and distance, the electromagnetic interference weight experienced by each grid cell is calculated. ;

[0050] The calculated electromagnetic interference weight With the preset isolation threshold When comparing, If the condition is met, the grid cell is marked as 1; otherwise, it is marked as 0, generating a binarized region labeling matrix. This is used to determine the allowable wiring area in step S5.

[0051] S5: Distributed RLC Mesh Modeling

[0052] According to the region label matrix It identifies all grid cells with a flag value of 0, which constitute the wiring allowable area and can be used for metal wiring design.

[0053] Each grid cell (i, j) within the wiring allowable area is treated as a circuit node. Adjacent grid cells are connected in series by a resistor R and an inductor L. Each grid cell is grounded through a parallel capacitor C, forming a two-dimensional distributed RLC network.

[0054] Define a metal density parameter for each grid cell (i, j). , represents the metal fill rate within the grid cell, where ρ=0 indicates no metal, ρ=1 indicates complete metal filling, and 0<ρ<1 indicates partial filling.

[0055] (1) Resistance parameter mapping: ;

[0056] in: The Euclidean distance between the centers of adjacent grid cells;

[0057] Sheet resistance per unit length (Ω / □) is determined by the manufacturing process, where □ represents sheet resistance, which refers to the resistance value per unit square film.

[0058] The effective width of the metal wire;

[0059] It represents the geometric mean of the metal density of two grid cells, reflecting the effective conductivity of the connection path;

[0060] (2) Inductance parameter mapping:

[0061] ;

[0062] in: Permeability of free space;

[0063] Logarithmic terms This reflects the nonlinear effect of metal density on inductance; the higher the metal density, the smaller the inductance.

[0064] (3) Capacitor parameter mapping: ;

[0065] in:

[0066] The capacitance per unit area (F / m²) is determined by the thickness of the dielectric layer and the dielectric constant.

[0067] Area of ​​the grid cell;

[0068] This indicates the percentage of metal area; capacitance is directly proportional to the metal area.

[0069] Integrating the above mapping relationships forms a system based on metal density distribution. The parameterized circuit model is designed to handle variables. This model can automatically calculate the corresponding RLC parameter values ​​based on different metal density distributions, which can be used for subsequent circuit simulation and optimization.

[0070] S6: Construction and Solving of Frequency Domain Equations

[0071] Based on the mapping relationship and current metal density distribution parameters Calculate the resistance parameters between adjacent grid cells within the allowable area of ​​the wiring. Inductance parameters and the capacitance parameters of each grid cell. ;

[0072] For each grid node (i, j) within the allowable wiring area, establish the frequency domain node voltage equation: ;in, Let (i, j) be the voltage phasor to be determined for grid node (i, j); For the grid nodes adjacent to node (i, j) Voltage phasors; For node (i, j) and its neighboring nodes between the admittances, where and The resistance and inductance parameters are defined; j is the imaginary unit; The operating angular frequency is determined from the performance index dataset; Let (i, j) be the capacitance parameter of the grid cell (i, j). The current density value is the value of the grid attribute matrix; and These are the grid cell size parameters;

[0073] Linear indexing is applied to all grid nodes within the allowable wiring area, mapping the two-dimensional coordinates (i, j) to a one-dimensional index. Where N is the number of grid columns, representing the voltage of all grid nodes. Arranged in order of index k, a voltage vector of length K is formed. Where K is the total number of nodes within the allowable cabling area;

[0074] Construct a K×K dimensional total admittance matrix Its k-th row, the Column elements Determined according to the following rules:

[0075] when Time (diagonal element) The summation iterates through all nodes adjacent to node (i, j). ;

[0076] When node k and Adjacent elements (non-diagonal elements) , representing the mutual admittance between two nodes;

[0077] When node k and When they are not adjacent, ;

[0078] Construct a current vector I of length K, whose k-th element... , represents the equivalent current source corresponding to node (i, j);

[0079] To build The combination of V and I forms a sparse linear system of equations. This set of equations represents the circuit balance equations in the frequency domain for the entire allowable wiring area.

[0080] Solving the sparse linear equations yields the voltage distribution data for each grid cell. Specifically, in this scheme, the sparse linear equations... Refers to the coefficient matrix A system of linear equations with most elements equal to zero. Specifically, since each node in the distributed RLC mesh model is electrically connected to only its four adjacent nodes (top, bottom, left, and right), the total admittance matrix is ​​K×K dimensional. In this system, each row contains at most 5 non-zero elements (1 diagonal element and at most 4 off-diagonal elements), with the remaining positions containing zeros. For a system with K nodes, the number of non-zero elements is approximately 5K, much smaller than... A matrix with a very low percentage of non-zero elements is called a sparse matrix.

[0081] More specifically, for sparse matrices Preprocessing is performed by constructing a preconditioner M using either incomplete LU decomposition (ILU) or algebraic multigrid (AMG) methods, such that... The condition number is significantly reduced, accelerating iterative convergence; due to It is a complex sparse matrix with a symmetric structure. Iterative solutions are obtained using the preconditional conjugate gradient method (PCG) or the generalized minimum residual method (GMRES): Initialization: Set the initial voltage vector. Calculate the initial residual Iterative updates: ,in, For the search direction, Let the step size be ; convergence criterion: when (like The iteration stops when the solution is obtained. After the solution is completed, the one-dimensional voltage vector is... According to the index mapping relationship The inverse transformation restores the voltage distribution to a two-dimensional grid. This yields the complex voltage value, including amplitude, for each grid cell within the permissible wiring area. and phase This provides foundational data for subsequent performance evaluation and optimization.

[0082] S7: Multi-objective optimization and density update

[0083] Construct the comprehensive objective function:

[0084] ;

[0085] Among them, the first item The second term is a voltage stability index, which improves the uniformity of voltage distribution by minimizing the sum of squares of voltage amplitudes. The third item is a metal usage indicator to control the total amount of metal materials used. This is a density smoothness index, where, This represents the spatial gradient of metal density, used to ensure the continuity of metal density between adjacent grid cells; This is the weighting coefficient, with a value ranging from 0 to 1. ; For the voltage phasor of the grid node (i, j) obtained in step S6, Indicates voltage amplitude;

[0086] Calculate the gradient ∂J / ∂ρ(i,j) of the objective function with respect to density, and update it using the conjugate gradient method: Where η is the learning rate parameter, This represents the metal density value in the current iteration. The updated metal density value; the updated metal density distribution parameters Substitute the mapping relationship from step S5 and recalculate the circuit parameter values ​​of the distributed circuit model; repeat steps S6 and S7 to calculate the change in the evaluation function between two adjacent iterations. When the change is less than the preset convergence threshold ε, the optimization process is considered to have converged, and the final metal density distribution parameters are output.

[0087] S8: Layout Generation and Verification Feedback

[0088] Obtain the metal density distribution parameters after optimization and convergence in step S7. Binarization is performed on each grid cell within the wiring allowable area: when When, set This indicates that the mesh cell is a metallic region; when When, set This indicates that the grid cell is a blank area; where, The preset binarization threshold has a value range of [0.4, 0.6].

[0089] For the binarized layout matrix Morphological processing is performed to eliminate isolated points and fill small holes to ensure the connectivity of the metal area;

[0090] The processed binarized layout matrix Convert to a layout data file, where each grid cell with a value of 1 is converted into a metal polygon at the corresponding coordinates, and grid cells with a value of 0 remain blank;

[0091] Electromagnetic field simulation was performed on the generated layout to verify it, and actual circuit parameters were extracted and performance indicators were calculated. The simulation results Compared with the target value in the performance metric dataset in step S1 Compare and calculate the deviation ;

[0092] When the deviation ΔP is greater than the preset tolerance value, the weighting coefficient in step S7 is adjusted according to the deviation information. Or binarization threshold Return to step S5 and re-execute the optimization process; when the deviation ΔP is less than or equal to the preset tolerance value, output the final layout data file.

[0093] The foregoing illustrative description of the present application and its embodiments is not restrictive and can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. The accompanying drawings are only one embodiment of the present application, and the actual structure is not limited thereto. Therefore, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the present application, such designs should fall within the scope of protection of this application. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" preceding an element does not exclude the inclusion of "a plurality" of that element. Terms such as "first," "second," etc., are used to indicate names and do not indicate any specific order.

Claims

1. A method for designing radio frequency communication circuit layouts, characterized in that, include: S1, Obtain the process parameter dataset and performance index dataset of the RF communication circuit, and construct the design constraint parameter library; S2, analyze the circuit topology, identify the circuit node types and extract node attribute information, and generate a node feature dataset containing node type, current characteristics and spatial location; S3 discretizes the layout design area into a grid cell array. Based on the node feature dataset, a spatial mapping function is used to establish the correspondence between nodes and grid cells. Based on the node current characteristics mapped to each grid cell, a grid attribute matrix reflecting the current distribution characteristics is generated. S4. Based on the power consumption and noise sensitivity values ​​of each node in the node feature dataset, calculate the electromagnetic interference intensity of each grid cell, mark the grid cells with electromagnetic interference intensity exceeding the preset threshold as regions that need to be isolated, and generate a region marking matrix. S5. Based on the region marking matrix, the grid cells that are not marked as needing isolation are identified as the wiring allowable region. A parameterized distributed circuit model is constructed for the wiring allowable region. Using the process parameters in the design constraint parameter library, the mapping relationship between the resistance, inductance, and capacitance parameters of the distributed circuit model and the metal density distribution parameters to be optimized is established. S6. The current distribution data in the grid attribute matrix is ​​used as the input excitation of the distributed circuit model. Based on the mapping relationship and metal density distribution parameters, the circuit parameter values ​​of the distributed circuit model are calculated, the frequency domain node voltage equation system is constructed and solved, and the voltage distribution data of each grid cell is obtained. S7. Based on the voltage distribution data, construct a multi-objective evaluation function that includes voltage stability, metal usage and density smoothness. Use the gradient descent method to update the metal density distribution parameters. Substitute the updated metal density distribution parameters into step S5 to recalculate the circuit parameters of the distributed circuit model. Repeat steps S6 and S7 until the change in the evaluation function is less than the preset convergence threshold. S8 performs binarization on the optimized and converged metal density distribution parameters, sets grid cells with density values ​​greater than a preset threshold as metal regions, and sets the rest as blank regions, and generates a layout data file based on the binarization results.

2. The radio frequency communication circuit layout design method according to claim 1, characterized in that: S2 generates a node feature dataset containing node type, current characteristics, and spatial location, including: Read the circuit netlist file, extract the circuit element connection information, and construct a circuit topology graph containing the node set V and the edge set E; A path search algorithm is executed on the circuit topology to identify the signal transmission path from the input to the output. Based on the power consumption characteristics and noise tolerance of each node on the signal transmission path, the node set V is divided into a power node subset, a sensitive node subset, and a power supply node subset. The power node subset includes nodes whose power consumption is greater than a preset power consumption threshold, and the sensitive node subset includes nodes whose noise tolerance is less than a preset noise threshold. For each node in the node set V, construct a multi-dimensional attribute vector. The attribute vector contains the node type identifier, DC current value, AC current spectrum data and node spatial coordinate information. Build a node feature dataset based on the attribute vectors of each node.

3. The radio frequency communication circuit layout design method according to claim 1, characterized in that: S3 generates a grid attribute matrix reflecting the characteristics of the current distribution, including: Based on the size parameters and preset resolution parameters of the layout design area, the layout design area is discretized into a grid cell array; Based on the node spatial coordinate information in the node feature dataset, each node is mapped to the corresponding grid cell using a spatial mapping function; For each grid cell, data aggregation is performed based on the current characteristic data of the nodes mapped to the corresponding grid cell to generate the current density value of the corresponding grid cell; A grid attribute matrix is ​​constructed based on the current density values ​​of each grid cell.

4. The radio frequency communication circuit layout design method according to claim 1, characterized in that: S4 generates a region label matrix, including: Extract the power consumption value of each power node from the power node subset. and spatial coordinates; For each grid cell (i, j) in the grid cell array, calculate the Euclidean distance between the corresponding grid cell and each power node. ; According to Euclidean distance Calculate the electromagnetic interference weight of each grid cell. ;in, Represents a subset of power nodes; The calculated electromagnetic interference weight With the preset isolation threshold When comparing, When the condition is met, the corresponding grid cell is marked as 1; otherwise, it is marked as 0, generating a binary region labeling matrix. .

5. The radio frequency communication circuit layout design method according to claim 1, characterized in that: S5. Establish the mapping relationship between the resistance, inductance, and capacitance parameters of the distributed circuit model and the metal density distribution parameters to be optimized, including: According to the region label matrix Grid cells with a flag value of 0 are defined as allowed wiring areas; Construct a distributed RLC mesh model for the wiring allowable region, where adjacent mesh cells (i, j) and The connection parameters between them are determined by the following mapping relationship: Resistance parameters: ; Inductance parameters: ; Capacitor parameters: ; in, Let (i,j) be the metal density distribution parameters to be optimized for the grid cell (i,j). The unit length sheet resistance is provided by the design constraint parameter library; Permeability of free space; Capacitance per unit area; Effective line width; and is the mesh cell size parameter; d is the Euclidean distance between the center points of adjacent mesh cells (i,j) and (i',j'); The mapping relationship is used as a parameterized distributed circuit model.

6. The radio frequency communication circuit layout design method according to claim 5, characterized in that: S6. Construct and solve the frequency domain nodal voltage equations to obtain the voltage distribution data of each grid cell, including: The current density values ​​of each grid cell are extracted from the grid attribute matrix and used as the current source excitation for the distributed circuit model. Based on the mapping relationship and the current metal density distribution parameter ρ(i,j), calculate the circuit parameter values ​​within the allowable wiring area; For each grid node within the allowable wiring area, establish the frequency domain node voltage equation; By mapping node numbers and assembling admittance matrices, all node voltage equations are integrated into a system-level sparse linear equation set. Solve the sparse linear equations to obtain the voltage distribution data of each grid cell.

7. The radio frequency communication circuit layout design method according to claim 6, characterized in that: The frequency domain nodal voltage equation is expressed as follows: ； in, Let (i, j) be the voltage phasor to be determined for grid node (i, j); For the grid nodes adjacent to node (i, j) Voltage phasors; For node (i, j) and its neighboring nodes Admittance between; j is the imaginary unit; The operating angular frequency; The current density value is the value of the grid attribute matrix.

8. The radio frequency communication circuit layout design method according to claim 1, characterized in that: S7, based on the construction of a multi-objective evaluation function that includes voltage stability, metal content, and density smoothness, including: The expression for the multi-objective evaluation function is: ； in, These are weighting coefficients, ranging from 0 to 1; where, Represents the voltage phasor of the grid node (i, j); For voltage stability indicators; The spatial gradient of metal density; This is an indicator of metal usage. This is an index of density smoothness.

9. The radio frequency communication circuit layout design method according to claim 1, characterized in that: S8 performs binarization processing on the optimized and converged metal density distribution parameters, including: Based on step S7, optimize the converged metal density distribution parameters. By comparing with a preset binarization threshold By comparing the data, each grid cell within the allowable wiring area is divided into a metal area or a blank area, generating a binary layout data file.

10. A radio frequency communication circuit layout design system, characterized in that, include: The parameter library construction module is used to obtain the process parameter dataset and performance index dataset of RF communication circuits and build a design constraint parameter library. The node feature extraction module is used to parse the circuit topology, identify the circuit node type and extract node attribute information, and generate a node feature dataset containing node type, current characteristics and spatial location. The grid mapping module is used to discretize the layout design area into a grid cell array. Based on the node feature dataset, it establishes the correspondence between nodes and grid cells through a spatial mapping function. Based on the node current characteristics mapped to each grid cell, it generates a grid attribute matrix that reflects the current distribution characteristics. The electromagnetic interference analysis module is used to calculate the electromagnetic interference intensity of each grid cell based on the power consumption and noise sensitivity values ​​of each node in the node feature dataset, mark the grid cells with electromagnetic interference intensity exceeding a preset threshold as areas that need to be isolated, and generate an area marking matrix. The circuit model building module is used to identify unmarked grid cells that need to be isolated as wiring allowable regions based on the region marking matrix, build parameterized distributed circuit models for the wiring allowable regions, and establish the mapping relationship between the resistance, inductance, and capacitance parameters of the distributed circuit model and the metal density distribution parameters to be optimized using the process parameters in the design constraint parameter library. The voltage solving module is used to take the current distribution data in the grid attribute matrix as the input excitation of the distributed circuit model, calculate the circuit parameter values ​​of the distributed circuit model based on the mapping relationship and metal density distribution parameters, construct and solve the frequency domain node voltage equation system, and obtain the voltage distribution data of each grid cell. The optimization iteration module is used to construct a multi-objective evaluation function that includes voltage stability, metal usage and density smoothness based on voltage distribution data. It updates the metal density distribution parameters using the gradient descent method, and passes the updated metal density distribution parameters to the circuit model construction module to recalculate the circuit parameters of the distributed circuit model. It controls the voltage solution module and the optimization iteration module to execute repeatedly until the change in the evaluation function is less than the preset convergence threshold. The layout generation module is used to binarize the optimized and converged metal density distribution parameters, set grid cells with density values ​​greater than a preset threshold as metal regions, and set the rest as blank regions, and generate a layout data file based on the binarization results.

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