An oscillator acceleration circuit, chip, and electronic device

Abstract

An oscillator acceleration circuit for accelerating oscillation startup includes an inverting amplifier, a feedback resistor, and an acceleration circuit. The inverting amplifier has an input terminal and an output terminal, correspondingly coupled to the input and output terminals of the oscillator. The feedback resistor and the acceleration circuit are coupled between the input and output terminals of the oscillator. The acceleration circuit includes two N-type transistors and three capacitors. The drains of the first and second N-type transistors are coupled to a first reference voltage, and the sources of the first and second N-type transistors are coupled to a second reference voltage. The gate of the second N-type transistor is coupled to the drain of the first N-type transistor, and the gate of the first N-type transistor is coupled to the drain of the second N-type transistor. A first capacitor is coupled between the drain of the first N-type transistor and the input terminal of the oscillator; a second capacitor is coupled between the drain of the second N-type transistor and the output terminal of the oscillator; and a third capacitor is coupled between the sources of the first and second N-type transistors.

Description

Technical Field

[0001] This work relates to a circuit used in oscillators, particularly an oscillator acceleration circuit, chip, and electronic device. Background Technology

[0002] In circuit systems, crystal oscillators are typically required to provide a precise clock. Compared to other clock oscillation circuits, such as RC relaxation oscillators, crystal clocks offer superior clock stability and low clock jitter, and are commonly used as the clock source for frequency multiplication or frequency synthesis. However, crystal oscillators have relatively long start-up times. For example, MHz-level crystal oscillators typically have start-up times in the millisecond range, while kHz-level oscillators typically have start-up times in the seconds range. Therefore, in scenarios requiring rapid crystal wake-up, such as in Bluetooth, an additional fast-start circuit is needed to accelerate the crystal oscillator's start-up process. Summary of the Invention

[0003] This invention provides an oscillator acceleration circuit for accelerating the start-up process of a crystal oscillator.

[0004] This invention provides an oscillator acceleration circuit for accelerating the start-up of an oscillator. The oscillator has an input terminal and an output terminal. The oscillator acceleration circuit includes an inverting amplifier, a feedback resistor, and an acceleration circuit. The inverting amplifier has an input terminal and an output terminal correspondingly coupled to the input terminal and the output terminal of the oscillator. The feedback resistor is coupled between the input terminal and the output terminal of the oscillator. The acceleration circuit is coupled between the input terminal and the output terminal of the oscillator and includes a first N-type transistor, a second N-type transistor, a first capacitor, a second capacitor, and a third capacitor. The drain of the first N-type transistor is coupled to a first reference voltage, and the source of the first N-type transistor is coupled to a second reference voltage, wherein the first reference voltage is higher than the second reference voltage. The drain of the second N-type transistor is coupled to the first reference voltage, and the source of the second N-type transistor is coupled to the second reference voltage. The gate of the second N-type transistor is coupled to the drain of the first N-type transistor, and the gate of the first N-type transistor is coupled to the drain of the second N-type transistor. The first capacitor is coupled between the drain of the first N-type transistor and the input terminal of the oscillator; the second capacitor is coupled between the drain of the second N-type transistor and the output terminal of the oscillator. The third capacitor is coupled between the source of the first N-type transistor and the source of the second N-type transistor.

[0005] In some embodiments, the acceleration circuit further includes a first current source and a second current source; the first current source is coupled between the drain of the first N-type transistor and the first reference voltage, and the second current source is coupled between the drain of the second N-type transistor and the first reference voltage.

[0006] In some embodiments, the current value provided by the first current source is equal to the current value provided by the second current source.

[0007] In some embodiments, the accelerating circuit further includes a third N-type transistor, a fourth N-type transistor, and a fifth N-type transistor, and a third current source; the drain of the third N-type transistor is coupled to its own gate, and the source of the third N-type transistor is coupled to the second reference voltage. The gate of the fourth N-type transistor is coupled to the gate of the third N-type transistor, the drain of the fourth N-type transistor is coupled to the source of the first N-type transistor, and the source of the fourth N-type transistor is coupled to the second reference voltage. The gate of the fifth N-type transistor is coupled to the gate of the third N-type transistor, the drain of the fifth N-type transistor is coupled to the source of the second N-type transistor, and the source of the fifth N-type transistor is coupled to the second reference voltage. The third current source is coupled between the drain of the third N-type transistor and the first reference voltage.

[0008] In some embodiments, the acceleration circuit further includes a fourth current source and a fifth current source; the fourth current source is coupled between the source of the first N-type transistor and the second reference voltage, and the fifth current source is coupled between the source of the second N-type transistor and the second reference voltage.

[0009] In some embodiments, the acceleration circuit further includes a first resistor and a second resistor, the first resistor being coupled between the drain of the first N-type transistor and the first reference voltage, and the second resistor being coupled between the drain of the second N-type transistor and the first reference voltage.

[0010] In some embodiments, the resistance value of the first resistor is equal to the resistance value of the second resistor.

[0011] In some embodiments, the accelerating circuit further includes a third N-type transistor, a fourth N-type transistor, and a fifth N-type transistor, and a constant current source; the drain of the third N-type transistor is coupled to its own gate, and the source of the third N-type transistor is coupled to the second reference voltage. The gate of the fourth N-type transistor is coupled to the gate of the third N-type transistor, the drain of the fourth N-type transistor is coupled to the source of the first N-type transistor, and the source of the fourth N-type transistor is coupled to the second reference voltage. The gate of the fifth N-type transistor is coupled to the gate of the third N-type transistor, the drain of the fifth N-type transistor is coupled to the source of the second N-type transistor, and the source of the fifth N-type transistor is coupled to the second reference voltage. The constant current source is coupled between the drain of the third N-type transistor and the first reference voltage.

[0012] In some embodiments, the acceleration circuit further includes a fourth current source and a fifth current source; the fourth current source is coupled between the source of the first N-type transistor and the second reference voltage, and the fifth current source is coupled between the source of the second N-type transistor and the second reference voltage.

[0013] In some embodiments, the acceleration circuit is coupled between the input and output terminals of the oscillator, wherein the acceleration circuit provides a system function that is the same as the system function provided by the parallel-connected resistor and capacitor, wherein the resistance of the resistor is less than zero, and the capacitance of the capacitor is less than zero when the oscillator operates at an intermediate frequency and greater than zero when the oscillator operates at a low frequency.

[0014] In some embodiments, the oscillator acceleration circuit further includes a counter coupled between the output terminal of the oscillator and the acceleration circuit, the counter controlling the acceleration circuit according to the oscillation signal generated by the oscillator. This invention provides an oscillator acceleration circuit for accelerating the start-up of an oscillator. The oscillator has an input terminal and an output terminal, and the electrical oscillator acceleration circuit includes an inverting amplifier, a feedback resistor, and an acceleration circuit. The inverting amplifier has an input terminal and an output terminal correspondingly coupled to the input terminal and the output terminal of the oscillator, and the feedback resistor is coupled between the input terminal and the output terminal of the oscillator. The acceleration circuit is coupled between the input terminal and the output terminal of the oscillator, and the acceleration circuit includes a first P-type transistor, a second P-type transistor, a first capacitor, a second capacitor, and a third capacitor; the source of the first P-type transistor is coupled to a first reference voltage, and the drain of the first P-type transistor is coupled to a second reference voltage, wherein the first reference voltage is higher than the second reference voltage. The source of the second P-type transistor is coupled to the first reference voltage, the drain of the first P-type transistor is coupled to the second reference voltage, the gate of the second P-type transistor is coupled to the drain of the first P-type transistor, and one gate of the first P-type transistor is coupled to the drain of the second P-type transistor. The first capacitor is coupled between the drain of the first P-type transistor and the input terminal of the oscillator, the second capacitor is coupled between the drain of the second P-type transistor and the output terminal of the oscillator, and the third capacitor is coupled between the source of the first P-type transistor and the source of the second P-type transistor.

[0015] In some embodiments, the acceleration circuit further includes a first current source and a second current source; the first current source is coupled between the drain of the first P-type transistor and the second reference voltage, and the second current source is coupled between the drain of the second P-type transistor and the second reference voltage.

[0016] In some embodiments, the current value provided by the first current source is equal to the current value provided by the second current source.

[0017] In some embodiments, the accelerating circuit further includes a third P-type transistor, a fourth P-type transistor, and a fifth P-type transistor, and a third current source; the source of the third P-type transistor is coupled to its own gate, and the drain of the third P-type transistor is coupled to the second reference voltage. The gate of the fourth P-type transistor is coupled to the gate of the third P-type transistor, and the drain of the fourth P-type transistor is coupled to the source of the first P-type transistor, and the source of the fourth P-type transistor is coupled to the first reference voltage. The gate of the fifth P-type transistor is coupled to the gate of the third P-type transistor, and the drain of the fifth P-type transistor is coupled to the source of the second P-type transistor, and the source of the fifth P-type transistor is coupled to the first reference voltage. The third current source is coupled between the drain of the third P-type transistor and the second reference voltage.

[0018] In some embodiments, the acceleration circuit further includes a fourth current source and a fifth current source; the fourth current source is coupled between the source of the first P-type transistor and the first reference voltage, and the fifth current source is coupled between the source of the second P-type transistor and the first reference voltage.

[0019] In some embodiments, the acceleration circuit further includes a first resistor and a second resistor, the first resistor being coupled between the drain of the first P-type transistor and the second reference voltage, and the second resistor being coupled between the drain of the second P-type transistor and the second reference voltage.

[0020] In some embodiments, the resistance value of the first resistor is equal to the resistance value of the second resistor.

[0021] In some embodiments, the accelerating circuit further includes a third P-type transistor, a fourth P-type transistor, a fifth P-type transistor, and a constant current source; the drain of the third P-type transistor is coupled to its own gate, and the source of the third P-type transistor is coupled to the first reference voltage. The gate of the fourth P-type transistor is coupled to the gate of the third P-type transistor, the drain of the fourth P-type transistor is coupled to the source of the first P-type transistor, and the source of the fourth P-type transistor is coupled to the first reference voltage. The gate of the fifth P-type transistor is coupled to the gate of the third P-type transistor, the drain of the fifth P-type transistor is coupled to the source of the second P-type transistor, and the source of the fifth P-type transistor is coupled to the first reference voltage. The constant current source is coupled between the drain of the third P-type transistor and the second reference voltage.

[0022] In some embodiments, the acceleration circuit further includes a fourth current source and a fifth current source, the fourth current source being coupled between the first reference voltage and the source of the first P-type transistor, and the fifth current source being coupled between the first reference voltage and the source of the second P-type transistor.

[0023] In some embodiments, the acceleration circuit is coupled between the input and output terminals of the oscillator, wherein the acceleration circuit provides a system function that is the same as the system function provided by the parallel-connected resistor and capacitor, wherein the resistance of the resistor is less than zero, and the capacitance of the capacitor is less than zero when the oscillator operates at an intermediate frequency and greater than zero when the oscillator operates at a low frequency.

[0024] When the oscillator operates at a low frequency, the capacitance of the capacitor is greater than zero; when the oscillator operates at a medium frequency, the capacitance of the capacitor is less than zero.

[0025] In some embodiments, the oscillator acceleration circuit further includes a counter coupled between the output terminal of the oscillator and the acceleration circuit, the counter controlling the acceleration circuit according to the oscillation signal generated by the oscillator.

[0026] The present invention also provides a chip comprising the aforementioned oscillator acceleration circuit.

[0027] This invention provides an electronic device comprising the aforementioned chip and the oscillator coupled to the chip.

[0028] The oscillator acceleration circuit in this invention can effectively enable the crystal oscillator to quickly establish and reach stability, thereby shortening the crystal oscillator's start-up time. Attached Figure Description

[0029] The following implementation will refer to the accompanying drawings, which will be briefly described below.

[0030] Figure 1 This is a circuit diagram of an embodiment of the oscillation signal generation circuit disclosed herein.

[0031] Figure 2 for Figure 1 The equivalent circuit diagram of the oscillator.

[0032] Figure 3 for Figure 1 A circuit diagram of the first embodiment of the acceleration circuit in the oscillation signal generation circuit.

[0033] Figure 4a for Figure 3The impedance analysis diagrams of the first N-type transistor, the second N-type transistor, the fourth N-type transistor, the fifth N-type transistor, and the third capacitor are shown.

[0034] Figure 4b for Figure 3 The equivalent circuit of the first N-type transistor, the second N-type transistor, the fourth N-type transistor, the fifth N-type transistor, the first capacitor, the second capacitor, and the third capacitor is shown.

[0035] Figure 4c for Figure 4b The equivalent circuit.

[0036] Figure 5 for Figure 1 The circuit diagram of the second embodiment of the acceleration circuit in the oscillation signal generation circuit.

[0037] Figure 6 for Figure 1 A circuit diagram of the third embodiment of the acceleration circuit in the oscillation signal generation circuit.

[0038] Figure 7 for Figure 1 The circuit diagram of the fourth embodiment of the acceleration circuit in the oscillation signal generation circuit.

[0039] Figure 8 for Figure 1 The circuit diagram of the fifth embodiment of the acceleration circuit in the oscillation signal generation circuit.

[0040] Figure 9 for Figure 1 The circuit diagram of the sixth embodiment of the acceleration circuit in the oscillation signal generation circuit.

[0041] Figure 10 for Figure 1 The circuit diagram of the seventh embodiment of the acceleration circuit in the oscillation signal generation circuit.

[0042] Figure 11 for Figure 1 The circuit diagram of the eighth embodiment of the acceleration circuit in the oscillation signal generation circuit. Detailed Implementation

[0043] This disclosure provides several different implementations or embodiments that can be used to achieve different features of the invention. For the sake of simplicity, this disclosure also describes examples of specific components and arrangements. Please note that these specific examples are provided for illustrative purposes only and are not intended to be limiting. For example, in the following description of how a first feature is on or above a second feature, some embodiments may be included where the first and second features are in direct contact, while other different embodiments may be included where there are other features between the first and second features such that the first and second features are not in direct contact. Furthermore, the various examples in this disclosure may use repeated reference numerals and / or textual annotations to simplify and clarify the document; these repeated reference numerals and annotations do not represent a correlation between different embodiments and / or configurations. Moreover, in the following description, "coupled" means not only that components are directly coupled to each other, but also that components are coupled to each other with another component inserted therebetween.

[0044] Figure 1 A circuit diagram illustrating an embodiment of the oscillation signal generation circuit disclosed herein is provided. Please refer to... Figure 1 The oscillation signal generation circuit 10 includes an oscillator 100 and an oscillator acceleration circuit 200. The oscillator 100 has an input terminal XI and an output terminal XO. The oscillator acceleration circuit 200 is coupled between the input terminal XI and the output terminal XO of the oscillator 100 to enable the crystal oscillator to quickly establish and reach stability, thereby shortening the start-up time of the crystal oscillator. In some embodiments, the oscillator 100 can be implemented using a quartz crystal. Figure 2 The equivalent circuit diagram of the oscillator of this invention is shown below. Please refer to... Figure 2 The oscillator 100 may include capacitors Cm and Cshunt, inductor Lm and resistor Rm; inductor Lm, resistor Rm and capacitor Cm are connected in series and then connected in parallel with capacitor Cshunt, and the end of inductor Lm coupled to capacitor Cshunt serves as the input terminal X1 of oscillator 100, and the end of capacitor Cm coupled to Cshunt serves as the output terminal XO of oscillator 100.

[0045] Rereference Figure 1The oscillation signal generation circuit 200 includes an inverting amplifier 202, a feedback resistor 204, and an acceleration circuit 206. The input terminal of the inverting amplifier 202 is coupled to the input terminal XI of the oscillator 100, and the output terminal of the inverting amplifier 202 is coupled to the output terminal XO of the oscillator 100, providing energy for crystal oscillation. The gain of the inverting amplifier 202 is negative, and the absolute value of the gain is greater than 1, amplifying the signal generated by the oscillator 100. The oscillation signal is output from the main signal output terminal XO_CLK as a clock signal (clock plus) for example, used by an external circuit; in some embodiments, the oscillator 100 can generate a sine wave. The feedback resistor 204 is coupled between the input terminal XI and the output terminal XO of the oscillator 100. The acceleration circuit 206 is coupled between the input terminal XI and the output terminal XO of the oscillator 100; in other words, the acceleration circuit 206 is connected in parallel across the inverting amplifier 202. Acceleration circuit 206 provides a system function that is identical to the system function provided by the parallel-connected resistor Rp and capacitor Cp; wherein the resistance value of resistor Rp is less than zero. Acceleration circuit 206 provides additional drive capability to oscillator 100 to speed up the start-up process.

[0046] The oscillator acceleration circuit 200 further includes a counter 208 and a buffer 210; the buffer 210 is coupled between the output of the inverting amplifier 202 and the main signal output XO_CLK. The counter 208 is coupled to the output of the buffer 210; the counter 208 periodically counts the number of oscillation signals transmitted to the main signal output XO_CLK, and shuts down the acceleration circuit 200 when it determines that the oscillator 100 has entered a stable state; thereby, the additional losses caused by the acceleration circuit 200 and the shift in the oscillation frequency of the oscillator 100 caused by negative capacitance can be avoided. The buffer 210 may be, for example, a pulse wave generator for a square wave buffer. Wherein, when the level of the sine wave output by the oscillator 100 is greater than the threshold of the buffer 210, the square wave may have a first state (high level state); when the level of the sine wave provided by the oscillator 100 is less than the threshold of the buffer 210, the square wave may have a second state (low level state). In some embodiments, the pulse wave generated by the buffer 210 may be a rectangular wave with a duty cycle of equal to 50%, such as a square wave. In some embodiments, the pulse wave generated by the buffer 210 may be a rectangular wave with a duty cycle other than 50%.

[0047] The oscillator acceleration circuit 200 may further include a first load capacitor CL1 and a second load capacitor CL2; the first load capacitor CL1 is coupled to the input terminal X1 of the oscillator 100, and the second load capacitor CL2 is coupled to the output terminal XO of the oscillator 100. Adjusting the first load capacitor CL1 and the second load capacitor CL2 can be used to reduce... Figure 2The effects of the capacitor Chaunt and the trace capacitance in the parallel resonant circuit shown on the resonant frequency are explained to improve the accuracy of the oscillation frequency. Figure 3 for Figure 1 A circuit diagram of a first embodiment of the acceleration circuit 206 in the oscillation signal generation circuit 10. As previously described, Figure 3 The acceleration circuit is used to provide the system function, which is the same as the system function provided by the parallel-connected resistor Rp and capacitor Cp; wherein the resistance value of resistor Rp is less than zero. Please refer to... Figure 3 The acceleration circuit 206 may include a first N-type transistor Mn1, a second N-type transistor Mn2, a first capacitor C1, a second capacitor C2, and a third capacitor Cx. The first N-type transistor Mn1 and the second N-type transistor Mn2 form an interactive coupling pair and, together with the third capacitor Cx, provide the negative impedance required by the acceleration circuit 206 to shorten the start-up time of the oscillator 100. In some embodiments, the first N-type transistor Mn1 and the second N-type transistor Mn2 have the same geometry (channel width, channel length) and electrical characteristics. More specifically, the drain of the first N-type transistor Mn1 is coupled to a first reference voltage VDD, and the source is coupled to a second reference voltage GND, wherein the first reference voltage VDD is higher than the second reference voltage GND. The drain of the second N-type transistor Mn2 is coupled to the first reference voltage VDD, and its source is coupled to the second reference voltage GND. The gate of the second N-type transistor Mn2 is coupled to the drain of the first N-type transistor Mn1, and the drain of the second N-type transistor Mn2 is coupled to the gate of the first N-type transistor Mn1. A third capacitor Cx is coupled between the source of the first N-type transistor Mn1 and the source of the second N-type transistor Mn2.

[0048] The first capacitor C1 is coupled to the drain of the first N-type transistor Mn1 and the oscillator 100 (e.g., Figure 1 The second capacitor C2 is coupled between the input terminal X1 of the second N-type transistor Mn2 and the output terminal XO of the oscillator 100 (as shown). Figure 1 (As shown); in some embodiments, the first capacitor C1 and the second capacitor C2 have the same capacitance value. The capacitance values ​​of the first capacitor C1 and the second capacitor C2 are respectively smaller than the capacitance values ​​of the first load capacitor CL1 and the second load capacitor CL2. The first capacitor C1 and the second capacitor C2 have the function of isolating DC current to avoid affecting the DC bias point of other circuits.

[0049] The acceleration circuit 206 may further include a third N-type transistor Mn3, a fourth N-type transistor Mn4, a fifth N-type transistor Mn5, a first current source I1, a second current source I2, and a third current source I3. The third N-type transistor Mn3, the fourth N-type transistor Mn4, and the fifth N-type transistor Mn5, along with the third current source I3, form a current mirror. The fourth N-type transistor Mn4 and the fifth N-type transistor Mn5 have the same geometric dimensions (channel width, channel length) and electrical parameters. The drain of the third N-type transistor Mn3 is coupled to its own gate and also coupled to the first reference voltage VDD through the third current source I3; the source of the third N-type transistor Mn3 is grounded. The drain of the fourth N-type transistor Mn4 is coupled to the source of the first N-type transistor Mn1, and the gate of the fourth N-type transistor Mn4 is coupled to the gate of the third N-type transistor Mn3; the source of the fourth N-type transistor Mn4 is grounded. The drain of the fifth N-type transistor Mn5 is coupled to the source of the second N-type transistor Mn2, and the gate of the fifth N-type transistor Mn5 is coupled to the gate of the third N-type transistor Mn3; the source of the fifth N-type transistor Mn5 is grounded. A first current source I1 is connected between the first reference voltage VDD and the drain of the first N-type transistor Mn1, and a second current source I2 is connected between the first reference voltage VDD and the drain of the second N-type transistor Mn2. In some embodiments, the current value provided by the first current source I1 is equal to the current value provided by the second current source I2 to reduce circuit design complexity. In some embodiments, the current ratio of the first current source I1 to the third current source I3 is equal to the ratio of the geometric dimensions (channel width, channel length) of the fourth N-type transistor Mn4 to the third N-type transistor Mn3; similarly, the current ratio of the second current source I2 to the third current source I3 is equal to the ratio of the geometric dimensions (channel width, channel length) of the fifth N-type transistor Mn5 to the third N-type transistor Mn3.

[0050] Figure 4a for Figure 3 The impedance analysis diagrams of the first N-type transistor Mn1, the second N-type transistor Mn2, the fourth N-type transistor Mn4, the fifth N-type transistor Mn5, and the third capacitor Cx are shown. Figure 4b for Figure 3 The equivalent circuit shown includes the first N-type transistor Mn1, the second N-type transistor Mn2, the fourth N-type transistor Mn4, the fifth N-type transistor Mn5, the first capacitor, the second capacitor, and the third capacitor Cx. Figure 4c for Figure 4b The equivalent circuit. Please refer to... Figure 3 and Figures 4a to 4cAs mentioned earlier, the first N-type transistor Mn1 and the second N-type transistor Mn2 have the same geometric dimensions and electrical characteristics, the fourth N-type transistor Mn4 and the fifth N-type transistor Mn5 have the same geometric dimensions and electrical parameters, and the current value provided by the first current source I1 is equal to the current value provided by the second current source I2. This makes the path through which the first current I1 passes the same as the path through which the second current I2 passes. Therefore, the following impedance characteristic analysis of the first N-type transistor Mn1, the second N-type transistor Mn2, the fourth N-type transistor Mn4, and the fifth N-type transistor Mn5 only considers the impedance on one current branch (e.g., the first current I1 branch). Figure 4a Only the drain of the fourth N-type transistor Mn4 is shown to be coupled to the source of the first N-type transistor Mn1, and the third capacitor Cx is adjusted to capacitor 2Cx, with one end of capacitor 2Cx coupled to the drain of the fourth N-type transistor Mn4 and the source of the first N-type transistor Mn1. Figure 4a The impedance Z1 of node VO1 to ground shown can be expressed as follows:

[0051]

[0052]

[0053] Where Z is Figure 4a The parallel impedance of the output resistor ro4 and capacitor 2Cx of the fourth N-type transistor Mn4 is shown. gm1 is the transconductance of the first N-type transistor Mn1, and ro1 is the output resistor of the first N-type transistor Mn1. The output impedance of the first current source I1 is infinite and can be ignored. Therefore, the impedance of node VO1 is Z1.

[0054] The main operating frequency of oscillator 100 is in the low to medium frequency range (i.e., the oscillation frequency is from tens of thousands of hertz to tens of millions of hertz); when the operating frequency is low, the impedance of the third capacitor Cx is much greater than the output resistor ro4 of the fourth N-type transistor Mn4 and the output resistor ro5 of the fifth N-type transistor Mn5. Therefore, the impedance Z1 can be expressed by the following formula:

[0055]

[0056] Therefore, the equivalent impedance between nodes VO1 and VO2 can be expressed as:

[0057]

[0058] Of course, the equivalent impedance between nodes VO1 and VO2 can be expressed as:

[0059]

[0060] Therefore, the equivalent impedance between the input terminal XI and the output terminal XO of the oscillator 100 is:

[0061]

[0062] in, This is a necessary condition.

[0063] Alternatively, the equivalent impedance between the input terminal XI and the output terminal XO of the oscillator 100 is:

[0064]

[0065] in, As a necessary condition, gm2 is the transconductance of the second N-type transistor Mn2.

[0066] When the operating frequency is in the mid-frequency range (e.g., 1MHz to 48MHz), the impedance of the third capacitor Cx is much smaller than the resistance values ​​of the output resistors ro4 and ro5 of the fourth N-type transistor Mn4 and the fifth N-type transistor Mn5, therefore the impedance Z1 can be expressed by the following formula:

[0067] S = j * 2πf, where f is the oscillation frequency.

[0068] The equivalent impedance between nodes V01 and V02 can be expressed as:

[0069]

[0070] Or it can be expressed as:

[0071]

[0072] Therefore, the equivalent impedance between the input terminal XI and the output terminal XO of the oscillator 100 is:

[0073]

[0074]

[0075] when At this time, Cs exhibits a negative capacitance and has Then, the equivalent impedance between the input terminal XI and the output terminal XO of oscillator 100, where Cs > Cx, can also be expressed as:

[0076]

[0077]

[0078] when At this time, Cs exhibits a negative capacitance and has Then Cs > Cx

[0079] Therefore, it can be seen that by adjusting Figure 3 The sizes of the first capacitor C1 and the second capacitor C2 shown can amplify the negative capacitance of the acceleration circuit 206, and even multiply the capacitance value, thereby minimizing the load capacitance value. When the acceleration circuit 206 is implemented with integrated circuits, the capacitance multiplication effect provided by the first capacitor C1 and the second capacitor C2 allows the use of a third capacitor Cx with a smaller capacitance value, thereby reducing the chip footprint.

[0080] By converting the series branch of Cs and Rs into a parallel branch, we can obtain... Figure 1 The acceleration circuit 206 in the figure is of the form of parallel Rp and Cp, where

[0081]

[0082]

[0083] Q 2 =(R s *C s *ω) 2 ω is the angular frequency (2πf); given that the operating frequency of a crystal oscillator is usually in the low to medium frequency range, we have Q 2 << 1, therefore there is

[0084]

[0085] In summary, when the crystal oscillator operates at low frequencies, the acceleration circuit 206 provides a negative resistor and a positive capacitor. The negative resistor provides greater drive capability for the oscillator 100 to start oscillation, while the positive capacitor increases the load on the oscillator 100. Therefore, in this application scenario, it is necessary to minimize the capacitance values ​​of the first capacitor C1 and the second capacitor C2 to avoid affecting the start-up speed. In some embodiments, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are in the pF level. When the oscillator 100 operates in the mid-frequency range, the acceleration circuit 206 provides a negative resistor and a negative capacitor, reducing the load capacitance across the oscillator 100, thereby further shortening the start-up time.

[0086] It should be noted that the acceleration circuit 206 in this application is for illustrative purposes only. In practice, the acceleration circuit 206 can be modified to achieve substantially the same effect. For example, in some embodiments, the polarity of the transistors in the acceleration circuit 206 can be changed, and the circuit can be adjusted accordingly; in other embodiments, the configuration of the current source in the acceleration circuit 206 can be changed. Three different embodiments are listed below for illustrative purposes.

[0087] Figure 5 for Figure 1 A circuit diagram of a second embodiment of the acceleration circuit in the oscillation signal generation circuit. Please refer to... Figure 3 and Figure 5 As mentioned above, Figure 5 The acceleration circuit is used to provide the system function, which is the same as the system function provided by the parallel-connected resistor Rp and capacitor Cp; wherein the resistance value of resistor Rp is less than zero. Figure 3 In the acceleration circuit 206, a current mirror is formed using a third N-type transistor Mn3, a fourth N-type transistor Mn4, a fifth N-type transistor Mn5, and a third current source I3 to provide current I4 at the source of the first N-type transistor Mn1 and current I5 at the source of the second N-type transistor Mn2. To effectively reduce circuit size and cost, a fourth current source Ia and a fifth current source Ib can be directly provided at the sources of the first N-type transistor Mn1 and the second N-type transistor Mn2, respectively, to provide currents I4 and I5. Figure 6 for Figure 1 A circuit diagram of the third embodiment of the acceleration circuit in the oscillation signal generation circuit. As mentioned above, Figure 6 The acceleration circuit is used to provide the system function, which is the same as the system function provided by the parallel-connected resistor Rp and capacitor Cp; wherein the resistance value of resistor Rp is less than zero. Please refer to... Figure 5 The acceleration circuit 206 may include a first P-type transistor Mp1, a second P-type transistor Mp2, a third P-type transistor Mp3, a fourth P-type transistor Mp4, a fifth P-type transistor Mp5, a first capacitor C1, a second capacitor C2, a third capacitor Cx, a first current source I1, and a second current source I2. The first P-type transistor Mp1 and the second P-type transistor Mp2 form an interactive coupling pair and, together with the third capacitor Cx, provide the negative impedance required by the acceleration circuit 206. Specifically, the drain of the first P-type transistor Mp1 is coupled to the second reference voltage GND through the first current source I1, and its gate is coupled to the second reference voltage GND through the second current source I2. The drain of the second P-type transistor Mp2 is coupled to the gate of the first P-type transistor Mp1, and the gate of the second P-type transistor Mp2 is coupled to the drain of the first P-type transistor Mp1. In some embodiments, the first P-type transistor Mp1 and the second P-type transistor Mp2 have the same geometry (channel width, channel length) and electrical characteristics, and the first reference voltage VDD is higher than the second reference voltage GND. A third capacitor Cx is coupled between the source of the first P-type transistor Mp1 and the source of the second P-type transistor Mp2.

[0088] The third P-type transistor Mp3, the fourth P-type transistor Mp4, the fifth P-type transistor Mp5, and the third current source I3 constitute a current mirror; among them, the fourth P-type transistor Mp4 and the fifth P-type transistor Mp5 have the same geometric dimensions and electrical parameters. The coupling method of the third to fifth P-type transistors Mp3-Mp5 is described in detail below. The sources of the third P-type transistor Mp3, the fourth P-type transistor Mp4, and the fifth P-type transistor Mp5 are respectively coupled to the first reference voltage VDD; the gate of the third P-type transistor Mp3 is coupled to its drain, and the drain is coupled to the second reference voltage GND through the third current source I3. The gate of the fourth P-type transistor Mp4 is coupled to the gate of the third P-type transistor Mp3, and the drain of the fourth P-type transistor Mp4 is coupled to the source of the first P-type transistor Mp1. The gate of the fifth P-type transistor Mp5 is coupled to the gate of the third P-type transistor Mp3, and the drain of the fifth P-type transistor Mp5 is coupled to the source of the second P-type transistor Mp2. The current mirror, composed of the third P-type transistor Mp3, the fourth P-type transistor Mp4, the fifth P-type transistor Mp5, and the third current source I3, can be implemented by using the fourth current source Ia located at the source of the first P-type transistor Mp1 and the fifth current source Ib located at the source of the second P-type transistor Mp2, as follows: Figure 7 As shown.

[0089] See also Figure 6 The first capacitor C1 is coupled to the drain of the first P-type transistor Mp1 and the oscillator 100 (e.g., Figure 1 The second capacitor C2 is coupled between the input terminal X1 of the second P-type transistor Mp2 and the output terminal XO of the oscillator 100 (as shown). Figure 1 (as shown); in some embodiments, the first capacitor C1 and the second capacitor C2 have the same capacitance value. In addition to isolating DC power, the first capacitor C1 and the second capacitor C2 can further amplify the negative capacitance value of the acceleration circuit 206.

[0090] Figure 8 for Figure 1 A circuit diagram of the fifth embodiment of the acceleration circuit in the oscillation signal generation circuit. As previously described, Figure 8 The acceleration circuit is used to provide the system function, which is the same as the system function provided by the parallel-connected resistor Rp and capacitor Cp; wherein the resistance value of resistor Rp is less than zero. Please refer to... Figure 8The acceleration circuit 206 may include a first N-type transistor Mn1, a second N-type transistor Mn2, a third N-type transistor Mn3, a fourth N-type transistor Mn4, a fifth N-type transistor Mn5, a first capacitor C1, a second capacitor C2, a third capacitor Cx, a constant current source I, a first resistor R1, and a second resistor R2. The drain of the first N-type transistor Mn1 is coupled to a first reference voltage VDD through the first resistor R1, and its gate is coupled to the first reference voltage VDD through the second resistor R2; wherein, the first reference voltage VDD is higher than the second reference voltage GND. The drain of the second N-type transistor Mn2 is coupled to the gate of the first N-type transistor Mn1, and the gate of the second N-type transistor Mn2 is coupled to the drain of the first N-type transistor Mn1. The first resistor R1 and the second resistor R2 have the same resistance value. In some embodiments, the first N-type transistor Mn1 and the second N-type transistor Mn2 have the same geometric dimensions (channel width, channel length) and electrical characteristics. The third N-type transistor Mn3, the fourth N-type transistor Mn4, the fifth N-type transistor Mn5, and the constant current source I constitute a current mirror. More specifically, the drain of the third N-type transistor Mn3 is coupled to its own gate and also to the first reference voltage VDD through the constant current source I; the sources of the third N-type transistor Mn3, the fourth N-type transistor Mn4, and the fifth N-type transistor Mn5 are respectively coupled to the second reference voltage GND. The gates of the fourth N-type transistor Mn4 and the fifth N-type transistor Mn5 are respectively coupled to the gate of the third N-type transistor Mn3, the drain of the fourth N-type transistor Mn4 is coupled to the source of the first N-type transistor Mn1, and the drain of the fifth N-type transistor Mn5 is coupled to the source of the second N-type transistor Mn2; wherein, the fourth N-type transistor Mn4 and the fifth N-type transistor Mn5 may have the same geometric dimensions and electrical parameters. In short, the acceleration circuit 206 uses a third N-type transistor Mn3, a fourth N-type transistor Mn4, a fifth N-type transistor Mn5, and a constant current source I to form a current mirror to provide current I4 at the source of the first N-type transistor Mn1 and current I5 at the source of the second N-type transistor Mn2. Please refer to... Figure 3 and Figure 8 , Figure 8 The contents shown are replaced by the first resistor R1 and the second resistor R2. Figure 3 The first current source I1 and the second current source I2 in the circuit can be freed from the constraints that the current value of the second current source I2 must be equal to the current value of the first current source I1, and that currents I4 and I5 must simultaneously be equal to the current value of the first current source I1, allowing for greater flexibility in the selection of resistance values. Ideally, the internal resistance of the first current source I1 and the second current source I2 is infinite; therefore, while replacing the first current source I1 and the second current source I2 with the first resistor R1 and the second resistor R2 can effectively reduce circuit configuration costs, it will reduce the equivalent negative impedance, thus making the effect of the acceleration circuit 206 on accelerating the crystal oscillator startup less significant.

[0091] Furthermore, the current mirror composed of the third N-type transistor Mn3, the fourth N-type transistor Mn4, the fifth N-type transistor Mn5, and the constant current source I can be replaced by the fourth current source Ia disposed at the source of the first N-type transistor Mn1 and the fifth current source Ib disposed at the source of the second N-type transistor Mn2, as follows: Figure 9 As shown.

[0092] See also Figure 8 The first capacitor C1 is coupled to the drain of the first N-type transistor Mn1 and the oscillator 100 (e.g., Figure 1 The second capacitor C2 is coupled between the input terminal X1 of the second N-type transistor Mn2 and the output terminal XO of the oscillator 100 (as shown). Figure 1 (As shown); in some embodiments, the first capacitor C1 and the second capacitor C2 have the same capacitance value. In addition to isolating DC power, the first capacitor C1 and the second capacitor C2 can further amplify the negative capacitance value of the acceleration circuit 206. The third capacitor Cx is coupled between the source of the first N-type transistor Mn1 and the source of the second N-type transistor Mn2, and together with the first N-type transistor Mn1 and the second N-type transistor Mn2, forms an interactive coupling pair to provide the negative impedance required by the acceleration circuit 206.

[0093] Figure 10 for Figure 1 A circuit diagram of the seventh embodiment of the acceleration circuit in the oscillation signal generation circuit. As previously described, Figure 10 The acceleration circuit is used to provide the system function, which is the same as the system function provided by the parallel-connected resistor Rp and capacitor Cp; wherein the resistance value of resistor Rp is less than zero. Please refer to... Figure 10 The acceleration circuit 206 is coupled between a first reference voltage VDD and a second reference voltage GND, and may include a first P-type transistor Mp1, a second P-type transistor Mp2, a third P-type transistor Mp3, a fourth P-type transistor Mp4, a fifth P-type transistor Mp5, a first capacitor C1, a second capacitor C2, a third capacitor Cx, a current source I, a first resistor R1, and a second resistor R2. Figure 7As shown, the drain of the first P-type transistor Mp1 is connected to the second reference voltage GND through a first resistor R1, and the gate of the first P-type transistor Mp1 is connected to the second reference voltage GND through a second resistor R2; wherein, the first reference voltage VDD is higher than the second reference voltage GND. The gate of the second P-type transistor Mp2 is coupled to the drain of the first P-type transistor Mp1, and the drain of the second P-type transistor Mp2 is coupled to the gate of the first P-type transistor Mp1; the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2. In some embodiments, the first P-type transistor Mp1 and the second P-type transistor Mp2 have the same geometric dimensions (channel width, channel length) and electrical characteristics.

[0094] The third P-type transistor Mp3, the fourth P-type transistor Mp4, the fifth P-type transistor Mp5, and the constant current source 3 constitute a current mirror. More specifically, the drain of the third P-type transistor Mp3 is coupled to its own gate and also to the second reference voltage GND through the constant current source I; the sources of the third P-type transistor Mp3, the fourth P-type transistor Mp4, and the fifth P-type transistor Mp5 are respectively coupled to the first reference voltage VDD. The gates of the fourth P-type transistor Mp4 and the fifth P-type transistor Mp5 are respectively coupled to the gate of the third P-type transistor Mp3, the drain of the fourth P-type transistor Mp4 is coupled to the source of the first P-type transistor Mp1, and the drain of the fifth P-type transistor Mp5 is coupled to the source of the second P-type transistor Mp2; wherein, the fourth P-type transistor Mp4 and the fifth P-type transistor Mp5 may have the same geometric dimensions and electrical parameters. The current mirror, composed of the third P-type transistor Mp3, the fourth P-type transistor Mp4, the fifth P-type transistor Mp5, and a constant current source I, can be implemented by using the fourth current source Ia located at the source of the first P-type transistor Mp1 and the fifth current source Ib located at the source of the second P-type transistor Mp2, as follows: Figure 11 As shown.

[0095] See also Figure 10 The first capacitor C1 is coupled to the drain of the first P-type transistor Mp1 and the oscillator 100 (e.g., Figure 1 The second capacitor C2 is coupled between the input terminal X1 of the second P-type transistor Mp2 and the output terminal XO of the oscillator 100 (as shown). Figure 1 (as shown); in some embodiments, the first capacitor C1 and the second capacitor C2 have the same capacitance value. The third capacitor Cx is coupled between the source of the first P-type transistor Mp1 and the source of the second P-type transistor Mp2, and together with the first P-type transistor Mp1 and the second P-type transistor Mp2, forms an interactive coupling pair to provide the negative impedance required by the acceleration circuit 206; in addition to having the function of isolating DC power, the first capacitor C1 and the second capacitor C2 can further amplify the negative capacitance value of the acceleration circuit 206.

[0096] The foregoing description briefly outlines the features of certain embodiments of the present invention, enabling those skilled in the art to more fully understand the various forms of this disclosure. Those skilled in the art will readily recognize that this disclosure serves as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of the disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the disclosure.

Claims

1. An oscillator acceleration circuit for accelerating the start-up of an oscillator, the oscillator having an input terminal and an output terminal, the oscillator acceleration circuit comprising: An inverting amplifier having an input terminal and an output terminal correspondingly coupled to the input terminal and the output terminal of the oscillator; A feedback resistor is coupled between the input and output terminals of the oscillator; as well as Acceleration circuit, including: A first N-type transistor, wherein the drain of the first N-type transistor is coupled to a first reference voltage, and the source of the first N-type transistor is coupled to a second reference voltage, wherein the first reference voltage is higher than the second reference voltage; The second N-type transistor has its drain coupled to the first reference voltage, its source coupled to the second reference voltage, and one of its gates coupled to the drain of the first N-type transistor, and one of its gates coupled to the drain of the second N-type transistor. A first capacitor is coupled between the drain of the first N-type transistor and the input terminal of the oscillator; A second capacitor is coupled between the drain of the second N-type transistor and the output terminal of the oscillator; and A third capacitor is coupled between the source of the first N-type transistor and the source of the second N-type transistor.

2. The oscillator acceleration circuit of claim 1, wherein the acceleration circuit further comprises: A first current source is coupled between the drain of the first N-type transistor and the first reference voltage; as well as The second current source is coupled between the drain of the second N-type transistor and the first reference voltage.

3. The oscillator acceleration circuit as described in claim 2, wherein the current value provided by the first current source is equal to the current value provided by the second current source.

4. The oscillator acceleration circuit of claim 2, wherein the acceleration circuit further comprises: The third N-type transistor has its drain coupled to its gate and its source coupled to the second reference voltage. A fourth N-type transistor, wherein the gate of the fourth N-type transistor is coupled to the gate of the third N-type transistor, the drain of the fourth N-type transistor is coupled to the source of the first N-type transistor, and the source of the fourth N-type transistor is coupled to the second reference voltage; A fifth N-type transistor, wherein the gate of the fifth N-type transistor is coupled to the gate of the third N-type transistor, the drain of the fifth N-type transistor is coupled to the source of the second N-type transistor, and the source of the fifth N-type transistor is coupled to the second reference voltage; as well as The third current source is coupled between the drain of the third N-type transistor and the first reference voltage.

5. The oscillator acceleration circuit of claim 2, wherein the acceleration circuit further comprises: A fourth current source is coupled between the source of the first N-type transistor and the second reference voltage; as well as The fifth current source is coupled between the source of the second N-type transistor and the second reference voltage.

6. The oscillator acceleration circuit of claim 1, wherein the acceleration circuit further comprises: A first resistor is coupled between the drain of the first N-type transistor and the first reference voltage; as well as The second resistor is coupled between the drain of the second N-type transistor and the first reference voltage.

7. The oscillator acceleration circuit of claim 6, wherein the resistance value of the first resistor is equal to the resistance value of the second resistor.

8. The oscillator acceleration circuit of claim 6, wherein the acceleration circuit further comprises: The third N-type transistor has its drain coupled to its gate and its source coupled to the second reference voltage. A fourth N-type transistor, wherein the gate of the fourth N-type transistor is coupled to the gate of the third N-type transistor, the drain of the fourth N-type transistor is coupled to the source of the first N-type transistor, and the source of the fourth N-type transistor is coupled to the second reference voltage; A fifth N-type transistor, wherein the gate of the fifth N-type transistor is coupled to the gate of the third N-type transistor, the drain of the fifth N-type transistor is coupled to the source of the second N-type transistor, and the source of the fifth N-type transistor is coupled to the second reference voltage; as well as A constant current source is coupled between the drain of the third N-type transistor and the first reference voltage.

9. The oscillator acceleration circuit of claim 6, wherein the acceleration circuit further comprises: A fourth current source is coupled between the source of the first N-type transistor and the second reference voltage; as well as The fifth current source is coupled between the source of the second N-type transistor and the second reference voltage.

10. The oscillator acceleration circuit of claim 1 further includes a counter coupled between the output terminal of the oscillator and the acceleration circuit, the counter controlling the acceleration circuit according to the oscillation signal generated by the oscillator, and turning off the acceleration circuit when it is determined that the oscillator has entered a stable state.

11. The oscillator acceleration circuit of claim 1, wherein the acceleration circuit is coupled between the input terminal and the output terminal of the oscillator, wherein the acceleration circuit is used to provide a system function that is the same as the system function provided by the parallel-connected resistor and capacitor, wherein the resistance value of the resistor is less than zero, and the capacitance value of the capacitor is less than zero when the oscillator operates at an intermediate frequency, and the capacitance value of the capacitor is greater than zero when the oscillator operates at a low frequency.

12. An oscillator acceleration circuit for accelerating the start-up of an oscillator, the oscillator having an input terminal and an output terminal, the oscillator acceleration circuit comprising: An inverting amplifier having an input terminal and an output terminal correspondingly coupled to the input terminal and the output terminal of the oscillator; A feedback resistor is coupled between the input and output terminals of the oscillator; as well as Acceleration circuit, including: A first P-type transistor, wherein the source of the first P-type transistor is coupled to a first reference voltage and the drain of the first P-type transistor is coupled to a second reference voltage, wherein the first reference voltage is higher than the second reference voltage; The second P-type transistor has its source coupled to the first reference voltage, its drain coupled to the second reference voltage, its gate coupled to the drain of the first P-type transistor, and one of the gates of the first P-type transistor coupled to the drain of the second P-type transistor. A first capacitor is coupled between the drain of the first P-type transistor and the input terminal of the oscillator; A second capacitor is coupled between the drain of the second P-type transistor and the output terminal of the oscillator; and A third capacitor is coupled between the source of the first P-type transistor and the source of the second P-type transistor.

13. The oscillator acceleration circuit of claim 12, wherein the acceleration circuit further comprises: A first current source is coupled between the drain of the first P-type transistor and the second reference voltage; as well as The second current source is coupled between the drain of the second P-type transistor and the second reference voltage.

14. The oscillator acceleration circuit of claim 13, wherein the current value provided by the first current source is equal to the current value provided by the second current source.

15. The oscillator acceleration circuit of claim 13, wherein the acceleration circuit further comprises: The third P-type transistor has its source coupled to the first reference voltage and its drain coupled to its own gate. A fourth P-type transistor, wherein the gate of the fourth P-type transistor is coupled to the gate of the third P-type transistor, the drain of the fourth P-type transistor is coupled to the source of the first P-type transistor, and the source of the fourth P-type transistor is coupled to the first reference voltage. A fifth P-type transistor, wherein the gate of the fifth P-type transistor is coupled to the gate of the third P-type transistor, the drain of the fifth P-type transistor is coupled to the source of the second P-type transistor, and the source of the fifth P-type transistor is coupled to the first reference voltage. as well as A third current source is coupled between the drain of the third P-type transistor and the second reference voltage.

16. The oscillator acceleration circuit of claim 13, wherein the acceleration circuit further comprises: A fourth current source is coupled between the source of the first P-type transistor and the first reference voltage; as well as The fifth current source is coupled between the source of the second P-type transistor and the first reference voltage.

17. The oscillator acceleration circuit of claim 12, wherein the acceleration circuit further comprises: A first resistor is coupled between the drain of the first P-type transistor and the second reference voltage; as well as The second resistor is coupled between the drain of the second P-type transistor and the second reference voltage.

18. The oscillator acceleration circuit of claim 17, wherein the resistance value of the first resistor is equal to the resistance value of the second resistor.

19. The oscillator acceleration circuit of claim 17, wherein the acceleration circuit further comprises: The third P-type transistor has its drain coupled to its own gate and its source coupled to the first reference voltage. A fourth P-type transistor, wherein the gate of the fourth P-type transistor is coupled to the gate of the third P-type transistor, the drain of the fourth P-type transistor is coupled to the source of the first P-type transistor, and the source of the fourth P-type transistor is coupled to the first reference voltage. A fifth P-type transistor, wherein the gate of the fifth P-type transistor is coupled to the gate of the third P-type transistor, the drain of the fifth P-type transistor is coupled to the source of the second P-type transistor, and the source of the fifth P-type transistor is coupled to the first reference voltage. as well as A constant current source is coupled between the drain of the third P-type transistor and the second reference voltage.

20. The oscillator acceleration circuit of claim 17, wherein the acceleration circuit further comprises: A fourth current source is coupled between the first reference voltage and the source of the first P-type transistor; as well as The fifth current source is coupled between the first reference voltage and the source of the second P-type transistor.

21. The oscillator acceleration circuit of claim 12, wherein the acceleration circuit is coupled between the input terminal and the output terminal of the oscillator, wherein the acceleration circuit provides a system function that is the same as the system function provided by the parallel-connected resistor and capacitor, wherein the resistance value of the resistor is less than zero, and the capacitance value of the capacitor is less than zero when the oscillator operates at an intermediate frequency, and the capacitance value of the capacitor is greater than zero when the oscillator operates at a low frequency.

22. The oscillator acceleration circuit of claim 12 further includes a counter coupled between the output terminal of the oscillator and the acceleration circuit, the counter controlling the acceleration circuit according to the oscillation signal generated by the oscillator, and shutting down the acceleration circuit when it is determined that the oscillator has entered a stable state.

23. A chip comprising: The oscillator acceleration circuit as described in any one of claims 1 to 22.

24. An electronic device comprising: The chip as described in claim 23; and The oscillator is coupled to the chip.

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